drivers/clocksource/timer-prima2.c

   1 /*
   2  * System timer for CSR SiRFprimaII
   3  *
   4  * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
   5  *
   6  * Licensed under GPLv2 or later.
   7  */
   8
   9 #include <linux/kernel.h>
  10 #include <linux/interrupt.h>
  11 #include <linux/clockchips.h>
  12 #include <linux/clocksource.h>
  13 #include <linux/bitops.h>
  14 #include <linux/irq.h>
  15 #include <linux/clk.h>
  16 #include <linux/err.h>
  17 #include <linux/slab.h>
  18 #include <linux/of.h>
  19 #include <linux/of_irq.h>
  20 #include <linux/of_address.h>
  21 #include <linux/sched_clock.h>
  22 #include <asm/mach/time.h>
  23
  24 #define PRIMA2_CLOCK_FREQ 1000000
  25
  26 #define SIRFSOC_TIMER_COUNTER_LO        0x0000
  27 #define SIRFSOC_TIMER_COUNTER_HI        0x0004
  28 #define SIRFSOC_TIMER_MATCH_0           0x0008
  29 #define SIRFSOC_TIMER_MATCH_1           0x000C
  30 #define SIRFSOC_TIMER_MATCH_2           0x0010
  31 #define SIRFSOC_TIMER_MATCH_3           0x0014
  32 #define SIRFSOC_TIMER_MATCH_4           0x0018
  33 #define SIRFSOC_TIMER_MATCH_5           0x001C
  34 #define SIRFSOC_TIMER_STATUS            0x0020
  35 #define SIRFSOC_TIMER_INT_EN            0x0024
  36 #define SIRFSOC_TIMER_WATCHDOG_EN       0x0028
  37 #define SIRFSOC_TIMER_DIV               0x002C
  38 #define SIRFSOC_TIMER_LATCH             0x0030
  39 #define SIRFSOC_TIMER_LATCHED_LO        0x0034
  40 #define SIRFSOC_TIMER_LATCHED_HI        0x0038
  41
  42 #define SIRFSOC_TIMER_WDT_INDEX         5
  43
  44 #define SIRFSOC_TIMER_LATCH_BIT  BIT(0)
  45
  46 #define SIRFSOC_TIMER_REG_CNT 11
  47
  48 static const u32 sirfsoc_timer_reg_list[SIRFSOC_TIMER_REG_CNT] = {
  49         SIRFSOC_TIMER_MATCH_0, SIRFSOC_TIMER_MATCH_1, SIRFSOC_TIMER_MATCH_2,
  50         SIRFSOC_TIMER_MATCH_3, SIRFSOC_TIMER_MATCH_4, SIRFSOC_TIMER_MATCH_5,
  51         SIRFSOC_TIMER_INT_EN, SIRFSOC_TIMER_WATCHDOG_EN, SIRFSOC_TIMER_DIV,
  52         SIRFSOC_TIMER_LATCHED_LO, SIRFSOC_TIMER_LATCHED_HI,
  53 };
  54
  55 static u32 sirfsoc_timer_reg_val[SIRFSOC_TIMER_REG_CNT];
  56
  57 static void __iomem *sirfsoc_timer_base;
  58
  59 /* timer0 interrupt handler */
  60 static irqreturn_t sirfsoc_timer_interrupt(int irq, void *dev_id)
  61 {
  62         struct clock_event_device *ce = dev_id;
  63
  64         WARN_ON(!(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_STATUS) & BIT(0)));
  65
  66         /* clear timer0 interrupt */
  67         writel_relaxed(BIT(0), sirfsoc_timer_base + SIRFSOC_TIMER_STATUS);
  68
  69         ce->event_handler(ce);
  70
  71         return IRQ_HANDLED;
  72 }
  73
  74 /* read 64-bit timer counter */
  75 static cycle_t sirfsoc_timer_read(struct clocksource *cs)
  76 {
  77         u64 cycles;
  78
  79         /* latch the 64-bit timer counter */
  80         writel_relaxed(SIRFSOC_TIMER_LATCH_BIT, sirfsoc_timer_base + SIRFSOC_TIMER_LATCH);
  81         cycles = readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_LATCHED_HI);
  82         cycles = (cycles << 32) | readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_LATCHED_LO);
  83
  84         return cycles;
  85 }
  86
  87 static int sirfsoc_timer_set_next_event(unsigned long delta,
  88         struct clock_event_device *ce)
  89 {
  90         unsigned long now, next;
  91
  92         writel_relaxed(SIRFSOC_TIMER_LATCH_BIT, sirfsoc_timer_base + SIRFSOC_TIMER_LATCH);
  93         now = readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_LATCHED_LO);
  94         next = now + delta;
  95         writel_relaxed(next, sirfsoc_timer_base + SIRFSOC_TIMER_MATCH_0);
  96         writel_relaxed(SIRFSOC_TIMER_LATCH_BIT, sirfsoc_timer_base + SIRFSOC_TIMER_LATCH);
  97         now = readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_LATCHED_LO);
  98
  99         return next - now > delta ? -ETIME : 0;
 100 }
 101
 102 static void sirfsoc_timer_set_mode(enum clock_event_mode mode,
 103         struct clock_event_device *ce)
 104 {
 105         u32 val = readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_INT_EN);
 106         switch (mode) {
 107         case CLOCK_EVT_MODE_PERIODIC:
 108                 WARN_ON(1);
 109                 break;
 110         case CLOCK_EVT_MODE_ONESHOT:
 111                 writel_relaxed(val | BIT(0), sirfsoc_timer_base + SIRFSOC_TIMER_INT_EN);
 112                 break;
 113         case CLOCK_EVT_MODE_SHUTDOWN:
 114                 writel_relaxed(val & ~BIT(0), sirfsoc_timer_base + SIRFSOC_TIMER_INT_EN);
 115                 break;
 116         case CLOCK_EVT_MODE_UNUSED:
 117         case CLOCK_EVT_MODE_RESUME:
 118                 break;
 119         }
 120 }
 121
 122 static void sirfsoc_clocksource_suspend(struct clocksource *cs)
 123 {
 124         int i;
 125
 126         writel_relaxed(SIRFSOC_TIMER_LATCH_BIT, sirfsoc_timer_base + SIRFSOC_TIMER_LATCH);
 127
 128         for (i = 0; i < SIRFSOC_TIMER_REG_CNT; i++)
 129                 sirfsoc_timer_reg_val[i] = readl_relaxed(sirfsoc_timer_base + sirfsoc_timer_reg_list[i]);
 130 }
 131
 132 static void sirfsoc_clocksource_resume(struct clocksource *cs)
 133 {
 134         int i;
 135
 136         for (i = 0; i < SIRFSOC_TIMER_REG_CNT - 2; i++)
 137                 writel_relaxed(sirfsoc_timer_reg_val[i], sirfsoc_timer_base + sirfsoc_timer_reg_list[i]);
 138
 139         writel_relaxed(sirfsoc_timer_reg_val[SIRFSOC_TIMER_REG_CNT - 2], sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_LO);
 140         writel_relaxed(sirfsoc_timer_reg_val[SIRFSOC_TIMER_REG_CNT - 1], sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_HI);
 141 }
 142
 143 static struct clock_event_device sirfsoc_clockevent = {
 144         .name = "sirfsoc_clockevent",
 145         .rating = 200,
 146         .features = CLOCK_EVT_FEAT_ONESHOT,
 147         .set_mode = sirfsoc_timer_set_mode,
 148         .set_next_event = sirfsoc_timer_set_next_event,
 149 };
 150
 151 static struct clocksource sirfsoc_clocksource = {
 152         .name = "sirfsoc_clocksource",
 153         .rating = 200,
 154         .mask = CLOCKSOURCE_MASK(64),
 155         .flags = CLOCK_SOURCE_IS_CONTINUOUS,
 156         .read = sirfsoc_timer_read,
 157         .suspend = sirfsoc_clocksource_suspend,
 158         .resume = sirfsoc_clocksource_resume,
 159 };
 160
 161 static struct irqaction sirfsoc_timer_irq = {
 162         .name = "sirfsoc_timer0",
 163         .flags = IRQF_TIMER,
 164         .irq = 0,
 165         .handler = sirfsoc_timer_interrupt,
 166         .dev_id = &sirfsoc_clockevent,
 167 };
 168
 169 /* Overwrite weak default sched_clock with more precise one */
 170 static u64 notrace sirfsoc_read_sched_clock(void)
 171 {
 172         return sirfsoc_timer_read(NULL);
 173 }
 174
 175 static void __init sirfsoc_clockevent_init(void)
 176 {
 177         sirfsoc_clockevent.cpumask = cpumask_of(0);
 178         clockevents_config_and_register(&sirfsoc_clockevent, PRIMA2_CLOCK_FREQ,
 179                                         2, -2);
 180 }
 181
 182 /* initialize the kernel jiffy timer source */
 183 static void __init sirfsoc_prima2_timer_init(struct device_node *np)
 184 {
 185         unsigned long rate;
 186         struct clk *clk;
 187
 188         /* timer's input clock is io clock */
 189         clk = clk_get_sys("io", NULL);
 190
 191         BUG_ON(IS_ERR(clk));
 192
 193         rate = clk_get_rate(clk);
 194
 195         BUG_ON(rate < PRIMA2_CLOCK_FREQ);
 196         BUG_ON(rate % PRIMA2_CLOCK_FREQ);
 197
 198         sirfsoc_timer_base = of_iomap(np, 0);
 199         if (!sirfsoc_timer_base)
 200                 panic("unable to map timer cpu registers\n");
 201
 202         sirfsoc_timer_irq.irq = irq_of_parse_and_map(np, 0);
 203
 204         writel_relaxed(rate / PRIMA2_CLOCK_FREQ / 2 - 1,
 205                        sirfsoc_timer_base + SIRFSOC_TIMER_DIV);
 206         writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_LO);
 207         writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_HI);
 208         writel_relaxed(BIT(0), sirfsoc_timer_base + SIRFSOC_TIMER_STATUS);
 209
 210         BUG_ON(clocksource_register_hz(&sirfsoc_clocksource,
 211                                        PRIMA2_CLOCK_FREQ));
 212
 213         sched_clock_register(sirfsoc_read_sched_clock, 64, PRIMA2_CLOCK_FREQ);
 214
 215         BUG_ON(setup_irq(sirfsoc_timer_irq.irq, &sirfsoc_timer_irq));
 216
 217         sirfsoc_clockevent_init();
 218 }
 219 CLOCKSOURCE_OF_DECLARE(sirfsoc_prima2_timer, "sirf,prima2-tick", sirfsoc_prima2_timer_init);