?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
net: qmi_wwan: add Olivetti Olicard 500
[linux/fpc-iii.git] / drivers / media / i2c / soc_camera / mt9t112.c
blob46f431a13782800c04198547ebf906394086e20c
1 /*
2 * mt9t112 Camera Driver
3 *
4 * Copyright (C) 2009 Renesas Solutions Corp.
5 * Kuninori Morimoto <morimoto.kuninori@renesas.com>
6 *
7 * Based on ov772x driver, mt9m111 driver,
8 *
9 * Copyright (C) 2008 Kuninori Morimoto <morimoto.kuninori@renesas.com>
10 * Copyright (C) 2008, Robert Jarzmik <robert.jarzmik@free.fr>
11 * Copyright 2006-7 Jonathan Corbet <corbet@lwn.net>
12 * Copyright (C) 2008 Magnus Damm
13 * Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de>
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
18 */
19
20 #include <linux/delay.h>
21 #include <linux/i2c.h>
22 #include <linux/init.h>
23 #include <linux/module.h>
24 #include <linux/slab.h>
25 #include <linux/v4l2-mediabus.h>
26 #include <linux/videodev2.h>
27
28 #include <media/mt9t112.h>
29 #include <media/soc_camera.h>
30 #include <media/v4l2-clk.h>
31 #include <media/v4l2-common.h>
32
33 /* you can check PLL/clock info */
34 /* #define EXT_CLOCK 24000000 */
35
36 /************************************************************************
37 macro
38 ************************************************************************/
39 /*
40 * frame size
41 */
42 #define MAX_WIDTH 2048
43 #define MAX_HEIGHT 1536
44
45 #define VGA_WIDTH 640
46 #define VGA_HEIGHT 480
47
48 /*
49 * macro of read/write
50 */
51 #define ECHECKER(ret, x) \
52 do { \
53 (ret) = (x); \
54 if ((ret) < 0) \
55 return (ret); \
56 } while (0)
57
58 #define mt9t112_reg_write(ret, client, a, b) \
59 ECHECKER(ret, __mt9t112_reg_write(client, a, b))
60 #define mt9t112_mcu_write(ret, client, a, b) \
61 ECHECKER(ret, __mt9t112_mcu_write(client, a, b))
62
63 #define mt9t112_reg_mask_set(ret, client, a, b, c) \
64 ECHECKER(ret, __mt9t112_reg_mask_set(client, a, b, c))
65 #define mt9t112_mcu_mask_set(ret, client, a, b, c) \
66 ECHECKER(ret, __mt9t112_mcu_mask_set(client, a, b, c))
67
68 #define mt9t112_reg_read(ret, client, a) \
69 ECHECKER(ret, __mt9t112_reg_read(client, a))
70
71 /*
72 * Logical address
73 */
74 #define _VAR(id, offset, base) (base | (id & 0x1f) << 10 | (offset & 0x3ff))
75 #define VAR(id, offset) _VAR(id, offset, 0x0000)
76 #define VAR8(id, offset) _VAR(id, offset, 0x8000)
77
78 /************************************************************************
79 struct
80 ************************************************************************/
81 struct mt9t112_format {
82 enum v4l2_mbus_pixelcode code;
83 enum v4l2_colorspace colorspace;
84 u16 fmt;
85 u16 order;
86 };
87
88 struct mt9t112_priv {
89 struct v4l2_subdev subdev;
90 struct mt9t112_camera_info *info;
91 struct i2c_client *client;
92 struct v4l2_rect frame;
93 struct v4l2_clk *clk;
94 const struct mt9t112_format *format;
95 int num_formats;
96 u32 flags;
97 /* for flags */
98 #define INIT_DONE (1 << 0)
99 #define PCLK_RISING (1 << 1)
100 };
101
102 /************************************************************************
103 supported format
104 ************************************************************************/
105
106 static const struct mt9t112_format mt9t112_cfmts[] = {
107 {
108 .code = V4L2_MBUS_FMT_UYVY8_2X8,
109 .colorspace = V4L2_COLORSPACE_JPEG,
110 .fmt = 1,
111 .order = 0,
112 }, {
113 .code = V4L2_MBUS_FMT_VYUY8_2X8,
114 .colorspace = V4L2_COLORSPACE_JPEG,
115 .fmt = 1,
116 .order = 1,
117 }, {
118 .code = V4L2_MBUS_FMT_YUYV8_2X8,
119 .colorspace = V4L2_COLORSPACE_JPEG,
120 .fmt = 1,
121 .order = 2,
122 }, {
123 .code = V4L2_MBUS_FMT_YVYU8_2X8,
124 .colorspace = V4L2_COLORSPACE_JPEG,
125 .fmt = 1,
126 .order = 3,
127 }, {
128 .code = V4L2_MBUS_FMT_RGB555_2X8_PADHI_LE,
129 .colorspace = V4L2_COLORSPACE_SRGB,
130 .fmt = 8,
131 .order = 2,
132 }, {
133 .code = V4L2_MBUS_FMT_RGB565_2X8_LE,
134 .colorspace = V4L2_COLORSPACE_SRGB,
135 .fmt = 4,
136 .order = 2,
137 },
138 };
139
140 /************************************************************************
141 general function
142 ************************************************************************/
143 static struct mt9t112_priv *to_mt9t112(const struct i2c_client *client)
144 {
145 return container_of(i2c_get_clientdata(client),
146 struct mt9t112_priv,
147 subdev);
148 }
149
150 static int __mt9t112_reg_read(const struct i2c_client *client, u16 command)
151 {
152 struct i2c_msg msg[2];
153 u8 buf[2];
154 int ret;
155
156 command = swab16(command);
157
158 msg[0].addr = client->addr;
159 msg[0].flags = 0;
160 msg[0].len = 2;
161 msg[0].buf = (u8 *)&command;
162
163 msg[1].addr = client->addr;
164 msg[1].flags = I2C_M_RD;
165 msg[1].len = 2;
166 msg[1].buf = buf;
167
168 /*
169 * if return value of this function is < 0,
170 * it mean error.
171 * else, under 16bit is valid data.
172 */
173 ret = i2c_transfer(client->adapter, msg, 2);
174 if (ret < 0)
175 return ret;
176
177 memcpy(&ret, buf, 2);
178 return swab16(ret);
179 }
180
181 static int __mt9t112_reg_write(const struct i2c_client *client,
182 u16 command, u16 data)
183 {
184 struct i2c_msg msg;
185 u8 buf[4];
186 int ret;
187
188 command = swab16(command);
189 data = swab16(data);
190
191 memcpy(buf + 0, &command, 2);
192 memcpy(buf + 2, &data, 2);
193
194 msg.addr = client->addr;
195 msg.flags = 0;
196 msg.len = 4;
197 msg.buf = buf;
198
199 /*
200 * i2c_transfer return message length,
201 * but this function should return 0 if correct case
202 */
203 ret = i2c_transfer(client->adapter, &msg, 1);
204 if (ret >= 0)
205 ret = 0;
206
207 return ret;
208 }
209
210 static int __mt9t112_reg_mask_set(const struct i2c_client *client,
211 u16 command,
212 u16 mask,
213 u16 set)
214 {
215 int val = __mt9t112_reg_read(client, command);
216 if (val < 0)
217 return val;
218
219 val &= ~mask;
220 val |= set & mask;
221
222 return __mt9t112_reg_write(client, command, val);
223 }
224
225 /* mcu access */
226 static int __mt9t112_mcu_read(const struct i2c_client *client, u16 command)
227 {
228 int ret;
229
230 ret = __mt9t112_reg_write(client, 0x098E, command);
231 if (ret < 0)
232 return ret;
233
234 return __mt9t112_reg_read(client, 0x0990);
235 }
236
237 static int __mt9t112_mcu_write(const struct i2c_client *client,
238 u16 command, u16 data)
239 {
240 int ret;
241
242 ret = __mt9t112_reg_write(client, 0x098E, command);
243 if (ret < 0)
244 return ret;
245
246 return __mt9t112_reg_write(client, 0x0990, data);
247 }
248
249 static int __mt9t112_mcu_mask_set(const struct i2c_client *client,
250 u16 command,
251 u16 mask,
252 u16 set)
253 {
254 int val = __mt9t112_mcu_read(client, command);
255 if (val < 0)
256 return val;
257
258 val &= ~mask;
259 val |= set & mask;
260
261 return __mt9t112_mcu_write(client, command, val);
262 }
263
264 static int mt9t112_reset(const struct i2c_client *client)
265 {
266 int ret;
267
268 mt9t112_reg_mask_set(ret, client, 0x001a, 0x0001, 0x0001);
269 msleep(1);
270 mt9t112_reg_mask_set(ret, client, 0x001a, 0x0001, 0x0000);
271
272 return ret;
273 }
274
275 #ifndef EXT_CLOCK
276 #define CLOCK_INFO(a, b)
277 #else
278 #define CLOCK_INFO(a, b) mt9t112_clock_info(a, b)
279 static int mt9t112_clock_info(const struct i2c_client *client, u32 ext)
280 {
281 int m, n, p1, p2, p3, p4, p5, p6, p7;
282 u32 vco, clk;
283 char *enable;
284
285 ext /= 1000; /* kbyte order */
286
287 mt9t112_reg_read(n, client, 0x0012);
288 p1 = n & 0x000f;
289 n = n >> 4;
290 p2 = n & 0x000f;
291 n = n >> 4;
292 p3 = n & 0x000f;
293
294 mt9t112_reg_read(n, client, 0x002a);
295 p4 = n & 0x000f;
296 n = n >> 4;
297 p5 = n & 0x000f;
298 n = n >> 4;
299 p6 = n & 0x000f;
300
301 mt9t112_reg_read(n, client, 0x002c);
302 p7 = n & 0x000f;
303
304 mt9t112_reg_read(n, client, 0x0010);
305 m = n & 0x00ff;
306 n = (n >> 8) & 0x003f;
307
308 enable = ((6000 > ext) || (54000 < ext)) ? "X" : "";
309 dev_dbg(&client->dev, "EXTCLK : %10u K %s\n", ext, enable);
310
311 vco = 2 * m * ext / (n+1);
312 enable = ((384000 > vco) || (768000 < vco)) ? "X" : "";
313 dev_dbg(&client->dev, "VCO : %10u K %s\n", vco, enable);
314
315 clk = vco / (p1+1) / (p2+1);
316 enable = (96000 < clk) ? "X" : "";
317 dev_dbg(&client->dev, "PIXCLK : %10u K %s\n", clk, enable);
318
319 clk = vco / (p3+1);
320 enable = (768000 < clk) ? "X" : "";
321 dev_dbg(&client->dev, "MIPICLK : %10u K %s\n", clk, enable);
322
323 clk = vco / (p6+1);
324 enable = (96000 < clk) ? "X" : "";
325 dev_dbg(&client->dev, "MCU CLK : %10u K %s\n", clk, enable);
326
327 clk = vco / (p5+1);
328 enable = (54000 < clk) ? "X" : "";
329 dev_dbg(&client->dev, "SOC CLK : %10u K %s\n", clk, enable);
330
331 clk = vco / (p4+1);
332 enable = (70000 < clk) ? "X" : "";
333 dev_dbg(&client->dev, "Sensor CLK : %10u K %s\n", clk, enable);
334
335 clk = vco / (p7+1);
336 dev_dbg(&client->dev, "External sensor : %10u K\n", clk);
337
338 clk = ext / (n+1);
339 enable = ((2000 > clk) || (24000 < clk)) ? "X" : "";
340 dev_dbg(&client->dev, "PFD : %10u K %s\n", clk, enable);
341
342 return 0;
343 }
344 #endif
345
346 static void mt9t112_frame_check(u32 *width, u32 *height, u32 *left, u32 *top)
347 {
348 soc_camera_limit_side(left, width, 0, 0, MAX_WIDTH);
349 soc_camera_limit_side(top, height, 0, 0, MAX_HEIGHT);
350 }
351
352 static int mt9t112_set_a_frame_size(const struct i2c_client *client,
353 u16 width,
354 u16 height)
355 {
356 int ret;
357 u16 wstart = (MAX_WIDTH - width) / 2;
358 u16 hstart = (MAX_HEIGHT - height) / 2;
359
360 /* (Context A) Image Width/Height */
361 mt9t112_mcu_write(ret, client, VAR(26, 0), width);
362 mt9t112_mcu_write(ret, client, VAR(26, 2), height);
363
364 /* (Context A) Output Width/Height */
365 mt9t112_mcu_write(ret, client, VAR(18, 43), 8 + width);
366 mt9t112_mcu_write(ret, client, VAR(18, 45), 8 + height);
367
368 /* (Context A) Start Row/Column */
369 mt9t112_mcu_write(ret, client, VAR(18, 2), 4 + hstart);
370 mt9t112_mcu_write(ret, client, VAR(18, 4), 4 + wstart);
371
372 /* (Context A) End Row/Column */
373 mt9t112_mcu_write(ret, client, VAR(18, 6), 11 + height + hstart);
374 mt9t112_mcu_write(ret, client, VAR(18, 8), 11 + width + wstart);
375
376 mt9t112_mcu_write(ret, client, VAR8(1, 0), 0x06);
377
378 return ret;
379 }
380
381 static int mt9t112_set_pll_dividers(const struct i2c_client *client,
382 u8 m, u8 n,
383 u8 p1, u8 p2, u8 p3,
384 u8 p4, u8 p5, u8 p6,
385 u8 p7)
386 {
387 int ret;
388 u16 val;
389
390 /* N/M */
391 val = (n << 8) |
392 (m << 0);
393 mt9t112_reg_mask_set(ret, client, 0x0010, 0x3fff, val);
394
395 /* P1/P2/P3 */
396 val = ((p3 & 0x0F) << 8) |
397 ((p2 & 0x0F) << 4) |
398 ((p1 & 0x0F) << 0);
399 mt9t112_reg_mask_set(ret, client, 0x0012, 0x0fff, val);
400
401 /* P4/P5/P6 */
402 val = (0x7 << 12) |
403 ((p6 & 0x0F) << 8) |
404 ((p5 & 0x0F) << 4) |
405 ((p4 & 0x0F) << 0);
406 mt9t112_reg_mask_set(ret, client, 0x002A, 0x7fff, val);
407
408 /* P7 */
409 val = (0x1 << 12) |
410 ((p7 & 0x0F) << 0);
411 mt9t112_reg_mask_set(ret, client, 0x002C, 0x100f, val);
412
413 return ret;
414 }
415
416 static int mt9t112_init_pll(const struct i2c_client *client)
417 {
418 struct mt9t112_priv *priv = to_mt9t112(client);
419 int data, i, ret;
420
421 mt9t112_reg_mask_set(ret, client, 0x0014, 0x003, 0x0001);
422
423 /* PLL control: BYPASS PLL = 8517 */
424 mt9t112_reg_write(ret, client, 0x0014, 0x2145);
425
426 /* Replace these registers when new timing parameters are generated */
427 mt9t112_set_pll_dividers(client,
428 priv->info->divider.m,
429 priv->info->divider.n,
430 priv->info->divider.p1,
431 priv->info->divider.p2,
432 priv->info->divider.p3,
433 priv->info->divider.p4,
434 priv->info->divider.p5,
435 priv->info->divider.p6,
436 priv->info->divider.p7);
437
438 /*
439 * TEST_BYPASS on
440 * PLL_ENABLE on
441 * SEL_LOCK_DET on
442 * TEST_BYPASS off
443 */
444 mt9t112_reg_write(ret, client, 0x0014, 0x2525);
445 mt9t112_reg_write(ret, client, 0x0014, 0x2527);
446 mt9t112_reg_write(ret, client, 0x0014, 0x3427);
447 mt9t112_reg_write(ret, client, 0x0014, 0x3027);
448
449 mdelay(10);
450
451 /*
452 * PLL_BYPASS off
453 * Reference clock count
454 * I2C Master Clock Divider
455 */
456 mt9t112_reg_write(ret, client, 0x0014, 0x3046);
457 mt9t112_reg_write(ret, client, 0x0016, 0x0400); /* JPEG initialization workaround */
458 mt9t112_reg_write(ret, client, 0x0022, 0x0190);
459 mt9t112_reg_write(ret, client, 0x3B84, 0x0212);
460
461 /* External sensor clock is PLL bypass */
462 mt9t112_reg_write(ret, client, 0x002E, 0x0500);
463
464 mt9t112_reg_mask_set(ret, client, 0x0018, 0x0002, 0x0002);
465 mt9t112_reg_mask_set(ret, client, 0x3B82, 0x0004, 0x0004);
466
467 /* MCU disabled */
468 mt9t112_reg_mask_set(ret, client, 0x0018, 0x0004, 0x0004);
469
470 /* out of standby */
471 mt9t112_reg_mask_set(ret, client, 0x0018, 0x0001, 0);
472
473 mdelay(50);
474
475 /*
476 * Standby Workaround
477 * Disable Secondary I2C Pads
478 */
479 mt9t112_reg_write(ret, client, 0x0614, 0x0001);
480 mdelay(1);
481 mt9t112_reg_write(ret, client, 0x0614, 0x0001);
482 mdelay(1);
483 mt9t112_reg_write(ret, client, 0x0614, 0x0001);
484 mdelay(1);
485 mt9t112_reg_write(ret, client, 0x0614, 0x0001);
486 mdelay(1);
487 mt9t112_reg_write(ret, client, 0x0614, 0x0001);
488 mdelay(1);
489 mt9t112_reg_write(ret, client, 0x0614, 0x0001);
490 mdelay(1);
491
492 /* poll to verify out of standby. Must Poll this bit */
493 for (i = 0; i < 100; i++) {
494 mt9t112_reg_read(data, client, 0x0018);
495 if (!(0x4000 & data))
496 break;
497
498 mdelay(10);
499 }
500
501 return ret;
502 }
503
504 static int mt9t112_init_setting(const struct i2c_client *client)
505 {
506
507 int ret;
508
509 /* Adaptive Output Clock (A) */
510 mt9t112_mcu_mask_set(ret, client, VAR(26, 160), 0x0040, 0x0000);
511
512 /* Read Mode (A) */
513 mt9t112_mcu_write(ret, client, VAR(18, 12), 0x0024);
514
515 /* Fine Correction (A) */
516 mt9t112_mcu_write(ret, client, VAR(18, 15), 0x00CC);
517
518 /* Fine IT Min (A) */
519 mt9t112_mcu_write(ret, client, VAR(18, 17), 0x01f1);
520
521 /* Fine IT Max Margin (A) */
522 mt9t112_mcu_write(ret, client, VAR(18, 19), 0x00fF);
523
524 /* Base Frame Lines (A) */
525 mt9t112_mcu_write(ret, client, VAR(18, 29), 0x032D);
526
527 /* Min Line Length (A) */
528 mt9t112_mcu_write(ret, client, VAR(18, 31), 0x073a);
529
530 /* Line Length (A) */
531 mt9t112_mcu_write(ret, client, VAR(18, 37), 0x07d0);
532
533 /* Adaptive Output Clock (B) */
534 mt9t112_mcu_mask_set(ret, client, VAR(27, 160), 0x0040, 0x0000);
535
536 /* Row Start (B) */
537 mt9t112_mcu_write(ret, client, VAR(18, 74), 0x004);
538
539 /* Column Start (B) */
540 mt9t112_mcu_write(ret, client, VAR(18, 76), 0x004);
541
542 /* Row End (B) */
543 mt9t112_mcu_write(ret, client, VAR(18, 78), 0x60B);
544
545 /* Column End (B) */
546 mt9t112_mcu_write(ret, client, VAR(18, 80), 0x80B);
547
548 /* Fine Correction (B) */
549 mt9t112_mcu_write(ret, client, VAR(18, 87), 0x008C);
550
551 /* Fine IT Min (B) */
552 mt9t112_mcu_write(ret, client, VAR(18, 89), 0x01F1);
553
554 /* Fine IT Max Margin (B) */
555 mt9t112_mcu_write(ret, client, VAR(18, 91), 0x00FF);
556
557 /* Base Frame Lines (B) */
558 mt9t112_mcu_write(ret, client, VAR(18, 101), 0x0668);
559
560 /* Min Line Length (B) */
561 mt9t112_mcu_write(ret, client, VAR(18, 103), 0x0AF0);
562
563 /* Line Length (B) */
564 mt9t112_mcu_write(ret, client, VAR(18, 109), 0x0AF0);
565
566 /*
567 * Flicker Dectection registers
568 * This section should be replaced whenever new Timing file is generated
569 * All the following registers need to be replaced
570 * Following registers are generated from Register Wizard but user can
571 * modify them. For detail see auto flicker detection tuning
572 */
573
574 /* FD_FDPERIOD_SELECT */
575 mt9t112_mcu_write(ret, client, VAR8(8, 5), 0x01);
576
577 /* PRI_B_CONFIG_FD_ALGO_RUN */
578 mt9t112_mcu_write(ret, client, VAR(27, 17), 0x0003);
579
580 /* PRI_A_CONFIG_FD_ALGO_RUN */
581 mt9t112_mcu_write(ret, client, VAR(26, 17), 0x0003);
582
583 /*
584 * AFD range detection tuning registers
585 */
586
587 /* search_f1_50 */
588 mt9t112_mcu_write(ret, client, VAR8(18, 165), 0x25);
589
590 /* search_f2_50 */
591 mt9t112_mcu_write(ret, client, VAR8(18, 166), 0x28);
592
593 /* search_f1_60 */
594 mt9t112_mcu_write(ret, client, VAR8(18, 167), 0x2C);
595
596 /* search_f2_60 */
597 mt9t112_mcu_write(ret, client, VAR8(18, 168), 0x2F);
598
599 /* period_50Hz (A) */
600 mt9t112_mcu_write(ret, client, VAR8(18, 68), 0xBA);
601
602 /* secret register by aptina */
603 /* period_50Hz (A MSB) */
604 mt9t112_mcu_write(ret, client, VAR8(18, 303), 0x00);
605
606 /* period_60Hz (A) */
607 mt9t112_mcu_write(ret, client, VAR8(18, 69), 0x9B);
608
609 /* secret register by aptina */
610 /* period_60Hz (A MSB) */
611 mt9t112_mcu_write(ret, client, VAR8(18, 301), 0x00);
612
613 /* period_50Hz (B) */
614 mt9t112_mcu_write(ret, client, VAR8(18, 140), 0x82);
615
616 /* secret register by aptina */
617 /* period_50Hz (B) MSB */
618 mt9t112_mcu_write(ret, client, VAR8(18, 304), 0x00);
619
620 /* period_60Hz (B) */
621 mt9t112_mcu_write(ret, client, VAR8(18, 141), 0x6D);
622
623 /* secret register by aptina */
624 /* period_60Hz (B) MSB */
625 mt9t112_mcu_write(ret, client, VAR8(18, 302), 0x00);
626
627 /* FD Mode */
628 mt9t112_mcu_write(ret, client, VAR8(8, 2), 0x10);
629
630 /* Stat_min */
631 mt9t112_mcu_write(ret, client, VAR8(8, 9), 0x02);
632
633 /* Stat_max */
634 mt9t112_mcu_write(ret, client, VAR8(8, 10), 0x03);
635
636 /* Min_amplitude */
637 mt9t112_mcu_write(ret, client, VAR8(8, 12), 0x0A);
638
639 /* RX FIFO Watermark (A) */
640 mt9t112_mcu_write(ret, client, VAR(18, 70), 0x0014);
641
642 /* RX FIFO Watermark (B) */
643 mt9t112_mcu_write(ret, client, VAR(18, 142), 0x0014);
644
645 /* MCLK: 16MHz
646 * PCLK: 73MHz
647 * CorePixCLK: 36.5 MHz
648 */
649 mt9t112_mcu_write(ret, client, VAR8(18, 0x0044), 133);
650 mt9t112_mcu_write(ret, client, VAR8(18, 0x0045), 110);
651 mt9t112_mcu_write(ret, client, VAR8(18, 0x008c), 130);
652 mt9t112_mcu_write(ret, client, VAR8(18, 0x008d), 108);
653
654 mt9t112_mcu_write(ret, client, VAR8(18, 0x00A5), 27);
655 mt9t112_mcu_write(ret, client, VAR8(18, 0x00a6), 30);
656 mt9t112_mcu_write(ret, client, VAR8(18, 0x00a7), 32);
657 mt9t112_mcu_write(ret, client, VAR8(18, 0x00a8), 35);
658
659 return ret;
660 }
661
662 static int mt9t112_auto_focus_setting(const struct i2c_client *client)
663 {
664 int ret;
665
666 mt9t112_mcu_write(ret, client, VAR(12, 13), 0x000F);
667 mt9t112_mcu_write(ret, client, VAR(12, 23), 0x0F0F);
668 mt9t112_mcu_write(ret, client, VAR8(1, 0), 0x06);
669
670 mt9t112_reg_write(ret, client, 0x0614, 0x0000);
671
672 mt9t112_mcu_write(ret, client, VAR8(1, 0), 0x05);
673 mt9t112_mcu_write(ret, client, VAR8(12, 2), 0x02);
674 mt9t112_mcu_write(ret, client, VAR(12, 3), 0x0002);
675 mt9t112_mcu_write(ret, client, VAR(17, 3), 0x8001);
676 mt9t112_mcu_write(ret, client, VAR(17, 11), 0x0025);
677 mt9t112_mcu_write(ret, client, VAR(17, 13), 0x0193);
678 mt9t112_mcu_write(ret, client, VAR8(17, 33), 0x18);
679 mt9t112_mcu_write(ret, client, VAR8(1, 0), 0x05);
680
681 return ret;
682 }
683
684 static int mt9t112_auto_focus_trigger(const struct i2c_client *client)
685 {
686 int ret;
687
688 mt9t112_mcu_write(ret, client, VAR8(12, 25), 0x01);
689
690 return ret;
691 }
692
693 static int mt9t112_init_camera(const struct i2c_client *client)
694 {
695 int ret;
696
697 ECHECKER(ret, mt9t112_reset(client));
698
699 ECHECKER(ret, mt9t112_init_pll(client));
700
701 ECHECKER(ret, mt9t112_init_setting(client));
702
703 ECHECKER(ret, mt9t112_auto_focus_setting(client));
704
705 mt9t112_reg_mask_set(ret, client, 0x0018, 0x0004, 0);
706
707 /* Analog setting B */
708 mt9t112_reg_write(ret, client, 0x3084, 0x2409);
709 mt9t112_reg_write(ret, client, 0x3092, 0x0A49);
710 mt9t112_reg_write(ret, client, 0x3094, 0x4949);
711 mt9t112_reg_write(ret, client, 0x3096, 0x4950);
712
713 /*
714 * Disable adaptive clock
715 * PRI_A_CONFIG_JPEG_OB_TX_CONTROL_VAR
716 * PRI_B_CONFIG_JPEG_OB_TX_CONTROL_VAR
717 */
718 mt9t112_mcu_write(ret, client, VAR(26, 160), 0x0A2E);
719 mt9t112_mcu_write(ret, client, VAR(27, 160), 0x0A2E);
720
721 /* Configure STatus in Status_before_length Format and enable header */
722 /* PRI_B_CONFIG_JPEG_OB_TX_CONTROL_VAR */
723 mt9t112_mcu_write(ret, client, VAR(27, 144), 0x0CB4);
724
725 /* Enable JPEG in context B */
726 /* PRI_B_CONFIG_JPEG_OB_TX_CONTROL_VAR */
727 mt9t112_mcu_write(ret, client, VAR8(27, 142), 0x01);
728
729 /* Disable Dac_TXLO */
730 mt9t112_reg_write(ret, client, 0x316C, 0x350F);
731
732 /* Set max slew rates */
733 mt9t112_reg_write(ret, client, 0x1E, 0x777);
734
735 return ret;
736 }
737
738 /************************************************************************
739 v4l2_subdev_core_ops
740 ************************************************************************/
741
742 #ifdef CONFIG_VIDEO_ADV_DEBUG
743 static int mt9t112_g_register(struct v4l2_subdev *sd,
744 struct v4l2_dbg_register *reg)
745 {
746 struct i2c_client *client = v4l2_get_subdevdata(sd);
747 int ret;
748
749 reg->size = 2;
750 mt9t112_reg_read(ret, client, reg->reg);
751
752 reg->val = (__u64)ret;
753
754 return 0;
755 }
756
757 static int mt9t112_s_register(struct v4l2_subdev *sd,
758 const struct v4l2_dbg_register *reg)
759 {
760 struct i2c_client *client = v4l2_get_subdevdata(sd);
761 int ret;
762
763 mt9t112_reg_write(ret, client, reg->reg, reg->val);
764
765 return ret;
766 }
767 #endif
768
769 static int mt9t112_s_power(struct v4l2_subdev *sd, int on)
770 {
771 struct i2c_client *client = v4l2_get_subdevdata(sd);
772 struct soc_camera_subdev_desc *ssdd = soc_camera_i2c_to_desc(client);
773 struct mt9t112_priv *priv = to_mt9t112(client);
774
775 return soc_camera_set_power(&client->dev, ssdd, priv->clk, on);
776 }
777
778 static struct v4l2_subdev_core_ops mt9t112_subdev_core_ops = {
779 #ifdef CONFIG_VIDEO_ADV_DEBUG
780 .g_register = mt9t112_g_register,
781 .s_register = mt9t112_s_register,
782 #endif
783 .s_power = mt9t112_s_power,
784 };
785
786
787 /************************************************************************
788 v4l2_subdev_video_ops
789 ************************************************************************/
790 static int mt9t112_s_stream(struct v4l2_subdev *sd, int enable)
791 {
792 struct i2c_client *client = v4l2_get_subdevdata(sd);
793 struct mt9t112_priv *priv = to_mt9t112(client);
794 int ret = 0;
795
796 if (!enable) {
797 /* FIXME
798 *
799 * If user selected large output size,
800 * and used it long time,
801 * mt9t112 camera will be very warm.
802 *
803 * But current driver can not stop mt9t112 camera.
804 * So, set small size here to solve this problem.
805 */
806 mt9t112_set_a_frame_size(client, VGA_WIDTH, VGA_HEIGHT);
807 return ret;
808 }
809
810 if (!(priv->flags & INIT_DONE)) {
811 u16 param = PCLK_RISING & priv->flags ? 0x0001 : 0x0000;
812
813 ECHECKER(ret, mt9t112_init_camera(client));
814
815 /* Invert PCLK (Data sampled on falling edge of pixclk) */
816 mt9t112_reg_write(ret, client, 0x3C20, param);
817
818 mdelay(5);
819
820 priv->flags |= INIT_DONE;
821 }
822
823 mt9t112_mcu_write(ret, client, VAR(26, 7), priv->format->fmt);
824 mt9t112_mcu_write(ret, client, VAR(26, 9), priv->format->order);
825 mt9t112_mcu_write(ret, client, VAR8(1, 0), 0x06);
826
827 mt9t112_set_a_frame_size(client,
828 priv->frame.width,
829 priv->frame.height);
830
831 ECHECKER(ret, mt9t112_auto_focus_trigger(client));
832
833 dev_dbg(&client->dev, "format : %d\n", priv->format->code);
834 dev_dbg(&client->dev, "size : %d x %d\n",
835 priv->frame.width,
836 priv->frame.height);
837
838 CLOCK_INFO(client, EXT_CLOCK);
839
840 return ret;
841 }
842
843 static int mt9t112_set_params(struct mt9t112_priv *priv,
844 const struct v4l2_rect *rect,
845 enum v4l2_mbus_pixelcode code)
846 {
847 int i;
848
849 /*
850 * get color format
851 */
852 for (i = 0; i < priv->num_formats; i++)
853 if (mt9t112_cfmts[i].code == code)
854 break;
855
856 if (i == priv->num_formats)
857 return -EINVAL;
858
859 priv->frame = *rect;
860
861 /*
862 * frame size check
863 */
864 mt9t112_frame_check(&priv->frame.width, &priv->frame.height,
865 &priv->frame.left, &priv->frame.top);
866
867 priv->format = mt9t112_cfmts + i;
868
869 return 0;
870 }
871
872 static int mt9t112_cropcap(struct v4l2_subdev *sd, struct v4l2_cropcap *a)
873 {
874 a->bounds.left = 0;
875 a->bounds.top = 0;
876 a->bounds.width = MAX_WIDTH;
877 a->bounds.height = MAX_HEIGHT;
878 a->defrect.left = 0;
879 a->defrect.top = 0;
880 a->defrect.width = VGA_WIDTH;
881 a->defrect.height = VGA_HEIGHT;
882 a->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
883 a->pixelaspect.numerator = 1;
884 a->pixelaspect.denominator = 1;
885
886 return 0;
887 }
888
889 static int mt9t112_g_crop(struct v4l2_subdev *sd, struct v4l2_crop *a)
890 {
891 struct i2c_client *client = v4l2_get_subdevdata(sd);
892 struct mt9t112_priv *priv = to_mt9t112(client);
893
894 a->c = priv->frame;
895 a->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
896
897 return 0;
898 }
899
900 static int mt9t112_s_crop(struct v4l2_subdev *sd, const struct v4l2_crop *a)
901 {
902 struct i2c_client *client = v4l2_get_subdevdata(sd);
903 struct mt9t112_priv *priv = to_mt9t112(client);
904 const struct v4l2_rect *rect = &a->c;
905
906 return mt9t112_set_params(priv, rect, priv->format->code);
907 }
908
909 static int mt9t112_g_fmt(struct v4l2_subdev *sd,
910 struct v4l2_mbus_framefmt *mf)
911 {
912 struct i2c_client *client = v4l2_get_subdevdata(sd);
913 struct mt9t112_priv *priv = to_mt9t112(client);
914
915 mf->width = priv->frame.width;
916 mf->height = priv->frame.height;
917 mf->colorspace = priv->format->colorspace;
918 mf->code = priv->format->code;
919 mf->field = V4L2_FIELD_NONE;
920
921 return 0;
922 }
923
924 static int mt9t112_s_fmt(struct v4l2_subdev *sd,
925 struct v4l2_mbus_framefmt *mf)
926 {
927 struct i2c_client *client = v4l2_get_subdevdata(sd);
928 struct mt9t112_priv *priv = to_mt9t112(client);
929 struct v4l2_rect rect = {
930 .width = mf->width,
931 .height = mf->height,
932 .left = priv->frame.left,
933 .top = priv->frame.top,
934 };
935 int ret;
936
937 ret = mt9t112_set_params(priv, &rect, mf->code);
938
939 if (!ret)
940 mf->colorspace = priv->format->colorspace;
941
942 return ret;
943 }
944
945 static int mt9t112_try_fmt(struct v4l2_subdev *sd,
946 struct v4l2_mbus_framefmt *mf)
947 {
948 struct i2c_client *client = v4l2_get_subdevdata(sd);
949 struct mt9t112_priv *priv = to_mt9t112(client);
950 unsigned int top, left;
951 int i;
952
953 for (i = 0; i < priv->num_formats; i++)
954 if (mt9t112_cfmts[i].code == mf->code)
955 break;
956
957 if (i == priv->num_formats) {
958 mf->code = V4L2_MBUS_FMT_UYVY8_2X8;
959 mf->colorspace = V4L2_COLORSPACE_JPEG;
960 } else {
961 mf->colorspace = mt9t112_cfmts[i].colorspace;
962 }
963
964 mt9t112_frame_check(&mf->width, &mf->height, &left, &top);
965
966 mf->field = V4L2_FIELD_NONE;
967
968 return 0;
969 }
970
971 static int mt9t112_enum_fmt(struct v4l2_subdev *sd, unsigned int index,
972 enum v4l2_mbus_pixelcode *code)
973 {
974 struct i2c_client *client = v4l2_get_subdevdata(sd);
975 struct mt9t112_priv *priv = to_mt9t112(client);
976
977 if (index >= priv->num_formats)
978 return -EINVAL;
979
980 *code = mt9t112_cfmts[index].code;
981
982 return 0;
983 }
984
985 static int mt9t112_g_mbus_config(struct v4l2_subdev *sd,
986 struct v4l2_mbus_config *cfg)
987 {
988 struct i2c_client *client = v4l2_get_subdevdata(sd);
989 struct soc_camera_subdev_desc *ssdd = soc_camera_i2c_to_desc(client);
990
991 cfg->flags = V4L2_MBUS_MASTER | V4L2_MBUS_VSYNC_ACTIVE_HIGH |
992 V4L2_MBUS_HSYNC_ACTIVE_HIGH | V4L2_MBUS_DATA_ACTIVE_HIGH |
993 V4L2_MBUS_PCLK_SAMPLE_RISING | V4L2_MBUS_PCLK_SAMPLE_FALLING;
994 cfg->type = V4L2_MBUS_PARALLEL;
995 cfg->flags = soc_camera_apply_board_flags(ssdd, cfg);
996
997 return 0;
998 }
999
1000 static int mt9t112_s_mbus_config(struct v4l2_subdev *sd,
1001 const struct v4l2_mbus_config *cfg)
1002 {
1003 struct i2c_client *client = v4l2_get_subdevdata(sd);
1004 struct soc_camera_subdev_desc *ssdd = soc_camera_i2c_to_desc(client);
1005 struct mt9t112_priv *priv = to_mt9t112(client);
1006
1007 if (soc_camera_apply_board_flags(ssdd, cfg) & V4L2_MBUS_PCLK_SAMPLE_RISING)
1008 priv->flags |= PCLK_RISING;
1009
1010 return 0;
1011 }
1012
1013 static struct v4l2_subdev_video_ops mt9t112_subdev_video_ops = {
1014 .s_stream = mt9t112_s_stream,
1015 .g_mbus_fmt = mt9t112_g_fmt,
1016 .s_mbus_fmt = mt9t112_s_fmt,
1017 .try_mbus_fmt = mt9t112_try_fmt,
1018 .cropcap = mt9t112_cropcap,
1019 .g_crop = mt9t112_g_crop,
1020 .s_crop = mt9t112_s_crop,
1021 .enum_mbus_fmt = mt9t112_enum_fmt,
1022 .g_mbus_config = mt9t112_g_mbus_config,
1023 .s_mbus_config = mt9t112_s_mbus_config,
1024 };
1025
1026 /************************************************************************
1027 i2c driver
1028 ************************************************************************/
1029 static struct v4l2_subdev_ops mt9t112_subdev_ops = {
1030 .core = &mt9t112_subdev_core_ops,
1031 .video = &mt9t112_subdev_video_ops,
1032 };
1033
1034 static int mt9t112_camera_probe(struct i2c_client *client)
1035 {
1036 struct mt9t112_priv *priv = to_mt9t112(client);
1037 const char *devname;
1038 int chipid;
1039 int ret;
1040
1041 ret = mt9t112_s_power(&priv->subdev, 1);
1042 if (ret < 0)
1043 return ret;
1044
1045 /*
1046 * check and show chip ID
1047 */
1048 mt9t112_reg_read(chipid, client, 0x0000);
1049
1050 switch (chipid) {
1051 case 0x2680:
1052 devname = "mt9t111";
1053 priv->num_formats = 1;
1054 break;
1055 case 0x2682:
1056 devname = "mt9t112";
1057 priv->num_formats = ARRAY_SIZE(mt9t112_cfmts);
1058 break;
1059 default:
1060 dev_err(&client->dev, "Product ID error %04x\n", chipid);
1061 ret = -ENODEV;
1062 goto done;
1063 }
1064
1065 dev_info(&client->dev, "%s chip ID %04x\n", devname, chipid);
1066
1067 done:
1068 mt9t112_s_power(&priv->subdev, 0);
1069 return ret;
1070 }
1071
1072 static int mt9t112_probe(struct i2c_client *client,
1073 const struct i2c_device_id *did)
1074 {
1075 struct mt9t112_priv *priv;
1076 struct soc_camera_subdev_desc *ssdd = soc_camera_i2c_to_desc(client);
1077 struct v4l2_rect rect = {
1078 .width = VGA_WIDTH,
1079 .height = VGA_HEIGHT,
1080 .left = (MAX_WIDTH - VGA_WIDTH) / 2,
1081 .top = (MAX_HEIGHT - VGA_HEIGHT) / 2,
1082 };
1083 int ret;
1084
1085 if (!ssdd || !ssdd->drv_priv) {
1086 dev_err(&client->dev, "mt9t112: missing platform data!\n");
1087 return -EINVAL;
1088 }
1089
1090 priv = devm_kzalloc(&client->dev, sizeof(*priv), GFP_KERNEL);
1091 if (!priv)
1092 return -ENOMEM;
1093
1094 priv->info = ssdd->drv_priv;
1095
1096 v4l2_i2c_subdev_init(&priv->subdev, client, &mt9t112_subdev_ops);
1097
1098 priv->clk = v4l2_clk_get(&client->dev, "mclk");
1099 if (IS_ERR(priv->clk))
1100 return PTR_ERR(priv->clk);
1101
1102 ret = mt9t112_camera_probe(client);
1103
1104 /* Cannot fail: using the default supported pixel code */
1105 if (!ret)
1106 mt9t112_set_params(priv, &rect, V4L2_MBUS_FMT_UYVY8_2X8);
1107 else
1108 v4l2_clk_put(priv->clk);
1109
1110 return ret;
1111 }
1112
1113 static int mt9t112_remove(struct i2c_client *client)
1114 {
1115 struct mt9t112_priv *priv = to_mt9t112(client);
1116
1117 v4l2_clk_put(priv->clk);
1118 return 0;
1119 }
1120
1121 static const struct i2c_device_id mt9t112_id[] = {
1122 { "mt9t112", 0 },
1123 { }
1124 };
1125 MODULE_DEVICE_TABLE(i2c, mt9t112_id);
1126
1127 static struct i2c_driver mt9t112_i2c_driver = {
1128 .driver = {
1129 .name = "mt9t112",
1130 },
1131 .probe = mt9t112_probe,
1132 .remove = mt9t112_remove,
1133 .id_table = mt9t112_id,
1134 };
1135
1136 module_i2c_driver(mt9t112_i2c_driver);
1137
1138 MODULE_DESCRIPTION("SoC Camera driver for mt9t112");
1139 MODULE_AUTHOR("Kuninori Morimoto");
1140 MODULE_LICENSE("GPL v2");
Linux with added FPC-III support