?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
net: qmi_wwan: add Olivetti Olicard 500
[linux/fpc-iii.git] / drivers / media / i2c / soc_camera / tw9910.c
blobab54628d9411a0f97fe75884ff176f2dfa164253
1 /*
2 * tw9910 Video Driver
3 *
4 * Copyright (C) 2008 Renesas Solutions Corp.
5 * Kuninori Morimoto <morimoto.kuninori@renesas.com>
6 *
7 * Based on ov772x driver,
8 *
9 * Copyright (C) 2008 Kuninori Morimoto <morimoto.kuninori@renesas.com>
10 * Copyright 2006-7 Jonathan Corbet <corbet@lwn.net>
11 * Copyright (C) 2008 Magnus Damm
12 * Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de>
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License version 2 as
16 * published by the Free Software Foundation.
17 */
18
19 #include <linux/init.h>
20 #include <linux/module.h>
21 #include <linux/i2c.h>
22 #include <linux/slab.h>
23 #include <linux/kernel.h>
24 #include <linux/delay.h>
25 #include <linux/v4l2-mediabus.h>
26 #include <linux/videodev2.h>
27
28 #include <media/soc_camera.h>
29 #include <media/tw9910.h>
30 #include <media/v4l2-clk.h>
31 #include <media/v4l2-subdev.h>
32
33 #define GET_ID(val) ((val & 0xF8) >> 3)
34 #define GET_REV(val) (val & 0x07)
35
36 /*
37 * register offset
38 */
39 #define ID 0x00 /* Product ID Code Register */
40 #define STATUS1 0x01 /* Chip Status Register I */
41 #define INFORM 0x02 /* Input Format */
42 #define OPFORM 0x03 /* Output Format Control Register */
43 #define DLYCTR 0x04 /* Hysteresis and HSYNC Delay Control */
44 #define OUTCTR1 0x05 /* Output Control I */
45 #define ACNTL1 0x06 /* Analog Control Register 1 */
46 #define CROP_HI 0x07 /* Cropping Register, High */
47 #define VDELAY_LO 0x08 /* Vertical Delay Register, Low */
48 #define VACTIVE_LO 0x09 /* Vertical Active Register, Low */
49 #define HDELAY_LO 0x0A /* Horizontal Delay Register, Low */
50 #define HACTIVE_LO 0x0B /* Horizontal Active Register, Low */
51 #define CNTRL1 0x0C /* Control Register I */
52 #define VSCALE_LO 0x0D /* Vertical Scaling Register, Low */
53 #define SCALE_HI 0x0E /* Scaling Register, High */
54 #define HSCALE_LO 0x0F /* Horizontal Scaling Register, Low */
55 #define BRIGHT 0x10 /* BRIGHTNESS Control Register */
56 #define CONTRAST 0x11 /* CONTRAST Control Register */
57 #define SHARPNESS 0x12 /* SHARPNESS Control Register I */
58 #define SAT_U 0x13 /* Chroma (U) Gain Register */
59 #define SAT_V 0x14 /* Chroma (V) Gain Register */
60 #define HUE 0x15 /* Hue Control Register */
61 #define CORING1 0x17
62 #define CORING2 0x18 /* Coring and IF compensation */
63 #define VBICNTL 0x19 /* VBI Control Register */
64 #define ACNTL2 0x1A /* Analog Control 2 */
65 #define OUTCTR2 0x1B /* Output Control 2 */
66 #define SDT 0x1C /* Standard Selection */
67 #define SDTR 0x1D /* Standard Recognition */
68 #define TEST 0x1F /* Test Control Register */
69 #define CLMPG 0x20 /* Clamping Gain */
70 #define IAGC 0x21 /* Individual AGC Gain */
71 #define AGCGAIN 0x22 /* AGC Gain */
72 #define PEAKWT 0x23 /* White Peak Threshold */
73 #define CLMPL 0x24 /* Clamp level */
74 #define SYNCT 0x25 /* Sync Amplitude */
75 #define MISSCNT 0x26 /* Sync Miss Count Register */
76 #define PCLAMP 0x27 /* Clamp Position Register */
77 #define VCNTL1 0x28 /* Vertical Control I */
78 #define VCNTL2 0x29 /* Vertical Control II */
79 #define CKILL 0x2A /* Color Killer Level Control */
80 #define COMB 0x2B /* Comb Filter Control */
81 #define LDLY 0x2C /* Luma Delay and H Filter Control */
82 #define MISC1 0x2D /* Miscellaneous Control I */
83 #define LOOP 0x2E /* LOOP Control Register */
84 #define MISC2 0x2F /* Miscellaneous Control II */
85 #define MVSN 0x30 /* Macrovision Detection */
86 #define STATUS2 0x31 /* Chip STATUS II */
87 #define HFREF 0x32 /* H monitor */
88 #define CLMD 0x33 /* CLAMP MODE */
89 #define IDCNTL 0x34 /* ID Detection Control */
90 #define CLCNTL1 0x35 /* Clamp Control I */
91 #define ANAPLLCTL 0x4C
92 #define VBIMIN 0x4D
93 #define HSLOWCTL 0x4E
94 #define WSS3 0x4F
95 #define FILLDATA 0x50
96 #define SDID 0x51
97 #define DID 0x52
98 #define WSS1 0x53
99 #define WSS2 0x54
100 #define VVBI 0x55
101 #define LCTL6 0x56
102 #define LCTL7 0x57
103 #define LCTL8 0x58
104 #define LCTL9 0x59
105 #define LCTL10 0x5A
106 #define LCTL11 0x5B
107 #define LCTL12 0x5C
108 #define LCTL13 0x5D
109 #define LCTL14 0x5E
110 #define LCTL15 0x5F
111 #define LCTL16 0x60
112 #define LCTL17 0x61
113 #define LCTL18 0x62
114 #define LCTL19 0x63
115 #define LCTL20 0x64
116 #define LCTL21 0x65
117 #define LCTL22 0x66
118 #define LCTL23 0x67
119 #define LCTL24 0x68
120 #define LCTL25 0x69
121 #define LCTL26 0x6A
122 #define HSBEGIN 0x6B
123 #define HSEND 0x6C
124 #define OVSDLY 0x6D
125 #define OVSEND 0x6E
126 #define VBIDELAY 0x6F
127
128 /*
129 * register detail
130 */
131
132 /* INFORM */
133 #define FC27_ON 0x40 /* 1 : Input crystal clock frequency is 27MHz */
134 #define FC27_FF 0x00 /* 0 : Square pixel mode. */
135 /* Must use 24.54MHz for 60Hz field rate */
136 /* source or 29.5MHz for 50Hz field rate */
137 #define IFSEL_S 0x10 /* 01 : S-video decoding */
138 #define IFSEL_C 0x00 /* 00 : Composite video decoding */
139 /* Y input video selection */
140 #define YSEL_M0 0x00 /* 00 : Mux0 selected */
141 #define YSEL_M1 0x04 /* 01 : Mux1 selected */
142 #define YSEL_M2 0x08 /* 10 : Mux2 selected */
143 #define YSEL_M3 0x10 /* 11 : Mux3 selected */
144
145 /* OPFORM */
146 #define MODE 0x80 /* 0 : CCIR601 compatible YCrCb 4:2:2 format */
147 /* 1 : ITU-R-656 compatible data sequence format */
148 #define LEN 0x40 /* 0 : 8-bit YCrCb 4:2:2 output format */
149 /* 1 : 16-bit YCrCb 4:2:2 output format.*/
150 #define LLCMODE 0x20 /* 1 : LLC output mode. */
151 /* 0 : free-run output mode */
152 #define AINC 0x10 /* Serial interface auto-indexing control */
153 /* 0 : auto-increment */
154 /* 1 : non-auto */
155 #define VSCTL 0x08 /* 1 : Vertical out ctrl by DVALID */
156 /* 0 : Vertical out ctrl by HACTIVE and DVALID */
157 #define OEN_TRI_SEL_MASK 0x07
158 #define OEN_TRI_SEL_ALL_ON 0x00 /* Enable output for Rev0/Rev1 */
159 #define OEN_TRI_SEL_ALL_OFF_r0 0x06 /* All tri-stated for Rev0 */
160 #define OEN_TRI_SEL_ALL_OFF_r1 0x07 /* All tri-stated for Rev1 */
161
162 /* OUTCTR1 */
163 #define VSP_LO 0x00 /* 0 : VS pin output polarity is active low */
164 #define VSP_HI 0x80 /* 1 : VS pin output polarity is active high. */
165 /* VS pin output control */
166 #define VSSL_VSYNC 0x00 /* 0 : VSYNC */
167 #define VSSL_VACT 0x10 /* 1 : VACT */
168 #define VSSL_FIELD 0x20 /* 2 : FIELD */
169 #define VSSL_VVALID 0x30 /* 3 : VVALID */
170 #define VSSL_ZERO 0x70 /* 7 : 0 */
171 #define HSP_LOW 0x00 /* 0 : HS pin output polarity is active low */
172 #define HSP_HI 0x08 /* 1 : HS pin output polarity is active high.*/
173 /* HS pin output control */
174 #define HSSL_HACT 0x00 /* 0 : HACT */
175 #define HSSL_HSYNC 0x01 /* 1 : HSYNC */
176 #define HSSL_DVALID 0x02 /* 2 : DVALID */
177 #define HSSL_HLOCK 0x03 /* 3 : HLOCK */
178 #define HSSL_ASYNCW 0x04 /* 4 : ASYNCW */
179 #define HSSL_ZERO 0x07 /* 7 : 0 */
180
181 /* ACNTL1 */
182 #define SRESET 0x80 /* resets the device to its default state
183 * but all register content remain unchanged.
184 * This bit is self-resetting.
185 */
186 #define ACNTL1_PDN_MASK 0x0e
187 #define CLK_PDN 0x08 /* system clock power down */
188 #define Y_PDN 0x04 /* Luma ADC power down */
189 #define C_PDN 0x02 /* Chroma ADC power down */
190
191 /* ACNTL2 */
192 #define ACNTL2_PDN_MASK 0x40
193 #define PLL_PDN 0x40 /* PLL power down */
194
195 /* VBICNTL */
196
197 /* RTSEL : control the real time signal output from the MPOUT pin */
198 #define RTSEL_MASK 0x07
199 #define RTSEL_VLOSS 0x00 /* 0000 = Video loss */
200 #define RTSEL_HLOCK 0x01 /* 0001 = H-lock */
201 #define RTSEL_SLOCK 0x02 /* 0010 = S-lock */
202 #define RTSEL_VLOCK 0x03 /* 0011 = V-lock */
203 #define RTSEL_MONO 0x04 /* 0100 = MONO */
204 #define RTSEL_DET50 0x05 /* 0101 = DET50 */
205 #define RTSEL_FIELD 0x06 /* 0110 = FIELD */
206 #define RTSEL_RTCO 0x07 /* 0111 = RTCO ( Real Time Control ) */
207
208 /* HSYNC start and end are constant for now */
209 #define HSYNC_START 0x0260
210 #define HSYNC_END 0x0300
211
212 /*
213 * structure
214 */
215
216 struct regval_list {
217 unsigned char reg_num;
218 unsigned char value;
219 };
220
221 struct tw9910_scale_ctrl {
222 char *name;
223 unsigned short width;
224 unsigned short height;
225 u16 hscale;
226 u16 vscale;
227 };
228
229 struct tw9910_priv {
230 struct v4l2_subdev subdev;
231 struct v4l2_clk *clk;
232 struct tw9910_video_info *info;
233 const struct tw9910_scale_ctrl *scale;
234 v4l2_std_id norm;
235 u32 revision;
236 };
237
238 static const struct tw9910_scale_ctrl tw9910_ntsc_scales[] = {
239 {
240 .name = "NTSC SQ",
241 .width = 640,
242 .height = 480,
243 .hscale = 0x0100,
244 .vscale = 0x0100,
245 },
246 {
247 .name = "NTSC CCIR601",
248 .width = 720,
249 .height = 480,
250 .hscale = 0x0100,
251 .vscale = 0x0100,
252 },
253 {
254 .name = "NTSC SQ (CIF)",
255 .width = 320,
256 .height = 240,
257 .hscale = 0x0200,
258 .vscale = 0x0200,
259 },
260 {
261 .name = "NTSC CCIR601 (CIF)",
262 .width = 360,
263 .height = 240,
264 .hscale = 0x0200,
265 .vscale = 0x0200,
266 },
267 {
268 .name = "NTSC SQ (QCIF)",
269 .width = 160,
270 .height = 120,
271 .hscale = 0x0400,
272 .vscale = 0x0400,
273 },
274 {
275 .name = "NTSC CCIR601 (QCIF)",
276 .width = 180,
277 .height = 120,
278 .hscale = 0x0400,
279 .vscale = 0x0400,
280 },
281 };
282
283 static const struct tw9910_scale_ctrl tw9910_pal_scales[] = {
284 {
285 .name = "PAL SQ",
286 .width = 768,
287 .height = 576,
288 .hscale = 0x0100,
289 .vscale = 0x0100,
290 },
291 {
292 .name = "PAL CCIR601",
293 .width = 720,
294 .height = 576,
295 .hscale = 0x0100,
296 .vscale = 0x0100,
297 },
298 {
299 .name = "PAL SQ (CIF)",
300 .width = 384,
301 .height = 288,
302 .hscale = 0x0200,
303 .vscale = 0x0200,
304 },
305 {
306 .name = "PAL CCIR601 (CIF)",
307 .width = 360,
308 .height = 288,
309 .hscale = 0x0200,
310 .vscale = 0x0200,
311 },
312 {
313 .name = "PAL SQ (QCIF)",
314 .width = 192,
315 .height = 144,
316 .hscale = 0x0400,
317 .vscale = 0x0400,
318 },
319 {
320 .name = "PAL CCIR601 (QCIF)",
321 .width = 180,
322 .height = 144,
323 .hscale = 0x0400,
324 .vscale = 0x0400,
325 },
326 };
327
328 /*
329 * general function
330 */
331 static struct tw9910_priv *to_tw9910(const struct i2c_client *client)
332 {
333 return container_of(i2c_get_clientdata(client), struct tw9910_priv,
334 subdev);
335 }
336
337 static int tw9910_mask_set(struct i2c_client *client, u8 command,
338 u8 mask, u8 set)
339 {
340 s32 val = i2c_smbus_read_byte_data(client, command);
341 if (val < 0)
342 return val;
343
344 val &= ~mask;
345 val |= set & mask;
346
347 return i2c_smbus_write_byte_data(client, command, val);
348 }
349
350 static int tw9910_set_scale(struct i2c_client *client,
351 const struct tw9910_scale_ctrl *scale)
352 {
353 int ret;
354
355 ret = i2c_smbus_write_byte_data(client, SCALE_HI,
356 (scale->vscale & 0x0F00) >> 4 |
357 (scale->hscale & 0x0F00) >> 8);
358 if (ret < 0)
359 return ret;
360
361 ret = i2c_smbus_write_byte_data(client, HSCALE_LO,
362 scale->hscale & 0x00FF);
363 if (ret < 0)
364 return ret;
365
366 ret = i2c_smbus_write_byte_data(client, VSCALE_LO,
367 scale->vscale & 0x00FF);
368
369 return ret;
370 }
371
372 static int tw9910_set_hsync(struct i2c_client *client)
373 {
374 struct tw9910_priv *priv = to_tw9910(client);
375 int ret;
376
377 /* bit 10 - 3 */
378 ret = i2c_smbus_write_byte_data(client, HSBEGIN,
379 (HSYNC_START & 0x07F8) >> 3);
380 if (ret < 0)
381 return ret;
382
383 /* bit 10 - 3 */
384 ret = i2c_smbus_write_byte_data(client, HSEND,
385 (HSYNC_END & 0x07F8) >> 3);
386 if (ret < 0)
387 return ret;
388
389 /* So far only revisions 0 and 1 have been seen */
390 /* bit 2 - 0 */
391 if (1 == priv->revision)
392 ret = tw9910_mask_set(client, HSLOWCTL, 0x77,
393 (HSYNC_START & 0x0007) << 4 |
394 (HSYNC_END & 0x0007));
395
396 return ret;
397 }
398
399 static void tw9910_reset(struct i2c_client *client)
400 {
401 tw9910_mask_set(client, ACNTL1, SRESET, SRESET);
402 msleep(1);
403 }
404
405 static int tw9910_power(struct i2c_client *client, int enable)
406 {
407 int ret;
408 u8 acntl1;
409 u8 acntl2;
410
411 if (enable) {
412 acntl1 = 0;
413 acntl2 = 0;
414 } else {
415 acntl1 = CLK_PDN | Y_PDN | C_PDN;
416 acntl2 = PLL_PDN;
417 }
418
419 ret = tw9910_mask_set(client, ACNTL1, ACNTL1_PDN_MASK, acntl1);
420 if (ret < 0)
421 return ret;
422
423 return tw9910_mask_set(client, ACNTL2, ACNTL2_PDN_MASK, acntl2);
424 }
425
426 static const struct tw9910_scale_ctrl *tw9910_select_norm(v4l2_std_id norm,
427 u32 width, u32 height)
428 {
429 const struct tw9910_scale_ctrl *scale;
430 const struct tw9910_scale_ctrl *ret = NULL;
431 __u32 diff = 0xffffffff, tmp;
432 int size, i;
433
434 if (norm & V4L2_STD_NTSC) {
435 scale = tw9910_ntsc_scales;
436 size = ARRAY_SIZE(tw9910_ntsc_scales);
437 } else if (norm & V4L2_STD_PAL) {
438 scale = tw9910_pal_scales;
439 size = ARRAY_SIZE(tw9910_pal_scales);
440 } else {
441 return NULL;
442 }
443
444 for (i = 0; i < size; i++) {
445 tmp = abs(width - scale[i].width) +
446 abs(height - scale[i].height);
447 if (tmp < diff) {
448 diff = tmp;
449 ret = scale + i;
450 }
451 }
452
453 return ret;
454 }
455
456 /*
457 * subdevice operations
458 */
459 static int tw9910_s_stream(struct v4l2_subdev *sd, int enable)
460 {
461 struct i2c_client *client = v4l2_get_subdevdata(sd);
462 struct tw9910_priv *priv = to_tw9910(client);
463 u8 val;
464 int ret;
465
466 if (!enable) {
467 switch (priv->revision) {
468 case 0:
469 val = OEN_TRI_SEL_ALL_OFF_r0;
470 break;
471 case 1:
472 val = OEN_TRI_SEL_ALL_OFF_r1;
473 break;
474 default:
475 dev_err(&client->dev, "un-supported revision\n");
476 return -EINVAL;
477 }
478 } else {
479 val = OEN_TRI_SEL_ALL_ON;
480
481 if (!priv->scale) {
482 dev_err(&client->dev, "norm select error\n");
483 return -EPERM;
484 }
485
486 dev_dbg(&client->dev, "%s %dx%d\n",
487 priv->scale->name,
488 priv->scale->width,
489 priv->scale->height);
490 }
491
492 ret = tw9910_mask_set(client, OPFORM, OEN_TRI_SEL_MASK, val);
493 if (ret < 0)
494 return ret;
495
496 return tw9910_power(client, enable);
497 }
498
499 static int tw9910_g_std(struct v4l2_subdev *sd, v4l2_std_id *norm)
500 {
501 struct i2c_client *client = v4l2_get_subdevdata(sd);
502 struct tw9910_priv *priv = to_tw9910(client);
503
504 *norm = priv->norm;
505
506 return 0;
507 }
508
509 static int tw9910_s_std(struct v4l2_subdev *sd, v4l2_std_id norm)
510 {
511 struct i2c_client *client = v4l2_get_subdevdata(sd);
512 struct tw9910_priv *priv = to_tw9910(client);
513
514 if (!(norm & (V4L2_STD_NTSC | V4L2_STD_PAL)))
515 return -EINVAL;
516
517 priv->norm = norm;
518
519 return 0;
520 }
521
522 #ifdef CONFIG_VIDEO_ADV_DEBUG
523 static int tw9910_g_register(struct v4l2_subdev *sd,
524 struct v4l2_dbg_register *reg)
525 {
526 struct i2c_client *client = v4l2_get_subdevdata(sd);
527 int ret;
528
529 if (reg->reg > 0xff)
530 return -EINVAL;
531
532 reg->size = 1;
533 ret = i2c_smbus_read_byte_data(client, reg->reg);
534 if (ret < 0)
535 return ret;
536
537 /*
538 * ret = int
539 * reg->val = __u64
540 */
541 reg->val = (__u64)ret;
542
543 return 0;
544 }
545
546 static int tw9910_s_register(struct v4l2_subdev *sd,
547 const struct v4l2_dbg_register *reg)
548 {
549 struct i2c_client *client = v4l2_get_subdevdata(sd);
550
551 if (reg->reg > 0xff ||
552 reg->val > 0xff)
553 return -EINVAL;
554
555 return i2c_smbus_write_byte_data(client, reg->reg, reg->val);
556 }
557 #endif
558
559 static int tw9910_s_power(struct v4l2_subdev *sd, int on)
560 {
561 struct i2c_client *client = v4l2_get_subdevdata(sd);
562 struct soc_camera_subdev_desc *ssdd = soc_camera_i2c_to_desc(client);
563 struct tw9910_priv *priv = to_tw9910(client);
564
565 return soc_camera_set_power(&client->dev, ssdd, priv->clk, on);
566 }
567
568 static int tw9910_set_frame(struct v4l2_subdev *sd, u32 *width, u32 *height)
569 {
570 struct i2c_client *client = v4l2_get_subdevdata(sd);
571 struct tw9910_priv *priv = to_tw9910(client);
572 int ret = -EINVAL;
573 u8 val;
574
575 /*
576 * select suitable norm
577 */
578 priv->scale = tw9910_select_norm(priv->norm, *width, *height);
579 if (!priv->scale)
580 goto tw9910_set_fmt_error;
581
582 /*
583 * reset hardware
584 */
585 tw9910_reset(client);
586
587 /*
588 * set bus width
589 */
590 val = 0x00;
591 if (SOCAM_DATAWIDTH_16 == priv->info->buswidth)
592 val = LEN;
593
594 ret = tw9910_mask_set(client, OPFORM, LEN, val);
595 if (ret < 0)
596 goto tw9910_set_fmt_error;
597
598 /*
599 * select MPOUT behavior
600 */
601 switch (priv->info->mpout) {
602 case TW9910_MPO_VLOSS:
603 val = RTSEL_VLOSS; break;
604 case TW9910_MPO_HLOCK:
605 val = RTSEL_HLOCK; break;
606 case TW9910_MPO_SLOCK:
607 val = RTSEL_SLOCK; break;
608 case TW9910_MPO_VLOCK:
609 val = RTSEL_VLOCK; break;
610 case TW9910_MPO_MONO:
611 val = RTSEL_MONO; break;
612 case TW9910_MPO_DET50:
613 val = RTSEL_DET50; break;
614 case TW9910_MPO_FIELD:
615 val = RTSEL_FIELD; break;
616 case TW9910_MPO_RTCO:
617 val = RTSEL_RTCO; break;
618 default:
619 val = 0;
620 }
621
622 ret = tw9910_mask_set(client, VBICNTL, RTSEL_MASK, val);
623 if (ret < 0)
624 goto tw9910_set_fmt_error;
625
626 /*
627 * set scale
628 */
629 ret = tw9910_set_scale(client, priv->scale);
630 if (ret < 0)
631 goto tw9910_set_fmt_error;
632
633 /*
634 * set hsync
635 */
636 ret = tw9910_set_hsync(client);
637 if (ret < 0)
638 goto tw9910_set_fmt_error;
639
640 *width = priv->scale->width;
641 *height = priv->scale->height;
642
643 return ret;
644
645 tw9910_set_fmt_error:
646
647 tw9910_reset(client);
648 priv->scale = NULL;
649
650 return ret;
651 }
652
653 static int tw9910_g_crop(struct v4l2_subdev *sd, struct v4l2_crop *a)
654 {
655 struct i2c_client *client = v4l2_get_subdevdata(sd);
656 struct tw9910_priv *priv = to_tw9910(client);
657
658 a->c.left = 0;
659 a->c.top = 0;
660 if (priv->norm & V4L2_STD_NTSC) {
661 a->c.width = 640;
662 a->c.height = 480;
663 } else {
664 a->c.width = 768;
665 a->c.height = 576;
666 }
667 a->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
668
669 return 0;
670 }
671
672 static int tw9910_cropcap(struct v4l2_subdev *sd, struct v4l2_cropcap *a)
673 {
674 struct i2c_client *client = v4l2_get_subdevdata(sd);
675 struct tw9910_priv *priv = to_tw9910(client);
676
677 a->bounds.left = 0;
678 a->bounds.top = 0;
679 if (priv->norm & V4L2_STD_NTSC) {
680 a->bounds.width = 640;
681 a->bounds.height = 480;
682 } else {
683 a->bounds.width = 768;
684 a->bounds.height = 576;
685 }
686 a->defrect = a->bounds;
687 a->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
688 a->pixelaspect.numerator = 1;
689 a->pixelaspect.denominator = 1;
690
691 return 0;
692 }
693
694 static int tw9910_g_fmt(struct v4l2_subdev *sd,
695 struct v4l2_mbus_framefmt *mf)
696 {
697 struct i2c_client *client = v4l2_get_subdevdata(sd);
698 struct tw9910_priv *priv = to_tw9910(client);
699
700 if (!priv->scale) {
701 priv->scale = tw9910_select_norm(priv->norm, 640, 480);
702 if (!priv->scale)
703 return -EINVAL;
704 }
705
706 mf->width = priv->scale->width;
707 mf->height = priv->scale->height;
708 mf->code = V4L2_MBUS_FMT_UYVY8_2X8;
709 mf->colorspace = V4L2_COLORSPACE_JPEG;
710 mf->field = V4L2_FIELD_INTERLACED_BT;
711
712 return 0;
713 }
714
715 static int tw9910_s_fmt(struct v4l2_subdev *sd,
716 struct v4l2_mbus_framefmt *mf)
717 {
718 u32 width = mf->width, height = mf->height;
719 int ret;
720
721 WARN_ON(mf->field != V4L2_FIELD_ANY &&
722 mf->field != V4L2_FIELD_INTERLACED_BT);
723
724 /*
725 * check color format
726 */
727 if (mf->code != V4L2_MBUS_FMT_UYVY8_2X8)
728 return -EINVAL;
729
730 mf->colorspace = V4L2_COLORSPACE_JPEG;
731
732 ret = tw9910_set_frame(sd, &width, &height);
733 if (!ret) {
734 mf->width = width;
735 mf->height = height;
736 }
737 return ret;
738 }
739
740 static int tw9910_try_fmt(struct v4l2_subdev *sd,
741 struct v4l2_mbus_framefmt *mf)
742 {
743 struct i2c_client *client = v4l2_get_subdevdata(sd);
744 struct tw9910_priv *priv = to_tw9910(client);
745 const struct tw9910_scale_ctrl *scale;
746
747 if (V4L2_FIELD_ANY == mf->field) {
748 mf->field = V4L2_FIELD_INTERLACED_BT;
749 } else if (V4L2_FIELD_INTERLACED_BT != mf->field) {
750 dev_err(&client->dev, "Field type %d invalid.\n", mf->field);
751 return -EINVAL;
752 }
753
754 mf->code = V4L2_MBUS_FMT_UYVY8_2X8;
755 mf->colorspace = V4L2_COLORSPACE_JPEG;
756
757 /*
758 * select suitable norm
759 */
760 scale = tw9910_select_norm(priv->norm, mf->width, mf->height);
761 if (!scale)
762 return -EINVAL;
763
764 mf->width = scale->width;
765 mf->height = scale->height;
766
767 return 0;
768 }
769
770 static int tw9910_video_probe(struct i2c_client *client)
771 {
772 struct tw9910_priv *priv = to_tw9910(client);
773 s32 id;
774 int ret;
775
776 /*
777 * tw9910 only use 8 or 16 bit bus width
778 */
779 if (SOCAM_DATAWIDTH_16 != priv->info->buswidth &&
780 SOCAM_DATAWIDTH_8 != priv->info->buswidth) {
781 dev_err(&client->dev, "bus width error\n");
782 return -ENODEV;
783 }
784
785 ret = tw9910_s_power(&priv->subdev, 1);
786 if (ret < 0)
787 return ret;
788
789 /*
790 * check and show Product ID
791 * So far only revisions 0 and 1 have been seen
792 */
793 id = i2c_smbus_read_byte_data(client, ID);
794 priv->revision = GET_REV(id);
795 id = GET_ID(id);
796
797 if (0x0B != id ||
798 0x01 < priv->revision) {
799 dev_err(&client->dev,
800 "Product ID error %x:%x\n",
801 id, priv->revision);
802 ret = -ENODEV;
803 goto done;
804 }
805
806 dev_info(&client->dev,
807 "tw9910 Product ID %0x:%0x\n", id, priv->revision);
808
809 priv->norm = V4L2_STD_NTSC;
810
811 done:
812 tw9910_s_power(&priv->subdev, 0);
813 return ret;
814 }
815
816 static struct v4l2_subdev_core_ops tw9910_subdev_core_ops = {
817 .s_std = tw9910_s_std,
818 .g_std = tw9910_g_std,
819 #ifdef CONFIG_VIDEO_ADV_DEBUG
820 .g_register = tw9910_g_register,
821 .s_register = tw9910_s_register,
822 #endif
823 .s_power = tw9910_s_power,
824 };
825
826 static int tw9910_enum_fmt(struct v4l2_subdev *sd, unsigned int index,
827 enum v4l2_mbus_pixelcode *code)
828 {
829 if (index)
830 return -EINVAL;
831
832 *code = V4L2_MBUS_FMT_UYVY8_2X8;
833 return 0;
834 }
835
836 static int tw9910_g_mbus_config(struct v4l2_subdev *sd,
837 struct v4l2_mbus_config *cfg)
838 {
839 struct i2c_client *client = v4l2_get_subdevdata(sd);
840 struct soc_camera_subdev_desc *ssdd = soc_camera_i2c_to_desc(client);
841
842 cfg->flags = V4L2_MBUS_PCLK_SAMPLE_RISING | V4L2_MBUS_MASTER |
843 V4L2_MBUS_VSYNC_ACTIVE_HIGH | V4L2_MBUS_VSYNC_ACTIVE_LOW |
844 V4L2_MBUS_HSYNC_ACTIVE_HIGH | V4L2_MBUS_HSYNC_ACTIVE_LOW |
845 V4L2_MBUS_DATA_ACTIVE_HIGH;
846 cfg->type = V4L2_MBUS_PARALLEL;
847 cfg->flags = soc_camera_apply_board_flags(ssdd, cfg);
848
849 return 0;
850 }
851
852 static int tw9910_s_mbus_config(struct v4l2_subdev *sd,
853 const struct v4l2_mbus_config *cfg)
854 {
855 struct i2c_client *client = v4l2_get_subdevdata(sd);
856 struct soc_camera_subdev_desc *ssdd = soc_camera_i2c_to_desc(client);
857 u8 val = VSSL_VVALID | HSSL_DVALID;
858 unsigned long flags = soc_camera_apply_board_flags(ssdd, cfg);
859
860 /*
861 * set OUTCTR1
862 *
863 * We use VVALID and DVALID signals to control VSYNC and HSYNC
864 * outputs, in this mode their polarity is inverted.
865 */
866 if (flags & V4L2_MBUS_HSYNC_ACTIVE_LOW)
867 val |= HSP_HI;
868
869 if (flags & V4L2_MBUS_VSYNC_ACTIVE_LOW)
870 val |= VSP_HI;
871
872 return i2c_smbus_write_byte_data(client, OUTCTR1, val);
873 }
874
875 static struct v4l2_subdev_video_ops tw9910_subdev_video_ops = {
876 .s_stream = tw9910_s_stream,
877 .g_mbus_fmt = tw9910_g_fmt,
878 .s_mbus_fmt = tw9910_s_fmt,
879 .try_mbus_fmt = tw9910_try_fmt,
880 .cropcap = tw9910_cropcap,
881 .g_crop = tw9910_g_crop,
882 .enum_mbus_fmt = tw9910_enum_fmt,
883 .g_mbus_config = tw9910_g_mbus_config,
884 .s_mbus_config = tw9910_s_mbus_config,
885 };
886
887 static struct v4l2_subdev_ops tw9910_subdev_ops = {
888 .core = &tw9910_subdev_core_ops,
889 .video = &tw9910_subdev_video_ops,
890 };
891
892 /*
893 * i2c_driver function
894 */
895
896 static int tw9910_probe(struct i2c_client *client,
897 const struct i2c_device_id *did)
898
899 {
900 struct tw9910_priv *priv;
901 struct tw9910_video_info *info;
902 struct i2c_adapter *adapter =
903 to_i2c_adapter(client->dev.parent);
904 struct soc_camera_subdev_desc *ssdd = soc_camera_i2c_to_desc(client);
905 int ret;
906
907 if (!ssdd || !ssdd->drv_priv) {
908 dev_err(&client->dev, "TW9910: missing platform data!\n");
909 return -EINVAL;
910 }
911
912 info = ssdd->drv_priv;
913
914 if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA)) {
915 dev_err(&client->dev,
916 "I2C-Adapter doesn't support "
917 "I2C_FUNC_SMBUS_BYTE_DATA\n");
918 return -EIO;
919 }
920
921 priv = devm_kzalloc(&client->dev, sizeof(*priv), GFP_KERNEL);
922 if (!priv)
923 return -ENOMEM;
924
925 priv->info = info;
926
927 v4l2_i2c_subdev_init(&priv->subdev, client, &tw9910_subdev_ops);
928
929 priv->clk = v4l2_clk_get(&client->dev, "mclk");
930 if (IS_ERR(priv->clk))
931 return PTR_ERR(priv->clk);
932
933 ret = tw9910_video_probe(client);
934 if (ret < 0)
935 v4l2_clk_put(priv->clk);
936
937 return ret;
938 }
939
940 static int tw9910_remove(struct i2c_client *client)
941 {
942 struct tw9910_priv *priv = to_tw9910(client);
943 v4l2_clk_put(priv->clk);
944 return 0;
945 }
946
947 static const struct i2c_device_id tw9910_id[] = {
948 { "tw9910", 0 },
949 { }
950 };
951 MODULE_DEVICE_TABLE(i2c, tw9910_id);
952
953 static struct i2c_driver tw9910_i2c_driver = {
954 .driver = {
955 .name = "tw9910",
956 },
957 .probe = tw9910_probe,
958 .remove = tw9910_remove,
959 .id_table = tw9910_id,
960 };
961
962 module_i2c_driver(tw9910_i2c_driver);
963
964 MODULE_DESCRIPTION("SoC Camera driver for tw9910");
965 MODULE_AUTHOR("Kuninori Morimoto");
966 MODULE_LICENSE("GPL v2");
Linux with added FPC-III support