?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
net: qmi_wwan: add Olivetti Olicard 500
[linux/fpc-iii.git] / drivers / media / usb / dvb-usb / af9005-fe.c
blob740f3f496f12c171bfe19564eafaa69fdfa6f40d
1 /* Frontend part of the Linux driver for the Afatech 9005
2 * USB1.1 DVB-T receiver.
3 *
4 * Copyright (C) 2007 Luca Olivetti (luca@ventoso.org)
5 *
6 * Thanks to Afatech who kindly provided information.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 *
22 * see Documentation/dvb/README.dvb-usb for more information
23 */
24 #include "af9005.h"
25 #include "af9005-script.h"
26 #include "mt2060.h"
27 #include "qt1010.h"
28 #include <asm/div64.h>
29
30 struct af9005_fe_state {
31 struct dvb_usb_device *d;
32 fe_status_t stat;
33
34 /* retraining parameters */
35 u32 original_fcw;
36 u16 original_rf_top;
37 u16 original_if_top;
38 u16 original_if_min;
39 u16 original_aci0_if_top;
40 u16 original_aci1_if_top;
41 u16 original_aci0_if_min;
42 u8 original_if_unplug_th;
43 u8 original_rf_unplug_th;
44 u8 original_dtop_if_unplug_th;
45 u8 original_dtop_rf_unplug_th;
46
47 /* statistics */
48 u32 pre_vit_error_count;
49 u32 pre_vit_bit_count;
50 u32 ber;
51 u32 post_vit_error_count;
52 u32 post_vit_bit_count;
53 u32 unc;
54 u16 abort_count;
55
56 int opened;
57 int strong;
58 unsigned long next_status_check;
59 struct dvb_frontend frontend;
60 };
61
62 static int af9005_write_word_agc(struct dvb_usb_device *d, u16 reghi,
63 u16 reglo, u8 pos, u8 len, u16 value)
64 {
65 int ret;
66
67 if ((ret = af9005_write_ofdm_register(d, reglo, (u8) (value & 0xff))))
68 return ret;
69 return af9005_write_register_bits(d, reghi, pos, len,
70 (u8) ((value & 0x300) >> 8));
71 }
72
73 static int af9005_read_word_agc(struct dvb_usb_device *d, u16 reghi,
74 u16 reglo, u8 pos, u8 len, u16 * value)
75 {
76 int ret;
77 u8 temp0, temp1;
78
79 if ((ret = af9005_read_ofdm_register(d, reglo, &temp0)))
80 return ret;
81 if ((ret = af9005_read_ofdm_register(d, reghi, &temp1)))
82 return ret;
83 switch (pos) {
84 case 0:
85 *value = ((u16) (temp1 & 0x03) << 8) + (u16) temp0;
86 break;
87 case 2:
88 *value = ((u16) (temp1 & 0x0C) << 6) + (u16) temp0;
89 break;
90 case 4:
91 *value = ((u16) (temp1 & 0x30) << 4) + (u16) temp0;
92 break;
93 case 6:
94 *value = ((u16) (temp1 & 0xC0) << 2) + (u16) temp0;
95 break;
96 default:
97 err("invalid pos in read word agc");
98 return -EINVAL;
99 }
100 return 0;
101
102 }
103
104 static int af9005_is_fecmon_available(struct dvb_frontend *fe, int *available)
105 {
106 struct af9005_fe_state *state = fe->demodulator_priv;
107 int ret;
108 u8 temp;
109
110 *available = false;
111
112 ret = af9005_read_register_bits(state->d, xd_p_fec_vtb_rsd_mon_en,
113 fec_vtb_rsd_mon_en_pos,
114 fec_vtb_rsd_mon_en_len, &temp);
115 if (ret)
116 return ret;
117 if (temp & 1) {
118 ret =
119 af9005_read_register_bits(state->d,
120 xd_p_reg_ofsm_read_rbc_en,
121 reg_ofsm_read_rbc_en_pos,
122 reg_ofsm_read_rbc_en_len, &temp);
123 if (ret)
124 return ret;
125 if ((temp & 1) == 0)
126 *available = true;
127
128 }
129 return 0;
130 }
131
132 static int af9005_get_post_vit_err_cw_count(struct dvb_frontend *fe,
133 u32 * post_err_count,
134 u32 * post_cw_count,
135 u16 * abort_count)
136 {
137 struct af9005_fe_state *state = fe->demodulator_priv;
138 int ret;
139 u32 err_count;
140 u32 cw_count;
141 u8 temp, temp0, temp1, temp2;
142 u16 loc_abort_count;
143
144 *post_err_count = 0;
145 *post_cw_count = 0;
146
147 /* check if error bit count is ready */
148 ret =
149 af9005_read_register_bits(state->d, xd_r_fec_rsd_ber_rdy,
150 fec_rsd_ber_rdy_pos, fec_rsd_ber_rdy_len,
151 &temp);
152 if (ret)
153 return ret;
154 if (!temp) {
155 deb_info("rsd counter not ready\n");
156 return 100;
157 }
158 /* get abort count */
159 ret =
160 af9005_read_ofdm_register(state->d,
161 xd_r_fec_rsd_abort_packet_cnt_7_0,
162 &temp0);
163 if (ret)
164 return ret;
165 ret =
166 af9005_read_ofdm_register(state->d,
167 xd_r_fec_rsd_abort_packet_cnt_15_8,
168 &temp1);
169 if (ret)
170 return ret;
171 loc_abort_count = ((u16) temp1 << 8) + temp0;
172
173 /* get error count */
174 ret =
175 af9005_read_ofdm_register(state->d, xd_r_fec_rsd_bit_err_cnt_7_0,
176 &temp0);
177 if (ret)
178 return ret;
179 ret =
180 af9005_read_ofdm_register(state->d, xd_r_fec_rsd_bit_err_cnt_15_8,
181 &temp1);
182 if (ret)
183 return ret;
184 ret =
185 af9005_read_ofdm_register(state->d, xd_r_fec_rsd_bit_err_cnt_23_16,
186 &temp2);
187 if (ret)
188 return ret;
189 err_count = ((u32) temp2 << 16) + ((u32) temp1 << 8) + temp0;
190 *post_err_count = err_count - (u32) loc_abort_count *8 * 8;
191
192 /* get RSD packet number */
193 ret =
194 af9005_read_ofdm_register(state->d, xd_p_fec_rsd_packet_unit_7_0,
195 &temp0);
196 if (ret)
197 return ret;
198 ret =
199 af9005_read_ofdm_register(state->d, xd_p_fec_rsd_packet_unit_15_8,
200 &temp1);
201 if (ret)
202 return ret;
203 cw_count = ((u32) temp1 << 8) + temp0;
204 if (cw_count == 0) {
205 err("wrong RSD packet count");
206 return -EIO;
207 }
208 deb_info("POST abort count %d err count %d rsd packets %d\n",
209 loc_abort_count, err_count, cw_count);
210 *post_cw_count = cw_count - (u32) loc_abort_count;
211 *abort_count = loc_abort_count;
212 return 0;
213
214 }
215
216 static int af9005_get_post_vit_ber(struct dvb_frontend *fe,
217 u32 * post_err_count, u32 * post_cw_count,
218 u16 * abort_count)
219 {
220 u32 loc_cw_count = 0, loc_err_count;
221 u16 loc_abort_count = 0;
222 int ret;
223
224 ret =
225 af9005_get_post_vit_err_cw_count(fe, &loc_err_count, &loc_cw_count,
226 &loc_abort_count);
227 if (ret)
228 return ret;
229 *post_err_count = loc_err_count;
230 *post_cw_count = loc_cw_count * 204 * 8;
231 *abort_count = loc_abort_count;
232
233 return 0;
234 }
235
236 static int af9005_get_pre_vit_err_bit_count(struct dvb_frontend *fe,
237 u32 * pre_err_count,
238 u32 * pre_bit_count)
239 {
240 struct af9005_fe_state *state = fe->demodulator_priv;
241 u8 temp, temp0, temp1, temp2;
242 u32 super_frame_count, x, bits;
243 int ret;
244
245 ret =
246 af9005_read_register_bits(state->d, xd_r_fec_vtb_ber_rdy,
247 fec_vtb_ber_rdy_pos, fec_vtb_ber_rdy_len,
248 &temp);
249 if (ret)
250 return ret;
251 if (!temp) {
252 deb_info("viterbi counter not ready\n");
253 return 101; /* ERR_APO_VTB_COUNTER_NOT_READY; */
254 }
255 ret =
256 af9005_read_ofdm_register(state->d, xd_r_fec_vtb_err_bit_cnt_7_0,
257 &temp0);
258 if (ret)
259 return ret;
260 ret =
261 af9005_read_ofdm_register(state->d, xd_r_fec_vtb_err_bit_cnt_15_8,
262 &temp1);
263 if (ret)
264 return ret;
265 ret =
266 af9005_read_ofdm_register(state->d, xd_r_fec_vtb_err_bit_cnt_23_16,
267 &temp2);
268 if (ret)
269 return ret;
270 *pre_err_count = ((u32) temp2 << 16) + ((u32) temp1 << 8) + temp0;
271
272 ret =
273 af9005_read_ofdm_register(state->d, xd_p_fec_super_frm_unit_7_0,
274 &temp0);
275 if (ret)
276 return ret;
277 ret =
278 af9005_read_ofdm_register(state->d, xd_p_fec_super_frm_unit_15_8,
279 &temp1);
280 if (ret)
281 return ret;
282 super_frame_count = ((u32) temp1 << 8) + temp0;
283 if (super_frame_count == 0) {
284 deb_info("super frame count 0\n");
285 return 102;
286 }
287
288 /* read fft mode */
289 ret =
290 af9005_read_register_bits(state->d, xd_g_reg_tpsd_txmod,
291 reg_tpsd_txmod_pos, reg_tpsd_txmod_len,
292 &temp);
293 if (ret)
294 return ret;
295 if (temp == 0) {
296 /* 2K */
297 x = 1512;
298 } else if (temp == 1) {
299 /* 8k */
300 x = 6048;
301 } else {
302 err("Invalid fft mode");
303 return -EINVAL;
304 }
305
306 /* read modulation mode */
307 ret =
308 af9005_read_register_bits(state->d, xd_g_reg_tpsd_const,
309 reg_tpsd_const_pos, reg_tpsd_const_len,
310 &temp);
311 if (ret)
312 return ret;
313 switch (temp) {
314 case 0: /* QPSK */
315 bits = 2;
316 break;
317 case 1: /* QAM_16 */
318 bits = 4;
319 break;
320 case 2: /* QAM_64 */
321 bits = 6;
322 break;
323 default:
324 err("invalid modulation mode");
325 return -EINVAL;
326 }
327 *pre_bit_count = super_frame_count * 68 * 4 * x * bits;
328 deb_info("PRE err count %d frame count %d bit count %d\n",
329 *pre_err_count, super_frame_count, *pre_bit_count);
330 return 0;
331 }
332
333 static int af9005_reset_pre_viterbi(struct dvb_frontend *fe)
334 {
335 struct af9005_fe_state *state = fe->demodulator_priv;
336 int ret;
337
338 /* set super frame count to 1 */
339 ret =
340 af9005_write_ofdm_register(state->d, xd_p_fec_super_frm_unit_7_0,
341 1 & 0xff);
342 if (ret)
343 return ret;
344 ret = af9005_write_ofdm_register(state->d, xd_p_fec_super_frm_unit_15_8,
345 1 >> 8);
346 if (ret)
347 return ret;
348 /* reset pre viterbi error count */
349 ret =
350 af9005_write_register_bits(state->d, xd_p_fec_vtb_ber_rst,
351 fec_vtb_ber_rst_pos, fec_vtb_ber_rst_len,
352 1);
353
354 return ret;
355 }
356
357 static int af9005_reset_post_viterbi(struct dvb_frontend *fe)
358 {
359 struct af9005_fe_state *state = fe->demodulator_priv;
360 int ret;
361
362 /* set packet unit */
363 ret =
364 af9005_write_ofdm_register(state->d, xd_p_fec_rsd_packet_unit_7_0,
365 10000 & 0xff);
366 if (ret)
367 return ret;
368 ret =
369 af9005_write_ofdm_register(state->d, xd_p_fec_rsd_packet_unit_15_8,
370 10000 >> 8);
371 if (ret)
372 return ret;
373 /* reset post viterbi error count */
374 ret =
375 af9005_write_register_bits(state->d, xd_p_fec_rsd_ber_rst,
376 fec_rsd_ber_rst_pos, fec_rsd_ber_rst_len,
377 1);
378
379 return ret;
380 }
381
382 static int af9005_get_statistic(struct dvb_frontend *fe)
383 {
384 struct af9005_fe_state *state = fe->demodulator_priv;
385 int ret, fecavailable;
386 u64 numerator, denominator;
387
388 deb_info("GET STATISTIC\n");
389 ret = af9005_is_fecmon_available(fe, &fecavailable);
390 if (ret)
391 return ret;
392 if (!fecavailable) {
393 deb_info("fecmon not available\n");
394 return 0;
395 }
396
397 ret = af9005_get_pre_vit_err_bit_count(fe, &state->pre_vit_error_count,
398 &state->pre_vit_bit_count);
399 if (ret == 0) {
400 af9005_reset_pre_viterbi(fe);
401 if (state->pre_vit_bit_count > 0) {
402 /* according to v 0.0.4 of the dvb api ber should be a multiple
403 of 10E-9 so we have to multiply the error count by
404 10E9=1000000000 */
405 numerator =
406 (u64) state->pre_vit_error_count * (u64) 1000000000;
407 denominator = (u64) state->pre_vit_bit_count;
408 state->ber = do_div(numerator, denominator);
409 } else {
410 state->ber = 0xffffffff;
411 }
412 }
413
414 ret = af9005_get_post_vit_ber(fe, &state->post_vit_error_count,
415 &state->post_vit_bit_count,
416 &state->abort_count);
417 if (ret == 0) {
418 ret = af9005_reset_post_viterbi(fe);
419 state->unc += state->abort_count;
420 if (ret)
421 return ret;
422 }
423 return 0;
424 }
425
426 static int af9005_fe_refresh_state(struct dvb_frontend *fe)
427 {
428 struct af9005_fe_state *state = fe->demodulator_priv;
429 if (time_after(jiffies, state->next_status_check)) {
430 deb_info("REFRESH STATE\n");
431
432 /* statistics */
433 if (af9005_get_statistic(fe))
434 err("get_statistic_failed");
435 state->next_status_check = jiffies + 250 * HZ / 1000;
436 }
437 return 0;
438 }
439
440 static int af9005_fe_read_status(struct dvb_frontend *fe, fe_status_t * stat)
441 {
442 struct af9005_fe_state *state = fe->demodulator_priv;
443 u8 temp;
444 int ret;
445
446 if (fe->ops.tuner_ops.release == NULL)
447 return -ENODEV;
448
449 *stat = 0;
450 ret = af9005_read_register_bits(state->d, xd_p_agc_lock,
451 agc_lock_pos, agc_lock_len, &temp);
452 if (ret)
453 return ret;
454 if (temp)
455 *stat |= FE_HAS_SIGNAL;
456
457 ret = af9005_read_register_bits(state->d, xd_p_fd_tpsd_lock,
458 fd_tpsd_lock_pos, fd_tpsd_lock_len,
459 &temp);
460 if (ret)
461 return ret;
462 if (temp)
463 *stat |= FE_HAS_CARRIER;
464
465 ret = af9005_read_register_bits(state->d,
466 xd_r_mp2if_sync_byte_locked,
467 mp2if_sync_byte_locked_pos,
468 mp2if_sync_byte_locked_pos, &temp);
469 if (ret)
470 return ret;
471 if (temp)
472 *stat |= FE_HAS_SYNC | FE_HAS_VITERBI | FE_HAS_LOCK;
473 if (state->opened)
474 af9005_led_control(state->d, *stat & FE_HAS_LOCK);
475
476 ret =
477 af9005_read_register_bits(state->d, xd_p_reg_strong_sginal_detected,
478 reg_strong_sginal_detected_pos,
479 reg_strong_sginal_detected_len, &temp);
480 if (ret)
481 return ret;
482 if (temp != state->strong) {
483 deb_info("adjust for strong signal %d\n", temp);
484 state->strong = temp;
485 }
486 return 0;
487 }
488
489 static int af9005_fe_read_ber(struct dvb_frontend *fe, u32 * ber)
490 {
491 struct af9005_fe_state *state = fe->demodulator_priv;
492 if (fe->ops.tuner_ops.release == NULL)
493 return -ENODEV;
494 af9005_fe_refresh_state(fe);
495 *ber = state->ber;
496 return 0;
497 }
498
499 static int af9005_fe_read_unc_blocks(struct dvb_frontend *fe, u32 * unc)
500 {
501 struct af9005_fe_state *state = fe->demodulator_priv;
502 if (fe->ops.tuner_ops.release == NULL)
503 return -ENODEV;
504 af9005_fe_refresh_state(fe);
505 *unc = state->unc;
506 return 0;
507 }
508
509 static int af9005_fe_read_signal_strength(struct dvb_frontend *fe,
510 u16 * strength)
511 {
512 struct af9005_fe_state *state = fe->demodulator_priv;
513 int ret;
514 u8 if_gain, rf_gain;
515
516 if (fe->ops.tuner_ops.release == NULL)
517 return -ENODEV;
518 ret =
519 af9005_read_ofdm_register(state->d, xd_r_reg_aagc_rf_gain,
520 &rf_gain);
521 if (ret)
522 return ret;
523 ret =
524 af9005_read_ofdm_register(state->d, xd_r_reg_aagc_if_gain,
525 &if_gain);
526 if (ret)
527 return ret;
528 /* this value has no real meaning, but i don't have the tables that relate
529 the rf and if gain with the dbm, so I just scale the value */
530 *strength = (512 - rf_gain - if_gain) << 7;
531 return 0;
532 }
533
534 static int af9005_fe_read_snr(struct dvb_frontend *fe, u16 * snr)
535 {
536 /* the snr can be derived from the ber and the modulation
537 but I don't think this kind of complex calculations belong
538 in the driver. I may be wrong.... */
539 return -ENOSYS;
540 }
541
542 static int af9005_fe_program_cfoe(struct dvb_usb_device *d, u32 bw)
543 {
544 u8 temp0, temp1, temp2, temp3, buf[4];
545 int ret;
546 u32 NS_coeff1_2048Nu;
547 u32 NS_coeff1_8191Nu;
548 u32 NS_coeff1_8192Nu;
549 u32 NS_coeff1_8193Nu;
550 u32 NS_coeff2_2k;
551 u32 NS_coeff2_8k;
552
553 switch (bw) {
554 case 6000000:
555 NS_coeff1_2048Nu = 0x2ADB6DC;
556 NS_coeff1_8191Nu = 0xAB7313;
557 NS_coeff1_8192Nu = 0xAB6DB7;
558 NS_coeff1_8193Nu = 0xAB685C;
559 NS_coeff2_2k = 0x156DB6E;
560 NS_coeff2_8k = 0x55B6DC;
561 break;
562
563 case 7000000:
564 NS_coeff1_2048Nu = 0x3200001;
565 NS_coeff1_8191Nu = 0xC80640;
566 NS_coeff1_8192Nu = 0xC80000;
567 NS_coeff1_8193Nu = 0xC7F9C0;
568 NS_coeff2_2k = 0x1900000;
569 NS_coeff2_8k = 0x640000;
570 break;
571
572 case 8000000:
573 NS_coeff1_2048Nu = 0x3924926;
574 NS_coeff1_8191Nu = 0xE4996E;
575 NS_coeff1_8192Nu = 0xE49249;
576 NS_coeff1_8193Nu = 0xE48B25;
577 NS_coeff2_2k = 0x1C92493;
578 NS_coeff2_8k = 0x724925;
579 break;
580 default:
581 err("Invalid bandwidth %d.", bw);
582 return -EINVAL;
583 }
584
585 /*
586 * write NS_coeff1_2048Nu
587 */
588
589 temp0 = (u8) (NS_coeff1_2048Nu & 0x000000FF);
590 temp1 = (u8) ((NS_coeff1_2048Nu & 0x0000FF00) >> 8);
591 temp2 = (u8) ((NS_coeff1_2048Nu & 0x00FF0000) >> 16);
592 temp3 = (u8) ((NS_coeff1_2048Nu & 0x03000000) >> 24);
593
594 /* big endian to make 8051 happy */
595 buf[0] = temp3;
596 buf[1] = temp2;
597 buf[2] = temp1;
598 buf[3] = temp0;
599
600 /* cfoe_NS_2k_coeff1_25_24 */
601 ret = af9005_write_ofdm_register(d, 0xAE00, buf[0]);
602 if (ret)
603 return ret;
604
605 /* cfoe_NS_2k_coeff1_23_16 */
606 ret = af9005_write_ofdm_register(d, 0xAE01, buf[1]);
607 if (ret)
608 return ret;
609
610 /* cfoe_NS_2k_coeff1_15_8 */
611 ret = af9005_write_ofdm_register(d, 0xAE02, buf[2]);
612 if (ret)
613 return ret;
614
615 /* cfoe_NS_2k_coeff1_7_0 */
616 ret = af9005_write_ofdm_register(d, 0xAE03, buf[3]);
617 if (ret)
618 return ret;
619
620 /*
621 * write NS_coeff2_2k
622 */
623
624 temp0 = (u8) ((NS_coeff2_2k & 0x0000003F));
625 temp1 = (u8) ((NS_coeff2_2k & 0x00003FC0) >> 6);
626 temp2 = (u8) ((NS_coeff2_2k & 0x003FC000) >> 14);
627 temp3 = (u8) ((NS_coeff2_2k & 0x01C00000) >> 22);
628
629 /* big endian to make 8051 happy */
630 buf[0] = temp3;
631 buf[1] = temp2;
632 buf[2] = temp1;
633 buf[3] = temp0;
634
635 ret = af9005_write_ofdm_register(d, 0xAE04, buf[0]);
636 if (ret)
637 return ret;
638
639 ret = af9005_write_ofdm_register(d, 0xAE05, buf[1]);
640 if (ret)
641 return ret;
642
643 ret = af9005_write_ofdm_register(d, 0xAE06, buf[2]);
644 if (ret)
645 return ret;
646
647 ret = af9005_write_ofdm_register(d, 0xAE07, buf[3]);
648 if (ret)
649 return ret;
650
651 /*
652 * write NS_coeff1_8191Nu
653 */
654
655 temp0 = (u8) ((NS_coeff1_8191Nu & 0x000000FF));
656 temp1 = (u8) ((NS_coeff1_8191Nu & 0x0000FF00) >> 8);
657 temp2 = (u8) ((NS_coeff1_8191Nu & 0x00FFC000) >> 16);
658 temp3 = (u8) ((NS_coeff1_8191Nu & 0x03000000) >> 24);
659
660 /* big endian to make 8051 happy */
661 buf[0] = temp3;
662 buf[1] = temp2;
663 buf[2] = temp1;
664 buf[3] = temp0;
665
666 ret = af9005_write_ofdm_register(d, 0xAE08, buf[0]);
667 if (ret)
668 return ret;
669
670 ret = af9005_write_ofdm_register(d, 0xAE09, buf[1]);
671 if (ret)
672 return ret;
673
674 ret = af9005_write_ofdm_register(d, 0xAE0A, buf[2]);
675 if (ret)
676 return ret;
677
678 ret = af9005_write_ofdm_register(d, 0xAE0B, buf[3]);
679 if (ret)
680 return ret;
681
682 /*
683 * write NS_coeff1_8192Nu
684 */
685
686 temp0 = (u8) (NS_coeff1_8192Nu & 0x000000FF);
687 temp1 = (u8) ((NS_coeff1_8192Nu & 0x0000FF00) >> 8);
688 temp2 = (u8) ((NS_coeff1_8192Nu & 0x00FFC000) >> 16);
689 temp3 = (u8) ((NS_coeff1_8192Nu & 0x03000000) >> 24);
690
691 /* big endian to make 8051 happy */
692 buf[0] = temp3;
693 buf[1] = temp2;
694 buf[2] = temp1;
695 buf[3] = temp0;
696
697 ret = af9005_write_ofdm_register(d, 0xAE0C, buf[0]);
698 if (ret)
699 return ret;
700
701 ret = af9005_write_ofdm_register(d, 0xAE0D, buf[1]);
702 if (ret)
703 return ret;
704
705 ret = af9005_write_ofdm_register(d, 0xAE0E, buf[2]);
706 if (ret)
707 return ret;
708
709 ret = af9005_write_ofdm_register(d, 0xAE0F, buf[3]);
710 if (ret)
711 return ret;
712
713 /*
714 * write NS_coeff1_8193Nu
715 */
716
717 temp0 = (u8) ((NS_coeff1_8193Nu & 0x000000FF));
718 temp1 = (u8) ((NS_coeff1_8193Nu & 0x0000FF00) >> 8);
719 temp2 = (u8) ((NS_coeff1_8193Nu & 0x00FFC000) >> 16);
720 temp3 = (u8) ((NS_coeff1_8193Nu & 0x03000000) >> 24);
721
722 /* big endian to make 8051 happy */
723 buf[0] = temp3;
724 buf[1] = temp2;
725 buf[2] = temp1;
726 buf[3] = temp0;
727
728 ret = af9005_write_ofdm_register(d, 0xAE10, buf[0]);
729 if (ret)
730 return ret;
731
732 ret = af9005_write_ofdm_register(d, 0xAE11, buf[1]);
733 if (ret)
734 return ret;
735
736 ret = af9005_write_ofdm_register(d, 0xAE12, buf[2]);
737 if (ret)
738 return ret;
739
740 ret = af9005_write_ofdm_register(d, 0xAE13, buf[3]);
741 if (ret)
742 return ret;
743
744 /*
745 * write NS_coeff2_8k
746 */
747
748 temp0 = (u8) ((NS_coeff2_8k & 0x0000003F));
749 temp1 = (u8) ((NS_coeff2_8k & 0x00003FC0) >> 6);
750 temp2 = (u8) ((NS_coeff2_8k & 0x003FC000) >> 14);
751 temp3 = (u8) ((NS_coeff2_8k & 0x01C00000) >> 22);
752
753 /* big endian to make 8051 happy */
754 buf[0] = temp3;
755 buf[1] = temp2;
756 buf[2] = temp1;
757 buf[3] = temp0;
758
759 ret = af9005_write_ofdm_register(d, 0xAE14, buf[0]);
760 if (ret)
761 return ret;
762
763 ret = af9005_write_ofdm_register(d, 0xAE15, buf[1]);
764 if (ret)
765 return ret;
766
767 ret = af9005_write_ofdm_register(d, 0xAE16, buf[2]);
768 if (ret)
769 return ret;
770
771 ret = af9005_write_ofdm_register(d, 0xAE17, buf[3]);
772 return ret;
773
774 }
775
776 static int af9005_fe_select_bw(struct dvb_usb_device *d, u32 bw)
777 {
778 u8 temp;
779 switch (bw) {
780 case 6000000:
781 temp = 0;
782 break;
783 case 7000000:
784 temp = 1;
785 break;
786 case 8000000:
787 temp = 2;
788 break;
789 default:
790 err("Invalid bandwidth %d.", bw);
791 return -EINVAL;
792 }
793 return af9005_write_register_bits(d, xd_g_reg_bw, reg_bw_pos,
794 reg_bw_len, temp);
795 }
796
797 static int af9005_fe_power(struct dvb_frontend *fe, int on)
798 {
799 struct af9005_fe_state *state = fe->demodulator_priv;
800 u8 temp = on;
801 int ret;
802 deb_info("power %s tuner\n", on ? "on" : "off");
803 ret = af9005_send_command(state->d, 0x03, &temp, 1, NULL, 0);
804 return ret;
805 }
806
807 static struct mt2060_config af9005_mt2060_config = {
808 0xC0
809 };
810
811 static struct qt1010_config af9005_qt1010_config = {
812 0xC4
813 };
814
815 static int af9005_fe_init(struct dvb_frontend *fe)
816 {
817 struct af9005_fe_state *state = fe->demodulator_priv;
818 struct dvb_usb_adapter *adap = fe->dvb->priv;
819 int ret, i, scriptlen;
820 u8 temp, temp0 = 0, temp1 = 0, temp2 = 0;
821 u8 buf[2];
822 u16 if1;
823
824 deb_info("in af9005_fe_init\n");
825
826 /* reset */
827 deb_info("reset\n");
828 if ((ret =
829 af9005_write_register_bits(state->d, xd_I2C_reg_ofdm_rst_en,
830 4, 1, 0x01)))
831 return ret;
832 if ((ret = af9005_write_ofdm_register(state->d, APO_REG_RESET, 0)))
833 return ret;
834 /* clear ofdm reset */
835 deb_info("clear ofdm reset\n");
836 for (i = 0; i < 150; i++) {
837 if ((ret =
838 af9005_read_ofdm_register(state->d,
839 xd_I2C_reg_ofdm_rst, &temp)))
840 return ret;
841 if (temp & (regmask[reg_ofdm_rst_len - 1] << reg_ofdm_rst_pos))
842 break;
843 msleep(10);
844 }
845 if (i == 150)
846 return -ETIMEDOUT;
847
848 /*FIXME in the dump
849 write B200 A9
850 write xd_g_reg_ofsm_clk 7
851 read eepr c6 (2)
852 read eepr c7 (2)
853 misc ctrl 3 -> 1
854 read eepr ca (6)
855 write xd_g_reg_ofsm_clk 0
856 write B200 a1
857 */
858 ret = af9005_write_ofdm_register(state->d, 0xb200, 0xa9);
859 if (ret)
860 return ret;
861 ret = af9005_write_ofdm_register(state->d, xd_g_reg_ofsm_clk, 0x07);
862 if (ret)
863 return ret;
864 temp = 0x01;
865 ret = af9005_send_command(state->d, 0x03, &temp, 1, NULL, 0);
866 if (ret)
867 return ret;
868 ret = af9005_write_ofdm_register(state->d, xd_g_reg_ofsm_clk, 0x00);
869 if (ret)
870 return ret;
871 ret = af9005_write_ofdm_register(state->d, 0xb200, 0xa1);
872 if (ret)
873 return ret;
874
875 temp = regmask[reg_ofdm_rst_len - 1] << reg_ofdm_rst_pos;
876 if ((ret =
877 af9005_write_register_bits(state->d, xd_I2C_reg_ofdm_rst,
878 reg_ofdm_rst_pos, reg_ofdm_rst_len, 1)))
879 return ret;
880 ret = af9005_write_register_bits(state->d, xd_I2C_reg_ofdm_rst,
881 reg_ofdm_rst_pos, reg_ofdm_rst_len, 0);
882
883 if (ret)
884 return ret;
885 /* don't know what register aefc is, but this is what the windows driver does */
886 ret = af9005_write_ofdm_register(state->d, 0xaefc, 0);
887 if (ret)
888 return ret;
889
890 /* set stand alone chip */
891 deb_info("set stand alone chip\n");
892 if ((ret =
893 af9005_write_register_bits(state->d, xd_p_reg_dca_stand_alone,
894 reg_dca_stand_alone_pos,
895 reg_dca_stand_alone_len, 1)))
896 return ret;
897
898 /* set dca upper & lower chip */
899 deb_info("set dca upper & lower chip\n");
900 if ((ret =
901 af9005_write_register_bits(state->d, xd_p_reg_dca_upper_chip,
902 reg_dca_upper_chip_pos,
903 reg_dca_upper_chip_len, 0)))
904 return ret;
905 if ((ret =
906 af9005_write_register_bits(state->d, xd_p_reg_dca_lower_chip,
907 reg_dca_lower_chip_pos,
908 reg_dca_lower_chip_len, 0)))
909 return ret;
910
911 /* set 2wire master clock to 0x14 (for 60KHz) */
912 deb_info("set 2wire master clock to 0x14 (for 60KHz)\n");
913 if ((ret =
914 af9005_write_ofdm_register(state->d, xd_I2C_i2c_m_period, 0x14)))
915 return ret;
916
917 /* clear dca enable chip */
918 deb_info("clear dca enable chip\n");
919 if ((ret =
920 af9005_write_register_bits(state->d, xd_p_reg_dca_en,
921 reg_dca_en_pos, reg_dca_en_len, 0)))
922 return ret;
923 /* FIXME these are register bits, but I don't know which ones */
924 ret = af9005_write_ofdm_register(state->d, 0xa16c, 1);
925 if (ret)
926 return ret;
927 ret = af9005_write_ofdm_register(state->d, 0xa3c1, 0);
928 if (ret)
929 return ret;
930
931 /* init other parameters: program cfoe and select bandwidth */
932 deb_info("program cfoe\n");
933 ret = af9005_fe_program_cfoe(state->d, 6000000);
934 if (ret)
935 return ret;
936 /* set read-update bit for modulation */
937 deb_info("set read-update bit for modulation\n");
938 if ((ret =
939 af9005_write_register_bits(state->d, xd_p_reg_feq_read_update,
940 reg_feq_read_update_pos,
941 reg_feq_read_update_len, 1)))
942 return ret;
943
944 /* sample code has a set MPEG TS code here
945 but sniffing reveals that it doesn't do it */
946
947 /* set read-update bit to 1 for DCA modulation */
948 deb_info("set read-update bit 1 for DCA modulation\n");
949 if ((ret =
950 af9005_write_register_bits(state->d, xd_p_reg_dca_read_update,
951 reg_dca_read_update_pos,
952 reg_dca_read_update_len, 1)))
953 return ret;
954
955 /* enable fec monitor */
956 deb_info("enable fec monitor\n");
957 if ((ret =
958 af9005_write_register_bits(state->d, xd_p_fec_vtb_rsd_mon_en,
959 fec_vtb_rsd_mon_en_pos,
960 fec_vtb_rsd_mon_en_len, 1)))
961 return ret;
962
963 /* FIXME should be register bits, I don't know which ones */
964 ret = af9005_write_ofdm_register(state->d, 0xa601, 0);
965
966 /* set api_retrain_never_freeze */
967 deb_info("set api_retrain_never_freeze\n");
968 if ((ret = af9005_write_ofdm_register(state->d, 0xaefb, 0x01)))
969 return ret;
970
971 /* load init script */
972 deb_info("load init script\n");
973 scriptlen = sizeof(script) / sizeof(RegDesc);
974 for (i = 0; i < scriptlen; i++) {
975 if ((ret =
976 af9005_write_register_bits(state->d, script[i].reg,
977 script[i].pos,
978 script[i].len, script[i].val)))
979 return ret;
980 /* save 3 bytes of original fcw */
981 if (script[i].reg == 0xae18)
982 temp2 = script[i].val;
983 if (script[i].reg == 0xae19)
984 temp1 = script[i].val;
985 if (script[i].reg == 0xae1a)
986 temp0 = script[i].val;
987
988 /* save original unplug threshold */
989 if (script[i].reg == xd_p_reg_unplug_th)
990 state->original_if_unplug_th = script[i].val;
991 if (script[i].reg == xd_p_reg_unplug_rf_gain_th)
992 state->original_rf_unplug_th = script[i].val;
993 if (script[i].reg == xd_p_reg_unplug_dtop_if_gain_th)
994 state->original_dtop_if_unplug_th = script[i].val;
995 if (script[i].reg == xd_p_reg_unplug_dtop_rf_gain_th)
996 state->original_dtop_rf_unplug_th = script[i].val;
997
998 }
999 state->original_fcw =
1000 ((u32) temp2 << 16) + ((u32) temp1 << 8) + (u32) temp0;
1001
1002
1003 /* save original TOPs */
1004 deb_info("save original TOPs\n");
1005
1006 /* RF TOP */
1007 ret =
1008 af9005_read_word_agc(state->d,
1009 xd_p_reg_aagc_rf_top_numerator_9_8,
1010 xd_p_reg_aagc_rf_top_numerator_7_0, 0, 2,
1011 &state->original_rf_top);
1012 if (ret)
1013 return ret;
1014
1015 /* IF TOP */
1016 ret =
1017 af9005_read_word_agc(state->d,
1018 xd_p_reg_aagc_if_top_numerator_9_8,
1019 xd_p_reg_aagc_if_top_numerator_7_0, 0, 2,
1020 &state->original_if_top);
1021 if (ret)
1022 return ret;
1023
1024 /* ACI 0 IF TOP */
1025 ret =
1026 af9005_read_word_agc(state->d, 0xA60E, 0xA60A, 4, 2,
1027 &state->original_aci0_if_top);
1028 if (ret)
1029 return ret;
1030
1031 /* ACI 1 IF TOP */
1032 ret =
1033 af9005_read_word_agc(state->d, 0xA60E, 0xA60B, 6, 2,
1034 &state->original_aci1_if_top);
1035 if (ret)
1036 return ret;
1037
1038 /* attach tuner and init */
1039 if (fe->ops.tuner_ops.release == NULL) {
1040 /* read tuner and board id from eeprom */
1041 ret = af9005_read_eeprom(adap->dev, 0xc6, buf, 2);
1042 if (ret) {
1043 err("Impossible to read EEPROM\n");
1044 return ret;
1045 }
1046 deb_info("Tuner id %d, board id %d\n", buf[0], buf[1]);
1047 switch (buf[0]) {
1048 case 2: /* MT2060 */
1049 /* read if1 from eeprom */
1050 ret = af9005_read_eeprom(adap->dev, 0xc8, buf, 2);
1051 if (ret) {
1052 err("Impossible to read EEPROM\n");
1053 return ret;
1054 }
1055 if1 = (u16) (buf[0] << 8) + buf[1];
1056 if (dvb_attach(mt2060_attach, fe, &adap->dev->i2c_adap,
1057 &af9005_mt2060_config, if1) == NULL) {
1058 deb_info("MT2060 attach failed\n");
1059 return -ENODEV;
1060 }
1061 break;
1062 case 3: /* QT1010 */
1063 case 9: /* QT1010B */
1064 if (dvb_attach(qt1010_attach, fe, &adap->dev->i2c_adap,
1065 &af9005_qt1010_config) ==NULL) {
1066 deb_info("QT1010 attach failed\n");
1067 return -ENODEV;
1068 }
1069 break;
1070 default:
1071 err("Unsupported tuner type %d", buf[0]);
1072 return -ENODEV;
1073 }
1074 ret = fe->ops.tuner_ops.init(fe);
1075 if (ret)
1076 return ret;
1077 }
1078
1079 deb_info("profit!\n");
1080 return 0;
1081 }
1082
1083 static int af9005_fe_sleep(struct dvb_frontend *fe)
1084 {
1085 return af9005_fe_power(fe, 0);
1086 }
1087
1088 static int af9005_ts_bus_ctrl(struct dvb_frontend *fe, int acquire)
1089 {
1090 struct af9005_fe_state *state = fe->demodulator_priv;
1091
1092 if (acquire) {
1093 state->opened++;
1094 } else {
1095
1096 state->opened--;
1097 if (!state->opened)
1098 af9005_led_control(state->d, 0);
1099 }
1100 return 0;
1101 }
1102
1103 static int af9005_fe_set_frontend(struct dvb_frontend *fe)
1104 {
1105 struct dtv_frontend_properties *fep = &fe->dtv_property_cache;
1106 struct af9005_fe_state *state = fe->demodulator_priv;
1107 int ret;
1108 u8 temp, temp0, temp1, temp2;
1109
1110 deb_info("af9005_fe_set_frontend freq %d bw %d\n", fep->frequency,
1111 fep->bandwidth_hz);
1112 if (fe->ops.tuner_ops.release == NULL) {
1113 err("Tuner not attached");
1114 return -ENODEV;
1115 }
1116
1117 deb_info("turn off led\n");
1118 /* not in the log */
1119 ret = af9005_led_control(state->d, 0);
1120 if (ret)
1121 return ret;
1122 /* not sure about the bits */
1123 ret = af9005_write_register_bits(state->d, XD_MP2IF_MISC, 2, 1, 0);
1124 if (ret)
1125 return ret;
1126
1127 /* set FCW to default value */
1128 deb_info("set FCW to default value\n");
1129 temp0 = (u8) (state->original_fcw & 0x000000ff);
1130 temp1 = (u8) ((state->original_fcw & 0x0000ff00) >> 8);
1131 temp2 = (u8) ((state->original_fcw & 0x00ff0000) >> 16);
1132 ret = af9005_write_ofdm_register(state->d, 0xae1a, temp0);
1133 if (ret)
1134 return ret;
1135 ret = af9005_write_ofdm_register(state->d, 0xae19, temp1);
1136 if (ret)
1137 return ret;
1138 ret = af9005_write_ofdm_register(state->d, 0xae18, temp2);
1139 if (ret)
1140 return ret;
1141
1142 /* restore original TOPs */
1143 deb_info("restore original TOPs\n");
1144 ret =
1145 af9005_write_word_agc(state->d,
1146 xd_p_reg_aagc_rf_top_numerator_9_8,
1147 xd_p_reg_aagc_rf_top_numerator_7_0, 0, 2,
1148 state->original_rf_top);
1149 if (ret)
1150 return ret;
1151 ret =
1152 af9005_write_word_agc(state->d,
1153 xd_p_reg_aagc_if_top_numerator_9_8,
1154 xd_p_reg_aagc_if_top_numerator_7_0, 0, 2,
1155 state->original_if_top);
1156 if (ret)
1157 return ret;
1158 ret =
1159 af9005_write_word_agc(state->d, 0xA60E, 0xA60A, 4, 2,
1160 state->original_aci0_if_top);
1161 if (ret)
1162 return ret;
1163 ret =
1164 af9005_write_word_agc(state->d, 0xA60E, 0xA60B, 6, 2,
1165 state->original_aci1_if_top);
1166 if (ret)
1167 return ret;
1168
1169 /* select bandwidth */
1170 deb_info("select bandwidth");
1171 ret = af9005_fe_select_bw(state->d, fep->bandwidth_hz);
1172 if (ret)
1173 return ret;
1174 ret = af9005_fe_program_cfoe(state->d, fep->bandwidth_hz);
1175 if (ret)
1176 return ret;
1177
1178 /* clear easy mode flag */
1179 deb_info("clear easy mode flag\n");
1180 ret = af9005_write_ofdm_register(state->d, 0xaefd, 0);
1181 if (ret)
1182 return ret;
1183
1184 /* set unplug threshold to original value */
1185 deb_info("set unplug threshold to original value\n");
1186 ret =
1187 af9005_write_ofdm_register(state->d, xd_p_reg_unplug_th,
1188 state->original_if_unplug_th);
1189 if (ret)
1190 return ret;
1191 /* set tuner */
1192 deb_info("set tuner\n");
1193 ret = fe->ops.tuner_ops.set_params(fe);
1194 if (ret)
1195 return ret;
1196
1197 /* trigger ofsm */
1198 deb_info("trigger ofsm\n");
1199 temp = 0;
1200 ret = af9005_write_tuner_registers(state->d, 0xffff, &temp, 1);
1201 if (ret)
1202 return ret;
1203
1204 /* clear retrain and freeze flag */
1205 deb_info("clear retrain and freeze flag\n");
1206 ret =
1207 af9005_write_register_bits(state->d,
1208 xd_p_reg_api_retrain_request,
1209 reg_api_retrain_request_pos, 2, 0);
1210 if (ret)
1211 return ret;
1212
1213 /* reset pre viterbi and post viterbi registers and statistics */
1214 af9005_reset_pre_viterbi(fe);
1215 af9005_reset_post_viterbi(fe);
1216 state->pre_vit_error_count = 0;
1217 state->pre_vit_bit_count = 0;
1218 state->ber = 0;
1219 state->post_vit_error_count = 0;
1220 /* state->unc = 0; commented out since it should be ever increasing */
1221 state->abort_count = 0;
1222
1223 state->next_status_check = jiffies;
1224 state->strong = -1;
1225
1226 return 0;
1227 }
1228
1229 static int af9005_fe_get_frontend(struct dvb_frontend *fe)
1230 {
1231 struct dtv_frontend_properties *fep = &fe->dtv_property_cache;
1232 struct af9005_fe_state *state = fe->demodulator_priv;
1233 int ret;
1234 u8 temp;
1235
1236 /* mode */
1237 ret =
1238 af9005_read_register_bits(state->d, xd_g_reg_tpsd_const,
1239 reg_tpsd_const_pos, reg_tpsd_const_len,
1240 &temp);
1241 if (ret)
1242 return ret;
1243 deb_info("===== fe_get_frontend_legacy = =============\n");
1244 deb_info("CONSTELLATION ");
1245 switch (temp) {
1246 case 0:
1247 fep->modulation = QPSK;
1248 deb_info("QPSK\n");
1249 break;
1250 case 1:
1251 fep->modulation = QAM_16;
1252 deb_info("QAM_16\n");
1253 break;
1254 case 2:
1255 fep->modulation = QAM_64;
1256 deb_info("QAM_64\n");
1257 break;
1258 }
1259
1260 /* tps hierarchy and alpha value */
1261 ret =
1262 af9005_read_register_bits(state->d, xd_g_reg_tpsd_hier,
1263 reg_tpsd_hier_pos, reg_tpsd_hier_len,
1264 &temp);
1265 if (ret)
1266 return ret;
1267 deb_info("HIERARCHY ");
1268 switch (temp) {
1269 case 0:
1270 fep->hierarchy = HIERARCHY_NONE;
1271 deb_info("NONE\n");
1272 break;
1273 case 1:
1274 fep->hierarchy = HIERARCHY_1;
1275 deb_info("1\n");
1276 break;
1277 case 2:
1278 fep->hierarchy = HIERARCHY_2;
1279 deb_info("2\n");
1280 break;
1281 case 3:
1282 fep->hierarchy = HIERARCHY_4;
1283 deb_info("4\n");
1284 break;
1285 }
1286
1287 /* high/low priority */
1288 ret =
1289 af9005_read_register_bits(state->d, xd_g_reg_dec_pri,
1290 reg_dec_pri_pos, reg_dec_pri_len, &temp);
1291 if (ret)
1292 return ret;
1293 /* if temp is set = high priority */
1294 deb_info("PRIORITY %s\n", temp ? "high" : "low");
1295
1296 /* high coderate */
1297 ret =
1298 af9005_read_register_bits(state->d, xd_g_reg_tpsd_hpcr,
1299 reg_tpsd_hpcr_pos, reg_tpsd_hpcr_len,
1300 &temp);
1301 if (ret)
1302 return ret;
1303 deb_info("CODERATE HP ");
1304 switch (temp) {
1305 case 0:
1306 fep->code_rate_HP = FEC_1_2;
1307 deb_info("FEC_1_2\n");
1308 break;
1309 case 1:
1310 fep->code_rate_HP = FEC_2_3;
1311 deb_info("FEC_2_3\n");
1312 break;
1313 case 2:
1314 fep->code_rate_HP = FEC_3_4;
1315 deb_info("FEC_3_4\n");
1316 break;
1317 case 3:
1318 fep->code_rate_HP = FEC_5_6;
1319 deb_info("FEC_5_6\n");
1320 break;
1321 case 4:
1322 fep->code_rate_HP = FEC_7_8;
1323 deb_info("FEC_7_8\n");
1324 break;
1325 }
1326
1327 /* low coderate */
1328 ret =
1329 af9005_read_register_bits(state->d, xd_g_reg_tpsd_lpcr,
1330 reg_tpsd_lpcr_pos, reg_tpsd_lpcr_len,
1331 &temp);
1332 if (ret)
1333 return ret;
1334 deb_info("CODERATE LP ");
1335 switch (temp) {
1336 case 0:
1337 fep->code_rate_LP = FEC_1_2;
1338 deb_info("FEC_1_2\n");
1339 break;
1340 case 1:
1341 fep->code_rate_LP = FEC_2_3;
1342 deb_info("FEC_2_3\n");
1343 break;
1344 case 2:
1345 fep->code_rate_LP = FEC_3_4;
1346 deb_info("FEC_3_4\n");
1347 break;
1348 case 3:
1349 fep->code_rate_LP = FEC_5_6;
1350 deb_info("FEC_5_6\n");
1351 break;
1352 case 4:
1353 fep->code_rate_LP = FEC_7_8;
1354 deb_info("FEC_7_8\n");
1355 break;
1356 }
1357
1358 /* guard interval */
1359 ret =
1360 af9005_read_register_bits(state->d, xd_g_reg_tpsd_gi,
1361 reg_tpsd_gi_pos, reg_tpsd_gi_len, &temp);
1362 if (ret)
1363 return ret;
1364 deb_info("GUARD INTERVAL ");
1365 switch (temp) {
1366 case 0:
1367 fep->guard_interval = GUARD_INTERVAL_1_32;
1368 deb_info("1_32\n");
1369 break;
1370 case 1:
1371 fep->guard_interval = GUARD_INTERVAL_1_16;
1372 deb_info("1_16\n");
1373 break;
1374 case 2:
1375 fep->guard_interval = GUARD_INTERVAL_1_8;
1376 deb_info("1_8\n");
1377 break;
1378 case 3:
1379 fep->guard_interval = GUARD_INTERVAL_1_4;
1380 deb_info("1_4\n");
1381 break;
1382 }
1383
1384 /* fft */
1385 ret =
1386 af9005_read_register_bits(state->d, xd_g_reg_tpsd_txmod,
1387 reg_tpsd_txmod_pos, reg_tpsd_txmod_len,
1388 &temp);
1389 if (ret)
1390 return ret;
1391 deb_info("TRANSMISSION MODE ");
1392 switch (temp) {
1393 case 0:
1394 fep->transmission_mode = TRANSMISSION_MODE_2K;
1395 deb_info("2K\n");
1396 break;
1397 case 1:
1398 fep->transmission_mode = TRANSMISSION_MODE_8K;
1399 deb_info("8K\n");
1400 break;
1401 }
1402
1403 /* bandwidth */
1404 ret =
1405 af9005_read_register_bits(state->d, xd_g_reg_bw, reg_bw_pos,
1406 reg_bw_len, &temp);
1407 deb_info("BANDWIDTH ");
1408 switch (temp) {
1409 case 0:
1410 fep->bandwidth_hz = 6000000;
1411 deb_info("6\n");
1412 break;
1413 case 1:
1414 fep->bandwidth_hz = 7000000;
1415 deb_info("7\n");
1416 break;
1417 case 2:
1418 fep->bandwidth_hz = 8000000;
1419 deb_info("8\n");
1420 break;
1421 }
1422 return 0;
1423 }
1424
1425 static void af9005_fe_release(struct dvb_frontend *fe)
1426 {
1427 struct af9005_fe_state *state =
1428 (struct af9005_fe_state *)fe->demodulator_priv;
1429 kfree(state);
1430 }
1431
1432 static struct dvb_frontend_ops af9005_fe_ops;
1433
1434 struct dvb_frontend *af9005_fe_attach(struct dvb_usb_device *d)
1435 {
1436 struct af9005_fe_state *state = NULL;
1437
1438 /* allocate memory for the internal state */
1439 state = kzalloc(sizeof(struct af9005_fe_state), GFP_KERNEL);
1440 if (state == NULL)
1441 goto error;
1442
1443 deb_info("attaching frontend af9005\n");
1444
1445 state->d = d;
1446 state->opened = 0;
1447
1448 memcpy(&state->frontend.ops, &af9005_fe_ops,
1449 sizeof(struct dvb_frontend_ops));
1450 state->frontend.demodulator_priv = state;
1451
1452 return &state->frontend;
1453 error:
1454 return NULL;
1455 }
1456
1457 static struct dvb_frontend_ops af9005_fe_ops = {
1458 .delsys = { SYS_DVBT },
1459 .info = {
1460 .name = "AF9005 USB DVB-T",
1461 .frequency_min = 44250000,
1462 .frequency_max = 867250000,
1463 .frequency_stepsize = 250000,
1464 .caps = FE_CAN_INVERSION_AUTO |
1465 FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
1466 FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
1467 FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 |
1468 FE_CAN_QAM_AUTO | FE_CAN_TRANSMISSION_MODE_AUTO |
1469 FE_CAN_GUARD_INTERVAL_AUTO | FE_CAN_RECOVER |
1470 FE_CAN_HIERARCHY_AUTO,
1471 },
1472
1473 .release = af9005_fe_release,
1474
1475 .init = af9005_fe_init,
1476 .sleep = af9005_fe_sleep,
1477 .ts_bus_ctrl = af9005_ts_bus_ctrl,
1478
1479 .set_frontend = af9005_fe_set_frontend,
1480 .get_frontend = af9005_fe_get_frontend,
1481
1482 .read_status = af9005_fe_read_status,
1483 .read_ber = af9005_fe_read_ber,
1484 .read_signal_strength = af9005_fe_read_signal_strength,
1485 .read_snr = af9005_fe_read_snr,
1486 .read_ucblocks = af9005_fe_read_unc_blocks,
1487 };
Linux with added FPC-III support