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ARM: dts: omap5: Add bus_dma_limit for L3 bus
[linux/fpc-iii.git] / sound / soc / codecs / adau17x1.c
blobb6352de077b52386301d34b10ddab7bffd179cd7
1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Common code for ADAU1X61 and ADAU1X81 codecs
4 *
5 * Copyright 2011-2014 Analog Devices Inc.
6 * Author: Lars-Peter Clausen <lars@metafoo.de>
7 */
8
9 #include <linux/module.h>
10 #include <linux/init.h>
11 #include <linux/clk.h>
12 #include <linux/delay.h>
13 #include <linux/slab.h>
14 #include <sound/core.h>
15 #include <sound/pcm.h>
16 #include <sound/pcm_params.h>
17 #include <sound/soc.h>
18 #include <sound/tlv.h>
19 #include <linux/gcd.h>
20 #include <linux/i2c.h>
21 #include <linux/spi/spi.h>
22 #include <linux/regmap.h>
23 #include <asm/unaligned.h>
24
25 #include "sigmadsp.h"
26 #include "adau17x1.h"
27 #include "adau-utils.h"
28
29 #define ADAU17X1_SAFELOAD_TARGET_ADDRESS 0x0006
30 #define ADAU17X1_SAFELOAD_TRIGGER 0x0007
31 #define ADAU17X1_SAFELOAD_DATA 0x0001
32 #define ADAU17X1_SAFELOAD_DATA_SIZE 20
33 #define ADAU17X1_WORD_SIZE 4
34
35 static const char * const adau17x1_capture_mixer_boost_text[] = {
36 "Normal operation", "Boost Level 1", "Boost Level 2", "Boost Level 3",
37 };
38
39 static SOC_ENUM_SINGLE_DECL(adau17x1_capture_boost_enum,
40 ADAU17X1_REC_POWER_MGMT, 5, adau17x1_capture_mixer_boost_text);
41
42 static const char * const adau17x1_mic_bias_mode_text[] = {
43 "Normal operation", "High performance",
44 };
45
46 static SOC_ENUM_SINGLE_DECL(adau17x1_mic_bias_mode_enum,
47 ADAU17X1_MICBIAS, 3, adau17x1_mic_bias_mode_text);
48
49 static const DECLARE_TLV_DB_MINMAX(adau17x1_digital_tlv, -9563, 0);
50
51 static const struct snd_kcontrol_new adau17x1_controls[] = {
52 SOC_DOUBLE_R_TLV("Digital Capture Volume",
53 ADAU17X1_LEFT_INPUT_DIGITAL_VOL,
54 ADAU17X1_RIGHT_INPUT_DIGITAL_VOL,
55 0, 0xff, 1, adau17x1_digital_tlv),
56 SOC_DOUBLE_R_TLV("Digital Playback Volume", ADAU17X1_DAC_CONTROL1,
57 ADAU17X1_DAC_CONTROL2, 0, 0xff, 1, adau17x1_digital_tlv),
58
59 SOC_SINGLE("ADC High Pass Filter Switch", ADAU17X1_ADC_CONTROL,
60 5, 1, 0),
61 SOC_SINGLE("Playback De-emphasis Switch", ADAU17X1_DAC_CONTROL0,
62 2, 1, 0),
63
64 SOC_ENUM("Capture Boost", adau17x1_capture_boost_enum),
65
66 SOC_ENUM("Mic Bias Mode", adau17x1_mic_bias_mode_enum),
67 };
68
69 static int adau17x1_setup_firmware(struct snd_soc_component *component,
70 unsigned int rate);
71
72 static int adau17x1_pll_event(struct snd_soc_dapm_widget *w,
73 struct snd_kcontrol *kcontrol, int event)
74 {
75 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
76 struct adau *adau = snd_soc_component_get_drvdata(component);
77
78 if (SND_SOC_DAPM_EVENT_ON(event)) {
79 adau->pll_regs[5] = 1;
80 } else {
81 adau->pll_regs[5] = 0;
82 /* Bypass the PLL when disabled, otherwise registers will become
83 * inaccessible. */
84 regmap_update_bits(adau->regmap, ADAU17X1_CLOCK_CONTROL,
85 ADAU17X1_CLOCK_CONTROL_CORECLK_SRC_PLL, 0);
86 }
87
88 /* The PLL register is 6 bytes long and can only be written at once. */
89 regmap_raw_write(adau->regmap, ADAU17X1_PLL_CONTROL,
90 adau->pll_regs, ARRAY_SIZE(adau->pll_regs));
91
92 if (SND_SOC_DAPM_EVENT_ON(event)) {
93 mdelay(5);
94 regmap_update_bits(adau->regmap, ADAU17X1_CLOCK_CONTROL,
95 ADAU17X1_CLOCK_CONTROL_CORECLK_SRC_PLL,
96 ADAU17X1_CLOCK_CONTROL_CORECLK_SRC_PLL);
97 }
98
99 return 0;
100 }
101
102 static int adau17x1_adc_fixup(struct snd_soc_dapm_widget *w,
103 struct snd_kcontrol *kcontrol, int event)
104 {
105 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
106 struct adau *adau = snd_soc_component_get_drvdata(component);
107
108 /*
109 * If we are capturing, toggle the ADOSR bit in Converter Control 0 to
110 * avoid losing SNR (workaround from ADI). This must be done after
111 * the ADC(s) have been enabled. According to the data sheet, it is
112 * normally illegal to set this bit when the sampling rate is 96 kHz,
113 * but according to ADI it is acceptable for this workaround.
114 */
115 regmap_update_bits(adau->regmap, ADAU17X1_CONVERTER0,
116 ADAU17X1_CONVERTER0_ADOSR, ADAU17X1_CONVERTER0_ADOSR);
117 regmap_update_bits(adau->regmap, ADAU17X1_CONVERTER0,
118 ADAU17X1_CONVERTER0_ADOSR, 0);
119
120 return 0;
121 }
122
123 static const char * const adau17x1_mono_stereo_text[] = {
124 "Stereo",
125 "Mono Left Channel (L+R)",
126 "Mono Right Channel (L+R)",
127 "Mono (L+R)",
128 };
129
130 static SOC_ENUM_SINGLE_DECL(adau17x1_dac_mode_enum,
131 ADAU17X1_DAC_CONTROL0, 6, adau17x1_mono_stereo_text);
132
133 static const struct snd_kcontrol_new adau17x1_dac_mode_mux =
134 SOC_DAPM_ENUM("DAC Mono-Stereo-Mode", adau17x1_dac_mode_enum);
135
136 static const struct snd_soc_dapm_widget adau17x1_dapm_widgets[] = {
137 SND_SOC_DAPM_SUPPLY_S("PLL", 3, SND_SOC_NOPM, 0, 0, adau17x1_pll_event,
138 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
139
140 SND_SOC_DAPM_SUPPLY("AIFCLK", SND_SOC_NOPM, 0, 0, NULL, 0),
141
142 SND_SOC_DAPM_SUPPLY("MICBIAS", ADAU17X1_MICBIAS, 0, 0, NULL, 0),
143
144 SND_SOC_DAPM_SUPPLY("Left Playback Enable", ADAU17X1_PLAY_POWER_MGMT,
145 0, 0, NULL, 0),
146 SND_SOC_DAPM_SUPPLY("Right Playback Enable", ADAU17X1_PLAY_POWER_MGMT,
147 1, 0, NULL, 0),
148
149 SND_SOC_DAPM_MUX("Left DAC Mode Mux", SND_SOC_NOPM, 0, 0,
150 &adau17x1_dac_mode_mux),
151 SND_SOC_DAPM_MUX("Right DAC Mode Mux", SND_SOC_NOPM, 0, 0,
152 &adau17x1_dac_mode_mux),
153
154 SND_SOC_DAPM_ADC_E("Left Decimator", NULL, ADAU17X1_ADC_CONTROL, 0, 0,
155 adau17x1_adc_fixup, SND_SOC_DAPM_POST_PMU),
156 SND_SOC_DAPM_ADC("Right Decimator", NULL, ADAU17X1_ADC_CONTROL, 1, 0),
157 SND_SOC_DAPM_DAC("Left DAC", NULL, ADAU17X1_DAC_CONTROL0, 0, 0),
158 SND_SOC_DAPM_DAC("Right DAC", NULL, ADAU17X1_DAC_CONTROL0, 1, 0),
159 };
160
161 static const struct snd_soc_dapm_route adau17x1_dapm_routes[] = {
162 { "Left Decimator", NULL, "SYSCLK" },
163 { "Right Decimator", NULL, "SYSCLK" },
164 { "Left DAC", NULL, "SYSCLK" },
165 { "Right DAC", NULL, "SYSCLK" },
166 { "Capture", NULL, "SYSCLK" },
167 { "Playback", NULL, "SYSCLK" },
168
169 { "Left DAC", NULL, "Left DAC Mode Mux" },
170 { "Right DAC", NULL, "Right DAC Mode Mux" },
171
172 { "Capture", NULL, "AIFCLK" },
173 { "Playback", NULL, "AIFCLK" },
174 };
175
176 static const struct snd_soc_dapm_route adau17x1_dapm_pll_route = {
177 "SYSCLK", NULL, "PLL",
178 };
179
180 /*
181 * The MUX register for the Capture and Playback MUXs selects either DSP as
182 * source/destination or one of the TDM slots. The TDM slot is selected via
183 * snd_soc_dai_set_tdm_slot(), so we only expose whether to go to the DSP or
184 * directly to the DAI interface with this control.
185 */
186 static int adau17x1_dsp_mux_enum_put(struct snd_kcontrol *kcontrol,
187 struct snd_ctl_elem_value *ucontrol)
188 {
189 struct snd_soc_component *component = snd_soc_dapm_kcontrol_component(kcontrol);
190 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
191 struct adau *adau = snd_soc_component_get_drvdata(component);
192 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
193 struct snd_soc_dapm_update update = {};
194 unsigned int stream = e->shift_l;
195 unsigned int val, change;
196 int reg;
197
198 if (ucontrol->value.enumerated.item[0] >= e->items)
199 return -EINVAL;
200
201 switch (ucontrol->value.enumerated.item[0]) {
202 case 0:
203 val = 0;
204 adau->dsp_bypass[stream] = false;
205 break;
206 default:
207 val = (adau->tdm_slot[stream] * 2) + 1;
208 adau->dsp_bypass[stream] = true;
209 break;
210 }
211
212 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
213 reg = ADAU17X1_SERIAL_INPUT_ROUTE;
214 else
215 reg = ADAU17X1_SERIAL_OUTPUT_ROUTE;
216
217 change = snd_soc_component_test_bits(component, reg, 0xff, val);
218 if (change) {
219 update.kcontrol = kcontrol;
220 update.mask = 0xff;
221 update.reg = reg;
222 update.val = val;
223
224 snd_soc_dapm_mux_update_power(dapm, kcontrol,
225 ucontrol->value.enumerated.item[0], e, &update);
226 }
227
228 return change;
229 }
230
231 static int adau17x1_dsp_mux_enum_get(struct snd_kcontrol *kcontrol,
232 struct snd_ctl_elem_value *ucontrol)
233 {
234 struct snd_soc_component *component = snd_soc_dapm_kcontrol_component(kcontrol);
235 struct adau *adau = snd_soc_component_get_drvdata(component);
236 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
237 unsigned int stream = e->shift_l;
238 unsigned int reg, val;
239 int ret;
240
241 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
242 reg = ADAU17X1_SERIAL_INPUT_ROUTE;
243 else
244 reg = ADAU17X1_SERIAL_OUTPUT_ROUTE;
245
246 ret = regmap_read(adau->regmap, reg, &val);
247 if (ret)
248 return ret;
249
250 if (val != 0)
251 val = 1;
252 ucontrol->value.enumerated.item[0] = val;
253
254 return 0;
255 }
256
257 #define DECLARE_ADAU17X1_DSP_MUX_CTRL(_name, _label, _stream, _text) \
258 const struct snd_kcontrol_new _name = \
259 SOC_DAPM_ENUM_EXT(_label, (const struct soc_enum)\
260 SOC_ENUM_SINGLE(SND_SOC_NOPM, _stream, \
261 ARRAY_SIZE(_text), _text), \
262 adau17x1_dsp_mux_enum_get, adau17x1_dsp_mux_enum_put)
263
264 static const char * const adau17x1_dac_mux_text[] = {
265 "DSP",
266 "AIFIN",
267 };
268
269 static const char * const adau17x1_capture_mux_text[] = {
270 "DSP",
271 "Decimator",
272 };
273
274 static DECLARE_ADAU17X1_DSP_MUX_CTRL(adau17x1_dac_mux, "DAC Playback Mux",
275 SNDRV_PCM_STREAM_PLAYBACK, adau17x1_dac_mux_text);
276
277 static DECLARE_ADAU17X1_DSP_MUX_CTRL(adau17x1_capture_mux, "Capture Mux",
278 SNDRV_PCM_STREAM_CAPTURE, adau17x1_capture_mux_text);
279
280 static const struct snd_soc_dapm_widget adau17x1_dsp_dapm_widgets[] = {
281 SND_SOC_DAPM_PGA("DSP", ADAU17X1_DSP_RUN, 0, 0, NULL, 0),
282 SND_SOC_DAPM_SIGGEN("DSP Siggen"),
283
284 SND_SOC_DAPM_MUX("DAC Playback Mux", SND_SOC_NOPM, 0, 0,
285 &adau17x1_dac_mux),
286 SND_SOC_DAPM_MUX("Capture Mux", SND_SOC_NOPM, 0, 0,
287 &adau17x1_capture_mux),
288 };
289
290 static const struct snd_soc_dapm_route adau17x1_dsp_dapm_routes[] = {
291 { "DAC Playback Mux", "DSP", "DSP" },
292 { "DAC Playback Mux", "AIFIN", "Playback" },
293
294 { "Left DAC Mode Mux", "Stereo", "DAC Playback Mux" },
295 { "Left DAC Mode Mux", "Mono (L+R)", "DAC Playback Mux" },
296 { "Left DAC Mode Mux", "Mono Left Channel (L+R)", "DAC Playback Mux" },
297 { "Right DAC Mode Mux", "Stereo", "DAC Playback Mux" },
298 { "Right DAC Mode Mux", "Mono (L+R)", "DAC Playback Mux" },
299 { "Right DAC Mode Mux", "Mono Right Channel (L+R)", "DAC Playback Mux" },
300
301 { "Capture Mux", "DSP", "DSP" },
302 { "Capture Mux", "Decimator", "Left Decimator" },
303 { "Capture Mux", "Decimator", "Right Decimator" },
304
305 { "Capture", NULL, "Capture Mux" },
306
307 { "DSP", NULL, "DSP Siggen" },
308
309 { "DSP", NULL, "Left Decimator" },
310 { "DSP", NULL, "Right Decimator" },
311 { "DSP", NULL, "Playback" },
312 };
313
314 static const struct snd_soc_dapm_route adau17x1_no_dsp_dapm_routes[] = {
315 { "Left DAC Mode Mux", "Stereo", "Playback" },
316 { "Left DAC Mode Mux", "Mono (L+R)", "Playback" },
317 { "Left DAC Mode Mux", "Mono Left Channel (L+R)", "Playback" },
318 { "Right DAC Mode Mux", "Stereo", "Playback" },
319 { "Right DAC Mode Mux", "Mono (L+R)", "Playback" },
320 { "Right DAC Mode Mux", "Mono Right Channel (L+R)", "Playback" },
321 { "Capture", NULL, "Left Decimator" },
322 { "Capture", NULL, "Right Decimator" },
323 };
324
325 static bool adau17x1_has_dsp(struct adau *adau)
326 {
327 switch (adau->type) {
328 case ADAU1761:
329 case ADAU1381:
330 case ADAU1781:
331 return true;
332 default:
333 return false;
334 }
335 }
336
337 static bool adau17x1_has_safeload(struct adau *adau)
338 {
339 switch (adau->type) {
340 case ADAU1761:
341 case ADAU1781:
342 return true;
343 default:
344 return false;
345 }
346 }
347
348 static int adau17x1_set_dai_pll(struct snd_soc_dai *dai, int pll_id,
349 int source, unsigned int freq_in, unsigned int freq_out)
350 {
351 struct snd_soc_component *component = dai->component;
352 struct adau *adau = snd_soc_component_get_drvdata(component);
353 int ret;
354
355 if (freq_in < 8000000 || freq_in > 27000000)
356 return -EINVAL;
357
358 ret = adau_calc_pll_cfg(freq_in, freq_out, adau->pll_regs);
359 if (ret < 0)
360 return ret;
361
362 /* The PLL register is 6 bytes long and can only be written at once. */
363 ret = regmap_raw_write(adau->regmap, ADAU17X1_PLL_CONTROL,
364 adau->pll_regs, ARRAY_SIZE(adau->pll_regs));
365 if (ret)
366 return ret;
367
368 adau->pll_freq = freq_out;
369
370 return 0;
371 }
372
373 static int adau17x1_set_dai_sysclk(struct snd_soc_dai *dai,
374 int clk_id, unsigned int freq, int dir)
375 {
376 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(dai->component);
377 struct adau *adau = snd_soc_component_get_drvdata(dai->component);
378 bool is_pll;
379 bool was_pll;
380
381 switch (clk_id) {
382 case ADAU17X1_CLK_SRC_MCLK:
383 is_pll = false;
384 break;
385 case ADAU17X1_CLK_SRC_PLL_AUTO:
386 if (!adau->mclk)
387 return -EINVAL;
388 /* Fall-through */
389 case ADAU17X1_CLK_SRC_PLL:
390 is_pll = true;
391 break;
392 default:
393 return -EINVAL;
394 }
395
396 switch (adau->clk_src) {
397 case ADAU17X1_CLK_SRC_MCLK:
398 was_pll = false;
399 break;
400 case ADAU17X1_CLK_SRC_PLL:
401 case ADAU17X1_CLK_SRC_PLL_AUTO:
402 was_pll = true;
403 break;
404 default:
405 return -EINVAL;
406 }
407
408 adau->sysclk = freq;
409
410 if (is_pll != was_pll) {
411 if (is_pll) {
412 snd_soc_dapm_add_routes(dapm,
413 &adau17x1_dapm_pll_route, 1);
414 } else {
415 snd_soc_dapm_del_routes(dapm,
416 &adau17x1_dapm_pll_route, 1);
417 }
418 }
419
420 adau->clk_src = clk_id;
421
422 return 0;
423 }
424
425 static int adau17x1_auto_pll(struct snd_soc_dai *dai,
426 struct snd_pcm_hw_params *params)
427 {
428 struct adau *adau = snd_soc_dai_get_drvdata(dai);
429 unsigned int pll_rate;
430
431 switch (params_rate(params)) {
432 case 48000:
433 case 8000:
434 case 12000:
435 case 16000:
436 case 24000:
437 case 32000:
438 case 96000:
439 pll_rate = 48000 * 1024;
440 break;
441 case 44100:
442 case 7350:
443 case 11025:
444 case 14700:
445 case 22050:
446 case 29400:
447 case 88200:
448 pll_rate = 44100 * 1024;
449 break;
450 default:
451 return -EINVAL;
452 }
453
454 return adau17x1_set_dai_pll(dai, ADAU17X1_PLL, ADAU17X1_PLL_SRC_MCLK,
455 clk_get_rate(adau->mclk), pll_rate);
456 }
457
458 static int adau17x1_hw_params(struct snd_pcm_substream *substream,
459 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
460 {
461 struct snd_soc_component *component = dai->component;
462 struct adau *adau = snd_soc_component_get_drvdata(component);
463 unsigned int val, div, dsp_div;
464 unsigned int freq;
465 int ret;
466
467 switch (adau->clk_src) {
468 case ADAU17X1_CLK_SRC_PLL_AUTO:
469 ret = adau17x1_auto_pll(dai, params);
470 if (ret)
471 return ret;
472 /* Fall-through */
473 case ADAU17X1_CLK_SRC_PLL:
474 freq = adau->pll_freq;
475 break;
476 default:
477 freq = adau->sysclk;
478 break;
479 }
480
481 if (freq % params_rate(params) != 0)
482 return -EINVAL;
483
484 switch (freq / params_rate(params)) {
485 case 1024: /* fs */
486 div = 0;
487 dsp_div = 1;
488 break;
489 case 6144: /* fs / 6 */
490 div = 1;
491 dsp_div = 6;
492 break;
493 case 4096: /* fs / 4 */
494 div = 2;
495 dsp_div = 5;
496 break;
497 case 3072: /* fs / 3 */
498 div = 3;
499 dsp_div = 4;
500 break;
501 case 2048: /* fs / 2 */
502 div = 4;
503 dsp_div = 3;
504 break;
505 case 1536: /* fs / 1.5 */
506 div = 5;
507 dsp_div = 2;
508 break;
509 case 512: /* fs / 0.5 */
510 div = 6;
511 dsp_div = 0;
512 break;
513 default:
514 return -EINVAL;
515 }
516
517 regmap_update_bits(adau->regmap, ADAU17X1_CONVERTER0,
518 ADAU17X1_CONVERTER0_CONVSR_MASK, div);
519 if (adau17x1_has_dsp(adau)) {
520 regmap_write(adau->regmap, ADAU17X1_SERIAL_SAMPLING_RATE, div);
521 regmap_write(adau->regmap, ADAU17X1_DSP_SAMPLING_RATE, dsp_div);
522 }
523
524 if (adau->sigmadsp) {
525 ret = adau17x1_setup_firmware(component, params_rate(params));
526 if (ret < 0)
527 return ret;
528 }
529
530 if (adau->dai_fmt != SND_SOC_DAIFMT_RIGHT_J)
531 return 0;
532
533 switch (params_width(params)) {
534 case 16:
535 val = ADAU17X1_SERIAL_PORT1_DELAY16;
536 break;
537 case 24:
538 val = ADAU17X1_SERIAL_PORT1_DELAY8;
539 break;
540 case 32:
541 val = ADAU17X1_SERIAL_PORT1_DELAY0;
542 break;
543 default:
544 return -EINVAL;
545 }
546
547 return regmap_update_bits(adau->regmap, ADAU17X1_SERIAL_PORT1,
548 ADAU17X1_SERIAL_PORT1_DELAY_MASK, val);
549 }
550
551 static int adau17x1_set_dai_fmt(struct snd_soc_dai *dai,
552 unsigned int fmt)
553 {
554 struct adau *adau = snd_soc_component_get_drvdata(dai->component);
555 unsigned int ctrl0, ctrl1;
556 int lrclk_pol;
557
558 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
559 case SND_SOC_DAIFMT_CBM_CFM:
560 ctrl0 = ADAU17X1_SERIAL_PORT0_MASTER;
561 adau->master = true;
562 break;
563 case SND_SOC_DAIFMT_CBS_CFS:
564 ctrl0 = 0;
565 adau->master = false;
566 break;
567 default:
568 return -EINVAL;
569 }
570
571 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
572 case SND_SOC_DAIFMT_I2S:
573 lrclk_pol = 0;
574 ctrl1 = ADAU17X1_SERIAL_PORT1_DELAY1;
575 break;
576 case SND_SOC_DAIFMT_LEFT_J:
577 case SND_SOC_DAIFMT_RIGHT_J:
578 lrclk_pol = 1;
579 ctrl1 = ADAU17X1_SERIAL_PORT1_DELAY0;
580 break;
581 case SND_SOC_DAIFMT_DSP_A:
582 lrclk_pol = 1;
583 ctrl0 |= ADAU17X1_SERIAL_PORT0_PULSE_MODE;
584 ctrl1 = ADAU17X1_SERIAL_PORT1_DELAY1;
585 break;
586 case SND_SOC_DAIFMT_DSP_B:
587 lrclk_pol = 1;
588 ctrl0 |= ADAU17X1_SERIAL_PORT0_PULSE_MODE;
589 ctrl1 = ADAU17X1_SERIAL_PORT1_DELAY0;
590 break;
591 default:
592 return -EINVAL;
593 }
594
595 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
596 case SND_SOC_DAIFMT_NB_NF:
597 break;
598 case SND_SOC_DAIFMT_IB_NF:
599 ctrl0 |= ADAU17X1_SERIAL_PORT0_BCLK_POL;
600 break;
601 case SND_SOC_DAIFMT_NB_IF:
602 lrclk_pol = !lrclk_pol;
603 break;
604 case SND_SOC_DAIFMT_IB_IF:
605 ctrl0 |= ADAU17X1_SERIAL_PORT0_BCLK_POL;
606 lrclk_pol = !lrclk_pol;
607 break;
608 default:
609 return -EINVAL;
610 }
611
612 if (lrclk_pol)
613 ctrl0 |= ADAU17X1_SERIAL_PORT0_LRCLK_POL;
614
615 regmap_write(adau->regmap, ADAU17X1_SERIAL_PORT0, ctrl0);
616 regmap_write(adau->regmap, ADAU17X1_SERIAL_PORT1, ctrl1);
617
618 adau->dai_fmt = fmt & SND_SOC_DAIFMT_FORMAT_MASK;
619
620 return 0;
621 }
622
623 static int adau17x1_set_dai_tdm_slot(struct snd_soc_dai *dai,
624 unsigned int tx_mask, unsigned int rx_mask, int slots, int slot_width)
625 {
626 struct adau *adau = snd_soc_component_get_drvdata(dai->component);
627 unsigned int ser_ctrl0, ser_ctrl1;
628 unsigned int conv_ctrl0, conv_ctrl1;
629
630 /* I2S mode */
631 if (slots == 0) {
632 slots = 2;
633 rx_mask = 3;
634 tx_mask = 3;
635 slot_width = 32;
636 }
637
638 switch (slots) {
639 case 2:
640 ser_ctrl0 = ADAU17X1_SERIAL_PORT0_STEREO;
641 break;
642 case 4:
643 ser_ctrl0 = ADAU17X1_SERIAL_PORT0_TDM4;
644 break;
645 case 8:
646 if (adau->type == ADAU1361)
647 return -EINVAL;
648
649 ser_ctrl0 = ADAU17X1_SERIAL_PORT0_TDM8;
650 break;
651 default:
652 return -EINVAL;
653 }
654
655 switch (slot_width * slots) {
656 case 32:
657 if (adau->type == ADAU1761)
658 return -EINVAL;
659
660 ser_ctrl1 = ADAU17X1_SERIAL_PORT1_BCLK32;
661 break;
662 case 64:
663 ser_ctrl1 = ADAU17X1_SERIAL_PORT1_BCLK64;
664 break;
665 case 48:
666 ser_ctrl1 = ADAU17X1_SERIAL_PORT1_BCLK48;
667 break;
668 case 128:
669 ser_ctrl1 = ADAU17X1_SERIAL_PORT1_BCLK128;
670 break;
671 case 256:
672 if (adau->type == ADAU1361)
673 return -EINVAL;
674
675 ser_ctrl1 = ADAU17X1_SERIAL_PORT1_BCLK256;
676 break;
677 default:
678 return -EINVAL;
679 }
680
681 switch (rx_mask) {
682 case 0x03:
683 conv_ctrl1 = ADAU17X1_CONVERTER1_ADC_PAIR(1);
684 adau->tdm_slot[SNDRV_PCM_STREAM_CAPTURE] = 0;
685 break;
686 case 0x0c:
687 conv_ctrl1 = ADAU17X1_CONVERTER1_ADC_PAIR(2);
688 adau->tdm_slot[SNDRV_PCM_STREAM_CAPTURE] = 1;
689 break;
690 case 0x30:
691 conv_ctrl1 = ADAU17X1_CONVERTER1_ADC_PAIR(3);
692 adau->tdm_slot[SNDRV_PCM_STREAM_CAPTURE] = 2;
693 break;
694 case 0xc0:
695 conv_ctrl1 = ADAU17X1_CONVERTER1_ADC_PAIR(4);
696 adau->tdm_slot[SNDRV_PCM_STREAM_CAPTURE] = 3;
697 break;
698 default:
699 return -EINVAL;
700 }
701
702 switch (tx_mask) {
703 case 0x03:
704 conv_ctrl0 = ADAU17X1_CONVERTER0_DAC_PAIR(1);
705 adau->tdm_slot[SNDRV_PCM_STREAM_PLAYBACK] = 0;
706 break;
707 case 0x0c:
708 conv_ctrl0 = ADAU17X1_CONVERTER0_DAC_PAIR(2);
709 adau->tdm_slot[SNDRV_PCM_STREAM_PLAYBACK] = 1;
710 break;
711 case 0x30:
712 conv_ctrl0 = ADAU17X1_CONVERTER0_DAC_PAIR(3);
713 adau->tdm_slot[SNDRV_PCM_STREAM_PLAYBACK] = 2;
714 break;
715 case 0xc0:
716 conv_ctrl0 = ADAU17X1_CONVERTER0_DAC_PAIR(4);
717 adau->tdm_slot[SNDRV_PCM_STREAM_PLAYBACK] = 3;
718 break;
719 default:
720 return -EINVAL;
721 }
722
723 regmap_update_bits(adau->regmap, ADAU17X1_CONVERTER0,
724 ADAU17X1_CONVERTER0_DAC_PAIR_MASK, conv_ctrl0);
725 regmap_update_bits(adau->regmap, ADAU17X1_CONVERTER1,
726 ADAU17X1_CONVERTER1_ADC_PAIR_MASK, conv_ctrl1);
727 regmap_update_bits(adau->regmap, ADAU17X1_SERIAL_PORT0,
728 ADAU17X1_SERIAL_PORT0_TDM_MASK, ser_ctrl0);
729 regmap_update_bits(adau->regmap, ADAU17X1_SERIAL_PORT1,
730 ADAU17X1_SERIAL_PORT1_BCLK_MASK, ser_ctrl1);
731
732 if (!adau17x1_has_dsp(adau))
733 return 0;
734
735 if (adau->dsp_bypass[SNDRV_PCM_STREAM_PLAYBACK]) {
736 regmap_write(adau->regmap, ADAU17X1_SERIAL_INPUT_ROUTE,
737 (adau->tdm_slot[SNDRV_PCM_STREAM_PLAYBACK] * 2) + 1);
738 }
739
740 if (adau->dsp_bypass[SNDRV_PCM_STREAM_CAPTURE]) {
741 regmap_write(adau->regmap, ADAU17X1_SERIAL_OUTPUT_ROUTE,
742 (adau->tdm_slot[SNDRV_PCM_STREAM_CAPTURE] * 2) + 1);
743 }
744
745 return 0;
746 }
747
748 static int adau17x1_startup(struct snd_pcm_substream *substream,
749 struct snd_soc_dai *dai)
750 {
751 struct adau *adau = snd_soc_component_get_drvdata(dai->component);
752
753 if (adau->sigmadsp)
754 return sigmadsp_restrict_params(adau->sigmadsp, substream);
755
756 return 0;
757 }
758
759 const struct snd_soc_dai_ops adau17x1_dai_ops = {
760 .hw_params = adau17x1_hw_params,
761 .set_sysclk = adau17x1_set_dai_sysclk,
762 .set_fmt = adau17x1_set_dai_fmt,
763 .set_pll = adau17x1_set_dai_pll,
764 .set_tdm_slot = adau17x1_set_dai_tdm_slot,
765 .startup = adau17x1_startup,
766 };
767 EXPORT_SYMBOL_GPL(adau17x1_dai_ops);
768
769 int adau17x1_set_micbias_voltage(struct snd_soc_component *component,
770 enum adau17x1_micbias_voltage micbias)
771 {
772 struct adau *adau = snd_soc_component_get_drvdata(component);
773
774 switch (micbias) {
775 case ADAU17X1_MICBIAS_0_90_AVDD:
776 case ADAU17X1_MICBIAS_0_65_AVDD:
777 break;
778 default:
779 return -EINVAL;
780 }
781
782 return regmap_write(adau->regmap, ADAU17X1_MICBIAS, micbias << 2);
783 }
784 EXPORT_SYMBOL_GPL(adau17x1_set_micbias_voltage);
785
786 bool adau17x1_precious_register(struct device *dev, unsigned int reg)
787 {
788 /* SigmaDSP parameter memory */
789 if (reg < 0x400)
790 return true;
791
792 return false;
793 }
794 EXPORT_SYMBOL_GPL(adau17x1_precious_register);
795
796 bool adau17x1_readable_register(struct device *dev, unsigned int reg)
797 {
798 /* SigmaDSP parameter memory */
799 if (reg < 0x400)
800 return true;
801
802 switch (reg) {
803 case ADAU17X1_CLOCK_CONTROL:
804 case ADAU17X1_PLL_CONTROL:
805 case ADAU17X1_REC_POWER_MGMT:
806 case ADAU17X1_MICBIAS:
807 case ADAU17X1_SERIAL_PORT0:
808 case ADAU17X1_SERIAL_PORT1:
809 case ADAU17X1_CONVERTER0:
810 case ADAU17X1_CONVERTER1:
811 case ADAU17X1_LEFT_INPUT_DIGITAL_VOL:
812 case ADAU17X1_RIGHT_INPUT_DIGITAL_VOL:
813 case ADAU17X1_ADC_CONTROL:
814 case ADAU17X1_PLAY_POWER_MGMT:
815 case ADAU17X1_DAC_CONTROL0:
816 case ADAU17X1_DAC_CONTROL1:
817 case ADAU17X1_DAC_CONTROL2:
818 case ADAU17X1_SERIAL_PORT_PAD:
819 case ADAU17X1_CONTROL_PORT_PAD0:
820 case ADAU17X1_CONTROL_PORT_PAD1:
821 case ADAU17X1_DSP_SAMPLING_RATE:
822 case ADAU17X1_SERIAL_INPUT_ROUTE:
823 case ADAU17X1_SERIAL_OUTPUT_ROUTE:
824 case ADAU17X1_DSP_ENABLE:
825 case ADAU17X1_DSP_RUN:
826 case ADAU17X1_SERIAL_SAMPLING_RATE:
827 return true;
828 default:
829 break;
830 }
831 return false;
832 }
833 EXPORT_SYMBOL_GPL(adau17x1_readable_register);
834
835 bool adau17x1_volatile_register(struct device *dev, unsigned int reg)
836 {
837 /* SigmaDSP parameter and program memory */
838 if (reg < 0x4000)
839 return true;
840
841 switch (reg) {
842 /* The PLL register is 6 bytes long */
843 case ADAU17X1_PLL_CONTROL:
844 case ADAU17X1_PLL_CONTROL + 1:
845 case ADAU17X1_PLL_CONTROL + 2:
846 case ADAU17X1_PLL_CONTROL + 3:
847 case ADAU17X1_PLL_CONTROL + 4:
848 case ADAU17X1_PLL_CONTROL + 5:
849 return true;
850 default:
851 break;
852 }
853
854 return false;
855 }
856 EXPORT_SYMBOL_GPL(adau17x1_volatile_register);
857
858 static int adau17x1_setup_firmware(struct snd_soc_component *component,
859 unsigned int rate)
860 {
861 int ret;
862 int dspsr, dsp_run;
863 struct adau *adau = snd_soc_component_get_drvdata(component);
864 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
865
866 /* Check if sample rate is the same as before. If it is there is no
867 * point in performing the below steps as the call to
868 * sigmadsp_setup(...) will return directly when it finds the sample
869 * rate to be the same as before. By checking this we can prevent an
870 * audiable popping noise which occours when toggling DSP_RUN.
871 */
872 if (adau->sigmadsp->current_samplerate == rate)
873 return 0;
874
875 snd_soc_dapm_mutex_lock(dapm);
876
877 ret = regmap_read(adau->regmap, ADAU17X1_DSP_SAMPLING_RATE, &dspsr);
878 if (ret)
879 goto err;
880
881 ret = regmap_read(adau->regmap, ADAU17X1_DSP_RUN, &dsp_run);
882 if (ret)
883 goto err;
884
885 regmap_write(adau->regmap, ADAU17X1_DSP_ENABLE, 1);
886 regmap_write(adau->regmap, ADAU17X1_DSP_SAMPLING_RATE, 0xf);
887 regmap_write(adau->regmap, ADAU17X1_DSP_RUN, 0);
888
889 ret = sigmadsp_setup(adau->sigmadsp, rate);
890 if (ret) {
891 regmap_write(adau->regmap, ADAU17X1_DSP_ENABLE, 0);
892 goto err;
893 }
894 regmap_write(adau->regmap, ADAU17X1_DSP_SAMPLING_RATE, dspsr);
895 regmap_write(adau->regmap, ADAU17X1_DSP_RUN, dsp_run);
896
897 err:
898 snd_soc_dapm_mutex_unlock(dapm);
899
900 return ret;
901 }
902
903 int adau17x1_add_widgets(struct snd_soc_component *component)
904 {
905 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
906 struct adau *adau = snd_soc_component_get_drvdata(component);
907 int ret;
908
909 ret = snd_soc_add_component_controls(component, adau17x1_controls,
910 ARRAY_SIZE(adau17x1_controls));
911 if (ret)
912 return ret;
913 ret = snd_soc_dapm_new_controls(dapm, adau17x1_dapm_widgets,
914 ARRAY_SIZE(adau17x1_dapm_widgets));
915 if (ret)
916 return ret;
917
918 if (adau17x1_has_dsp(adau)) {
919 ret = snd_soc_dapm_new_controls(dapm, adau17x1_dsp_dapm_widgets,
920 ARRAY_SIZE(adau17x1_dsp_dapm_widgets));
921 if (ret)
922 return ret;
923
924 if (!adau->sigmadsp)
925 return 0;
926
927 ret = sigmadsp_attach(adau->sigmadsp, component);
928 if (ret) {
929 dev_err(component->dev, "Failed to attach firmware: %d\n",
930 ret);
931 return ret;
932 }
933 }
934
935 return 0;
936 }
937 EXPORT_SYMBOL_GPL(adau17x1_add_widgets);
938
939 int adau17x1_add_routes(struct snd_soc_component *component)
940 {
941 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
942 struct adau *adau = snd_soc_component_get_drvdata(component);
943 int ret;
944
945 ret = snd_soc_dapm_add_routes(dapm, adau17x1_dapm_routes,
946 ARRAY_SIZE(adau17x1_dapm_routes));
947 if (ret)
948 return ret;
949
950 if (adau17x1_has_dsp(adau)) {
951 ret = snd_soc_dapm_add_routes(dapm, adau17x1_dsp_dapm_routes,
952 ARRAY_SIZE(adau17x1_dsp_dapm_routes));
953 } else {
954 ret = snd_soc_dapm_add_routes(dapm, adau17x1_no_dsp_dapm_routes,
955 ARRAY_SIZE(adau17x1_no_dsp_dapm_routes));
956 }
957
958 if (adau->clk_src != ADAU17X1_CLK_SRC_MCLK)
959 snd_soc_dapm_add_routes(dapm, &adau17x1_dapm_pll_route, 1);
960
961 return ret;
962 }
963 EXPORT_SYMBOL_GPL(adau17x1_add_routes);
964
965 int adau17x1_resume(struct snd_soc_component *component)
966 {
967 struct adau *adau = snd_soc_component_get_drvdata(component);
968
969 if (adau->switch_mode)
970 adau->switch_mode(component->dev);
971
972 regcache_sync(adau->regmap);
973
974 return 0;
975 }
976 EXPORT_SYMBOL_GPL(adau17x1_resume);
977
978 static int adau17x1_safeload(struct sigmadsp *sigmadsp, unsigned int addr,
979 const uint8_t bytes[], size_t len)
980 {
981 uint8_t buf[ADAU17X1_WORD_SIZE];
982 uint8_t data[ADAU17X1_SAFELOAD_DATA_SIZE];
983 unsigned int addr_offset;
984 unsigned int nbr_words;
985 int ret;
986
987 /* write data to safeload addresses. Check if len is not a multiple of
988 * 4 bytes, if so we need to zero pad.
989 */
990 nbr_words = len / ADAU17X1_WORD_SIZE;
991 if ((len - nbr_words * ADAU17X1_WORD_SIZE) == 0) {
992 ret = regmap_raw_write(sigmadsp->control_data,
993 ADAU17X1_SAFELOAD_DATA, bytes, len);
994 } else {
995 nbr_words++;
996 memset(data, 0, ADAU17X1_SAFELOAD_DATA_SIZE);
997 memcpy(data, bytes, len);
998 ret = regmap_raw_write(sigmadsp->control_data,
999 ADAU17X1_SAFELOAD_DATA, data,
1000 nbr_words * ADAU17X1_WORD_SIZE);
1001 }
1002
1003 if (ret < 0)
1004 return ret;
1005
1006 /* Write target address, target address is offset by 1 */
1007 addr_offset = addr - 1;
1008 put_unaligned_be32(addr_offset, buf);
1009 ret = regmap_raw_write(sigmadsp->control_data,
1010 ADAU17X1_SAFELOAD_TARGET_ADDRESS, buf, ADAU17X1_WORD_SIZE);
1011 if (ret < 0)
1012 return ret;
1013
1014 /* write nbr of words to trigger address */
1015 put_unaligned_be32(nbr_words, buf);
1016 ret = regmap_raw_write(sigmadsp->control_data,
1017 ADAU17X1_SAFELOAD_TRIGGER, buf, ADAU17X1_WORD_SIZE);
1018 if (ret < 0)
1019 return ret;
1020
1021 return 0;
1022 }
1023
1024 static const struct sigmadsp_ops adau17x1_sigmadsp_ops = {
1025 .safeload = adau17x1_safeload,
1026 };
1027
1028 int adau17x1_probe(struct device *dev, struct regmap *regmap,
1029 enum adau17x1_type type, void (*switch_mode)(struct device *dev),
1030 const char *firmware_name)
1031 {
1032 struct adau *adau;
1033 int ret;
1034
1035 if (IS_ERR(regmap))
1036 return PTR_ERR(regmap);
1037
1038 adau = devm_kzalloc(dev, sizeof(*adau), GFP_KERNEL);
1039 if (!adau)
1040 return -ENOMEM;
1041
1042 adau->mclk = devm_clk_get(dev, "mclk");
1043 if (IS_ERR(adau->mclk)) {
1044 if (PTR_ERR(adau->mclk) != -ENOENT)
1045 return PTR_ERR(adau->mclk);
1046 /* Clock is optional (for the driver) */
1047 adau->mclk = NULL;
1048 } else if (adau->mclk) {
1049 adau->clk_src = ADAU17X1_CLK_SRC_PLL_AUTO;
1050
1051 /*
1052 * Any valid PLL output rate will work at this point, use one
1053 * that is likely to be chosen later as well. The register will
1054 * be written when the PLL is powered up for the first time.
1055 */
1056 ret = adau_calc_pll_cfg(clk_get_rate(adau->mclk), 48000 * 1024,
1057 adau->pll_regs);
1058 if (ret < 0)
1059 return ret;
1060
1061 ret = clk_prepare_enable(adau->mclk);
1062 if (ret)
1063 return ret;
1064 }
1065
1066 adau->regmap = regmap;
1067 adau->switch_mode = switch_mode;
1068 adau->type = type;
1069
1070 dev_set_drvdata(dev, adau);
1071
1072 if (firmware_name) {
1073 if (adau17x1_has_safeload(adau)) {
1074 adau->sigmadsp = devm_sigmadsp_init_regmap(dev, regmap,
1075 &adau17x1_sigmadsp_ops, firmware_name);
1076 } else {
1077 adau->sigmadsp = devm_sigmadsp_init_regmap(dev, regmap,
1078 NULL, firmware_name);
1079 }
1080 if (IS_ERR(adau->sigmadsp)) {
1081 dev_warn(dev, "Could not find firmware file: %ld\n",
1082 PTR_ERR(adau->sigmadsp));
1083 adau->sigmadsp = NULL;
1084 }
1085 }
1086
1087 if (switch_mode)
1088 switch_mode(dev);
1089
1090 return 0;
1091 }
1092 EXPORT_SYMBOL_GPL(adau17x1_probe);
1093
1094 void adau17x1_remove(struct device *dev)
1095 {
1096 struct adau *adau = dev_get_drvdata(dev);
1097
1098 if (adau->mclk)
1099 clk_disable_unprepare(adau->mclk);
1100 }
1101 EXPORT_SYMBOL_GPL(adau17x1_remove);
1102
1103 MODULE_DESCRIPTION("ASoC ADAU1X61/ADAU1X81 common code");
1104 MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
1105 MODULE_LICENSE("GPL");
Linux with added FPC-III support