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ARM: dts: omap5: Add bus_dma_limit for L3 bus
[linux/fpc-iii.git] / sound / soc / codecs / max98095.c
blobc7e0a55f3dc243d65905cd861278320bc081ab4c
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * max98095.c -- MAX98095 ALSA SoC Audio driver
4 *
5 * Copyright 2011 Maxim Integrated Products
6 */
7
8 #include <linux/module.h>
9 #include <linux/moduleparam.h>
10 #include <linux/kernel.h>
11 #include <linux/init.h>
12 #include <linux/delay.h>
13 #include <linux/pm.h>
14 #include <linux/i2c.h>
15 #include <linux/clk.h>
16 #include <linux/mutex.h>
17 #include <sound/core.h>
18 #include <sound/pcm.h>
19 #include <sound/pcm_params.h>
20 #include <sound/soc.h>
21 #include <sound/initval.h>
22 #include <sound/tlv.h>
23 #include <linux/slab.h>
24 #include <asm/div64.h>
25 #include <sound/max98095.h>
26 #include <sound/jack.h>
27 #include "max98095.h"
28
29 enum max98095_type {
30 MAX98095,
31 };
32
33 struct max98095_cdata {
34 unsigned int rate;
35 unsigned int fmt;
36 int eq_sel;
37 int bq_sel;
38 };
39
40 struct max98095_priv {
41 struct regmap *regmap;
42 enum max98095_type devtype;
43 struct max98095_pdata *pdata;
44 struct clk *mclk;
45 unsigned int sysclk;
46 struct max98095_cdata dai[3];
47 const char **eq_texts;
48 const char **bq_texts;
49 struct soc_enum eq_enum;
50 struct soc_enum bq_enum;
51 int eq_textcnt;
52 int bq_textcnt;
53 u8 lin_state;
54 unsigned int mic1pre;
55 unsigned int mic2pre;
56 struct snd_soc_jack *headphone_jack;
57 struct snd_soc_jack *mic_jack;
58 struct mutex lock;
59 };
60
61 static const struct reg_default max98095_reg_def[] = {
62 { 0xf, 0x00 }, /* 0F */
63 { 0x10, 0x00 }, /* 10 */
64 { 0x11, 0x00 }, /* 11 */
65 { 0x12, 0x00 }, /* 12 */
66 { 0x13, 0x00 }, /* 13 */
67 { 0x14, 0x00 }, /* 14 */
68 { 0x15, 0x00 }, /* 15 */
69 { 0x16, 0x00 }, /* 16 */
70 { 0x17, 0x00 }, /* 17 */
71 { 0x18, 0x00 }, /* 18 */
72 { 0x19, 0x00 }, /* 19 */
73 { 0x1a, 0x00 }, /* 1A */
74 { 0x1b, 0x00 }, /* 1B */
75 { 0x1c, 0x00 }, /* 1C */
76 { 0x1d, 0x00 }, /* 1D */
77 { 0x1e, 0x00 }, /* 1E */
78 { 0x1f, 0x00 }, /* 1F */
79 { 0x20, 0x00 }, /* 20 */
80 { 0x21, 0x00 }, /* 21 */
81 { 0x22, 0x00 }, /* 22 */
82 { 0x23, 0x00 }, /* 23 */
83 { 0x24, 0x00 }, /* 24 */
84 { 0x25, 0x00 }, /* 25 */
85 { 0x26, 0x00 }, /* 26 */
86 { 0x27, 0x00 }, /* 27 */
87 { 0x28, 0x00 }, /* 28 */
88 { 0x29, 0x00 }, /* 29 */
89 { 0x2a, 0x00 }, /* 2A */
90 { 0x2b, 0x00 }, /* 2B */
91 { 0x2c, 0x00 }, /* 2C */
92 { 0x2d, 0x00 }, /* 2D */
93 { 0x2e, 0x00 }, /* 2E */
94 { 0x2f, 0x00 }, /* 2F */
95 { 0x30, 0x00 }, /* 30 */
96 { 0x31, 0x00 }, /* 31 */
97 { 0x32, 0x00 }, /* 32 */
98 { 0x33, 0x00 }, /* 33 */
99 { 0x34, 0x00 }, /* 34 */
100 { 0x35, 0x00 }, /* 35 */
101 { 0x36, 0x00 }, /* 36 */
102 { 0x37, 0x00 }, /* 37 */
103 { 0x38, 0x00 }, /* 38 */
104 { 0x39, 0x00 }, /* 39 */
105 { 0x3a, 0x00 }, /* 3A */
106 { 0x3b, 0x00 }, /* 3B */
107 { 0x3c, 0x00 }, /* 3C */
108 { 0x3d, 0x00 }, /* 3D */
109 { 0x3e, 0x00 }, /* 3E */
110 { 0x3f, 0x00 }, /* 3F */
111 { 0x40, 0x00 }, /* 40 */
112 { 0x41, 0x00 }, /* 41 */
113 { 0x42, 0x00 }, /* 42 */
114 { 0x43, 0x00 }, /* 43 */
115 { 0x44, 0x00 }, /* 44 */
116 { 0x45, 0x00 }, /* 45 */
117 { 0x46, 0x00 }, /* 46 */
118 { 0x47, 0x00 }, /* 47 */
119 { 0x48, 0x00 }, /* 48 */
120 { 0x49, 0x00 }, /* 49 */
121 { 0x4a, 0x00 }, /* 4A */
122 { 0x4b, 0x00 }, /* 4B */
123 { 0x4c, 0x00 }, /* 4C */
124 { 0x4d, 0x00 }, /* 4D */
125 { 0x4e, 0x00 }, /* 4E */
126 { 0x4f, 0x00 }, /* 4F */
127 { 0x50, 0x00 }, /* 50 */
128 { 0x51, 0x00 }, /* 51 */
129 { 0x52, 0x00 }, /* 52 */
130 { 0x53, 0x00 }, /* 53 */
131 { 0x54, 0x00 }, /* 54 */
132 { 0x55, 0x00 }, /* 55 */
133 { 0x56, 0x00 }, /* 56 */
134 { 0x57, 0x00 }, /* 57 */
135 { 0x58, 0x00 }, /* 58 */
136 { 0x59, 0x00 }, /* 59 */
137 { 0x5a, 0x00 }, /* 5A */
138 { 0x5b, 0x00 }, /* 5B */
139 { 0x5c, 0x00 }, /* 5C */
140 { 0x5d, 0x00 }, /* 5D */
141 { 0x5e, 0x00 }, /* 5E */
142 { 0x5f, 0x00 }, /* 5F */
143 { 0x60, 0x00 }, /* 60 */
144 { 0x61, 0x00 }, /* 61 */
145 { 0x62, 0x00 }, /* 62 */
146 { 0x63, 0x00 }, /* 63 */
147 { 0x64, 0x00 }, /* 64 */
148 { 0x65, 0x00 }, /* 65 */
149 { 0x66, 0x00 }, /* 66 */
150 { 0x67, 0x00 }, /* 67 */
151 { 0x68, 0x00 }, /* 68 */
152 { 0x69, 0x00 }, /* 69 */
153 { 0x6a, 0x00 }, /* 6A */
154 { 0x6b, 0x00 }, /* 6B */
155 { 0x6c, 0x00 }, /* 6C */
156 { 0x6d, 0x00 }, /* 6D */
157 { 0x6e, 0x00 }, /* 6E */
158 { 0x6f, 0x00 }, /* 6F */
159 { 0x70, 0x00 }, /* 70 */
160 { 0x71, 0x00 }, /* 71 */
161 { 0x72, 0x00 }, /* 72 */
162 { 0x73, 0x00 }, /* 73 */
163 { 0x74, 0x00 }, /* 74 */
164 { 0x75, 0x00 }, /* 75 */
165 { 0x76, 0x00 }, /* 76 */
166 { 0x77, 0x00 }, /* 77 */
167 { 0x78, 0x00 }, /* 78 */
168 { 0x79, 0x00 }, /* 79 */
169 { 0x7a, 0x00 }, /* 7A */
170 { 0x7b, 0x00 }, /* 7B */
171 { 0x7c, 0x00 }, /* 7C */
172 { 0x7d, 0x00 }, /* 7D */
173 { 0x7e, 0x00 }, /* 7E */
174 { 0x7f, 0x00 }, /* 7F */
175 { 0x80, 0x00 }, /* 80 */
176 { 0x81, 0x00 }, /* 81 */
177 { 0x82, 0x00 }, /* 82 */
178 { 0x83, 0x00 }, /* 83 */
179 { 0x84, 0x00 }, /* 84 */
180 { 0x85, 0x00 }, /* 85 */
181 { 0x86, 0x00 }, /* 86 */
182 { 0x87, 0x00 }, /* 87 */
183 { 0x88, 0x00 }, /* 88 */
184 { 0x89, 0x00 }, /* 89 */
185 { 0x8a, 0x00 }, /* 8A */
186 { 0x8b, 0x00 }, /* 8B */
187 { 0x8c, 0x00 }, /* 8C */
188 { 0x8d, 0x00 }, /* 8D */
189 { 0x8e, 0x00 }, /* 8E */
190 { 0x8f, 0x00 }, /* 8F */
191 { 0x90, 0x00 }, /* 90 */
192 { 0x91, 0x00 }, /* 91 */
193 { 0x92, 0x30 }, /* 92 */
194 { 0x93, 0xF0 }, /* 93 */
195 { 0x94, 0x00 }, /* 94 */
196 { 0x95, 0x00 }, /* 95 */
197 { 0x96, 0x3F }, /* 96 */
198 { 0x97, 0x00 }, /* 97 */
199 { 0xff, 0x00 }, /* FF */
200 };
201
202 static bool max98095_readable(struct device *dev, unsigned int reg)
203 {
204 switch (reg) {
205 case M98095_001_HOST_INT_STS ... M98095_097_PWR_SYS:
206 case M98095_0FF_REV_ID:
207 return true;
208 default:
209 return false;
210 }
211 }
212
213 static bool max98095_writeable(struct device *dev, unsigned int reg)
214 {
215 switch (reg) {
216 case M98095_00F_HOST_CFG ... M98095_097_PWR_SYS:
217 return true;
218 default:
219 return false;
220 }
221 }
222
223 static bool max98095_volatile(struct device *dev, unsigned int reg)
224 {
225 switch (reg) {
226 case M98095_000_HOST_DATA ... M98095_00E_TEMP_SENSOR_STS:
227 case M98095_REG_MAX_CACHED + 1 ... M98095_0FF_REV_ID:
228 return true;
229 default:
230 return false;
231 }
232 }
233
234 static const struct regmap_config max98095_regmap = {
235 .reg_bits = 8,
236 .val_bits = 8,
237
238 .reg_defaults = max98095_reg_def,
239 .num_reg_defaults = ARRAY_SIZE(max98095_reg_def),
240 .max_register = M98095_0FF_REV_ID,
241 .cache_type = REGCACHE_RBTREE,
242
243 .readable_reg = max98095_readable,
244 .writeable_reg = max98095_writeable,
245 .volatile_reg = max98095_volatile,
246 };
247
248 /*
249 * Load equalizer DSP coefficient configurations registers
250 */
251 static void m98095_eq_band(struct snd_soc_component *component, unsigned int dai,
252 unsigned int band, u16 *coefs)
253 {
254 unsigned int eq_reg;
255 unsigned int i;
256
257 if (WARN_ON(band > 4) ||
258 WARN_ON(dai > 1))
259 return;
260
261 /* Load the base register address */
262 eq_reg = dai ? M98095_142_DAI2_EQ_BASE : M98095_110_DAI1_EQ_BASE;
263
264 /* Add the band address offset, note adjustment for word address */
265 eq_reg += band * (M98095_COEFS_PER_BAND << 1);
266
267 /* Step through the registers and coefs */
268 for (i = 0; i < M98095_COEFS_PER_BAND; i++) {
269 snd_soc_component_write(component, eq_reg++, M98095_BYTE1(coefs[i]));
270 snd_soc_component_write(component, eq_reg++, M98095_BYTE0(coefs[i]));
271 }
272 }
273
274 /*
275 * Load biquad filter coefficient configurations registers
276 */
277 static void m98095_biquad_band(struct snd_soc_component *component, unsigned int dai,
278 unsigned int band, u16 *coefs)
279 {
280 unsigned int bq_reg;
281 unsigned int i;
282
283 if (WARN_ON(band > 1) ||
284 WARN_ON(dai > 1))
285 return;
286
287 /* Load the base register address */
288 bq_reg = dai ? M98095_17E_DAI2_BQ_BASE : M98095_174_DAI1_BQ_BASE;
289
290 /* Add the band address offset, note adjustment for word address */
291 bq_reg += band * (M98095_COEFS_PER_BAND << 1);
292
293 /* Step through the registers and coefs */
294 for (i = 0; i < M98095_COEFS_PER_BAND; i++) {
295 snd_soc_component_write(component, bq_reg++, M98095_BYTE1(coefs[i]));
296 snd_soc_component_write(component, bq_reg++, M98095_BYTE0(coefs[i]));
297 }
298 }
299
300 static const char * const max98095_fltr_mode[] = { "Voice", "Music" };
301 static SOC_ENUM_SINGLE_DECL(max98095_dai1_filter_mode_enum,
302 M98095_02E_DAI1_FILTERS, 7,
303 max98095_fltr_mode);
304 static SOC_ENUM_SINGLE_DECL(max98095_dai2_filter_mode_enum,
305 M98095_038_DAI2_FILTERS, 7,
306 max98095_fltr_mode);
307
308 static const char * const max98095_extmic_text[] = { "None", "MIC1", "MIC2" };
309
310 static SOC_ENUM_SINGLE_DECL(max98095_extmic_enum,
311 M98095_087_CFG_MIC, 0,
312 max98095_extmic_text);
313
314 static const struct snd_kcontrol_new max98095_extmic_mux =
315 SOC_DAPM_ENUM("External MIC Mux", max98095_extmic_enum);
316
317 static const char * const max98095_linein_text[] = { "INA", "INB" };
318
319 static SOC_ENUM_SINGLE_DECL(max98095_linein_enum,
320 M98095_086_CFG_LINE, 6,
321 max98095_linein_text);
322
323 static const struct snd_kcontrol_new max98095_linein_mux =
324 SOC_DAPM_ENUM("Linein Input Mux", max98095_linein_enum);
325
326 static const char * const max98095_line_mode_text[] = {
327 "Stereo", "Differential"};
328
329 static SOC_ENUM_SINGLE_DECL(max98095_linein_mode_enum,
330 M98095_086_CFG_LINE, 7,
331 max98095_line_mode_text);
332
333 static SOC_ENUM_SINGLE_DECL(max98095_lineout_mode_enum,
334 M98095_086_CFG_LINE, 4,
335 max98095_line_mode_text);
336
337 static const char * const max98095_dai_fltr[] = {
338 "Off", "Elliptical-HPF-16k", "Butterworth-HPF-16k",
339 "Elliptical-HPF-8k", "Butterworth-HPF-8k", "Butterworth-HPF-Fs/240"};
340 static SOC_ENUM_SINGLE_DECL(max98095_dai1_dac_filter_enum,
341 M98095_02E_DAI1_FILTERS, 0,
342 max98095_dai_fltr);
343 static SOC_ENUM_SINGLE_DECL(max98095_dai2_dac_filter_enum,
344 M98095_038_DAI2_FILTERS, 0,
345 max98095_dai_fltr);
346 static SOC_ENUM_SINGLE_DECL(max98095_dai3_dac_filter_enum,
347 M98095_042_DAI3_FILTERS, 0,
348 max98095_dai_fltr);
349
350 static int max98095_mic1pre_set(struct snd_kcontrol *kcontrol,
351 struct snd_ctl_elem_value *ucontrol)
352 {
353 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
354 struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component);
355 unsigned int sel = ucontrol->value.integer.value[0];
356
357 max98095->mic1pre = sel;
358 snd_soc_component_update_bits(component, M98095_05F_LVL_MIC1, M98095_MICPRE_MASK,
359 (1+sel)<<M98095_MICPRE_SHIFT);
360
361 return 0;
362 }
363
364 static int max98095_mic1pre_get(struct snd_kcontrol *kcontrol,
365 struct snd_ctl_elem_value *ucontrol)
366 {
367 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
368 struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component);
369
370 ucontrol->value.integer.value[0] = max98095->mic1pre;
371 return 0;
372 }
373
374 static int max98095_mic2pre_set(struct snd_kcontrol *kcontrol,
375 struct snd_ctl_elem_value *ucontrol)
376 {
377 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
378 struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component);
379 unsigned int sel = ucontrol->value.integer.value[0];
380
381 max98095->mic2pre = sel;
382 snd_soc_component_update_bits(component, M98095_060_LVL_MIC2, M98095_MICPRE_MASK,
383 (1+sel)<<M98095_MICPRE_SHIFT);
384
385 return 0;
386 }
387
388 static int max98095_mic2pre_get(struct snd_kcontrol *kcontrol,
389 struct snd_ctl_elem_value *ucontrol)
390 {
391 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
392 struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component);
393
394 ucontrol->value.integer.value[0] = max98095->mic2pre;
395 return 0;
396 }
397
398 static const DECLARE_TLV_DB_RANGE(max98095_micboost_tlv,
399 0, 1, TLV_DB_SCALE_ITEM(0, 2000, 0),
400 2, 2, TLV_DB_SCALE_ITEM(3000, 0, 0)
401 );
402
403 static const DECLARE_TLV_DB_SCALE(max98095_mic_tlv, 0, 100, 0);
404 static const DECLARE_TLV_DB_SCALE(max98095_adc_tlv, -1200, 100, 0);
405 static const DECLARE_TLV_DB_SCALE(max98095_adcboost_tlv, 0, 600, 0);
406
407 static const DECLARE_TLV_DB_RANGE(max98095_hp_tlv,
408 0, 6, TLV_DB_SCALE_ITEM(-6700, 400, 0),
409 7, 14, TLV_DB_SCALE_ITEM(-4000, 300, 0),
410 15, 21, TLV_DB_SCALE_ITEM(-1700, 200, 0),
411 22, 27, TLV_DB_SCALE_ITEM(-400, 100, 0),
412 28, 31, TLV_DB_SCALE_ITEM(150, 50, 0)
413 );
414
415 static const DECLARE_TLV_DB_RANGE(max98095_spk_tlv,
416 0, 10, TLV_DB_SCALE_ITEM(-5900, 400, 0),
417 11, 18, TLV_DB_SCALE_ITEM(-1700, 200, 0),
418 19, 27, TLV_DB_SCALE_ITEM(-200, 100, 0),
419 28, 39, TLV_DB_SCALE_ITEM(650, 50, 0)
420 );
421
422 static const DECLARE_TLV_DB_RANGE(max98095_rcv_lout_tlv,
423 0, 6, TLV_DB_SCALE_ITEM(-6200, 400, 0),
424 7, 14, TLV_DB_SCALE_ITEM(-3500, 300, 0),
425 15, 21, TLV_DB_SCALE_ITEM(-1200, 200, 0),
426 22, 27, TLV_DB_SCALE_ITEM(100, 100, 0),
427 28, 31, TLV_DB_SCALE_ITEM(650, 50, 0)
428 );
429
430 static const DECLARE_TLV_DB_RANGE(max98095_lin_tlv,
431 0, 2, TLV_DB_SCALE_ITEM(-600, 300, 0),
432 3, 3, TLV_DB_SCALE_ITEM(300, 1100, 0),
433 4, 5, TLV_DB_SCALE_ITEM(1400, 600, 0)
434 );
435
436 static const struct snd_kcontrol_new max98095_snd_controls[] = {
437
438 SOC_DOUBLE_R_TLV("Headphone Volume", M98095_064_LVL_HP_L,
439 M98095_065_LVL_HP_R, 0, 31, 0, max98095_hp_tlv),
440
441 SOC_DOUBLE_R_TLV("Speaker Volume", M98095_067_LVL_SPK_L,
442 M98095_068_LVL_SPK_R, 0, 39, 0, max98095_spk_tlv),
443
444 SOC_SINGLE_TLV("Receiver Volume", M98095_066_LVL_RCV,
445 0, 31, 0, max98095_rcv_lout_tlv),
446
447 SOC_DOUBLE_R_TLV("Lineout Volume", M98095_062_LVL_LINEOUT1,
448 M98095_063_LVL_LINEOUT2, 0, 31, 0, max98095_rcv_lout_tlv),
449
450 SOC_DOUBLE_R("Headphone Switch", M98095_064_LVL_HP_L,
451 M98095_065_LVL_HP_R, 7, 1, 1),
452
453 SOC_DOUBLE_R("Speaker Switch", M98095_067_LVL_SPK_L,
454 M98095_068_LVL_SPK_R, 7, 1, 1),
455
456 SOC_SINGLE("Receiver Switch", M98095_066_LVL_RCV, 7, 1, 1),
457
458 SOC_DOUBLE_R("Lineout Switch", M98095_062_LVL_LINEOUT1,
459 M98095_063_LVL_LINEOUT2, 7, 1, 1),
460
461 SOC_SINGLE_TLV("MIC1 Volume", M98095_05F_LVL_MIC1, 0, 20, 1,
462 max98095_mic_tlv),
463
464 SOC_SINGLE_TLV("MIC2 Volume", M98095_060_LVL_MIC2, 0, 20, 1,
465 max98095_mic_tlv),
466
467 SOC_SINGLE_EXT_TLV("MIC1 Boost Volume",
468 M98095_05F_LVL_MIC1, 5, 2, 0,
469 max98095_mic1pre_get, max98095_mic1pre_set,
470 max98095_micboost_tlv),
471 SOC_SINGLE_EXT_TLV("MIC2 Boost Volume",
472 M98095_060_LVL_MIC2, 5, 2, 0,
473 max98095_mic2pre_get, max98095_mic2pre_set,
474 max98095_micboost_tlv),
475
476 SOC_SINGLE_TLV("Linein Volume", M98095_061_LVL_LINEIN, 0, 5, 1,
477 max98095_lin_tlv),
478
479 SOC_SINGLE_TLV("ADCL Volume", M98095_05D_LVL_ADC_L, 0, 15, 1,
480 max98095_adc_tlv),
481 SOC_SINGLE_TLV("ADCR Volume", M98095_05E_LVL_ADC_R, 0, 15, 1,
482 max98095_adc_tlv),
483
484 SOC_SINGLE_TLV("ADCL Boost Volume", M98095_05D_LVL_ADC_L, 4, 3, 0,
485 max98095_adcboost_tlv),
486 SOC_SINGLE_TLV("ADCR Boost Volume", M98095_05E_LVL_ADC_R, 4, 3, 0,
487 max98095_adcboost_tlv),
488
489 SOC_SINGLE("EQ1 Switch", M98095_088_CFG_LEVEL, 0, 1, 0),
490 SOC_SINGLE("EQ2 Switch", M98095_088_CFG_LEVEL, 1, 1, 0),
491
492 SOC_SINGLE("Biquad1 Switch", M98095_088_CFG_LEVEL, 2, 1, 0),
493 SOC_SINGLE("Biquad2 Switch", M98095_088_CFG_LEVEL, 3, 1, 0),
494
495 SOC_ENUM("DAI1 Filter Mode", max98095_dai1_filter_mode_enum),
496 SOC_ENUM("DAI2 Filter Mode", max98095_dai2_filter_mode_enum),
497 SOC_ENUM("DAI1 DAC Filter", max98095_dai1_dac_filter_enum),
498 SOC_ENUM("DAI2 DAC Filter", max98095_dai2_dac_filter_enum),
499 SOC_ENUM("DAI3 DAC Filter", max98095_dai3_dac_filter_enum),
500
501 SOC_ENUM("Linein Mode", max98095_linein_mode_enum),
502 SOC_ENUM("Lineout Mode", max98095_lineout_mode_enum),
503 };
504
505 /* Left speaker mixer switch */
506 static const struct snd_kcontrol_new max98095_left_speaker_mixer_controls[] = {
507 SOC_DAPM_SINGLE("Left DAC1 Switch", M98095_050_MIX_SPK_LEFT, 0, 1, 0),
508 SOC_DAPM_SINGLE("Right DAC1 Switch", M98095_050_MIX_SPK_LEFT, 6, 1, 0),
509 SOC_DAPM_SINGLE("Mono DAC2 Switch", M98095_050_MIX_SPK_LEFT, 3, 1, 0),
510 SOC_DAPM_SINGLE("Mono DAC3 Switch", M98095_050_MIX_SPK_LEFT, 3, 1, 0),
511 SOC_DAPM_SINGLE("MIC1 Switch", M98095_050_MIX_SPK_LEFT, 4, 1, 0),
512 SOC_DAPM_SINGLE("MIC2 Switch", M98095_050_MIX_SPK_LEFT, 5, 1, 0),
513 SOC_DAPM_SINGLE("IN1 Switch", M98095_050_MIX_SPK_LEFT, 1, 1, 0),
514 SOC_DAPM_SINGLE("IN2 Switch", M98095_050_MIX_SPK_LEFT, 2, 1, 0),
515 };
516
517 /* Right speaker mixer switch */
518 static const struct snd_kcontrol_new max98095_right_speaker_mixer_controls[] = {
519 SOC_DAPM_SINGLE("Left DAC1 Switch", M98095_051_MIX_SPK_RIGHT, 6, 1, 0),
520 SOC_DAPM_SINGLE("Right DAC1 Switch", M98095_051_MIX_SPK_RIGHT, 0, 1, 0),
521 SOC_DAPM_SINGLE("Mono DAC2 Switch", M98095_051_MIX_SPK_RIGHT, 3, 1, 0),
522 SOC_DAPM_SINGLE("Mono DAC3 Switch", M98095_051_MIX_SPK_RIGHT, 3, 1, 0),
523 SOC_DAPM_SINGLE("MIC1 Switch", M98095_051_MIX_SPK_RIGHT, 5, 1, 0),
524 SOC_DAPM_SINGLE("MIC2 Switch", M98095_051_MIX_SPK_RIGHT, 4, 1, 0),
525 SOC_DAPM_SINGLE("IN1 Switch", M98095_051_MIX_SPK_RIGHT, 1, 1, 0),
526 SOC_DAPM_SINGLE("IN2 Switch", M98095_051_MIX_SPK_RIGHT, 2, 1, 0),
527 };
528
529 /* Left headphone mixer switch */
530 static const struct snd_kcontrol_new max98095_left_hp_mixer_controls[] = {
531 SOC_DAPM_SINGLE("Left DAC1 Switch", M98095_04C_MIX_HP_LEFT, 0, 1, 0),
532 SOC_DAPM_SINGLE("Right DAC1 Switch", M98095_04C_MIX_HP_LEFT, 5, 1, 0),
533 SOC_DAPM_SINGLE("MIC1 Switch", M98095_04C_MIX_HP_LEFT, 3, 1, 0),
534 SOC_DAPM_SINGLE("MIC2 Switch", M98095_04C_MIX_HP_LEFT, 4, 1, 0),
535 SOC_DAPM_SINGLE("IN1 Switch", M98095_04C_MIX_HP_LEFT, 1, 1, 0),
536 SOC_DAPM_SINGLE("IN2 Switch", M98095_04C_MIX_HP_LEFT, 2, 1, 0),
537 };
538
539 /* Right headphone mixer switch */
540 static const struct snd_kcontrol_new max98095_right_hp_mixer_controls[] = {
541 SOC_DAPM_SINGLE("Left DAC1 Switch", M98095_04D_MIX_HP_RIGHT, 5, 1, 0),
542 SOC_DAPM_SINGLE("Right DAC1 Switch", M98095_04D_MIX_HP_RIGHT, 0, 1, 0),
543 SOC_DAPM_SINGLE("MIC1 Switch", M98095_04D_MIX_HP_RIGHT, 3, 1, 0),
544 SOC_DAPM_SINGLE("MIC2 Switch", M98095_04D_MIX_HP_RIGHT, 4, 1, 0),
545 SOC_DAPM_SINGLE("IN1 Switch", M98095_04D_MIX_HP_RIGHT, 1, 1, 0),
546 SOC_DAPM_SINGLE("IN2 Switch", M98095_04D_MIX_HP_RIGHT, 2, 1, 0),
547 };
548
549 /* Receiver earpiece mixer switch */
550 static const struct snd_kcontrol_new max98095_mono_rcv_mixer_controls[] = {
551 SOC_DAPM_SINGLE("Left DAC1 Switch", M98095_04F_MIX_RCV, 0, 1, 0),
552 SOC_DAPM_SINGLE("Right DAC1 Switch", M98095_04F_MIX_RCV, 5, 1, 0),
553 SOC_DAPM_SINGLE("MIC1 Switch", M98095_04F_MIX_RCV, 3, 1, 0),
554 SOC_DAPM_SINGLE("MIC2 Switch", M98095_04F_MIX_RCV, 4, 1, 0),
555 SOC_DAPM_SINGLE("IN1 Switch", M98095_04F_MIX_RCV, 1, 1, 0),
556 SOC_DAPM_SINGLE("IN2 Switch", M98095_04F_MIX_RCV, 2, 1, 0),
557 };
558
559 /* Left lineout mixer switch */
560 static const struct snd_kcontrol_new max98095_left_lineout_mixer_controls[] = {
561 SOC_DAPM_SINGLE("Left DAC1 Switch", M98095_053_MIX_LINEOUT1, 5, 1, 0),
562 SOC_DAPM_SINGLE("Right DAC1 Switch", M98095_053_MIX_LINEOUT1, 0, 1, 0),
563 SOC_DAPM_SINGLE("MIC1 Switch", M98095_053_MIX_LINEOUT1, 3, 1, 0),
564 SOC_DAPM_SINGLE("MIC2 Switch", M98095_053_MIX_LINEOUT1, 4, 1, 0),
565 SOC_DAPM_SINGLE("IN1 Switch", M98095_053_MIX_LINEOUT1, 1, 1, 0),
566 SOC_DAPM_SINGLE("IN2 Switch", M98095_053_MIX_LINEOUT1, 2, 1, 0),
567 };
568
569 /* Right lineout mixer switch */
570 static const struct snd_kcontrol_new max98095_right_lineout_mixer_controls[] = {
571 SOC_DAPM_SINGLE("Left DAC1 Switch", M98095_054_MIX_LINEOUT2, 0, 1, 0),
572 SOC_DAPM_SINGLE("Right DAC1 Switch", M98095_054_MIX_LINEOUT2, 5, 1, 0),
573 SOC_DAPM_SINGLE("MIC1 Switch", M98095_054_MIX_LINEOUT2, 3, 1, 0),
574 SOC_DAPM_SINGLE("MIC2 Switch", M98095_054_MIX_LINEOUT2, 4, 1, 0),
575 SOC_DAPM_SINGLE("IN1 Switch", M98095_054_MIX_LINEOUT2, 1, 1, 0),
576 SOC_DAPM_SINGLE("IN2 Switch", M98095_054_MIX_LINEOUT2, 2, 1, 0),
577 };
578
579 /* Left ADC mixer switch */
580 static const struct snd_kcontrol_new max98095_left_ADC_mixer_controls[] = {
581 SOC_DAPM_SINGLE("MIC1 Switch", M98095_04A_MIX_ADC_LEFT, 7, 1, 0),
582 SOC_DAPM_SINGLE("MIC2 Switch", M98095_04A_MIX_ADC_LEFT, 6, 1, 0),
583 SOC_DAPM_SINGLE("IN1 Switch", M98095_04A_MIX_ADC_LEFT, 3, 1, 0),
584 SOC_DAPM_SINGLE("IN2 Switch", M98095_04A_MIX_ADC_LEFT, 2, 1, 0),
585 };
586
587 /* Right ADC mixer switch */
588 static const struct snd_kcontrol_new max98095_right_ADC_mixer_controls[] = {
589 SOC_DAPM_SINGLE("MIC1 Switch", M98095_04B_MIX_ADC_RIGHT, 7, 1, 0),
590 SOC_DAPM_SINGLE("MIC2 Switch", M98095_04B_MIX_ADC_RIGHT, 6, 1, 0),
591 SOC_DAPM_SINGLE("IN1 Switch", M98095_04B_MIX_ADC_RIGHT, 3, 1, 0),
592 SOC_DAPM_SINGLE("IN2 Switch", M98095_04B_MIX_ADC_RIGHT, 2, 1, 0),
593 };
594
595 static int max98095_mic_event(struct snd_soc_dapm_widget *w,
596 struct snd_kcontrol *kcontrol, int event)
597 {
598 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
599 struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component);
600
601 switch (event) {
602 case SND_SOC_DAPM_POST_PMU:
603 if (w->reg == M98095_05F_LVL_MIC1) {
604 snd_soc_component_update_bits(component, w->reg, M98095_MICPRE_MASK,
605 (1+max98095->mic1pre)<<M98095_MICPRE_SHIFT);
606 } else {
607 snd_soc_component_update_bits(component, w->reg, M98095_MICPRE_MASK,
608 (1+max98095->mic2pre)<<M98095_MICPRE_SHIFT);
609 }
610 break;
611 case SND_SOC_DAPM_POST_PMD:
612 snd_soc_component_update_bits(component, w->reg, M98095_MICPRE_MASK, 0);
613 break;
614 default:
615 return -EINVAL;
616 }
617
618 return 0;
619 }
620
621 /*
622 * The line inputs are stereo inputs with the left and right
623 * channels sharing a common PGA power control signal.
624 */
625 static int max98095_line_pga(struct snd_soc_dapm_widget *w,
626 int event, u8 channel)
627 {
628 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
629 struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component);
630 u8 *state;
631
632 if (WARN_ON(!(channel == 1 || channel == 2)))
633 return -EINVAL;
634
635 state = &max98095->lin_state;
636
637 switch (event) {
638 case SND_SOC_DAPM_POST_PMU:
639 *state |= channel;
640 snd_soc_component_update_bits(component, w->reg,
641 (1 << w->shift), (1 << w->shift));
642 break;
643 case SND_SOC_DAPM_POST_PMD:
644 *state &= ~channel;
645 if (*state == 0) {
646 snd_soc_component_update_bits(component, w->reg,
647 (1 << w->shift), 0);
648 }
649 break;
650 default:
651 return -EINVAL;
652 }
653
654 return 0;
655 }
656
657 static int max98095_pga_in1_event(struct snd_soc_dapm_widget *w,
658 struct snd_kcontrol *k, int event)
659 {
660 return max98095_line_pga(w, event, 1);
661 }
662
663 static int max98095_pga_in2_event(struct snd_soc_dapm_widget *w,
664 struct snd_kcontrol *k, int event)
665 {
666 return max98095_line_pga(w, event, 2);
667 }
668
669 /*
670 * The stereo line out mixer outputs to two stereo line outs.
671 * The 2nd pair has a separate set of enables.
672 */
673 static int max98095_lineout_event(struct snd_soc_dapm_widget *w,
674 struct snd_kcontrol *kcontrol, int event)
675 {
676 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
677
678 switch (event) {
679 case SND_SOC_DAPM_POST_PMU:
680 snd_soc_component_update_bits(component, w->reg,
681 (1 << (w->shift+2)), (1 << (w->shift+2)));
682 break;
683 case SND_SOC_DAPM_POST_PMD:
684 snd_soc_component_update_bits(component, w->reg,
685 (1 << (w->shift+2)), 0);
686 break;
687 default:
688 return -EINVAL;
689 }
690
691 return 0;
692 }
693
694 static const struct snd_soc_dapm_widget max98095_dapm_widgets[] = {
695
696 SND_SOC_DAPM_ADC("ADCL", "HiFi Capture", M98095_090_PWR_EN_IN, 0, 0),
697 SND_SOC_DAPM_ADC("ADCR", "HiFi Capture", M98095_090_PWR_EN_IN, 1, 0),
698
699 SND_SOC_DAPM_DAC("DACL1", "HiFi Playback",
700 M98095_091_PWR_EN_OUT, 0, 0),
701 SND_SOC_DAPM_DAC("DACR1", "HiFi Playback",
702 M98095_091_PWR_EN_OUT, 1, 0),
703 SND_SOC_DAPM_DAC("DACM2", "Aux Playback",
704 M98095_091_PWR_EN_OUT, 2, 0),
705 SND_SOC_DAPM_DAC("DACM3", "Voice Playback",
706 M98095_091_PWR_EN_OUT, 2, 0),
707
708 SND_SOC_DAPM_PGA("HP Left Out", M98095_091_PWR_EN_OUT,
709 6, 0, NULL, 0),
710 SND_SOC_DAPM_PGA("HP Right Out", M98095_091_PWR_EN_OUT,
711 7, 0, NULL, 0),
712
713 SND_SOC_DAPM_PGA("SPK Left Out", M98095_091_PWR_EN_OUT,
714 4, 0, NULL, 0),
715 SND_SOC_DAPM_PGA("SPK Right Out", M98095_091_PWR_EN_OUT,
716 5, 0, NULL, 0),
717
718 SND_SOC_DAPM_PGA("RCV Mono Out", M98095_091_PWR_EN_OUT,
719 3, 0, NULL, 0),
720
721 SND_SOC_DAPM_PGA_E("LINE Left Out", M98095_092_PWR_EN_OUT,
722 0, 0, NULL, 0, max98095_lineout_event, SND_SOC_DAPM_PRE_PMD),
723 SND_SOC_DAPM_PGA_E("LINE Right Out", M98095_092_PWR_EN_OUT,
724 1, 0, NULL, 0, max98095_lineout_event, SND_SOC_DAPM_PRE_PMD),
725
726 SND_SOC_DAPM_MUX("External MIC", SND_SOC_NOPM, 0, 0,
727 &max98095_extmic_mux),
728
729 SND_SOC_DAPM_MUX("Linein Mux", SND_SOC_NOPM, 0, 0,
730 &max98095_linein_mux),
731
732 SND_SOC_DAPM_MIXER("Left Headphone Mixer", SND_SOC_NOPM, 0, 0,
733 &max98095_left_hp_mixer_controls[0],
734 ARRAY_SIZE(max98095_left_hp_mixer_controls)),
735
736 SND_SOC_DAPM_MIXER("Right Headphone Mixer", SND_SOC_NOPM, 0, 0,
737 &max98095_right_hp_mixer_controls[0],
738 ARRAY_SIZE(max98095_right_hp_mixer_controls)),
739
740 SND_SOC_DAPM_MIXER("Left Speaker Mixer", SND_SOC_NOPM, 0, 0,
741 &max98095_left_speaker_mixer_controls[0],
742 ARRAY_SIZE(max98095_left_speaker_mixer_controls)),
743
744 SND_SOC_DAPM_MIXER("Right Speaker Mixer", SND_SOC_NOPM, 0, 0,
745 &max98095_right_speaker_mixer_controls[0],
746 ARRAY_SIZE(max98095_right_speaker_mixer_controls)),
747
748 SND_SOC_DAPM_MIXER("Receiver Mixer", SND_SOC_NOPM, 0, 0,
749 &max98095_mono_rcv_mixer_controls[0],
750 ARRAY_SIZE(max98095_mono_rcv_mixer_controls)),
751
752 SND_SOC_DAPM_MIXER("Left Lineout Mixer", SND_SOC_NOPM, 0, 0,
753 &max98095_left_lineout_mixer_controls[0],
754 ARRAY_SIZE(max98095_left_lineout_mixer_controls)),
755
756 SND_SOC_DAPM_MIXER("Right Lineout Mixer", SND_SOC_NOPM, 0, 0,
757 &max98095_right_lineout_mixer_controls[0],
758 ARRAY_SIZE(max98095_right_lineout_mixer_controls)),
759
760 SND_SOC_DAPM_MIXER("Left ADC Mixer", SND_SOC_NOPM, 0, 0,
761 &max98095_left_ADC_mixer_controls[0],
762 ARRAY_SIZE(max98095_left_ADC_mixer_controls)),
763
764 SND_SOC_DAPM_MIXER("Right ADC Mixer", SND_SOC_NOPM, 0, 0,
765 &max98095_right_ADC_mixer_controls[0],
766 ARRAY_SIZE(max98095_right_ADC_mixer_controls)),
767
768 SND_SOC_DAPM_PGA_E("MIC1 Input", M98095_05F_LVL_MIC1,
769 5, 0, NULL, 0, max98095_mic_event,
770 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
771
772 SND_SOC_DAPM_PGA_E("MIC2 Input", M98095_060_LVL_MIC2,
773 5, 0, NULL, 0, max98095_mic_event,
774 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
775
776 SND_SOC_DAPM_PGA_E("IN1 Input", M98095_090_PWR_EN_IN,
777 7, 0, NULL, 0, max98095_pga_in1_event,
778 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
779
780 SND_SOC_DAPM_PGA_E("IN2 Input", M98095_090_PWR_EN_IN,
781 7, 0, NULL, 0, max98095_pga_in2_event,
782 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
783
784 SND_SOC_DAPM_MICBIAS("MICBIAS1", M98095_090_PWR_EN_IN, 2, 0),
785 SND_SOC_DAPM_MICBIAS("MICBIAS2", M98095_090_PWR_EN_IN, 3, 0),
786
787 SND_SOC_DAPM_OUTPUT("HPL"),
788 SND_SOC_DAPM_OUTPUT("HPR"),
789 SND_SOC_DAPM_OUTPUT("SPKL"),
790 SND_SOC_DAPM_OUTPUT("SPKR"),
791 SND_SOC_DAPM_OUTPUT("RCV"),
792 SND_SOC_DAPM_OUTPUT("OUT1"),
793 SND_SOC_DAPM_OUTPUT("OUT2"),
794 SND_SOC_DAPM_OUTPUT("OUT3"),
795 SND_SOC_DAPM_OUTPUT("OUT4"),
796
797 SND_SOC_DAPM_INPUT("MIC1"),
798 SND_SOC_DAPM_INPUT("MIC2"),
799 SND_SOC_DAPM_INPUT("INA1"),
800 SND_SOC_DAPM_INPUT("INA2"),
801 SND_SOC_DAPM_INPUT("INB1"),
802 SND_SOC_DAPM_INPUT("INB2"),
803 };
804
805 static const struct snd_soc_dapm_route max98095_audio_map[] = {
806 /* Left headphone output mixer */
807 {"Left Headphone Mixer", "Left DAC1 Switch", "DACL1"},
808 {"Left Headphone Mixer", "Right DAC1 Switch", "DACR1"},
809 {"Left Headphone Mixer", "MIC1 Switch", "MIC1 Input"},
810 {"Left Headphone Mixer", "MIC2 Switch", "MIC2 Input"},
811 {"Left Headphone Mixer", "IN1 Switch", "IN1 Input"},
812 {"Left Headphone Mixer", "IN2 Switch", "IN2 Input"},
813
814 /* Right headphone output mixer */
815 {"Right Headphone Mixer", "Left DAC1 Switch", "DACL1"},
816 {"Right Headphone Mixer", "Right DAC1 Switch", "DACR1"},
817 {"Right Headphone Mixer", "MIC1 Switch", "MIC1 Input"},
818 {"Right Headphone Mixer", "MIC2 Switch", "MIC2 Input"},
819 {"Right Headphone Mixer", "IN1 Switch", "IN1 Input"},
820 {"Right Headphone Mixer", "IN2 Switch", "IN2 Input"},
821
822 /* Left speaker output mixer */
823 {"Left Speaker Mixer", "Left DAC1 Switch", "DACL1"},
824 {"Left Speaker Mixer", "Right DAC1 Switch", "DACR1"},
825 {"Left Speaker Mixer", "Mono DAC2 Switch", "DACM2"},
826 {"Left Speaker Mixer", "Mono DAC3 Switch", "DACM3"},
827 {"Left Speaker Mixer", "MIC1 Switch", "MIC1 Input"},
828 {"Left Speaker Mixer", "MIC2 Switch", "MIC2 Input"},
829 {"Left Speaker Mixer", "IN1 Switch", "IN1 Input"},
830 {"Left Speaker Mixer", "IN2 Switch", "IN2 Input"},
831
832 /* Right speaker output mixer */
833 {"Right Speaker Mixer", "Left DAC1 Switch", "DACL1"},
834 {"Right Speaker Mixer", "Right DAC1 Switch", "DACR1"},
835 {"Right Speaker Mixer", "Mono DAC2 Switch", "DACM2"},
836 {"Right Speaker Mixer", "Mono DAC3 Switch", "DACM3"},
837 {"Right Speaker Mixer", "MIC1 Switch", "MIC1 Input"},
838 {"Right Speaker Mixer", "MIC2 Switch", "MIC2 Input"},
839 {"Right Speaker Mixer", "IN1 Switch", "IN1 Input"},
840 {"Right Speaker Mixer", "IN2 Switch", "IN2 Input"},
841
842 /* Earpiece/Receiver output mixer */
843 {"Receiver Mixer", "Left DAC1 Switch", "DACL1"},
844 {"Receiver Mixer", "Right DAC1 Switch", "DACR1"},
845 {"Receiver Mixer", "MIC1 Switch", "MIC1 Input"},
846 {"Receiver Mixer", "MIC2 Switch", "MIC2 Input"},
847 {"Receiver Mixer", "IN1 Switch", "IN1 Input"},
848 {"Receiver Mixer", "IN2 Switch", "IN2 Input"},
849
850 /* Left Lineout output mixer */
851 {"Left Lineout Mixer", "Left DAC1 Switch", "DACL1"},
852 {"Left Lineout Mixer", "Right DAC1 Switch", "DACR1"},
853 {"Left Lineout Mixer", "MIC1 Switch", "MIC1 Input"},
854 {"Left Lineout Mixer", "MIC2 Switch", "MIC2 Input"},
855 {"Left Lineout Mixer", "IN1 Switch", "IN1 Input"},
856 {"Left Lineout Mixer", "IN2 Switch", "IN2 Input"},
857
858 /* Right lineout output mixer */
859 {"Right Lineout Mixer", "Left DAC1 Switch", "DACL1"},
860 {"Right Lineout Mixer", "Right DAC1 Switch", "DACR1"},
861 {"Right Lineout Mixer", "MIC1 Switch", "MIC1 Input"},
862 {"Right Lineout Mixer", "MIC2 Switch", "MIC2 Input"},
863 {"Right Lineout Mixer", "IN1 Switch", "IN1 Input"},
864 {"Right Lineout Mixer", "IN2 Switch", "IN2 Input"},
865
866 {"HP Left Out", NULL, "Left Headphone Mixer"},
867 {"HP Right Out", NULL, "Right Headphone Mixer"},
868 {"SPK Left Out", NULL, "Left Speaker Mixer"},
869 {"SPK Right Out", NULL, "Right Speaker Mixer"},
870 {"RCV Mono Out", NULL, "Receiver Mixer"},
871 {"LINE Left Out", NULL, "Left Lineout Mixer"},
872 {"LINE Right Out", NULL, "Right Lineout Mixer"},
873
874 {"HPL", NULL, "HP Left Out"},
875 {"HPR", NULL, "HP Right Out"},
876 {"SPKL", NULL, "SPK Left Out"},
877 {"SPKR", NULL, "SPK Right Out"},
878 {"RCV", NULL, "RCV Mono Out"},
879 {"OUT1", NULL, "LINE Left Out"},
880 {"OUT2", NULL, "LINE Right Out"},
881 {"OUT3", NULL, "LINE Left Out"},
882 {"OUT4", NULL, "LINE Right Out"},
883
884 /* Left ADC input mixer */
885 {"Left ADC Mixer", "MIC1 Switch", "MIC1 Input"},
886 {"Left ADC Mixer", "MIC2 Switch", "MIC2 Input"},
887 {"Left ADC Mixer", "IN1 Switch", "IN1 Input"},
888 {"Left ADC Mixer", "IN2 Switch", "IN2 Input"},
889
890 /* Right ADC input mixer */
891 {"Right ADC Mixer", "MIC1 Switch", "MIC1 Input"},
892 {"Right ADC Mixer", "MIC2 Switch", "MIC2 Input"},
893 {"Right ADC Mixer", "IN1 Switch", "IN1 Input"},
894 {"Right ADC Mixer", "IN2 Switch", "IN2 Input"},
895
896 /* Inputs */
897 {"ADCL", NULL, "Left ADC Mixer"},
898 {"ADCR", NULL, "Right ADC Mixer"},
899
900 {"IN1 Input", NULL, "INA1"},
901 {"IN2 Input", NULL, "INA2"},
902
903 {"MIC1 Input", NULL, "MIC1"},
904 {"MIC2 Input", NULL, "MIC2"},
905 };
906
907 /* codec mclk clock divider coefficients */
908 static const struct {
909 u32 rate;
910 u8 sr;
911 } rate_table[] = {
912 {8000, 0x01},
913 {11025, 0x02},
914 {16000, 0x03},
915 {22050, 0x04},
916 {24000, 0x05},
917 {32000, 0x06},
918 {44100, 0x07},
919 {48000, 0x08},
920 {88200, 0x09},
921 {96000, 0x0A},
922 };
923
924 static int rate_value(int rate, u8 *value)
925 {
926 int i;
927
928 for (i = 0; i < ARRAY_SIZE(rate_table); i++) {
929 if (rate_table[i].rate >= rate) {
930 *value = rate_table[i].sr;
931 return 0;
932 }
933 }
934 *value = rate_table[0].sr;
935 return -EINVAL;
936 }
937
938 static int max98095_dai1_hw_params(struct snd_pcm_substream *substream,
939 struct snd_pcm_hw_params *params,
940 struct snd_soc_dai *dai)
941 {
942 struct snd_soc_component *component = dai->component;
943 struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component);
944 struct max98095_cdata *cdata;
945 unsigned long long ni;
946 unsigned int rate;
947 u8 regval;
948
949 cdata = &max98095->dai[0];
950
951 rate = params_rate(params);
952
953 switch (params_width(params)) {
954 case 16:
955 snd_soc_component_update_bits(component, M98095_02A_DAI1_FORMAT,
956 M98095_DAI_WS, 0);
957 break;
958 case 24:
959 snd_soc_component_update_bits(component, M98095_02A_DAI1_FORMAT,
960 M98095_DAI_WS, M98095_DAI_WS);
961 break;
962 default:
963 return -EINVAL;
964 }
965
966 if (rate_value(rate, &regval))
967 return -EINVAL;
968
969 snd_soc_component_update_bits(component, M98095_027_DAI1_CLKMODE,
970 M98095_CLKMODE_MASK, regval);
971 cdata->rate = rate;
972
973 /* Configure NI when operating as master */
974 if (snd_soc_component_read32(component, M98095_02A_DAI1_FORMAT) & M98095_DAI_MAS) {
975 if (max98095->sysclk == 0) {
976 dev_err(component->dev, "Invalid system clock frequency\n");
977 return -EINVAL;
978 }
979 ni = 65536ULL * (rate < 50000 ? 96ULL : 48ULL)
980 * (unsigned long long int)rate;
981 do_div(ni, (unsigned long long int)max98095->sysclk);
982 snd_soc_component_write(component, M98095_028_DAI1_CLKCFG_HI,
983 (ni >> 8) & 0x7F);
984 snd_soc_component_write(component, M98095_029_DAI1_CLKCFG_LO,
985 ni & 0xFF);
986 }
987
988 /* Update sample rate mode */
989 if (rate < 50000)
990 snd_soc_component_update_bits(component, M98095_02E_DAI1_FILTERS,
991 M98095_DAI_DHF, 0);
992 else
993 snd_soc_component_update_bits(component, M98095_02E_DAI1_FILTERS,
994 M98095_DAI_DHF, M98095_DAI_DHF);
995
996 return 0;
997 }
998
999 static int max98095_dai2_hw_params(struct snd_pcm_substream *substream,
1000 struct snd_pcm_hw_params *params,
1001 struct snd_soc_dai *dai)
1002 {
1003 struct snd_soc_component *component = dai->component;
1004 struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component);
1005 struct max98095_cdata *cdata;
1006 unsigned long long ni;
1007 unsigned int rate;
1008 u8 regval;
1009
1010 cdata = &max98095->dai[1];
1011
1012 rate = params_rate(params);
1013
1014 switch (params_width(params)) {
1015 case 16:
1016 snd_soc_component_update_bits(component, M98095_034_DAI2_FORMAT,
1017 M98095_DAI_WS, 0);
1018 break;
1019 case 24:
1020 snd_soc_component_update_bits(component, M98095_034_DAI2_FORMAT,
1021 M98095_DAI_WS, M98095_DAI_WS);
1022 break;
1023 default:
1024 return -EINVAL;
1025 }
1026
1027 if (rate_value(rate, &regval))
1028 return -EINVAL;
1029
1030 snd_soc_component_update_bits(component, M98095_031_DAI2_CLKMODE,
1031 M98095_CLKMODE_MASK, regval);
1032 cdata->rate = rate;
1033
1034 /* Configure NI when operating as master */
1035 if (snd_soc_component_read32(component, M98095_034_DAI2_FORMAT) & M98095_DAI_MAS) {
1036 if (max98095->sysclk == 0) {
1037 dev_err(component->dev, "Invalid system clock frequency\n");
1038 return -EINVAL;
1039 }
1040 ni = 65536ULL * (rate < 50000 ? 96ULL : 48ULL)
1041 * (unsigned long long int)rate;
1042 do_div(ni, (unsigned long long int)max98095->sysclk);
1043 snd_soc_component_write(component, M98095_032_DAI2_CLKCFG_HI,
1044 (ni >> 8) & 0x7F);
1045 snd_soc_component_write(component, M98095_033_DAI2_CLKCFG_LO,
1046 ni & 0xFF);
1047 }
1048
1049 /* Update sample rate mode */
1050 if (rate < 50000)
1051 snd_soc_component_update_bits(component, M98095_038_DAI2_FILTERS,
1052 M98095_DAI_DHF, 0);
1053 else
1054 snd_soc_component_update_bits(component, M98095_038_DAI2_FILTERS,
1055 M98095_DAI_DHF, M98095_DAI_DHF);
1056
1057 return 0;
1058 }
1059
1060 static int max98095_dai3_hw_params(struct snd_pcm_substream *substream,
1061 struct snd_pcm_hw_params *params,
1062 struct snd_soc_dai *dai)
1063 {
1064 struct snd_soc_component *component = dai->component;
1065 struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component);
1066 struct max98095_cdata *cdata;
1067 unsigned long long ni;
1068 unsigned int rate;
1069 u8 regval;
1070
1071 cdata = &max98095->dai[2];
1072
1073 rate = params_rate(params);
1074
1075 switch (params_width(params)) {
1076 case 16:
1077 snd_soc_component_update_bits(component, M98095_03E_DAI3_FORMAT,
1078 M98095_DAI_WS, 0);
1079 break;
1080 case 24:
1081 snd_soc_component_update_bits(component, M98095_03E_DAI3_FORMAT,
1082 M98095_DAI_WS, M98095_DAI_WS);
1083 break;
1084 default:
1085 return -EINVAL;
1086 }
1087
1088 if (rate_value(rate, &regval))
1089 return -EINVAL;
1090
1091 snd_soc_component_update_bits(component, M98095_03B_DAI3_CLKMODE,
1092 M98095_CLKMODE_MASK, regval);
1093 cdata->rate = rate;
1094
1095 /* Configure NI when operating as master */
1096 if (snd_soc_component_read32(component, M98095_03E_DAI3_FORMAT) & M98095_DAI_MAS) {
1097 if (max98095->sysclk == 0) {
1098 dev_err(component->dev, "Invalid system clock frequency\n");
1099 return -EINVAL;
1100 }
1101 ni = 65536ULL * (rate < 50000 ? 96ULL : 48ULL)
1102 * (unsigned long long int)rate;
1103 do_div(ni, (unsigned long long int)max98095->sysclk);
1104 snd_soc_component_write(component, M98095_03C_DAI3_CLKCFG_HI,
1105 (ni >> 8) & 0x7F);
1106 snd_soc_component_write(component, M98095_03D_DAI3_CLKCFG_LO,
1107 ni & 0xFF);
1108 }
1109
1110 /* Update sample rate mode */
1111 if (rate < 50000)
1112 snd_soc_component_update_bits(component, M98095_042_DAI3_FILTERS,
1113 M98095_DAI_DHF, 0);
1114 else
1115 snd_soc_component_update_bits(component, M98095_042_DAI3_FILTERS,
1116 M98095_DAI_DHF, M98095_DAI_DHF);
1117
1118 return 0;
1119 }
1120
1121 static int max98095_dai_set_sysclk(struct snd_soc_dai *dai,
1122 int clk_id, unsigned int freq, int dir)
1123 {
1124 struct snd_soc_component *component = dai->component;
1125 struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component);
1126
1127 /* Requested clock frequency is already setup */
1128 if (freq == max98095->sysclk)
1129 return 0;
1130
1131 if (!IS_ERR(max98095->mclk)) {
1132 freq = clk_round_rate(max98095->mclk, freq);
1133 clk_set_rate(max98095->mclk, freq);
1134 }
1135
1136 /* Setup clocks for slave mode, and using the PLL
1137 * PSCLK = 0x01 (when master clk is 10MHz to 20MHz)
1138 * 0x02 (when master clk is 20MHz to 40MHz)..
1139 * 0x03 (when master clk is 40MHz to 60MHz)..
1140 */
1141 if ((freq >= 10000000) && (freq < 20000000)) {
1142 snd_soc_component_write(component, M98095_026_SYS_CLK, 0x10);
1143 } else if ((freq >= 20000000) && (freq < 40000000)) {
1144 snd_soc_component_write(component, M98095_026_SYS_CLK, 0x20);
1145 } else if ((freq >= 40000000) && (freq < 60000000)) {
1146 snd_soc_component_write(component, M98095_026_SYS_CLK, 0x30);
1147 } else {
1148 dev_err(component->dev, "Invalid master clock frequency\n");
1149 return -EINVAL;
1150 }
1151
1152 dev_dbg(dai->dev, "Clock source is %d at %uHz\n", clk_id, freq);
1153
1154 max98095->sysclk = freq;
1155 return 0;
1156 }
1157
1158 static int max98095_dai1_set_fmt(struct snd_soc_dai *codec_dai,
1159 unsigned int fmt)
1160 {
1161 struct snd_soc_component *component = codec_dai->component;
1162 struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component);
1163 struct max98095_cdata *cdata;
1164 u8 regval = 0;
1165
1166 cdata = &max98095->dai[0];
1167
1168 if (fmt != cdata->fmt) {
1169 cdata->fmt = fmt;
1170
1171 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1172 case SND_SOC_DAIFMT_CBS_CFS:
1173 /* Slave mode PLL */
1174 snd_soc_component_write(component, M98095_028_DAI1_CLKCFG_HI,
1175 0x80);
1176 snd_soc_component_write(component, M98095_029_DAI1_CLKCFG_LO,
1177 0x00);
1178 break;
1179 case SND_SOC_DAIFMT_CBM_CFM:
1180 /* Set to master mode */
1181 regval |= M98095_DAI_MAS;
1182 break;
1183 case SND_SOC_DAIFMT_CBS_CFM:
1184 case SND_SOC_DAIFMT_CBM_CFS:
1185 default:
1186 dev_err(component->dev, "Clock mode unsupported");
1187 return -EINVAL;
1188 }
1189
1190 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1191 case SND_SOC_DAIFMT_I2S:
1192 regval |= M98095_DAI_DLY;
1193 break;
1194 case SND_SOC_DAIFMT_LEFT_J:
1195 break;
1196 default:
1197 return -EINVAL;
1198 }
1199
1200 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1201 case SND_SOC_DAIFMT_NB_NF:
1202 break;
1203 case SND_SOC_DAIFMT_NB_IF:
1204 regval |= M98095_DAI_WCI;
1205 break;
1206 case SND_SOC_DAIFMT_IB_NF:
1207 regval |= M98095_DAI_BCI;
1208 break;
1209 case SND_SOC_DAIFMT_IB_IF:
1210 regval |= M98095_DAI_BCI|M98095_DAI_WCI;
1211 break;
1212 default:
1213 return -EINVAL;
1214 }
1215
1216 snd_soc_component_update_bits(component, M98095_02A_DAI1_FORMAT,
1217 M98095_DAI_MAS | M98095_DAI_DLY | M98095_DAI_BCI |
1218 M98095_DAI_WCI, regval);
1219
1220 snd_soc_component_write(component, M98095_02B_DAI1_CLOCK, M98095_DAI_BSEL64);
1221 }
1222
1223 return 0;
1224 }
1225
1226 static int max98095_dai2_set_fmt(struct snd_soc_dai *codec_dai,
1227 unsigned int fmt)
1228 {
1229 struct snd_soc_component *component = codec_dai->component;
1230 struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component);
1231 struct max98095_cdata *cdata;
1232 u8 regval = 0;
1233
1234 cdata = &max98095->dai[1];
1235
1236 if (fmt != cdata->fmt) {
1237 cdata->fmt = fmt;
1238
1239 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1240 case SND_SOC_DAIFMT_CBS_CFS:
1241 /* Slave mode PLL */
1242 snd_soc_component_write(component, M98095_032_DAI2_CLKCFG_HI,
1243 0x80);
1244 snd_soc_component_write(component, M98095_033_DAI2_CLKCFG_LO,
1245 0x00);
1246 break;
1247 case SND_SOC_DAIFMT_CBM_CFM:
1248 /* Set to master mode */
1249 regval |= M98095_DAI_MAS;
1250 break;
1251 case SND_SOC_DAIFMT_CBS_CFM:
1252 case SND_SOC_DAIFMT_CBM_CFS:
1253 default:
1254 dev_err(component->dev, "Clock mode unsupported");
1255 return -EINVAL;
1256 }
1257
1258 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1259 case SND_SOC_DAIFMT_I2S:
1260 regval |= M98095_DAI_DLY;
1261 break;
1262 case SND_SOC_DAIFMT_LEFT_J:
1263 break;
1264 default:
1265 return -EINVAL;
1266 }
1267
1268 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1269 case SND_SOC_DAIFMT_NB_NF:
1270 break;
1271 case SND_SOC_DAIFMT_NB_IF:
1272 regval |= M98095_DAI_WCI;
1273 break;
1274 case SND_SOC_DAIFMT_IB_NF:
1275 regval |= M98095_DAI_BCI;
1276 break;
1277 case SND_SOC_DAIFMT_IB_IF:
1278 regval |= M98095_DAI_BCI|M98095_DAI_WCI;
1279 break;
1280 default:
1281 return -EINVAL;
1282 }
1283
1284 snd_soc_component_update_bits(component, M98095_034_DAI2_FORMAT,
1285 M98095_DAI_MAS | M98095_DAI_DLY | M98095_DAI_BCI |
1286 M98095_DAI_WCI, regval);
1287
1288 snd_soc_component_write(component, M98095_035_DAI2_CLOCK,
1289 M98095_DAI_BSEL64);
1290 }
1291
1292 return 0;
1293 }
1294
1295 static int max98095_dai3_set_fmt(struct snd_soc_dai *codec_dai,
1296 unsigned int fmt)
1297 {
1298 struct snd_soc_component *component = codec_dai->component;
1299 struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component);
1300 struct max98095_cdata *cdata;
1301 u8 regval = 0;
1302
1303 cdata = &max98095->dai[2];
1304
1305 if (fmt != cdata->fmt) {
1306 cdata->fmt = fmt;
1307
1308 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1309 case SND_SOC_DAIFMT_CBS_CFS:
1310 /* Slave mode PLL */
1311 snd_soc_component_write(component, M98095_03C_DAI3_CLKCFG_HI,
1312 0x80);
1313 snd_soc_component_write(component, M98095_03D_DAI3_CLKCFG_LO,
1314 0x00);
1315 break;
1316 case SND_SOC_DAIFMT_CBM_CFM:
1317 /* Set to master mode */
1318 regval |= M98095_DAI_MAS;
1319 break;
1320 case SND_SOC_DAIFMT_CBS_CFM:
1321 case SND_SOC_DAIFMT_CBM_CFS:
1322 default:
1323 dev_err(component->dev, "Clock mode unsupported");
1324 return -EINVAL;
1325 }
1326
1327 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1328 case SND_SOC_DAIFMT_I2S:
1329 regval |= M98095_DAI_DLY;
1330 break;
1331 case SND_SOC_DAIFMT_LEFT_J:
1332 break;
1333 default:
1334 return -EINVAL;
1335 }
1336
1337 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1338 case SND_SOC_DAIFMT_NB_NF:
1339 break;
1340 case SND_SOC_DAIFMT_NB_IF:
1341 regval |= M98095_DAI_WCI;
1342 break;
1343 case SND_SOC_DAIFMT_IB_NF:
1344 regval |= M98095_DAI_BCI;
1345 break;
1346 case SND_SOC_DAIFMT_IB_IF:
1347 regval |= M98095_DAI_BCI|M98095_DAI_WCI;
1348 break;
1349 default:
1350 return -EINVAL;
1351 }
1352
1353 snd_soc_component_update_bits(component, M98095_03E_DAI3_FORMAT,
1354 M98095_DAI_MAS | M98095_DAI_DLY | M98095_DAI_BCI |
1355 M98095_DAI_WCI, regval);
1356
1357 snd_soc_component_write(component, M98095_03F_DAI3_CLOCK,
1358 M98095_DAI_BSEL64);
1359 }
1360
1361 return 0;
1362 }
1363
1364 static int max98095_set_bias_level(struct snd_soc_component *component,
1365 enum snd_soc_bias_level level)
1366 {
1367 struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component);
1368 int ret;
1369
1370 switch (level) {
1371 case SND_SOC_BIAS_ON:
1372 break;
1373
1374 case SND_SOC_BIAS_PREPARE:
1375 /*
1376 * SND_SOC_BIAS_PREPARE is called while preparing for a
1377 * transition to ON or away from ON. If current bias_level
1378 * is SND_SOC_BIAS_ON, then it is preparing for a transition
1379 * away from ON. Disable the clock in that case, otherwise
1380 * enable it.
1381 */
1382 if (IS_ERR(max98095->mclk))
1383 break;
1384
1385 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_ON) {
1386 clk_disable_unprepare(max98095->mclk);
1387 } else {
1388 ret = clk_prepare_enable(max98095->mclk);
1389 if (ret)
1390 return ret;
1391 }
1392 break;
1393
1394 case SND_SOC_BIAS_STANDBY:
1395 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
1396 ret = regcache_sync(max98095->regmap);
1397
1398 if (ret != 0) {
1399 dev_err(component->dev, "Failed to sync cache: %d\n", ret);
1400 return ret;
1401 }
1402 }
1403
1404 snd_soc_component_update_bits(component, M98095_090_PWR_EN_IN,
1405 M98095_MBEN, M98095_MBEN);
1406 break;
1407
1408 case SND_SOC_BIAS_OFF:
1409 snd_soc_component_update_bits(component, M98095_090_PWR_EN_IN,
1410 M98095_MBEN, 0);
1411 regcache_mark_dirty(max98095->regmap);
1412 break;
1413 }
1414 return 0;
1415 }
1416
1417 #define MAX98095_RATES SNDRV_PCM_RATE_8000_96000
1418 #define MAX98095_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE)
1419
1420 static const struct snd_soc_dai_ops max98095_dai1_ops = {
1421 .set_sysclk = max98095_dai_set_sysclk,
1422 .set_fmt = max98095_dai1_set_fmt,
1423 .hw_params = max98095_dai1_hw_params,
1424 };
1425
1426 static const struct snd_soc_dai_ops max98095_dai2_ops = {
1427 .set_sysclk = max98095_dai_set_sysclk,
1428 .set_fmt = max98095_dai2_set_fmt,
1429 .hw_params = max98095_dai2_hw_params,
1430 };
1431
1432 static const struct snd_soc_dai_ops max98095_dai3_ops = {
1433 .set_sysclk = max98095_dai_set_sysclk,
1434 .set_fmt = max98095_dai3_set_fmt,
1435 .hw_params = max98095_dai3_hw_params,
1436 };
1437
1438 static struct snd_soc_dai_driver max98095_dai[] = {
1439 {
1440 .name = "HiFi",
1441 .playback = {
1442 .stream_name = "HiFi Playback",
1443 .channels_min = 1,
1444 .channels_max = 2,
1445 .rates = MAX98095_RATES,
1446 .formats = MAX98095_FORMATS,
1447 },
1448 .capture = {
1449 .stream_name = "HiFi Capture",
1450 .channels_min = 1,
1451 .channels_max = 2,
1452 .rates = MAX98095_RATES,
1453 .formats = MAX98095_FORMATS,
1454 },
1455 .ops = &max98095_dai1_ops,
1456 },
1457 {
1458 .name = "Aux",
1459 .playback = {
1460 .stream_name = "Aux Playback",
1461 .channels_min = 1,
1462 .channels_max = 1,
1463 .rates = MAX98095_RATES,
1464 .formats = MAX98095_FORMATS,
1465 },
1466 .ops = &max98095_dai2_ops,
1467 },
1468 {
1469 .name = "Voice",
1470 .playback = {
1471 .stream_name = "Voice Playback",
1472 .channels_min = 1,
1473 .channels_max = 1,
1474 .rates = MAX98095_RATES,
1475 .formats = MAX98095_FORMATS,
1476 },
1477 .ops = &max98095_dai3_ops,
1478 }
1479
1480 };
1481
1482 static int max98095_get_eq_channel(const char *name)
1483 {
1484 if (strcmp(name, "EQ1 Mode") == 0)
1485 return 0;
1486 if (strcmp(name, "EQ2 Mode") == 0)
1487 return 1;
1488 return -EINVAL;
1489 }
1490
1491 static int max98095_put_eq_enum(struct snd_kcontrol *kcontrol,
1492 struct snd_ctl_elem_value *ucontrol)
1493 {
1494 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1495 struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component);
1496 struct max98095_pdata *pdata = max98095->pdata;
1497 int channel = max98095_get_eq_channel(kcontrol->id.name);
1498 struct max98095_cdata *cdata;
1499 unsigned int sel = ucontrol->value.enumerated.item[0];
1500 struct max98095_eq_cfg *coef_set;
1501 int fs, best, best_val, i;
1502 int regmask, regsave;
1503
1504 if (WARN_ON(channel > 1))
1505 return -EINVAL;
1506
1507 if (!pdata || !max98095->eq_textcnt)
1508 return 0;
1509
1510 if (sel >= pdata->eq_cfgcnt)
1511 return -EINVAL;
1512
1513 cdata = &max98095->dai[channel];
1514 cdata->eq_sel = sel;
1515 fs = cdata->rate;
1516
1517 /* Find the selected configuration with nearest sample rate */
1518 best = 0;
1519 best_val = INT_MAX;
1520 for (i = 0; i < pdata->eq_cfgcnt; i++) {
1521 if (strcmp(pdata->eq_cfg[i].name, max98095->eq_texts[sel]) == 0 &&
1522 abs(pdata->eq_cfg[i].rate - fs) < best_val) {
1523 best = i;
1524 best_val = abs(pdata->eq_cfg[i].rate - fs);
1525 }
1526 }
1527
1528 dev_dbg(component->dev, "Selected %s/%dHz for %dHz sample rate\n",
1529 pdata->eq_cfg[best].name,
1530 pdata->eq_cfg[best].rate, fs);
1531
1532 coef_set = &pdata->eq_cfg[best];
1533
1534 regmask = (channel == 0) ? M98095_EQ1EN : M98095_EQ2EN;
1535
1536 /* Disable filter while configuring, and save current on/off state */
1537 regsave = snd_soc_component_read32(component, M98095_088_CFG_LEVEL);
1538 snd_soc_component_update_bits(component, M98095_088_CFG_LEVEL, regmask, 0);
1539
1540 mutex_lock(&max98095->lock);
1541 snd_soc_component_update_bits(component, M98095_00F_HOST_CFG, M98095_SEG, M98095_SEG);
1542 m98095_eq_band(component, channel, 0, coef_set->band1);
1543 m98095_eq_band(component, channel, 1, coef_set->band2);
1544 m98095_eq_band(component, channel, 2, coef_set->band3);
1545 m98095_eq_band(component, channel, 3, coef_set->band4);
1546 m98095_eq_band(component, channel, 4, coef_set->band5);
1547 snd_soc_component_update_bits(component, M98095_00F_HOST_CFG, M98095_SEG, 0);
1548 mutex_unlock(&max98095->lock);
1549
1550 /* Restore the original on/off state */
1551 snd_soc_component_update_bits(component, M98095_088_CFG_LEVEL, regmask, regsave);
1552 return 0;
1553 }
1554
1555 static int max98095_get_eq_enum(struct snd_kcontrol *kcontrol,
1556 struct snd_ctl_elem_value *ucontrol)
1557 {
1558 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1559 struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component);
1560 int channel = max98095_get_eq_channel(kcontrol->id.name);
1561 struct max98095_cdata *cdata;
1562
1563 cdata = &max98095->dai[channel];
1564 ucontrol->value.enumerated.item[0] = cdata->eq_sel;
1565
1566 return 0;
1567 }
1568
1569 static void max98095_handle_eq_pdata(struct snd_soc_component *component)
1570 {
1571 struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component);
1572 struct max98095_pdata *pdata = max98095->pdata;
1573 struct max98095_eq_cfg *cfg;
1574 unsigned int cfgcnt;
1575 int i, j;
1576 const char **t;
1577 int ret;
1578
1579 struct snd_kcontrol_new controls[] = {
1580 SOC_ENUM_EXT("EQ1 Mode",
1581 max98095->eq_enum,
1582 max98095_get_eq_enum,
1583 max98095_put_eq_enum),
1584 SOC_ENUM_EXT("EQ2 Mode",
1585 max98095->eq_enum,
1586 max98095_get_eq_enum,
1587 max98095_put_eq_enum),
1588 };
1589
1590 cfg = pdata->eq_cfg;
1591 cfgcnt = pdata->eq_cfgcnt;
1592
1593 /* Setup an array of texts for the equalizer enum.
1594 * This is based on Mark Brown's equalizer driver code.
1595 */
1596 max98095->eq_textcnt = 0;
1597 max98095->eq_texts = NULL;
1598 for (i = 0; i < cfgcnt; i++) {
1599 for (j = 0; j < max98095->eq_textcnt; j++) {
1600 if (strcmp(cfg[i].name, max98095->eq_texts[j]) == 0)
1601 break;
1602 }
1603
1604 if (j != max98095->eq_textcnt)
1605 continue;
1606
1607 /* Expand the array */
1608 t = krealloc(max98095->eq_texts,
1609 sizeof(char *) * (max98095->eq_textcnt + 1),
1610 GFP_KERNEL);
1611 if (t == NULL)
1612 continue;
1613
1614 /* Store the new entry */
1615 t[max98095->eq_textcnt] = cfg[i].name;
1616 max98095->eq_textcnt++;
1617 max98095->eq_texts = t;
1618 }
1619
1620 /* Now point the soc_enum to .texts array items */
1621 max98095->eq_enum.texts = max98095->eq_texts;
1622 max98095->eq_enum.items = max98095->eq_textcnt;
1623
1624 ret = snd_soc_add_component_controls(component, controls, ARRAY_SIZE(controls));
1625 if (ret != 0)
1626 dev_err(component->dev, "Failed to add EQ control: %d\n", ret);
1627 }
1628
1629 static const char *bq_mode_name[] = {"Biquad1 Mode", "Biquad2 Mode"};
1630
1631 static int max98095_get_bq_channel(struct snd_soc_component *component,
1632 const char *name)
1633 {
1634 int ret;
1635
1636 ret = match_string(bq_mode_name, ARRAY_SIZE(bq_mode_name), name);
1637 if (ret < 0)
1638 dev_err(component->dev, "Bad biquad channel name '%s'\n", name);
1639 return ret;
1640 }
1641
1642 static int max98095_put_bq_enum(struct snd_kcontrol *kcontrol,
1643 struct snd_ctl_elem_value *ucontrol)
1644 {
1645 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1646 struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component);
1647 struct max98095_pdata *pdata = max98095->pdata;
1648 int channel = max98095_get_bq_channel(component, kcontrol->id.name);
1649 struct max98095_cdata *cdata;
1650 unsigned int sel = ucontrol->value.enumerated.item[0];
1651 struct max98095_biquad_cfg *coef_set;
1652 int fs, best, best_val, i;
1653 int regmask, regsave;
1654
1655 if (channel < 0)
1656 return channel;
1657
1658 if (!pdata || !max98095->bq_textcnt)
1659 return 0;
1660
1661 if (sel >= pdata->bq_cfgcnt)
1662 return -EINVAL;
1663
1664 cdata = &max98095->dai[channel];
1665 cdata->bq_sel = sel;
1666 fs = cdata->rate;
1667
1668 /* Find the selected configuration with nearest sample rate */
1669 best = 0;
1670 best_val = INT_MAX;
1671 for (i = 0; i < pdata->bq_cfgcnt; i++) {
1672 if (strcmp(pdata->bq_cfg[i].name, max98095->bq_texts[sel]) == 0 &&
1673 abs(pdata->bq_cfg[i].rate - fs) < best_val) {
1674 best = i;
1675 best_val = abs(pdata->bq_cfg[i].rate - fs);
1676 }
1677 }
1678
1679 dev_dbg(component->dev, "Selected %s/%dHz for %dHz sample rate\n",
1680 pdata->bq_cfg[best].name,
1681 pdata->bq_cfg[best].rate, fs);
1682
1683 coef_set = &pdata->bq_cfg[best];
1684
1685 regmask = (channel == 0) ? M98095_BQ1EN : M98095_BQ2EN;
1686
1687 /* Disable filter while configuring, and save current on/off state */
1688 regsave = snd_soc_component_read32(component, M98095_088_CFG_LEVEL);
1689 snd_soc_component_update_bits(component, M98095_088_CFG_LEVEL, regmask, 0);
1690
1691 mutex_lock(&max98095->lock);
1692 snd_soc_component_update_bits(component, M98095_00F_HOST_CFG, M98095_SEG, M98095_SEG);
1693 m98095_biquad_band(component, channel, 0, coef_set->band1);
1694 m98095_biquad_band(component, channel, 1, coef_set->band2);
1695 snd_soc_component_update_bits(component, M98095_00F_HOST_CFG, M98095_SEG, 0);
1696 mutex_unlock(&max98095->lock);
1697
1698 /* Restore the original on/off state */
1699 snd_soc_component_update_bits(component, M98095_088_CFG_LEVEL, regmask, regsave);
1700 return 0;
1701 }
1702
1703 static int max98095_get_bq_enum(struct snd_kcontrol *kcontrol,
1704 struct snd_ctl_elem_value *ucontrol)
1705 {
1706 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1707 struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component);
1708 int channel = max98095_get_bq_channel(component, kcontrol->id.name);
1709 struct max98095_cdata *cdata;
1710
1711 if (channel < 0)
1712 return channel;
1713
1714 cdata = &max98095->dai[channel];
1715 ucontrol->value.enumerated.item[0] = cdata->bq_sel;
1716
1717 return 0;
1718 }
1719
1720 static void max98095_handle_bq_pdata(struct snd_soc_component *component)
1721 {
1722 struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component);
1723 struct max98095_pdata *pdata = max98095->pdata;
1724 struct max98095_biquad_cfg *cfg;
1725 unsigned int cfgcnt;
1726 int i, j;
1727 const char **t;
1728 int ret;
1729
1730 struct snd_kcontrol_new controls[] = {
1731 SOC_ENUM_EXT((char *)bq_mode_name[0],
1732 max98095->bq_enum,
1733 max98095_get_bq_enum,
1734 max98095_put_bq_enum),
1735 SOC_ENUM_EXT((char *)bq_mode_name[1],
1736 max98095->bq_enum,
1737 max98095_get_bq_enum,
1738 max98095_put_bq_enum),
1739 };
1740 BUILD_BUG_ON(ARRAY_SIZE(controls) != ARRAY_SIZE(bq_mode_name));
1741
1742 cfg = pdata->bq_cfg;
1743 cfgcnt = pdata->bq_cfgcnt;
1744
1745 /* Setup an array of texts for the biquad enum.
1746 * This is based on Mark Brown's equalizer driver code.
1747 */
1748 max98095->bq_textcnt = 0;
1749 max98095->bq_texts = NULL;
1750 for (i = 0; i < cfgcnt; i++) {
1751 for (j = 0; j < max98095->bq_textcnt; j++) {
1752 if (strcmp(cfg[i].name, max98095->bq_texts[j]) == 0)
1753 break;
1754 }
1755
1756 if (j != max98095->bq_textcnt)
1757 continue;
1758
1759 /* Expand the array */
1760 t = krealloc(max98095->bq_texts,
1761 sizeof(char *) * (max98095->bq_textcnt + 1),
1762 GFP_KERNEL);
1763 if (t == NULL)
1764 continue;
1765
1766 /* Store the new entry */
1767 t[max98095->bq_textcnt] = cfg[i].name;
1768 max98095->bq_textcnt++;
1769 max98095->bq_texts = t;
1770 }
1771
1772 /* Now point the soc_enum to .texts array items */
1773 max98095->bq_enum.texts = max98095->bq_texts;
1774 max98095->bq_enum.items = max98095->bq_textcnt;
1775
1776 ret = snd_soc_add_component_controls(component, controls, ARRAY_SIZE(controls));
1777 if (ret != 0)
1778 dev_err(component->dev, "Failed to add Biquad control: %d\n", ret);
1779 }
1780
1781 static void max98095_handle_pdata(struct snd_soc_component *component)
1782 {
1783 struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component);
1784 struct max98095_pdata *pdata = max98095->pdata;
1785 u8 regval = 0;
1786
1787 if (!pdata) {
1788 dev_dbg(component->dev, "No platform data\n");
1789 return;
1790 }
1791
1792 /* Configure mic for analog/digital mic mode */
1793 if (pdata->digmic_left_mode)
1794 regval |= M98095_DIGMIC_L;
1795
1796 if (pdata->digmic_right_mode)
1797 regval |= M98095_DIGMIC_R;
1798
1799 snd_soc_component_write(component, M98095_087_CFG_MIC, regval);
1800
1801 /* Configure equalizers */
1802 if (pdata->eq_cfgcnt)
1803 max98095_handle_eq_pdata(component);
1804
1805 /* Configure bi-quad filters */
1806 if (pdata->bq_cfgcnt)
1807 max98095_handle_bq_pdata(component);
1808 }
1809
1810 static irqreturn_t max98095_report_jack(int irq, void *data)
1811 {
1812 struct snd_soc_component *component = data;
1813 struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component);
1814 unsigned int value;
1815 int hp_report = 0;
1816 int mic_report = 0;
1817
1818 /* Read the Jack Status Register */
1819 value = snd_soc_component_read32(component, M98095_007_JACK_AUTO_STS);
1820
1821 /* If ddone is not set, then detection isn't finished yet */
1822 if ((value & M98095_DDONE) == 0)
1823 return IRQ_NONE;
1824
1825 /* if hp, check its bit, and if set, clear it */
1826 if ((value & M98095_HP_IN || value & M98095_LO_IN) &&
1827 max98095->headphone_jack)
1828 hp_report |= SND_JACK_HEADPHONE;
1829
1830 /* if mic, check its bit, and if set, clear it */
1831 if ((value & M98095_MIC_IN) && max98095->mic_jack)
1832 mic_report |= SND_JACK_MICROPHONE;
1833
1834 if (max98095->headphone_jack == max98095->mic_jack) {
1835 snd_soc_jack_report(max98095->headphone_jack,
1836 hp_report | mic_report,
1837 SND_JACK_HEADSET);
1838 } else {
1839 if (max98095->headphone_jack)
1840 snd_soc_jack_report(max98095->headphone_jack,
1841 hp_report, SND_JACK_HEADPHONE);
1842 if (max98095->mic_jack)
1843 snd_soc_jack_report(max98095->mic_jack,
1844 mic_report, SND_JACK_MICROPHONE);
1845 }
1846
1847 return IRQ_HANDLED;
1848 }
1849
1850 static int max98095_jack_detect_enable(struct snd_soc_component *component)
1851 {
1852 struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component);
1853 int ret = 0;
1854 int detect_enable = M98095_JDEN;
1855 unsigned int slew = M98095_DEFAULT_SLEW_DELAY;
1856
1857 if (max98095->pdata->jack_detect_pin5en)
1858 detect_enable |= M98095_PIN5EN;
1859
1860 if (max98095->pdata->jack_detect_delay)
1861 slew = max98095->pdata->jack_detect_delay;
1862
1863 ret = snd_soc_component_write(component, M98095_08E_JACK_DC_SLEW, slew);
1864 if (ret < 0) {
1865 dev_err(component->dev, "Failed to cfg auto detect %d\n", ret);
1866 return ret;
1867 }
1868
1869 /* configure auto detection to be enabled */
1870 ret = snd_soc_component_write(component, M98095_089_JACK_DET_AUTO, detect_enable);
1871 if (ret < 0) {
1872 dev_err(component->dev, "Failed to cfg auto detect %d\n", ret);
1873 return ret;
1874 }
1875
1876 return ret;
1877 }
1878
1879 static int max98095_jack_detect_disable(struct snd_soc_component *component)
1880 {
1881 int ret = 0;
1882
1883 /* configure auto detection to be disabled */
1884 ret = snd_soc_component_write(component, M98095_089_JACK_DET_AUTO, 0x0);
1885 if (ret < 0) {
1886 dev_err(component->dev, "Failed to cfg auto detect %d\n", ret);
1887 return ret;
1888 }
1889
1890 return ret;
1891 }
1892
1893 int max98095_jack_detect(struct snd_soc_component *component,
1894 struct snd_soc_jack *hp_jack, struct snd_soc_jack *mic_jack)
1895 {
1896 struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component);
1897 struct i2c_client *client = to_i2c_client(component->dev);
1898 int ret = 0;
1899
1900 max98095->headphone_jack = hp_jack;
1901 max98095->mic_jack = mic_jack;
1902
1903 /* only progress if we have at least 1 jack pointer */
1904 if (!hp_jack && !mic_jack)
1905 return -EINVAL;
1906
1907 max98095_jack_detect_enable(component);
1908
1909 /* enable interrupts for headphone jack detection */
1910 ret = snd_soc_component_update_bits(component, M98095_013_JACK_INT_EN,
1911 M98095_IDDONE, M98095_IDDONE);
1912 if (ret < 0) {
1913 dev_err(component->dev, "Failed to cfg jack irqs %d\n", ret);
1914 return ret;
1915 }
1916
1917 max98095_report_jack(client->irq, component);
1918 return 0;
1919 }
1920 EXPORT_SYMBOL_GPL(max98095_jack_detect);
1921
1922 #ifdef CONFIG_PM
1923 static int max98095_suspend(struct snd_soc_component *component)
1924 {
1925 struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component);
1926
1927 if (max98095->headphone_jack || max98095->mic_jack)
1928 max98095_jack_detect_disable(component);
1929
1930 snd_soc_component_force_bias_level(component, SND_SOC_BIAS_OFF);
1931
1932 return 0;
1933 }
1934
1935 static int max98095_resume(struct snd_soc_component *component)
1936 {
1937 struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component);
1938 struct i2c_client *client = to_i2c_client(component->dev);
1939
1940 snd_soc_component_force_bias_level(component, SND_SOC_BIAS_STANDBY);
1941
1942 if (max98095->headphone_jack || max98095->mic_jack) {
1943 max98095_jack_detect_enable(component);
1944 max98095_report_jack(client->irq, component);
1945 }
1946
1947 return 0;
1948 }
1949 #else
1950 #define max98095_suspend NULL
1951 #define max98095_resume NULL
1952 #endif
1953
1954 static int max98095_reset(struct snd_soc_component *component)
1955 {
1956 int i, ret;
1957
1958 /* Gracefully reset the DSP core and the codec hardware
1959 * in a proper sequence */
1960 ret = snd_soc_component_write(component, M98095_00F_HOST_CFG, 0);
1961 if (ret < 0) {
1962 dev_err(component->dev, "Failed to reset DSP: %d\n", ret);
1963 return ret;
1964 }
1965
1966 ret = snd_soc_component_write(component, M98095_097_PWR_SYS, 0);
1967 if (ret < 0) {
1968 dev_err(component->dev, "Failed to reset component: %d\n", ret);
1969 return ret;
1970 }
1971
1972 /* Reset to hardware default for registers, as there is not
1973 * a soft reset hardware control register */
1974 for (i = M98095_010_HOST_INT_CFG; i < M98095_REG_MAX_CACHED; i++) {
1975 ret = snd_soc_component_write(component, i, snd_soc_component_read32(component, i));
1976 if (ret < 0) {
1977 dev_err(component->dev, "Failed to reset: %d\n", ret);
1978 return ret;
1979 }
1980 }
1981
1982 return ret;
1983 }
1984
1985 static int max98095_probe(struct snd_soc_component *component)
1986 {
1987 struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component);
1988 struct max98095_cdata *cdata;
1989 struct i2c_client *client;
1990 int ret = 0;
1991
1992 max98095->mclk = devm_clk_get(component->dev, "mclk");
1993 if (PTR_ERR(max98095->mclk) == -EPROBE_DEFER)
1994 return -EPROBE_DEFER;
1995
1996 /* reset the codec, the DSP core, and disable all interrupts */
1997 max98095_reset(component);
1998
1999 client = to_i2c_client(component->dev);
2000
2001 /* initialize private data */
2002
2003 max98095->sysclk = (unsigned)-1;
2004 max98095->eq_textcnt = 0;
2005 max98095->bq_textcnt = 0;
2006
2007 cdata = &max98095->dai[0];
2008 cdata->rate = (unsigned)-1;
2009 cdata->fmt = (unsigned)-1;
2010 cdata->eq_sel = 0;
2011 cdata->bq_sel = 0;
2012
2013 cdata = &max98095->dai[1];
2014 cdata->rate = (unsigned)-1;
2015 cdata->fmt = (unsigned)-1;
2016 cdata->eq_sel = 0;
2017 cdata->bq_sel = 0;
2018
2019 cdata = &max98095->dai[2];
2020 cdata->rate = (unsigned)-1;
2021 cdata->fmt = (unsigned)-1;
2022 cdata->eq_sel = 0;
2023 cdata->bq_sel = 0;
2024
2025 max98095->lin_state = 0;
2026 max98095->mic1pre = 0;
2027 max98095->mic2pre = 0;
2028
2029 if (client->irq) {
2030 /* register an audio interrupt */
2031 ret = request_threaded_irq(client->irq, NULL,
2032 max98095_report_jack,
2033 IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING |
2034 IRQF_ONESHOT, "max98095", component);
2035 if (ret) {
2036 dev_err(component->dev, "Failed to request IRQ: %d\n", ret);
2037 goto err_access;
2038 }
2039 }
2040
2041 ret = snd_soc_component_read32(component, M98095_0FF_REV_ID);
2042 if (ret < 0) {
2043 dev_err(component->dev, "Failure reading hardware revision: %d\n",
2044 ret);
2045 goto err_irq;
2046 }
2047 dev_info(component->dev, "Hardware revision: %c\n", ret - 0x40 + 'A');
2048
2049 snd_soc_component_write(component, M98095_097_PWR_SYS, M98095_PWRSV);
2050
2051 snd_soc_component_write(component, M98095_048_MIX_DAC_LR,
2052 M98095_DAI1L_TO_DACL|M98095_DAI1R_TO_DACR);
2053
2054 snd_soc_component_write(component, M98095_049_MIX_DAC_M,
2055 M98095_DAI2M_TO_DACM|M98095_DAI3M_TO_DACM);
2056
2057 snd_soc_component_write(component, M98095_092_PWR_EN_OUT, M98095_SPK_SPREADSPECTRUM);
2058 snd_soc_component_write(component, M98095_045_CFG_DSP, M98095_DSPNORMAL);
2059 snd_soc_component_write(component, M98095_04E_CFG_HP, M98095_HPNORMAL);
2060
2061 snd_soc_component_write(component, M98095_02C_DAI1_IOCFG,
2062 M98095_S1NORMAL|M98095_SDATA);
2063
2064 snd_soc_component_write(component, M98095_036_DAI2_IOCFG,
2065 M98095_S2NORMAL|M98095_SDATA);
2066
2067 snd_soc_component_write(component, M98095_040_DAI3_IOCFG,
2068 M98095_S3NORMAL|M98095_SDATA);
2069
2070 max98095_handle_pdata(component);
2071
2072 /* take the codec out of the shut down */
2073 snd_soc_component_update_bits(component, M98095_097_PWR_SYS, M98095_SHDNRUN,
2074 M98095_SHDNRUN);
2075
2076 return 0;
2077
2078 err_irq:
2079 if (client->irq)
2080 free_irq(client->irq, component);
2081 err_access:
2082 return ret;
2083 }
2084
2085 static void max98095_remove(struct snd_soc_component *component)
2086 {
2087 struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component);
2088 struct i2c_client *client = to_i2c_client(component->dev);
2089
2090 if (max98095->headphone_jack || max98095->mic_jack)
2091 max98095_jack_detect_disable(component);
2092
2093 if (client->irq)
2094 free_irq(client->irq, component);
2095 }
2096
2097 static const struct snd_soc_component_driver soc_component_dev_max98095 = {
2098 .probe = max98095_probe,
2099 .remove = max98095_remove,
2100 .suspend = max98095_suspend,
2101 .resume = max98095_resume,
2102 .set_bias_level = max98095_set_bias_level,
2103 .controls = max98095_snd_controls,
2104 .num_controls = ARRAY_SIZE(max98095_snd_controls),
2105 .dapm_widgets = max98095_dapm_widgets,
2106 .num_dapm_widgets = ARRAY_SIZE(max98095_dapm_widgets),
2107 .dapm_routes = max98095_audio_map,
2108 .num_dapm_routes = ARRAY_SIZE(max98095_audio_map),
2109 .idle_bias_on = 1,
2110 .use_pmdown_time = 1,
2111 .endianness = 1,
2112 .non_legacy_dai_naming = 1,
2113 };
2114
2115 static int max98095_i2c_probe(struct i2c_client *i2c,
2116 const struct i2c_device_id *id)
2117 {
2118 struct max98095_priv *max98095;
2119 int ret;
2120
2121 max98095 = devm_kzalloc(&i2c->dev, sizeof(struct max98095_priv),
2122 GFP_KERNEL);
2123 if (max98095 == NULL)
2124 return -ENOMEM;
2125
2126 mutex_init(&max98095->lock);
2127
2128 max98095->regmap = devm_regmap_init_i2c(i2c, &max98095_regmap);
2129 if (IS_ERR(max98095->regmap)) {
2130 ret = PTR_ERR(max98095->regmap);
2131 dev_err(&i2c->dev, "Failed to allocate regmap: %d\n", ret);
2132 return ret;
2133 }
2134
2135 max98095->devtype = id->driver_data;
2136 i2c_set_clientdata(i2c, max98095);
2137 max98095->pdata = i2c->dev.platform_data;
2138
2139 ret = devm_snd_soc_register_component(&i2c->dev,
2140 &soc_component_dev_max98095,
2141 max98095_dai, ARRAY_SIZE(max98095_dai));
2142 return ret;
2143 }
2144
2145 static const struct i2c_device_id max98095_i2c_id[] = {
2146 { "max98095", MAX98095 },
2147 { }
2148 };
2149 MODULE_DEVICE_TABLE(i2c, max98095_i2c_id);
2150
2151 static const struct of_device_id max98095_of_match[] = {
2152 { .compatible = "maxim,max98095", },
2153 { }
2154 };
2155 MODULE_DEVICE_TABLE(of, max98095_of_match);
2156
2157 static struct i2c_driver max98095_i2c_driver = {
2158 .driver = {
2159 .name = "max98095",
2160 .of_match_table = of_match_ptr(max98095_of_match),
2161 },
2162 .probe = max98095_i2c_probe,
2163 .id_table = max98095_i2c_id,
2164 };
2165
2166 module_i2c_driver(max98095_i2c_driver);
2167
2168 MODULE_DESCRIPTION("ALSA SoC MAX98095 driver");
2169 MODULE_AUTHOR("Peter Hsiang");
2170 MODULE_LICENSE("GPL");
Linux with added FPC-III support