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ARM: dts: omap5: Add bus_dma_limit for L3 bus
[linux/fpc-iii.git] / sound / soc / codecs / rt1305.c
blobe27742abfa765fcc989ea068f789c7b7fcbc493a
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * rt1305.c -- RT1305 ALSA SoC amplifier component driver
4 *
5 * Copyright 2018 Realtek Semiconductor Corp.
6 * Author: Shuming Fan <shumingf@realtek.com>
7 */
8
9 #include <linux/module.h>
10 #include <linux/moduleparam.h>
11 #include <linux/init.h>
12 #include <linux/delay.h>
13 #include <linux/pm.h>
14 #include <linux/acpi.h>
15 #include <linux/gpio.h>
16 #include <linux/i2c.h>
17 #include <linux/regmap.h>
18 #include <linux/of_gpio.h>
19 #include <linux/platform_device.h>
20 #include <linux/firmware.h>
21 #include <sound/core.h>
22 #include <sound/pcm.h>
23 #include <sound/pcm_params.h>
24 #include <sound/soc.h>
25 #include <sound/soc-dapm.h>
26 #include <sound/initval.h>
27 #include <sound/tlv.h>
28
29 #include "rl6231.h"
30 #include "rt1305.h"
31
32
33 #define RT1305_PR_RANGE_BASE (0xff + 1)
34 #define RT1305_PR_SPACING 0x100
35
36 #define RT1305_PR_BASE (RT1305_PR_RANGE_BASE + (0 * RT1305_PR_SPACING))
37
38
39 static const struct regmap_range_cfg rt1305_ranges[] = {
40 {
41 .name = "PR",
42 .range_min = RT1305_PR_BASE,
43 .range_max = RT1305_PR_BASE + 0xff,
44 .selector_reg = RT1305_PRIV_INDEX,
45 .selector_mask = 0xff,
46 .selector_shift = 0x0,
47 .window_start = RT1305_PRIV_DATA,
48 .window_len = 0x1,
49 },
50 };
51
52
53 static const struct reg_sequence init_list[] = {
54
55 { RT1305_PR_BASE + 0xcf, 0x5548 },
56 { RT1305_PR_BASE + 0x5d, 0x0442 },
57 { RT1305_PR_BASE + 0xc1, 0x0320 },
58
59 { RT1305_POWER_STATUS, 0x0000 },
60
61 { RT1305_SPK_TEMP_PROTECTION_1, 0xd6de },
62 { RT1305_SPK_TEMP_PROTECTION_2, 0x0707 },
63 { RT1305_SPK_TEMP_PROTECTION_3, 0x4090 },
64
65 { RT1305_DAC_SET_1, 0xdfdf }, /* 4 ohm 2W */
66 { RT1305_ADC_SET_3, 0x0219 },
67 { RT1305_ADC_SET_1, 0x170f }, /* 0.2 ohm RSense*/
68
69 };
70 #define RT1305_INIT_REG_LEN ARRAY_SIZE(init_list)
71
72 struct rt1305_priv {
73 struct snd_soc_component *component;
74 struct regmap *regmap;
75
76 int sysclk;
77 int sysclk_src;
78 int lrck;
79 int bclk;
80 int master;
81
82 int pll_src;
83 int pll_in;
84 int pll_out;
85 };
86
87 static const struct reg_default rt1305_reg[] = {
88
89 { 0x04, 0x0400 },
90 { 0x05, 0x0880 },
91 { 0x06, 0x0000 },
92 { 0x07, 0x3100 },
93 { 0x08, 0x8000 },
94 { 0x09, 0x0000 },
95 { 0x0a, 0x087e },
96 { 0x0b, 0x0020 },
97 { 0x0c, 0x0802 },
98 { 0x0d, 0x0020 },
99 { 0x10, 0x1d1d },
100 { 0x11, 0x1d1d },
101 { 0x12, 0xffff },
102 { 0x14, 0x000c },
103 { 0x16, 0x1717 },
104 { 0x17, 0x4000 },
105 { 0x18, 0x0019 },
106 { 0x20, 0x0000 },
107 { 0x22, 0x0000 },
108 { 0x24, 0x0000 },
109 { 0x26, 0x0000 },
110 { 0x28, 0x0000 },
111 { 0x2a, 0x4000 },
112 { 0x2b, 0x3000 },
113 { 0x2d, 0x6000 },
114 { 0x2e, 0x0000 },
115 { 0x2f, 0x8000 },
116 { 0x32, 0x0000 },
117 { 0x39, 0x0001 },
118 { 0x3a, 0x0000 },
119 { 0x3b, 0x1020 },
120 { 0x3c, 0x0000 },
121 { 0x3d, 0x0000 },
122 { 0x3e, 0x4c00 },
123 { 0x3f, 0x3000 },
124 { 0x40, 0x000c },
125 { 0x42, 0x0400 },
126 { 0x46, 0xc22c },
127 { 0x47, 0x0000 },
128 { 0x4b, 0x0000 },
129 { 0x4c, 0x0300 },
130 { 0x4f, 0xf000 },
131 { 0x50, 0xc200 },
132 { 0x51, 0x1f1f },
133 { 0x52, 0x01f0 },
134 { 0x53, 0x407f },
135 { 0x54, 0xffff },
136 { 0x58, 0x4005 },
137 { 0x5e, 0x0000 },
138 { 0x5f, 0x0000 },
139 { 0x60, 0xee13 },
140 { 0x62, 0x0000 },
141 { 0x63, 0x5f5f },
142 { 0x64, 0x0040 },
143 { 0x65, 0x4000 },
144 { 0x66, 0x4004 },
145 { 0x67, 0x0306 },
146 { 0x68, 0x8c04 },
147 { 0x69, 0xe021 },
148 { 0x6a, 0x0000 },
149 { 0x6c, 0xaaaa },
150 { 0x70, 0x0333 },
151 { 0x71, 0x3330 },
152 { 0x72, 0x3333 },
153 { 0x73, 0x3300 },
154 { 0x74, 0x0000 },
155 { 0x75, 0x0000 },
156 { 0x76, 0x0000 },
157 { 0x7a, 0x0003 },
158 { 0x7c, 0x10ec },
159 { 0x7e, 0x6251 },
160 { 0x80, 0x0800 },
161 { 0x81, 0x4000 },
162 { 0x82, 0x0000 },
163 { 0x90, 0x7a01 },
164 { 0x91, 0x8431 },
165 { 0x92, 0x0180 },
166 { 0x93, 0x0000 },
167 { 0x94, 0x0000 },
168 { 0x95, 0x0000 },
169 { 0x96, 0x0000 },
170 { 0x97, 0x0000 },
171 { 0x98, 0x0000 },
172 { 0x99, 0x0000 },
173 { 0x9a, 0x0000 },
174 { 0x9b, 0x0000 },
175 { 0x9c, 0x0000 },
176 { 0x9d, 0x0000 },
177 { 0x9e, 0x0000 },
178 { 0x9f, 0x0000 },
179 { 0xa0, 0x0000 },
180 { 0xb0, 0x8200 },
181 { 0xb1, 0x00ff },
182 { 0xb2, 0x0008 },
183 { 0xc0, 0x0200 },
184 { 0xc1, 0x0000 },
185 { 0xc2, 0x0000 },
186 { 0xc3, 0x0000 },
187 { 0xc4, 0x0000 },
188 { 0xc5, 0x0000 },
189 { 0xc6, 0x0000 },
190 { 0xc7, 0x0000 },
191 { 0xc8, 0x0000 },
192 { 0xc9, 0x0000 },
193 { 0xca, 0x0200 },
194 { 0xcb, 0x0000 },
195 { 0xcc, 0x0000 },
196 { 0xcd, 0x0000 },
197 { 0xce, 0x0000 },
198 { 0xcf, 0x0000 },
199 { 0xd0, 0x0000 },
200 { 0xd1, 0x0000 },
201 { 0xd2, 0x0000 },
202 { 0xd3, 0x0000 },
203 { 0xd4, 0x0200 },
204 { 0xd5, 0x0000 },
205 { 0xd6, 0x0000 },
206 { 0xd7, 0x0000 },
207 { 0xd8, 0x0000 },
208 { 0xd9, 0x0000 },
209 { 0xda, 0x0000 },
210 { 0xdb, 0x0000 },
211 { 0xdc, 0x0000 },
212 { 0xdd, 0x0000 },
213 { 0xde, 0x0200 },
214 { 0xdf, 0x0000 },
215 { 0xe0, 0x0000 },
216 { 0xe1, 0x0000 },
217 { 0xe2, 0x0000 },
218 { 0xe3, 0x0000 },
219 { 0xe4, 0x0000 },
220 { 0xe5, 0x0000 },
221 { 0xe6, 0x0000 },
222 { 0xe7, 0x0000 },
223 { 0xe8, 0x0200 },
224 { 0xe9, 0x0000 },
225 { 0xea, 0x0000 },
226 { 0xeb, 0x0000 },
227 { 0xec, 0x0000 },
228 { 0xed, 0x0000 },
229 { 0xee, 0x0000 },
230 { 0xef, 0x0000 },
231 { 0xf0, 0x0000 },
232 { 0xf1, 0x0000 },
233 { 0xf2, 0x0200 },
234 { 0xf3, 0x0000 },
235 { 0xf4, 0x0000 },
236 { 0xf5, 0x0000 },
237 { 0xf6, 0x0000 },
238 { 0xf7, 0x0000 },
239 { 0xf8, 0x0000 },
240 { 0xf9, 0x0000 },
241 { 0xfa, 0x0000 },
242 { 0xfb, 0x0000 },
243 };
244
245 static int rt1305_reg_init(struct snd_soc_component *component)
246 {
247 struct rt1305_priv *rt1305 = snd_soc_component_get_drvdata(component);
248
249 regmap_multi_reg_write(rt1305->regmap, init_list, RT1305_INIT_REG_LEN);
250 return 0;
251 }
252
253 static bool rt1305_volatile_register(struct device *dev, unsigned int reg)
254 {
255 int i;
256
257 for (i = 0; i < ARRAY_SIZE(rt1305_ranges); i++) {
258 if (reg >= rt1305_ranges[i].range_min &&
259 reg <= rt1305_ranges[i].range_max) {
260 return true;
261 }
262 }
263
264 switch (reg) {
265 case RT1305_RESET:
266 case RT1305_SPDIF_IN_SET_1:
267 case RT1305_SPDIF_IN_SET_2:
268 case RT1305_SPDIF_IN_SET_3:
269 case RT1305_POWER_CTRL_2:
270 case RT1305_CLOCK_DETECT:
271 case RT1305_BIQUAD_SET_1:
272 case RT1305_BIQUAD_SET_2:
273 case RT1305_EQ_SET_2:
274 case RT1305_SPK_TEMP_PROTECTION_0:
275 case RT1305_SPK_TEMP_PROTECTION_2:
276 case RT1305_SPK_DC_DETECT_1:
277 case RT1305_SILENCE_DETECT:
278 case RT1305_VERSION_ID:
279 case RT1305_VENDOR_ID:
280 case RT1305_DEVICE_ID:
281 case RT1305_EFUSE_1:
282 case RT1305_EFUSE_3:
283 case RT1305_DC_CALIB_1:
284 case RT1305_DC_CALIB_3:
285 case RT1305_DAC_OFFSET_1:
286 case RT1305_DAC_OFFSET_2:
287 case RT1305_DAC_OFFSET_3:
288 case RT1305_DAC_OFFSET_4:
289 case RT1305_DAC_OFFSET_5:
290 case RT1305_DAC_OFFSET_6:
291 case RT1305_DAC_OFFSET_7:
292 case RT1305_DAC_OFFSET_8:
293 case RT1305_DAC_OFFSET_9:
294 case RT1305_DAC_OFFSET_10:
295 case RT1305_DAC_OFFSET_11:
296 case RT1305_TRIM_1:
297 case RT1305_TRIM_2:
298 return true;
299
300 default:
301 return false;
302 }
303 }
304
305 static bool rt1305_readable_register(struct device *dev, unsigned int reg)
306 {
307 int i;
308
309 for (i = 0; i < ARRAY_SIZE(rt1305_ranges); i++) {
310 if (reg >= rt1305_ranges[i].range_min &&
311 reg <= rt1305_ranges[i].range_max) {
312 return true;
313 }
314 }
315
316 switch (reg) {
317 case RT1305_RESET:
318 case RT1305_CLK_1 ... RT1305_CAL_EFUSE_CLOCK:
319 case RT1305_PLL0_1 ... RT1305_PLL1_2:
320 case RT1305_MIXER_CTRL_1:
321 case RT1305_MIXER_CTRL_2:
322 case RT1305_DAC_SET_1:
323 case RT1305_DAC_SET_2:
324 case RT1305_ADC_SET_1:
325 case RT1305_ADC_SET_2:
326 case RT1305_ADC_SET_3:
327 case RT1305_PATH_SET:
328 case RT1305_SPDIF_IN_SET_1:
329 case RT1305_SPDIF_IN_SET_2:
330 case RT1305_SPDIF_IN_SET_3:
331 case RT1305_SPDIF_OUT_SET_1:
332 case RT1305_SPDIF_OUT_SET_2:
333 case RT1305_SPDIF_OUT_SET_3:
334 case RT1305_I2S_SET_1:
335 case RT1305_I2S_SET_2:
336 case RT1305_PBTL_MONO_MODE_SRC:
337 case RT1305_MANUALLY_I2C_DEVICE:
338 case RT1305_POWER_STATUS:
339 case RT1305_POWER_CTRL_1:
340 case RT1305_POWER_CTRL_2:
341 case RT1305_POWER_CTRL_3:
342 case RT1305_POWER_CTRL_4:
343 case RT1305_POWER_CTRL_5:
344 case RT1305_CLOCK_DETECT:
345 case RT1305_BIQUAD_SET_1:
346 case RT1305_BIQUAD_SET_2:
347 case RT1305_ADJUSTED_HPF_1:
348 case RT1305_ADJUSTED_HPF_2:
349 case RT1305_EQ_SET_1:
350 case RT1305_EQ_SET_2:
351 case RT1305_SPK_TEMP_PROTECTION_0:
352 case RT1305_SPK_TEMP_PROTECTION_1:
353 case RT1305_SPK_TEMP_PROTECTION_2:
354 case RT1305_SPK_TEMP_PROTECTION_3:
355 case RT1305_SPK_DC_DETECT_1:
356 case RT1305_SPK_DC_DETECT_2:
357 case RT1305_LOUDNESS:
358 case RT1305_THERMAL_FOLD_BACK_1:
359 case RT1305_THERMAL_FOLD_BACK_2:
360 case RT1305_SILENCE_DETECT ... RT1305_SPK_EXCURSION_LIMITER_7:
361 case RT1305_VERSION_ID:
362 case RT1305_VENDOR_ID:
363 case RT1305_DEVICE_ID:
364 case RT1305_EFUSE_1:
365 case RT1305_EFUSE_2:
366 case RT1305_EFUSE_3:
367 case RT1305_DC_CALIB_1:
368 case RT1305_DC_CALIB_2:
369 case RT1305_DC_CALIB_3:
370 case RT1305_DAC_OFFSET_1 ... RT1305_DAC_OFFSET_14:
371 case RT1305_TRIM_1:
372 case RT1305_TRIM_2:
373 case RT1305_TUNE_INTERNAL_OSC:
374 case RT1305_BIQUAD1_H0_L_28_16 ... RT1305_BIQUAD3_A2_R_15_0:
375 return true;
376 default:
377 return false;
378 }
379 }
380
381 static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -9435, 37, 0);
382
383 static const char * const rt1305_rx_data_ch_select[] = {
384 "LR",
385 "RL",
386 "Copy L",
387 "Copy R",
388 };
389
390 static SOC_ENUM_SINGLE_DECL(rt1305_rx_data_ch_enum, RT1305_I2S_SET_2, 2,
391 rt1305_rx_data_ch_select);
392
393 static void rt1305_reset(struct regmap *regmap)
394 {
395 regmap_write(regmap, RT1305_RESET, 0);
396 }
397
398 static const struct snd_kcontrol_new rt1305_snd_controls[] = {
399 SOC_DOUBLE_TLV("DAC Playback Volume", RT1305_DAC_SET_1,
400 8, 0, 0xff, 0, dac_vol_tlv),
401
402 /* I2S Data Channel Selection */
403 SOC_ENUM("RX Channel Select", rt1305_rx_data_ch_enum),
404 };
405
406 static int rt1305_is_rc_clk_from_pll(struct snd_soc_dapm_widget *source,
407 struct snd_soc_dapm_widget *sink)
408 {
409 struct snd_soc_component *component =
410 snd_soc_dapm_to_component(source->dapm);
411 struct rt1305_priv *rt1305 = snd_soc_component_get_drvdata(component);
412 unsigned int val;
413
414 snd_soc_component_read(component, RT1305_CLK_1, &val);
415
416 if (rt1305->sysclk_src == RT1305_FS_SYS_PRE_S_PLL1 &&
417 (val & RT1305_SEL_PLL_SRC_2_RCCLK))
418 return 1;
419 else
420 return 0;
421 }
422
423 static int rt1305_is_sys_clk_from_pll(struct snd_soc_dapm_widget *source,
424 struct snd_soc_dapm_widget *sink)
425 {
426 struct snd_soc_component *component =
427 snd_soc_dapm_to_component(source->dapm);
428 struct rt1305_priv *rt1305 = snd_soc_component_get_drvdata(component);
429
430 if (rt1305->sysclk_src == RT1305_FS_SYS_PRE_S_PLL1)
431 return 1;
432 else
433 return 0;
434 }
435
436 static int rt1305_classd_event(struct snd_soc_dapm_widget *w,
437 struct snd_kcontrol *kcontrol, int event)
438 {
439 struct snd_soc_component *component =
440 snd_soc_dapm_to_component(w->dapm);
441
442 switch (event) {
443 case SND_SOC_DAPM_POST_PMU:
444 snd_soc_component_update_bits(component, RT1305_POWER_CTRL_1,
445 RT1305_POW_PDB_JD_MASK, RT1305_POW_PDB_JD);
446 break;
447 case SND_SOC_DAPM_PRE_PMD:
448 snd_soc_component_update_bits(component, RT1305_POWER_CTRL_1,
449 RT1305_POW_PDB_JD_MASK, 0);
450 usleep_range(150000, 200000);
451 break;
452
453 default:
454 return 0;
455 }
456
457 return 0;
458 }
459
460 static const struct snd_kcontrol_new rt1305_sto_dac_l =
461 SOC_DAPM_SINGLE("Switch", RT1305_DAC_SET_2,
462 RT1305_DVOL_MUTE_L_EN_SFT, 1, 1);
463
464 static const struct snd_kcontrol_new rt1305_sto_dac_r =
465 SOC_DAPM_SINGLE("Switch", RT1305_DAC_SET_2,
466 RT1305_DVOL_MUTE_R_EN_SFT, 1, 1);
467
468 static const struct snd_soc_dapm_widget rt1305_dapm_widgets[] = {
469 SND_SOC_DAPM_SUPPLY("PLL0", RT1305_POWER_CTRL_1,
470 RT1305_POW_PLL0_EN_BIT, 0, NULL, 0),
471 SND_SOC_DAPM_SUPPLY("PLL1", RT1305_POWER_CTRL_1,
472 RT1305_POW_PLL1_EN_BIT, 0, NULL, 0),
473 SND_SOC_DAPM_SUPPLY("MBIAS", RT1305_POWER_CTRL_1,
474 RT1305_POW_MBIAS_LV_BIT, 0, NULL, 0),
475 SND_SOC_DAPM_SUPPLY("BG MBIAS", RT1305_POWER_CTRL_1,
476 RT1305_POW_BG_MBIAS_LV_BIT, 0, NULL, 0),
477 SND_SOC_DAPM_SUPPLY("LDO2", RT1305_POWER_CTRL_1,
478 RT1305_POW_LDO2_BIT, 0, NULL, 0),
479 SND_SOC_DAPM_SUPPLY("BG2", RT1305_POWER_CTRL_1,
480 RT1305_POW_BG2_BIT, 0, NULL, 0),
481 SND_SOC_DAPM_SUPPLY("LDO2 IB2", RT1305_POWER_CTRL_1,
482 RT1305_POW_LDO2_IB2_BIT, 0, NULL, 0),
483 SND_SOC_DAPM_SUPPLY("VREF", RT1305_POWER_CTRL_1,
484 RT1305_POW_VREF_BIT, 0, NULL, 0),
485 SND_SOC_DAPM_SUPPLY("VREF1", RT1305_POWER_CTRL_1,
486 RT1305_POW_VREF1_BIT, 0, NULL, 0),
487 SND_SOC_DAPM_SUPPLY("VREF2", RT1305_POWER_CTRL_1,
488 RT1305_POW_VREF2_BIT, 0, NULL, 0),
489
490
491 SND_SOC_DAPM_SUPPLY("DISC VREF", RT1305_POWER_CTRL_2,
492 RT1305_POW_DISC_VREF_BIT, 0, NULL, 0),
493 SND_SOC_DAPM_SUPPLY("FASTB VREF", RT1305_POWER_CTRL_2,
494 RT1305_POW_FASTB_VREF_BIT, 0, NULL, 0),
495 SND_SOC_DAPM_SUPPLY("ULTRA FAST VREF", RT1305_POWER_CTRL_2,
496 RT1305_POW_ULTRA_FAST_VREF_BIT, 0, NULL, 0),
497 SND_SOC_DAPM_SUPPLY("CHOP DAC", RT1305_POWER_CTRL_2,
498 RT1305_POW_CKXEN_DAC_BIT, 0, NULL, 0),
499 SND_SOC_DAPM_SUPPLY("CKGEN DAC", RT1305_POWER_CTRL_2,
500 RT1305_POW_EN_CKGEN_DAC_BIT, 0, NULL, 0),
501 SND_SOC_DAPM_SUPPLY("CLAMP", RT1305_POWER_CTRL_2,
502 RT1305_POW_CLAMP_BIT, 0, NULL, 0),
503 SND_SOC_DAPM_SUPPLY("BUFL", RT1305_POWER_CTRL_2,
504 RT1305_POW_BUFL_BIT, 0, NULL, 0),
505 SND_SOC_DAPM_SUPPLY("BUFR", RT1305_POWER_CTRL_2,
506 RT1305_POW_BUFR_BIT, 0, NULL, 0),
507 SND_SOC_DAPM_SUPPLY("CKGEN ADC", RT1305_POWER_CTRL_2,
508 RT1305_POW_EN_CKGEN_ADC_BIT, 0, NULL, 0),
509 SND_SOC_DAPM_SUPPLY("ADC3 L", RT1305_POWER_CTRL_2,
510 RT1305_POW_ADC3_L_BIT, 0, NULL, 0),
511 SND_SOC_DAPM_SUPPLY("ADC3 R", RT1305_POWER_CTRL_2,
512 RT1305_POW_ADC3_R_BIT, 0, NULL, 0),
513 SND_SOC_DAPM_SUPPLY("TRIOSC", RT1305_POWER_CTRL_2,
514 RT1305_POW_TRIOSC_BIT, 0, NULL, 0),
515 SND_SOC_DAPM_SUPPLY("AVDD1", RT1305_POWER_CTRL_2,
516 RT1305_POR_AVDD1_BIT, 0, NULL, 0),
517 SND_SOC_DAPM_SUPPLY("AVDD2", RT1305_POWER_CTRL_2,
518 RT1305_POR_AVDD2_BIT, 0, NULL, 0),
519
520
521 SND_SOC_DAPM_SUPPLY("VSENSE R", RT1305_POWER_CTRL_3,
522 RT1305_POW_VSENSE_RCH_BIT, 0, NULL, 0),
523 SND_SOC_DAPM_SUPPLY("VSENSE L", RT1305_POWER_CTRL_3,
524 RT1305_POW_VSENSE_LCH_BIT, 0, NULL, 0),
525 SND_SOC_DAPM_SUPPLY("ISENSE R", RT1305_POWER_CTRL_3,
526 RT1305_POW_ISENSE_RCH_BIT, 0, NULL, 0),
527 SND_SOC_DAPM_SUPPLY("ISENSE L", RT1305_POWER_CTRL_3,
528 RT1305_POW_ISENSE_LCH_BIT, 0, NULL, 0),
529 SND_SOC_DAPM_SUPPLY("POR AVDD1", RT1305_POWER_CTRL_3,
530 RT1305_POW_POR_AVDD1_BIT, 0, NULL, 0),
531 SND_SOC_DAPM_SUPPLY("POR AVDD2", RT1305_POWER_CTRL_3,
532 RT1305_POW_POR_AVDD2_BIT, 0, NULL, 0),
533 SND_SOC_DAPM_SUPPLY("VCM 6172", RT1305_POWER_CTRL_3,
534 RT1305_EN_VCM_6172_BIT, 0, NULL, 0),
535
536
537 /* Audio Interface */
538 SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
539
540 /* Digital Interface */
541 SND_SOC_DAPM_SUPPLY("DAC L Power", RT1305_POWER_CTRL_2,
542 RT1305_POW_DAC1_L_BIT, 0, NULL, 0),
543 SND_SOC_DAPM_SUPPLY("DAC R Power", RT1305_POWER_CTRL_2,
544 RT1305_POW_DAC1_R_BIT, 0, NULL, 0),
545 SND_SOC_DAPM_DAC("DAC", NULL, SND_SOC_NOPM, 0, 0),
546 SND_SOC_DAPM_SWITCH("DAC L", SND_SOC_NOPM, 0, 0, &rt1305_sto_dac_l),
547 SND_SOC_DAPM_SWITCH("DAC R", SND_SOC_NOPM, 0, 0, &rt1305_sto_dac_r),
548
549 /* Output Lines */
550 SND_SOC_DAPM_PGA_E("CLASS D", SND_SOC_NOPM, 0, 0, NULL, 0,
551 rt1305_classd_event,
552 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
553 SND_SOC_DAPM_OUTPUT("SPOL"),
554 SND_SOC_DAPM_OUTPUT("SPOR"),
555 };
556
557 static const struct snd_soc_dapm_route rt1305_dapm_routes[] = {
558
559 { "DAC", NULL, "AIF1RX" },
560
561 { "DAC", NULL, "PLL0", rt1305_is_rc_clk_from_pll },
562 { "DAC", NULL, "PLL1", rt1305_is_sys_clk_from_pll },
563
564 { "DAC", NULL, "MBIAS" },
565 { "DAC", NULL, "BG MBIAS" },
566 { "DAC", NULL, "LDO2" },
567 { "DAC", NULL, "BG2" },
568 { "DAC", NULL, "LDO2 IB2" },
569 { "DAC", NULL, "VREF" },
570 { "DAC", NULL, "VREF1" },
571 { "DAC", NULL, "VREF2" },
572
573 { "DAC", NULL, "DISC VREF" },
574 { "DAC", NULL, "FASTB VREF" },
575 { "DAC", NULL, "ULTRA FAST VREF" },
576 { "DAC", NULL, "CHOP DAC" },
577 { "DAC", NULL, "CKGEN DAC" },
578 { "DAC", NULL, "CLAMP" },
579 { "DAC", NULL, "CKGEN ADC" },
580 { "DAC", NULL, "TRIOSC" },
581 { "DAC", NULL, "AVDD1" },
582 { "DAC", NULL, "AVDD2" },
583
584 { "DAC", NULL, "POR AVDD1" },
585 { "DAC", NULL, "POR AVDD2" },
586 { "DAC", NULL, "VCM 6172" },
587
588 { "DAC L", "Switch", "DAC" },
589 { "DAC R", "Switch", "DAC" },
590
591 { "DAC R", NULL, "VSENSE R" },
592 { "DAC L", NULL, "VSENSE L" },
593 { "DAC R", NULL, "ISENSE R" },
594 { "DAC L", NULL, "ISENSE L" },
595 { "DAC L", NULL, "ADC3 L" },
596 { "DAC R", NULL, "ADC3 R" },
597 { "DAC L", NULL, "BUFL" },
598 { "DAC R", NULL, "BUFR" },
599 { "DAC L", NULL, "DAC L Power" },
600 { "DAC R", NULL, "DAC R Power" },
601
602 { "CLASS D", NULL, "DAC L" },
603 { "CLASS D", NULL, "DAC R" },
604
605 { "SPOL", NULL, "CLASS D" },
606 { "SPOR", NULL, "CLASS D" },
607 };
608
609 static int rt1305_get_clk_info(int sclk, int rate)
610 {
611 int i;
612 static const int pd[] = {1, 2, 3, 4, 6, 8, 12, 16};
613
614 if (sclk <= 0 || rate <= 0)
615 return -EINVAL;
616
617 rate = rate << 8;
618 for (i = 0; i < ARRAY_SIZE(pd); i++)
619 if (sclk == rate * pd[i])
620 return i;
621
622 return -EINVAL;
623 }
624
625 static int rt1305_hw_params(struct snd_pcm_substream *substream,
626 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
627 {
628 struct snd_soc_component *component = dai->component;
629 struct rt1305_priv *rt1305 = snd_soc_component_get_drvdata(component);
630 unsigned int val_len = 0, val_clk, mask_clk;
631 int pre_div, bclk_ms, frame_size;
632
633 rt1305->lrck = params_rate(params);
634 pre_div = rt1305_get_clk_info(rt1305->sysclk, rt1305->lrck);
635 if (pre_div < 0) {
636 dev_warn(component->dev, "Force using PLL ");
637 snd_soc_dai_set_pll(dai, 0, RT1305_PLL1_S_BCLK,
638 rt1305->lrck * 64, rt1305->lrck * 256);
639 snd_soc_dai_set_sysclk(dai, RT1305_FS_SYS_PRE_S_PLL1,
640 rt1305->lrck * 256, SND_SOC_CLOCK_IN);
641 pre_div = 0;
642 }
643 frame_size = snd_soc_params_to_frame_size(params);
644 if (frame_size < 0) {
645 dev_err(component->dev, "Unsupported frame size: %d\n",
646 frame_size);
647 return -EINVAL;
648 }
649
650 bclk_ms = frame_size > 32;
651 rt1305->bclk = rt1305->lrck * (32 << bclk_ms);
652
653 dev_dbg(component->dev, "bclk_ms is %d and pre_div is %d for iis %d\n",
654 bclk_ms, pre_div, dai->id);
655
656 dev_dbg(component->dev, "lrck is %dHz and pre_div is %d for iis %d\n",
657 rt1305->lrck, pre_div, dai->id);
658
659 switch (params_width(params)) {
660 case 16:
661 val_len |= RT1305_I2S_DL_SEL_16B;
662 break;
663 case 20:
664 val_len |= RT1305_I2S_DL_SEL_20B;
665 break;
666 case 24:
667 val_len |= RT1305_I2S_DL_SEL_24B;
668 break;
669 case 8:
670 val_len |= RT1305_I2S_DL_SEL_8B;
671 break;
672 default:
673 return -EINVAL;
674 }
675
676 switch (dai->id) {
677 case RT1305_AIF1:
678 mask_clk = RT1305_DIV_FS_SYS_MASK;
679 val_clk = pre_div << RT1305_DIV_FS_SYS_SFT;
680 snd_soc_component_update_bits(component, RT1305_I2S_SET_2,
681 RT1305_I2S_DL_SEL_MASK,
682 val_len);
683 break;
684 default:
685 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id);
686 return -EINVAL;
687 }
688
689 snd_soc_component_update_bits(component, RT1305_CLK_2,
690 mask_clk, val_clk);
691
692 return 0;
693 }
694
695 static int rt1305_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
696 {
697 struct snd_soc_component *component = dai->component;
698 struct rt1305_priv *rt1305 = snd_soc_component_get_drvdata(component);
699 unsigned int reg_val = 0, reg1_val = 0;
700
701 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
702 case SND_SOC_DAIFMT_CBM_CFM:
703 reg_val |= RT1305_SEL_I2S_OUT_MODE_M;
704 rt1305->master = 1;
705 break;
706 case SND_SOC_DAIFMT_CBS_CFS:
707 reg_val |= RT1305_SEL_I2S_OUT_MODE_S;
708 rt1305->master = 0;
709 break;
710 default:
711 return -EINVAL;
712 }
713
714 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
715 case SND_SOC_DAIFMT_NB_NF:
716 break;
717 case SND_SOC_DAIFMT_IB_NF:
718 reg1_val |= RT1305_I2S_BCLK_INV;
719 break;
720 default:
721 return -EINVAL;
722 }
723
724 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
725 case SND_SOC_DAIFMT_I2S:
726 break;
727 case SND_SOC_DAIFMT_LEFT_J:
728 reg1_val |= RT1305_I2S_DF_SEL_LEFT;
729 break;
730 case SND_SOC_DAIFMT_DSP_A:
731 reg1_val |= RT1305_I2S_DF_SEL_PCM_A;
732 break;
733 case SND_SOC_DAIFMT_DSP_B:
734 reg1_val |= RT1305_I2S_DF_SEL_PCM_B;
735 break;
736 default:
737 return -EINVAL;
738 }
739
740 switch (dai->id) {
741 case RT1305_AIF1:
742 snd_soc_component_update_bits(component, RT1305_I2S_SET_1,
743 RT1305_SEL_I2S_OUT_MODE_MASK, reg_val);
744 snd_soc_component_update_bits(component, RT1305_I2S_SET_2,
745 RT1305_I2S_DF_SEL_MASK | RT1305_I2S_BCLK_MASK,
746 reg1_val);
747 break;
748 default:
749 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id);
750 return -EINVAL;
751 }
752 return 0;
753 }
754
755 static int rt1305_set_component_sysclk(struct snd_soc_component *component,
756 int clk_id, int source, unsigned int freq, int dir)
757 {
758 struct rt1305_priv *rt1305 = snd_soc_component_get_drvdata(component);
759 unsigned int reg_val = 0;
760
761 if (freq == rt1305->sysclk && clk_id == rt1305->sysclk_src)
762 return 0;
763
764 switch (clk_id) {
765 case RT1305_FS_SYS_PRE_S_MCLK:
766 reg_val |= RT1305_SEL_FS_SYS_PRE_MCLK;
767 snd_soc_component_update_bits(component,
768 RT1305_CLOCK_DETECT, RT1305_SEL_CLK_DET_SRC_MASK,
769 RT1305_SEL_CLK_DET_SRC_MCLK);
770 break;
771 case RT1305_FS_SYS_PRE_S_PLL1:
772 reg_val |= RT1305_SEL_FS_SYS_PRE_PLL;
773 break;
774 case RT1305_FS_SYS_PRE_S_RCCLK:
775 reg_val |= RT1305_SEL_FS_SYS_PRE_RCCLK;
776 break;
777 default:
778 dev_err(component->dev, "Invalid clock id (%d)\n", clk_id);
779 return -EINVAL;
780 }
781 snd_soc_component_update_bits(component, RT1305_CLK_1,
782 RT1305_SEL_FS_SYS_PRE_MASK, reg_val);
783 rt1305->sysclk = freq;
784 rt1305->sysclk_src = clk_id;
785
786 dev_dbg(component->dev, "Sysclk is %dHz and clock id is %d\n",
787 freq, clk_id);
788
789 return 0;
790 }
791
792 static int rt1305_set_component_pll(struct snd_soc_component *component,
793 int pll_id, int source, unsigned int freq_in,
794 unsigned int freq_out)
795 {
796 struct rt1305_priv *rt1305 = snd_soc_component_get_drvdata(component);
797 struct rl6231_pll_code pll_code;
798 int ret;
799
800 if (source == rt1305->pll_src && freq_in == rt1305->pll_in &&
801 freq_out == rt1305->pll_out)
802 return 0;
803
804 if (!freq_in || !freq_out) {
805 dev_dbg(component->dev, "PLL disabled\n");
806
807 rt1305->pll_in = 0;
808 rt1305->pll_out = 0;
809 snd_soc_component_update_bits(component, RT1305_CLK_1,
810 RT1305_SEL_FS_SYS_PRE_MASK | RT1305_SEL_PLL_SRC_1_MASK,
811 RT1305_SEL_FS_SYS_PRE_PLL | RT1305_SEL_PLL_SRC_1_BCLK);
812 return 0;
813 }
814
815 switch (source) {
816 case RT1305_PLL2_S_MCLK:
817 snd_soc_component_update_bits(component, RT1305_CLK_1,
818 RT1305_SEL_PLL_SRC_2_MASK | RT1305_SEL_PLL_SRC_1_MASK |
819 RT1305_DIV_PLL_SRC_2_MASK,
820 RT1305_SEL_PLL_SRC_2_MCLK | RT1305_SEL_PLL_SRC_1_PLL2);
821 snd_soc_component_update_bits(component,
822 RT1305_CLOCK_DETECT, RT1305_SEL_CLK_DET_SRC_MASK,
823 RT1305_SEL_CLK_DET_SRC_MCLK);
824 break;
825 case RT1305_PLL1_S_BCLK:
826 snd_soc_component_update_bits(component,
827 RT1305_CLK_1, RT1305_SEL_PLL_SRC_1_MASK,
828 RT1305_SEL_PLL_SRC_1_BCLK);
829 break;
830 case RT1305_PLL2_S_RCCLK:
831 snd_soc_component_update_bits(component, RT1305_CLK_1,
832 RT1305_SEL_PLL_SRC_2_MASK | RT1305_SEL_PLL_SRC_1_MASK |
833 RT1305_DIV_PLL_SRC_2_MASK,
834 RT1305_SEL_PLL_SRC_2_RCCLK | RT1305_SEL_PLL_SRC_1_PLL2);
835 freq_in = 98304000;
836 break;
837 default:
838 dev_err(component->dev, "Unknown PLL Source %d\n", source);
839 return -EINVAL;
840 }
841
842 ret = rl6231_pll_calc(freq_in, freq_out, &pll_code);
843 if (ret < 0) {
844 dev_err(component->dev, "Unsupport input clock %d\n", freq_in);
845 return ret;
846 }
847
848 dev_dbg(component->dev, "bypass=%d m=%d n=%d k=%d\n",
849 pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
850 pll_code.n_code, pll_code.k_code);
851
852 snd_soc_component_write(component, RT1305_PLL1_1,
853 (pll_code.m_bp ? 0 : pll_code.m_code) << RT1305_PLL_1_M_SFT |
854 pll_code.m_bp << RT1305_PLL_1_M_BYPASS_SFT |
855 pll_code.n_code);
856 snd_soc_component_write(component, RT1305_PLL1_2,
857 pll_code.k_code);
858
859 rt1305->pll_in = freq_in;
860 rt1305->pll_out = freq_out;
861 rt1305->pll_src = source;
862
863 return 0;
864 }
865
866 static int rt1305_probe(struct snd_soc_component *component)
867 {
868 struct rt1305_priv *rt1305 = snd_soc_component_get_drvdata(component);
869
870 rt1305->component = component;
871
872 /* initial settings */
873 rt1305_reg_init(component);
874
875 return 0;
876 }
877
878 static void rt1305_remove(struct snd_soc_component *component)
879 {
880 struct rt1305_priv *rt1305 = snd_soc_component_get_drvdata(component);
881
882 rt1305_reset(rt1305->regmap);
883 }
884
885 #ifdef CONFIG_PM
886 static int rt1305_suspend(struct snd_soc_component *component)
887 {
888 struct rt1305_priv *rt1305 = snd_soc_component_get_drvdata(component);
889
890 regcache_cache_only(rt1305->regmap, true);
891 regcache_mark_dirty(rt1305->regmap);
892
893 return 0;
894 }
895
896 static int rt1305_resume(struct snd_soc_component *component)
897 {
898 struct rt1305_priv *rt1305 = snd_soc_component_get_drvdata(component);
899
900 regcache_cache_only(rt1305->regmap, false);
901 regcache_sync(rt1305->regmap);
902
903 return 0;
904 }
905 #else
906 #define rt1305_suspend NULL
907 #define rt1305_resume NULL
908 #endif
909
910 #define RT1305_STEREO_RATES SNDRV_PCM_RATE_8000_192000
911 #define RT1305_FORMATS (SNDRV_PCM_FMTBIT_S8 | \
912 SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S16_LE | \
913 SNDRV_PCM_FMTBIT_S24_LE)
914
915 static const struct snd_soc_dai_ops rt1305_aif_dai_ops = {
916 .hw_params = rt1305_hw_params,
917 .set_fmt = rt1305_set_dai_fmt,
918 };
919
920 static struct snd_soc_dai_driver rt1305_dai[] = {
921 {
922 .name = "rt1305-aif",
923 .playback = {
924 .stream_name = "AIF1 Playback",
925 .channels_min = 1,
926 .channels_max = 2,
927 .rates = RT1305_STEREO_RATES,
928 .formats = RT1305_FORMATS,
929 },
930 .ops = &rt1305_aif_dai_ops,
931 },
932 };
933
934 static const struct snd_soc_component_driver soc_component_dev_rt1305 = {
935 .probe = rt1305_probe,
936 .remove = rt1305_remove,
937 .suspend = rt1305_suspend,
938 .resume = rt1305_resume,
939 .controls = rt1305_snd_controls,
940 .num_controls = ARRAY_SIZE(rt1305_snd_controls),
941 .dapm_widgets = rt1305_dapm_widgets,
942 .num_dapm_widgets = ARRAY_SIZE(rt1305_dapm_widgets),
943 .dapm_routes = rt1305_dapm_routes,
944 .num_dapm_routes = ARRAY_SIZE(rt1305_dapm_routes),
945 .set_sysclk = rt1305_set_component_sysclk,
946 .set_pll = rt1305_set_component_pll,
947 .use_pmdown_time = 1,
948 .endianness = 1,
949 .non_legacy_dai_naming = 1,
950 };
951
952 static const struct regmap_config rt1305_regmap = {
953 .reg_bits = 8,
954 .val_bits = 16,
955 .max_register = RT1305_MAX_REG + 1 + (ARRAY_SIZE(rt1305_ranges) *
956 RT1305_PR_SPACING),
957 .volatile_reg = rt1305_volatile_register,
958 .readable_reg = rt1305_readable_register,
959 .cache_type = REGCACHE_RBTREE,
960 .reg_defaults = rt1305_reg,
961 .num_reg_defaults = ARRAY_SIZE(rt1305_reg),
962 .ranges = rt1305_ranges,
963 .num_ranges = ARRAY_SIZE(rt1305_ranges),
964 .use_single_read = true,
965 .use_single_write = true,
966 };
967
968 #if defined(CONFIG_OF)
969 static const struct of_device_id rt1305_of_match[] = {
970 { .compatible = "realtek,rt1305", },
971 { .compatible = "realtek,rt1306", },
972 {},
973 };
974 MODULE_DEVICE_TABLE(of, rt1305_of_match);
975 #endif
976
977 #ifdef CONFIG_ACPI
978 static struct acpi_device_id rt1305_acpi_match[] = {
979 {"10EC1305", 0,},
980 {"10EC1306", 0,},
981 {},
982 };
983 MODULE_DEVICE_TABLE(acpi, rt1305_acpi_match);
984 #endif
985
986 static const struct i2c_device_id rt1305_i2c_id[] = {
987 { "rt1305", 0 },
988 { "rt1306", 0 },
989 { }
990 };
991 MODULE_DEVICE_TABLE(i2c, rt1305_i2c_id);
992
993 static void rt1305_calibrate(struct rt1305_priv *rt1305)
994 {
995 unsigned int valmsb, vallsb, offsetl, offsetr;
996 unsigned int rh, rl, rhl, r0ohm;
997 u64 r0l, r0r;
998
999 regcache_cache_bypass(rt1305->regmap, true);
1000
1001 rt1305_reset(rt1305->regmap);
1002 regmap_write(rt1305->regmap, RT1305_ADC_SET_3, 0x0219);
1003 regmap_write(rt1305->regmap, RT1305_PR_BASE + 0xcf, 0x5548);
1004 regmap_write(rt1305->regmap, RT1305_PR_BASE + 0xc1, 0x0320);
1005 regmap_write(rt1305->regmap, RT1305_CLOCK_DETECT, 0x1000);
1006 regmap_write(rt1305->regmap, RT1305_CLK_1, 0x0600);
1007 regmap_write(rt1305->regmap, RT1305_POWER_CTRL_3, 0xffd0);
1008 regmap_write(rt1305->regmap, RT1305_EFUSE_1, 0x0080);
1009 regmap_write(rt1305->regmap, RT1305_EFUSE_1, 0x0880);
1010 regmap_write(rt1305->regmap, RT1305_POWER_CTRL_1, 0x0dfe);
1011
1012 /* Sin Gen */
1013 regmap_write(rt1305->regmap, RT1305_PR_BASE + 0x5d, 0x0442);
1014
1015 regmap_write(rt1305->regmap, RT1305_CAL_EFUSE_CLOCK, 0xb000);
1016 regmap_write(rt1305->regmap, RT1305_PR_BASE + 0xc3, 0xd4a0);
1017 regmap_write(rt1305->regmap, RT1305_PR_BASE + 0xcc, 0x00cc);
1018 regmap_write(rt1305->regmap, RT1305_PR_BASE + 0xc1, 0x0320);
1019 regmap_write(rt1305->regmap, RT1305_POWER_STATUS, 0x0000);
1020 regmap_write(rt1305->regmap, RT1305_POWER_CTRL_2, 0xffff);
1021 regmap_write(rt1305->regmap, RT1305_POWER_CTRL_3, 0xfc20);
1022 regmap_write(rt1305->regmap, RT1305_PR_BASE + 0x06, 0x00c0);
1023 regmap_write(rt1305->regmap, RT1305_POWER_CTRL_3, 0xfca0);
1024 regmap_write(rt1305->regmap, RT1305_POWER_CTRL_3, 0xfce0);
1025 regmap_write(rt1305->regmap, RT1305_POWER_CTRL_3, 0xfcf0);
1026
1027 /* EFUSE read */
1028 regmap_write(rt1305->regmap, RT1305_EFUSE_1, 0x0080);
1029 regmap_write(rt1305->regmap, RT1305_EFUSE_1, 0x0880);
1030 regmap_write(rt1305->regmap, RT1305_EFUSE_1, 0x0880);
1031 regmap_write(rt1305->regmap, RT1305_POWER_CTRL_3, 0xfce0);
1032 regmap_write(rt1305->regmap, RT1305_POWER_CTRL_3, 0xfca0);
1033 regmap_write(rt1305->regmap, RT1305_POWER_CTRL_3, 0xfc20);
1034 regmap_write(rt1305->regmap, RT1305_PR_BASE + 0x06, 0x0000);
1035 regmap_write(rt1305->regmap, RT1305_EFUSE_1, 0x0000);
1036
1037 regmap_read(rt1305->regmap, RT1305_DAC_OFFSET_5, &valmsb);
1038 regmap_read(rt1305->regmap, RT1305_DAC_OFFSET_6, &vallsb);
1039 offsetl = valmsb << 16 | vallsb;
1040 regmap_read(rt1305->regmap, RT1305_DAC_OFFSET_7, &valmsb);
1041 regmap_read(rt1305->regmap, RT1305_DAC_OFFSET_8, &vallsb);
1042 offsetr = valmsb << 16 | vallsb;
1043 pr_info("DC offsetl=0x%x, offsetr=0x%x\n", offsetl, offsetr);
1044
1045 /* R0 calibration */
1046 regmap_write(rt1305->regmap, RT1305_PR_BASE + 0x5d, 0x9542);
1047 regmap_write(rt1305->regmap, RT1305_POWER_CTRL_3, 0xfcf0);
1048 regmap_write(rt1305->regmap, RT1305_POWER_CTRL_2, 0xffff);
1049 regmap_write(rt1305->regmap, RT1305_POWER_CTRL_1, 0x1dfe);
1050 regmap_write(rt1305->regmap, RT1305_SILENCE_DETECT, 0x0e13);
1051 regmap_write(rt1305->regmap, RT1305_CLK_1, 0x0650);
1052
1053 regmap_write(rt1305->regmap, RT1305_PR_BASE + 0x50, 0x0064);
1054 regmap_write(rt1305->regmap, RT1305_PR_BASE + 0x51, 0x0770);
1055 regmap_write(rt1305->regmap, RT1305_PR_BASE + 0x52, 0xc30c);
1056 regmap_write(rt1305->regmap, RT1305_SPK_TEMP_PROTECTION_1, 0x8200);
1057 regmap_write(rt1305->regmap, RT1305_PR_BASE + 0xd4, 0xfb00);
1058 regmap_write(rt1305->regmap, RT1305_PR_BASE + 0xd4, 0xff80);
1059 msleep(2000);
1060 regmap_read(rt1305->regmap, RT1305_PR_BASE + 0x55, &rh);
1061 regmap_read(rt1305->regmap, RT1305_PR_BASE + 0x56, &rl);
1062 rhl = (rh << 16) | rl;
1063 r0ohm = (rhl*10) / 33554432;
1064
1065 pr_debug("Left_rhl = 0x%x rh=0x%x rl=0x%x\n", rhl, rh, rl);
1066 pr_info("Left channel %d.%dohm\n", (r0ohm/10), (r0ohm%10));
1067
1068 r0l = 562949953421312ULL;
1069 if (rhl != 0)
1070 do_div(r0l, rhl);
1071 pr_debug("Left_r0 = 0x%llx\n", r0l);
1072
1073 regmap_write(rt1305->regmap, RT1305_SPK_TEMP_PROTECTION_1, 0x9200);
1074 regmap_write(rt1305->regmap, RT1305_PR_BASE + 0xd4, 0xfb00);
1075 regmap_write(rt1305->regmap, RT1305_PR_BASE + 0xd4, 0xff80);
1076 msleep(2000);
1077 regmap_read(rt1305->regmap, RT1305_PR_BASE + 0x55, &rh);
1078 regmap_read(rt1305->regmap, RT1305_PR_BASE + 0x56, &rl);
1079 rhl = (rh << 16) | rl;
1080 r0ohm = (rhl*10) / 33554432;
1081
1082 pr_debug("Right_rhl = 0x%x rh=0x%x rl=0x%x\n", rhl, rh, rl);
1083 pr_info("Right channel %d.%dohm\n", (r0ohm/10), (r0ohm%10));
1084
1085 r0r = 562949953421312ULL;
1086 if (rhl != 0)
1087 do_div(r0r, rhl);
1088 pr_debug("Right_r0 = 0x%llx\n", r0r);
1089
1090 regmap_write(rt1305->regmap, RT1305_SPK_TEMP_PROTECTION_1, 0xc2ec);
1091
1092 if ((r0l > R0_UPPER) && (r0l < R0_LOWER) &&
1093 (r0r > R0_UPPER) && (r0r < R0_LOWER)) {
1094 regmap_write(rt1305->regmap, RT1305_PR_BASE + 0x4e,
1095 (r0l >> 16) & 0xffff);
1096 regmap_write(rt1305->regmap, RT1305_PR_BASE + 0x4f,
1097 r0l & 0xffff);
1098 regmap_write(rt1305->regmap, RT1305_PR_BASE + 0xfe,
1099 ((r0r >> 16) & 0xffff) | 0xf800);
1100 regmap_write(rt1305->regmap, RT1305_PR_BASE + 0xfd,
1101 r0r & 0xffff);
1102 } else {
1103 pr_err("R0 calibration failed\n");
1104 }
1105
1106 /* restore some registers */
1107 regmap_write(rt1305->regmap, RT1305_POWER_CTRL_1, 0x0dfe);
1108 usleep_range(200000, 400000);
1109 regmap_write(rt1305->regmap, RT1305_PR_BASE + 0x5d, 0x0442);
1110 regmap_write(rt1305->regmap, RT1305_CLOCK_DETECT, 0x3000);
1111 regmap_write(rt1305->regmap, RT1305_CLK_1, 0x0400);
1112 regmap_write(rt1305->regmap, RT1305_POWER_CTRL_1, 0x0000);
1113 regmap_write(rt1305->regmap, RT1305_CAL_EFUSE_CLOCK, 0x8000);
1114 regmap_write(rt1305->regmap, RT1305_POWER_CTRL_2, 0x1020);
1115 regmap_write(rt1305->regmap, RT1305_POWER_CTRL_3, 0x0000);
1116
1117 regcache_cache_bypass(rt1305->regmap, false);
1118 }
1119
1120 static int rt1305_i2c_probe(struct i2c_client *i2c,
1121 const struct i2c_device_id *id)
1122 {
1123 struct rt1305_priv *rt1305;
1124 int ret;
1125 unsigned int val;
1126
1127 rt1305 = devm_kzalloc(&i2c->dev, sizeof(struct rt1305_priv),
1128 GFP_KERNEL);
1129 if (rt1305 == NULL)
1130 return -ENOMEM;
1131
1132 i2c_set_clientdata(i2c, rt1305);
1133
1134 rt1305->regmap = devm_regmap_init_i2c(i2c, &rt1305_regmap);
1135 if (IS_ERR(rt1305->regmap)) {
1136 ret = PTR_ERR(rt1305->regmap);
1137 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
1138 ret);
1139 return ret;
1140 }
1141
1142 regmap_read(rt1305->regmap, RT1305_DEVICE_ID, &val);
1143 if (val != RT1305_DEVICE_ID_NUM) {
1144 dev_err(&i2c->dev,
1145 "Device with ID register %x is not rt1305\n", val);
1146 return -ENODEV;
1147 }
1148
1149 rt1305_reset(rt1305->regmap);
1150 rt1305_calibrate(rt1305);
1151
1152 return devm_snd_soc_register_component(&i2c->dev,
1153 &soc_component_dev_rt1305,
1154 rt1305_dai, ARRAY_SIZE(rt1305_dai));
1155 }
1156
1157 static void rt1305_i2c_shutdown(struct i2c_client *client)
1158 {
1159 struct rt1305_priv *rt1305 = i2c_get_clientdata(client);
1160
1161 rt1305_reset(rt1305->regmap);
1162 }
1163
1164
1165 static struct i2c_driver rt1305_i2c_driver = {
1166 .driver = {
1167 .name = "rt1305",
1168 #if defined(CONFIG_OF)
1169 .of_match_table = rt1305_of_match,
1170 #endif
1171 #if defined(CONFIG_ACPI)
1172 .acpi_match_table = ACPI_PTR(rt1305_acpi_match)
1173 #endif
1174 },
1175 .probe = rt1305_i2c_probe,
1176 .shutdown = rt1305_i2c_shutdown,
1177 .id_table = rt1305_i2c_id,
1178 };
1179 module_i2c_driver(rt1305_i2c_driver);
1180
1181 MODULE_DESCRIPTION("ASoC RT1305 amplifier driver");
1182 MODULE_AUTHOR("Shuming Fan <shumingf@realtek.com>");
1183 MODULE_LICENSE("GPL v2");
Linux with added FPC-III support