ARM: dts: omap5: Add bus_dma_limit for L3 bus
[linux/fpc-iii.git] / sound / soc / codecs / sirf-audio-codec.h
bloba7fe2680f4c7eb2db8d7351368c3ec953571f951
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*
3 * SiRF inner codec controllers define
5 * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
6 */
8 #ifndef _SIRF_AUDIO_CODEC_H
9 #define _SIRF_AUDIO_CODEC_H
12 #define AUDIO_IC_CODEC_PWR (0x00E0)
13 #define AUDIO_IC_CODEC_CTRL0 (0x00E4)
14 #define AUDIO_IC_CODEC_CTRL1 (0x00E8)
15 #define AUDIO_IC_CODEC_CTRL2 (0x00EC)
16 #define AUDIO_IC_CODEC_CTRL3 (0x00F0)
18 #define MICBIASEN (1 << 3)
20 #define IC_RDACEN (1 << 0)
21 #define IC_LDACEN (1 << 1)
22 #define IC_HSREN (1 << 2)
23 #define IC_HSLEN (1 << 3)
24 #define IC_SPEN (1 << 4)
25 #define IC_CPEN (1 << 5)
27 #define IC_HPRSELR (1 << 6)
28 #define IC_HPLSELR (1 << 7)
29 #define IC_HPRSELL (1 << 8)
30 #define IC_HPLSELL (1 << 9)
31 #define IC_SPSELR (1 << 10)
32 #define IC_SPSELL (1 << 11)
34 #define IC_MONOR (1 << 12)
35 #define IC_MONOL (1 << 13)
37 #define IC_RXOSRSEL (1 << 28)
38 #define IC_CPFREQ (1 << 29)
39 #define IC_HSINVEN (1 << 30)
41 #define IC_MICINREN (1 << 0)
42 #define IC_MICINLEN (1 << 1)
43 #define IC_MICIN1SEL (1 << 2)
44 #define IC_MICIN2SEL (1 << 3)
45 #define IC_MICDIFSEL (1 << 4)
46 #define IC_LINEIN1SEL (1 << 5)
47 #define IC_LINEIN2SEL (1 << 6)
48 #define IC_RADCEN (1 << 7)
49 #define IC_LADCEN (1 << 8)
50 #define IC_ALM (1 << 9)
52 #define IC_DIGMICEN (1 << 22)
53 #define IC_DIGMICFREQ (1 << 23)
54 #define IC_ADC14B_12 (1 << 24)
55 #define IC_FIRDAC_HSL_EN (1 << 25)
56 #define IC_FIRDAC_HSR_EN (1 << 26)
57 #define IC_FIRDAC_LOUT_EN (1 << 27)
58 #define IC_POR (1 << 28)
59 #define IC_CODEC_CLK_EN (1 << 29)
60 #define IC_HP_3DB_BOOST (1 << 30)
62 #define IC_ADC_LEFT_GAIN_SHIFT 16
63 #define IC_ADC_RIGHT_GAIN_SHIFT 10
64 #define IC_ADC_GAIN_MASK 0x3F
65 #define IC_MIC_MAX_GAIN 0x39
67 #define IC_RXPGAR_MASK 0x3F
68 #define IC_RXPGAR_SHIFT 14
69 #define IC_RXPGAL_MASK 0x3F
70 #define IC_RXPGAL_SHIFT 21
71 #define IC_RXPGAR 0x7B
72 #define IC_RXPGAL 0x7B
74 #define AUDIO_PORT_TX_FIFO_LEVEL_CHECK_MASK 0x3F
75 #define AUDIO_PORT_TX_FIFO_SC_OFFSET 0
76 #define AUDIO_PORT_TX_FIFO_LC_OFFSET 10
77 #define AUDIO_PORT_TX_FIFO_HC_OFFSET 20
79 #define TX_FIFO_SC(x) (((x) & AUDIO_PORT_TX_FIFO_LEVEL_CHECK_MASK) \
80 << AUDIO_PORT_TX_FIFO_SC_OFFSET)
81 #define TX_FIFO_LC(x) (((x) & AUDIO_PORT_TX_FIFO_LEVEL_CHECK_MASK) \
82 << AUDIO_PORT_TX_FIFO_LC_OFFSET)
83 #define TX_FIFO_HC(x) (((x) & AUDIO_PORT_TX_FIFO_LEVEL_CHECK_MASK) \
84 << AUDIO_PORT_TX_FIFO_HC_OFFSET)
86 #define AUDIO_PORT_RX_FIFO_LEVEL_CHECK_MASK 0x0F
87 #define AUDIO_PORT_RX_FIFO_SC_OFFSET 0
88 #define AUDIO_PORT_RX_FIFO_LC_OFFSET 10
89 #define AUDIO_PORT_RX_FIFO_HC_OFFSET 20
91 #define RX_FIFO_SC(x) (((x) & AUDIO_PORT_RX_FIFO_LEVEL_CHECK_MASK) \
92 << AUDIO_PORT_RX_FIFO_SC_OFFSET)
93 #define RX_FIFO_LC(x) (((x) & AUDIO_PORT_RX_FIFO_LEVEL_CHECK_MASK) \
94 << AUDIO_PORT_RX_FIFO_LC_OFFSET)
95 #define RX_FIFO_HC(x) (((x) & AUDIO_PORT_RX_FIFO_LEVEL_CHECK_MASK) \
96 << AUDIO_PORT_RX_FIFO_HC_OFFSET)
97 #define AUDIO_PORT_IC_CODEC_TX_CTRL (0x00F4)
98 #define AUDIO_PORT_IC_CODEC_RX_CTRL (0x00F8)
100 #define AUDIO_PORT_IC_TXFIFO_OP (0x00FC)
101 #define AUDIO_PORT_IC_TXFIFO_LEV_CHK (0x0100)
102 #define AUDIO_PORT_IC_TXFIFO_STS (0x0104)
103 #define AUDIO_PORT_IC_TXFIFO_INT (0x0108)
104 #define AUDIO_PORT_IC_TXFIFO_INT_MSK (0x010C)
106 #define AUDIO_PORT_IC_RXFIFO_OP (0x0110)
107 #define AUDIO_PORT_IC_RXFIFO_LEV_CHK (0x0114)
108 #define AUDIO_PORT_IC_RXFIFO_STS (0x0118)
109 #define AUDIO_PORT_IC_RXFIFO_INT (0x011C)
110 #define AUDIO_PORT_IC_RXFIFO_INT_MSK (0x0120)
112 #define AUDIO_FIFO_START (1 << 0)
113 #define AUDIO_FIFO_RESET (1 << 1)
115 #define AUDIO_FIFO_FULL (1 << 0)
116 #define AUDIO_FIFO_EMPTY (1 << 1)
117 #define AUDIO_FIFO_OFLOW (1 << 2)
118 #define AUDIO_FIFO_UFLOW (1 << 3)
120 #define IC_TX_ENABLE (0x03)
121 #define IC_RX_ENABLE_MONO (0x01)
122 #define IC_RX_ENABLE_STEREO (0x03)
124 #endif /*__SIRF_AUDIO_CODEC_H*/