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ARM: dts: omap5: Add bus_dma_limit for L3 bus
[linux/fpc-iii.git] / sound / soc / codecs / tscs454.c
blobc3587af9985c0b7a03768a1b25b448be1c73dd86
1 // SPDX-License-Identifier: GPL-2.0
2 // tscs454.c -- TSCS454 ALSA SoC Audio driver
3 // Copyright 2018 Tempo Semiconductor, Inc.
4 // Author: Steven Eckhoff <steven.eckhoff.opensource@gmail.com>
5
6 #include <linux/kernel.h>
7 #include <linux/clk.h>
8 #include <linux/device.h>
9 #include <linux/regmap.h>
10 #include <linux/i2c.h>
11 #include <linux/err.h>
12 #include <linux/string.h>
13 #include <linux/module.h>
14 #include <linux/delay.h>
15 #include <linux/mutex.h>
16
17 #include <sound/tlv.h>
18 #include <sound/pcm_params.h>
19 #include <sound/pcm.h>
20 #include <sound/soc.h>
21 #include <sound/soc-dapm.h>
22
23 #include "tscs454.h"
24
25 static const unsigned int PLL_44_1K_RATE = (44100 * 256);
26
27 #define COEFF_SIZE 3
28 #define BIQUAD_COEFF_COUNT 5
29 #define BIQUAD_SIZE (COEFF_SIZE * BIQUAD_COEFF_COUNT)
30
31 #define COEFF_RAM_MAX_ADDR 0xcd
32 #define COEFF_RAM_COEFF_COUNT (COEFF_RAM_MAX_ADDR + 1)
33 #define COEFF_RAM_SIZE (COEFF_SIZE * COEFF_RAM_COEFF_COUNT)
34
35 enum {
36 TSCS454_DAI1_ID,
37 TSCS454_DAI2_ID,
38 TSCS454_DAI3_ID,
39 TSCS454_DAI_COUNT,
40 };
41
42 struct pll {
43 int id;
44 unsigned int users;
45 struct mutex lock;
46 };
47
48 static inline void pll_init(struct pll *pll, int id)
49 {
50 pll->id = id;
51 mutex_init(&pll->lock);
52 }
53
54 struct internal_rate {
55 struct pll *pll;
56 };
57
58 struct aif {
59 unsigned int id;
60 bool master;
61 struct pll *pll;
62 };
63
64 static inline void aif_init(struct aif *aif, unsigned int id)
65 {
66 aif->id = id;
67 }
68
69 struct coeff_ram {
70 u8 cache[COEFF_RAM_SIZE];
71 bool synced;
72 struct mutex lock;
73 };
74
75 static inline void init_coeff_ram_cache(u8 *cache)
76 {
77 static const u8 norm_addrs[] = { 0x00, 0x05, 0x0a, 0x0f, 0x14, 0x19,
78 0x1f, 0x20, 0x25, 0x2a, 0x2f, 0x34, 0x39, 0x3f, 0x40, 0x45,
79 0x4a, 0x4f, 0x54, 0x59, 0x5f, 0x60, 0x65, 0x6a, 0x6f, 0x74,
80 0x79, 0x7f, 0x80, 0x85, 0x8c, 0x91, 0x96, 0x97, 0x9c, 0xa3,
81 0xa8, 0xad, 0xaf, 0xb0, 0xb5, 0xba, 0xbf, 0xc4, 0xc9};
82 int i;
83
84 for (i = 0; i < ARRAY_SIZE(norm_addrs); i++)
85 cache[((norm_addrs[i] + 1) * COEFF_SIZE) - 1] = 0x40;
86 }
87
88 static inline void coeff_ram_init(struct coeff_ram *ram)
89 {
90 init_coeff_ram_cache(ram->cache);
91 mutex_init(&ram->lock);
92 }
93
94 struct aifs_status {
95 u8 streams;
96 };
97
98 static inline void set_aif_status_active(struct aifs_status *status,
99 int aif_id, bool playback)
100 {
101 u8 mask = 0x01 << (aif_id * 2 + !playback);
102
103 status->streams |= mask;
104 }
105
106 static inline void set_aif_status_inactive(struct aifs_status *status,
107 int aif_id, bool playback)
108 {
109 u8 mask = ~(0x01 << (aif_id * 2 + !playback));
110
111 status->streams &= mask;
112 }
113
114 static bool aifs_active(struct aifs_status *status)
115 {
116 return status->streams;
117 }
118
119 static bool aif_active(struct aifs_status *status, int aif_id)
120 {
121 return (0x03 << aif_id * 2) & status->streams;
122 }
123
124 struct tscs454 {
125 struct regmap *regmap;
126 struct aif aifs[TSCS454_DAI_COUNT];
127
128 struct aifs_status aifs_status;
129 struct mutex aifs_status_lock;
130
131 struct pll pll1;
132 struct pll pll2;
133 struct internal_rate internal_rate;
134
135 struct coeff_ram dac_ram;
136 struct coeff_ram spk_ram;
137 struct coeff_ram sub_ram;
138
139 struct clk *sysclk;
140 int sysclk_src_id;
141 unsigned int bclk_freq;
142 };
143
144 struct coeff_ram_ctl {
145 unsigned int addr;
146 struct soc_bytes_ext bytes_ext;
147 };
148
149 static const struct reg_sequence tscs454_patch[] = {
150 /* Assign ASRC out of the box so DAI 1 just works */
151 { R_AUDIOMUX1, FV_ASRCIMUX_I2S1 | FV_I2S2MUX_I2S2 },
152 { R_AUDIOMUX2, FV_ASRCOMUX_I2S1 | FV_DACMUX_I2S1 | FV_I2S3MUX_I2S3 },
153 { R_AUDIOMUX3, FV_CLSSDMUX_I2S1 | FV_SUBMUX_I2S1_LR },
154 { R_TDMCTL0, FV_TDMMD_256 },
155 { VIRT_ADDR(0x0A, 0x13), 1 << 3 },
156 };
157
158 static bool tscs454_volatile(struct device *dev, unsigned int reg)
159 {
160 switch (reg) {
161 case R_PLLSTAT:
162
163 case R_SPKCRRDL:
164 case R_SPKCRRDM:
165 case R_SPKCRRDH:
166 case R_SPKCRS:
167
168 case R_DACCRRDL:
169 case R_DACCRRDM:
170 case R_DACCRRDH:
171 case R_DACCRS:
172
173 case R_SUBCRRDL:
174 case R_SUBCRRDM:
175 case R_SUBCRRDH:
176 case R_SUBCRS:
177 return true;
178 default:
179 return false;
180 };
181 }
182
183 static bool tscs454_writable(struct device *dev, unsigned int reg)
184 {
185 switch (reg) {
186 case R_SPKCRRDL:
187 case R_SPKCRRDM:
188 case R_SPKCRRDH:
189
190 case R_DACCRRDL:
191 case R_DACCRRDM:
192 case R_DACCRRDH:
193
194 case R_SUBCRRDL:
195 case R_SUBCRRDM:
196 case R_SUBCRRDH:
197 return false;
198 default:
199 return true;
200 };
201 }
202
203 static bool tscs454_readable(struct device *dev, unsigned int reg)
204 {
205 switch (reg) {
206 case R_SPKCRWDL:
207 case R_SPKCRWDM:
208 case R_SPKCRWDH:
209
210 case R_DACCRWDL:
211 case R_DACCRWDM:
212 case R_DACCRWDH:
213
214 case R_SUBCRWDL:
215 case R_SUBCRWDM:
216 case R_SUBCRWDH:
217 return false;
218 default:
219 return true;
220 };
221 }
222
223 static bool tscs454_precious(struct device *dev, unsigned int reg)
224 {
225 switch (reg) {
226 case R_SPKCRWDL:
227 case R_SPKCRWDM:
228 case R_SPKCRWDH:
229 case R_SPKCRRDL:
230 case R_SPKCRRDM:
231 case R_SPKCRRDH:
232
233 case R_DACCRWDL:
234 case R_DACCRWDM:
235 case R_DACCRWDH:
236 case R_DACCRRDL:
237 case R_DACCRRDM:
238 case R_DACCRRDH:
239
240 case R_SUBCRWDL:
241 case R_SUBCRWDM:
242 case R_SUBCRWDH:
243 case R_SUBCRRDL:
244 case R_SUBCRRDM:
245 case R_SUBCRRDH:
246 return true;
247 default:
248 return false;
249 };
250 }
251
252 static const struct regmap_range_cfg tscs454_regmap_range_cfg = {
253 .name = "Pages",
254 .range_min = VIRT_BASE,
255 .range_max = VIRT_ADDR(0xFE, 0x02),
256 .selector_reg = R_PAGESEL,
257 .selector_mask = 0xff,
258 .selector_shift = 0,
259 .window_start = 0,
260 .window_len = 0x100,
261 };
262
263 static struct regmap_config const tscs454_regmap_cfg = {
264 .reg_bits = 8,
265 .val_bits = 8,
266 .writeable_reg = tscs454_writable,
267 .readable_reg = tscs454_readable,
268 .volatile_reg = tscs454_volatile,
269 .precious_reg = tscs454_precious,
270 .ranges = &tscs454_regmap_range_cfg,
271 .num_ranges = 1,
272 .max_register = VIRT_ADDR(0xFE, 0x02),
273 .cache_type = REGCACHE_RBTREE,
274 };
275
276 static inline int tscs454_data_init(struct tscs454 *tscs454,
277 struct i2c_client *i2c)
278 {
279 int i;
280 int ret;
281
282 tscs454->regmap = devm_regmap_init_i2c(i2c, &tscs454_regmap_cfg);
283 if (IS_ERR(tscs454->regmap)) {
284 ret = PTR_ERR(tscs454->regmap);
285 return ret;
286 }
287
288 for (i = 0; i < TSCS454_DAI_COUNT; i++)
289 aif_init(&tscs454->aifs[i], i);
290
291 mutex_init(&tscs454->aifs_status_lock);
292 pll_init(&tscs454->pll1, 1);
293 pll_init(&tscs454->pll2, 2);
294
295 coeff_ram_init(&tscs454->dac_ram);
296 coeff_ram_init(&tscs454->spk_ram);
297 coeff_ram_init(&tscs454->sub_ram);
298
299 return 0;
300 }
301
302 struct reg_setting {
303 unsigned int addr;
304 unsigned int val;
305 };
306
307 static int coeff_ram_get(struct snd_kcontrol *kcontrol,
308 struct snd_ctl_elem_value *ucontrol)
309 {
310 struct snd_soc_component *component =
311 snd_soc_kcontrol_component(kcontrol);
312 struct tscs454 *tscs454 = snd_soc_component_get_drvdata(component);
313 struct coeff_ram_ctl *ctl =
314 (struct coeff_ram_ctl *)kcontrol->private_value;
315 struct soc_bytes_ext *params = &ctl->bytes_ext;
316 u8 *coeff_ram;
317 struct mutex *coeff_ram_lock;
318
319 if (strstr(kcontrol->id.name, "DAC")) {
320 coeff_ram = tscs454->dac_ram.cache;
321 coeff_ram_lock = &tscs454->dac_ram.lock;
322 } else if (strstr(kcontrol->id.name, "Speaker")) {
323 coeff_ram = tscs454->spk_ram.cache;
324 coeff_ram_lock = &tscs454->spk_ram.lock;
325 } else if (strstr(kcontrol->id.name, "Sub")) {
326 coeff_ram = tscs454->sub_ram.cache;
327 coeff_ram_lock = &tscs454->sub_ram.lock;
328 } else {
329 return -EINVAL;
330 }
331
332 mutex_lock(coeff_ram_lock);
333
334 memcpy(ucontrol->value.bytes.data,
335 &coeff_ram[ctl->addr * COEFF_SIZE], params->max);
336
337 mutex_unlock(coeff_ram_lock);
338
339 return 0;
340 }
341
342 #define DACCRSTAT_MAX_TRYS 10
343 static int write_coeff_ram(struct snd_soc_component *component, u8 *coeff_ram,
344 unsigned int r_stat, unsigned int r_addr, unsigned int r_wr,
345 unsigned int coeff_addr, unsigned int coeff_cnt)
346 {
347 struct tscs454 *tscs454 = snd_soc_component_get_drvdata(component);
348 unsigned int val;
349 int cnt;
350 int trys;
351 int ret;
352
353 for (cnt = 0; cnt < coeff_cnt; cnt++, coeff_addr++) {
354
355 for (trys = 0; trys < DACCRSTAT_MAX_TRYS; trys++) {
356 ret = snd_soc_component_read(component, r_stat, &val);
357 if (ret < 0) {
358 dev_err(component->dev,
359 "Failed to read stat (%d)\n", ret);
360 return ret;
361 }
362 if (!val)
363 break;
364 }
365
366 if (trys == DACCRSTAT_MAX_TRYS) {
367 ret = -EIO;
368 dev_err(component->dev,
369 "Coefficient write error (%d)\n", ret);
370 return ret;
371 }
372
373 ret = regmap_write(tscs454->regmap, r_addr, coeff_addr);
374 if (ret < 0) {
375 dev_err(component->dev,
376 "Failed to write dac ram address (%d)\n", ret);
377 return ret;
378 }
379
380 ret = regmap_bulk_write(tscs454->regmap, r_wr,
381 &coeff_ram[coeff_addr * COEFF_SIZE],
382 COEFF_SIZE);
383 if (ret < 0) {
384 dev_err(component->dev,
385 "Failed to write dac ram (%d)\n", ret);
386 return ret;
387 }
388 }
389
390 return 0;
391 }
392
393 static int coeff_ram_put(struct snd_kcontrol *kcontrol,
394 struct snd_ctl_elem_value *ucontrol)
395 {
396 struct snd_soc_component *component =
397 snd_soc_kcontrol_component(kcontrol);
398 struct tscs454 *tscs454 = snd_soc_component_get_drvdata(component);
399 struct coeff_ram_ctl *ctl =
400 (struct coeff_ram_ctl *)kcontrol->private_value;
401 struct soc_bytes_ext *params = &ctl->bytes_ext;
402 unsigned int coeff_cnt = params->max / COEFF_SIZE;
403 u8 *coeff_ram;
404 struct mutex *coeff_ram_lock;
405 bool *coeff_ram_synced;
406 unsigned int r_stat;
407 unsigned int r_addr;
408 unsigned int r_wr;
409 unsigned int val;
410 int ret;
411
412 if (strstr(kcontrol->id.name, "DAC")) {
413 coeff_ram = tscs454->dac_ram.cache;
414 coeff_ram_lock = &tscs454->dac_ram.lock;
415 coeff_ram_synced = &tscs454->dac_ram.synced;
416 r_stat = R_DACCRS;
417 r_addr = R_DACCRADD;
418 r_wr = R_DACCRWDL;
419 } else if (strstr(kcontrol->id.name, "Speaker")) {
420 coeff_ram = tscs454->spk_ram.cache;
421 coeff_ram_lock = &tscs454->spk_ram.lock;
422 coeff_ram_synced = &tscs454->spk_ram.synced;
423 r_stat = R_SPKCRS;
424 r_addr = R_SPKCRADD;
425 r_wr = R_SPKCRWDL;
426 } else if (strstr(kcontrol->id.name, "Sub")) {
427 coeff_ram = tscs454->sub_ram.cache;
428 coeff_ram_lock = &tscs454->sub_ram.lock;
429 coeff_ram_synced = &tscs454->sub_ram.synced;
430 r_stat = R_SUBCRS;
431 r_addr = R_SUBCRADD;
432 r_wr = R_SUBCRWDL;
433 } else {
434 return -EINVAL;
435 }
436
437 mutex_lock(coeff_ram_lock);
438
439 *coeff_ram_synced = false;
440
441 memcpy(&coeff_ram[ctl->addr * COEFF_SIZE],
442 ucontrol->value.bytes.data, params->max);
443
444 mutex_lock(&tscs454->pll1.lock);
445 mutex_lock(&tscs454->pll2.lock);
446
447 ret = snd_soc_component_read(component, R_PLLSTAT, &val);
448 if (ret < 0) {
449 dev_err(component->dev, "Failed to read PLL status (%d)\n",
450 ret);
451 goto exit;
452 }
453 if (val) { /* PLLs locked */
454 ret = write_coeff_ram(component, coeff_ram,
455 r_stat, r_addr, r_wr,
456 ctl->addr, coeff_cnt);
457 if (ret < 0) {
458 dev_err(component->dev,
459 "Failed to flush coeff ram cache (%d)\n", ret);
460 goto exit;
461 }
462 *coeff_ram_synced = true;
463 }
464
465 ret = 0;
466 exit:
467 mutex_unlock(&tscs454->pll2.lock);
468 mutex_unlock(&tscs454->pll1.lock);
469 mutex_unlock(coeff_ram_lock);
470
471 return ret;
472 }
473
474 static inline int coeff_ram_sync(struct snd_soc_component *component,
475 struct tscs454 *tscs454)
476 {
477 int ret;
478
479 mutex_lock(&tscs454->dac_ram.lock);
480 if (!tscs454->dac_ram.synced) {
481 ret = write_coeff_ram(component, tscs454->dac_ram.cache,
482 R_DACCRS, R_DACCRADD, R_DACCRWDL,
483 0x00, COEFF_RAM_COEFF_COUNT);
484 if (ret < 0) {
485 mutex_unlock(&tscs454->dac_ram.lock);
486 return ret;
487 }
488 }
489 mutex_unlock(&tscs454->dac_ram.lock);
490
491 mutex_lock(&tscs454->spk_ram.lock);
492 if (!tscs454->spk_ram.synced) {
493 ret = write_coeff_ram(component, tscs454->spk_ram.cache,
494 R_SPKCRS, R_SPKCRADD, R_SPKCRWDL,
495 0x00, COEFF_RAM_COEFF_COUNT);
496 if (ret < 0) {
497 mutex_unlock(&tscs454->spk_ram.lock);
498 return ret;
499 }
500 }
501 mutex_unlock(&tscs454->spk_ram.lock);
502
503 mutex_lock(&tscs454->sub_ram.lock);
504 if (!tscs454->sub_ram.synced) {
505 ret = write_coeff_ram(component, tscs454->sub_ram.cache,
506 R_SUBCRS, R_SUBCRADD, R_SUBCRWDL,
507 0x00, COEFF_RAM_COEFF_COUNT);
508 if (ret < 0) {
509 mutex_unlock(&tscs454->sub_ram.lock);
510 return ret;
511 }
512 }
513 mutex_unlock(&tscs454->sub_ram.lock);
514
515 return 0;
516 }
517
518 #define PLL_REG_SETTINGS_COUNT 11
519 struct pll_ctl {
520 int freq_in;
521 struct reg_setting settings[PLL_REG_SETTINGS_COUNT];
522 };
523
524 #define PLL_CTL(f, t, c1, r1, o1, f1l, f1h, c2, r2, o2, f2l, f2h) \
525 { \
526 .freq_in = f, \
527 .settings = { \
528 {R_PLL1CTL, c1}, \
529 {R_PLL1RDIV, r1}, \
530 {R_PLL1ODIV, o1}, \
531 {R_PLL1FDIVL, f1l}, \
532 {R_PLL1FDIVH, f1h}, \
533 {R_PLL2CTL, c2}, \
534 {R_PLL2RDIV, r2}, \
535 {R_PLL2ODIV, o2}, \
536 {R_PLL2FDIVL, f2l}, \
537 {R_PLL2FDIVH, f2h}, \
538 {R_TIMEBASE, t}, \
539 }, \
540 }
541
542 static const struct pll_ctl pll_ctls[] = {
543 PLL_CTL(1411200, 0x05,
544 0xB9, 0x07, 0x02, 0xC3, 0x04,
545 0x5A, 0x02, 0x03, 0xE0, 0x01),
546 PLL_CTL(1536000, 0x05,
547 0x5A, 0x02, 0x03, 0xE0, 0x01,
548 0x5A, 0x02, 0x03, 0xB9, 0x01),
549 PLL_CTL(2822400, 0x0A,
550 0x63, 0x07, 0x04, 0xC3, 0x04,
551 0x62, 0x07, 0x03, 0x48, 0x03),
552 PLL_CTL(3072000, 0x0B,
553 0x62, 0x07, 0x03, 0x48, 0x03,
554 0x5A, 0x04, 0x03, 0xB9, 0x01),
555 PLL_CTL(5644800, 0x15,
556 0x63, 0x0E, 0x04, 0xC3, 0x04,
557 0x5A, 0x08, 0x03, 0xE0, 0x01),
558 PLL_CTL(6144000, 0x17,
559 0x5A, 0x08, 0x03, 0xE0, 0x01,
560 0x5A, 0x08, 0x03, 0xB9, 0x01),
561 PLL_CTL(12000000, 0x2E,
562 0x5B, 0x19, 0x03, 0x00, 0x03,
563 0x6A, 0x19, 0x05, 0x98, 0x04),
564 PLL_CTL(19200000, 0x4A,
565 0x53, 0x14, 0x03, 0x80, 0x01,
566 0x5A, 0x19, 0x03, 0xB9, 0x01),
567 PLL_CTL(22000000, 0x55,
568 0x6A, 0x37, 0x05, 0x00, 0x06,
569 0x62, 0x26, 0x03, 0x49, 0x02),
570 PLL_CTL(22579200, 0x57,
571 0x62, 0x31, 0x03, 0x20, 0x03,
572 0x53, 0x1D, 0x03, 0xB3, 0x01),
573 PLL_CTL(24000000, 0x5D,
574 0x53, 0x19, 0x03, 0x80, 0x01,
575 0x5B, 0x19, 0x05, 0x4C, 0x02),
576 PLL_CTL(24576000, 0x5F,
577 0x53, 0x1D, 0x03, 0xB3, 0x01,
578 0x62, 0x40, 0x03, 0x72, 0x03),
579 PLL_CTL(27000000, 0x68,
580 0x62, 0x4B, 0x03, 0x00, 0x04,
581 0x6A, 0x7D, 0x03, 0x20, 0x06),
582 PLL_CTL(36000000, 0x8C,
583 0x5B, 0x4B, 0x03, 0x00, 0x03,
584 0x6A, 0x7D, 0x03, 0x98, 0x04),
585 PLL_CTL(11289600, 0x2B,
586 0x6A, 0x31, 0x03, 0x40, 0x06,
587 0x5A, 0x12, 0x03, 0x1C, 0x02),
588 PLL_CTL(26000000, 0x65,
589 0x63, 0x41, 0x05, 0x00, 0x06,
590 0x5A, 0x26, 0x03, 0xEF, 0x01),
591 PLL_CTL(12288000, 0x2F,
592 0x5A, 0x12, 0x03, 0x1C, 0x02,
593 0x62, 0x20, 0x03, 0x72, 0x03),
594 PLL_CTL(40000000, 0x9B,
595 0xA2, 0x7D, 0x03, 0x80, 0x04,
596 0x63, 0x7D, 0x05, 0xE4, 0x06),
597 PLL_CTL(512000, 0x01,
598 0x62, 0x01, 0x03, 0xD0, 0x02,
599 0x5B, 0x01, 0x04, 0x72, 0x03),
600 PLL_CTL(705600, 0x02,
601 0x62, 0x02, 0x03, 0x15, 0x04,
602 0x62, 0x01, 0x04, 0x80, 0x02),
603 PLL_CTL(1024000, 0x03,
604 0x62, 0x02, 0x03, 0xD0, 0x02,
605 0x5B, 0x02, 0x04, 0x72, 0x03),
606 PLL_CTL(2048000, 0x07,
607 0x62, 0x04, 0x03, 0xD0, 0x02,
608 0x5B, 0x04, 0x04, 0x72, 0x03),
609 PLL_CTL(2400000, 0x08,
610 0x62, 0x05, 0x03, 0x00, 0x03,
611 0x63, 0x05, 0x05, 0x98, 0x04),
612 };
613
614 static inline const struct pll_ctl *get_pll_ctl(unsigned long freq_in)
615 {
616 int i;
617 struct pll_ctl const *pll_ctl = NULL;
618
619 for (i = 0; i < ARRAY_SIZE(pll_ctls); ++i)
620 if (pll_ctls[i].freq_in == freq_in) {
621 pll_ctl = &pll_ctls[i];
622 break;
623 }
624
625 return pll_ctl;
626 }
627
628 enum {
629 PLL_INPUT_XTAL = 0,
630 PLL_INPUT_MCLK1,
631 PLL_INPUT_MCLK2,
632 PLL_INPUT_BCLK,
633 };
634
635 static int set_sysclk(struct snd_soc_component *component)
636 {
637 struct tscs454 *tscs454 = snd_soc_component_get_drvdata(component);
638 struct pll_ctl const *pll_ctl;
639 unsigned long freq;
640 int i;
641 int ret;
642
643 if (tscs454->sysclk_src_id < PLL_INPUT_BCLK)
644 freq = clk_get_rate(tscs454->sysclk);
645 else
646 freq = tscs454->bclk_freq;
647 pll_ctl = get_pll_ctl(freq);
648 if (!pll_ctl) {
649 ret = -EINVAL;
650 dev_err(component->dev,
651 "Invalid PLL input %lu (%d)\n", freq, ret);
652 return ret;
653 }
654
655 for (i = 0; i < PLL_REG_SETTINGS_COUNT; ++i) {
656 ret = snd_soc_component_write(component,
657 pll_ctl->settings[i].addr,
658 pll_ctl->settings[i].val);
659 if (ret < 0) {
660 dev_err(component->dev,
661 "Failed to set pll setting (%d)\n",
662 ret);
663 return ret;
664 }
665 }
666
667 return 0;
668 }
669
670 static inline void reserve_pll(struct pll *pll)
671 {
672 mutex_lock(&pll->lock);
673 pll->users++;
674 mutex_unlock(&pll->lock);
675 }
676
677 static inline void free_pll(struct pll *pll)
678 {
679 mutex_lock(&pll->lock);
680 pll->users--;
681 mutex_unlock(&pll->lock);
682 }
683
684 static int pll_connected(struct snd_soc_dapm_widget *source,
685 struct snd_soc_dapm_widget *sink)
686 {
687 struct snd_soc_component *component =
688 snd_soc_dapm_to_component(source->dapm);
689 struct tscs454 *tscs454 = snd_soc_component_get_drvdata(component);
690 int users;
691
692 if (strstr(source->name, "PLL 1")) {
693 mutex_lock(&tscs454->pll1.lock);
694 users = tscs454->pll1.users;
695 mutex_unlock(&tscs454->pll1.lock);
696 dev_dbg(component->dev, "%s(): PLL 1 users = %d\n", __func__,
697 users);
698 } else {
699 mutex_lock(&tscs454->pll2.lock);
700 users = tscs454->pll2.users;
701 mutex_unlock(&tscs454->pll2.lock);
702 dev_dbg(component->dev, "%s(): PLL 2 users = %d\n", __func__,
703 users);
704 }
705
706 return users;
707 }
708
709 /*
710 * PLL must be enabled after power up and must be disabled before power down
711 * for proper clock switching.
712 */
713 static int pll_power_event(struct snd_soc_dapm_widget *w,
714 struct snd_kcontrol *kcontrol, int event)
715 {
716 struct snd_soc_component *component =
717 snd_soc_dapm_to_component(w->dapm);
718 struct tscs454 *tscs454 = snd_soc_component_get_drvdata(component);
719 bool enable;
720 bool pll1;
721 unsigned int msk;
722 unsigned int val;
723 int ret;
724
725 if (strstr(w->name, "PLL 1"))
726 pll1 = true;
727 else
728 pll1 = false;
729
730 msk = pll1 ? FM_PLLCTL_PLL1CLKEN : FM_PLLCTL_PLL2CLKEN;
731
732 if (event == SND_SOC_DAPM_POST_PMU)
733 enable = true;
734 else
735 enable = false;
736
737 if (enable)
738 val = pll1 ? FV_PLL1CLKEN_ENABLE : FV_PLL2CLKEN_ENABLE;
739 else
740 val = pll1 ? FV_PLL1CLKEN_DISABLE : FV_PLL2CLKEN_DISABLE;
741
742 ret = snd_soc_component_update_bits(component, R_PLLCTL, msk, val);
743 if (ret < 0) {
744 dev_err(component->dev, "Failed to %s PLL %d (%d)\n",
745 enable ? "enable" : "disable",
746 pll1 ? 1 : 2,
747 ret);
748 return ret;
749 }
750
751 if (enable) {
752 msleep(20); // Wait for lock
753 ret = coeff_ram_sync(component, tscs454);
754 if (ret < 0) {
755 dev_err(component->dev,
756 "Failed to sync coeff ram (%d)\n", ret);
757 return ret;
758 }
759 }
760
761 return 0;
762 }
763
764 static inline int aif_set_master(struct snd_soc_component *component,
765 unsigned int aif_id, bool master)
766 {
767 unsigned int reg;
768 unsigned int mask;
769 unsigned int val;
770 int ret;
771
772 switch (aif_id) {
773 case TSCS454_DAI1_ID:
774 reg = R_I2SP1CTL;
775 break;
776 case TSCS454_DAI2_ID:
777 reg = R_I2SP2CTL;
778 break;
779 case TSCS454_DAI3_ID:
780 reg = R_I2SP3CTL;
781 break;
782 default:
783 ret = -ENODEV;
784 dev_err(component->dev, "Unknown DAI %d (%d)\n", aif_id, ret);
785 return ret;
786 }
787 mask = FM_I2SPCTL_PORTMS;
788 val = master ? FV_PORTMS_MASTER : FV_PORTMS_SLAVE;
789
790 ret = snd_soc_component_update_bits(component, reg, mask, val);
791 if (ret < 0) {
792 dev_err(component->dev, "Failed to set DAI %d to %s (%d)\n",
793 aif_id, master ? "master" : "slave", ret);
794 return ret;
795 }
796
797 return 0;
798 }
799
800 static inline
801 int aif_prepare(struct snd_soc_component *component, struct aif *aif)
802 {
803 int ret;
804
805 ret = aif_set_master(component, aif->id, aif->master);
806 if (ret < 0)
807 return ret;
808
809 return 0;
810 }
811
812 static inline int aif_free(struct snd_soc_component *component,
813 struct aif *aif, bool playback)
814 {
815 struct tscs454 *tscs454 = snd_soc_component_get_drvdata(component);
816
817 mutex_lock(&tscs454->aifs_status_lock);
818
819 dev_dbg(component->dev, "%s(): aif %d\n", __func__, aif->id);
820
821 set_aif_status_inactive(&tscs454->aifs_status, aif->id, playback);
822
823 dev_dbg(component->dev, "Set aif %d inactive. Streams status is 0x%x\n",
824 aif->id, tscs454->aifs_status.streams);
825
826 if (!aif_active(&tscs454->aifs_status, aif->id)) {
827 /* Do config in slave mode */
828 aif_set_master(component, aif->id, false);
829 dev_dbg(component->dev, "Freeing pll %d from aif %d\n",
830 aif->pll->id, aif->id);
831 free_pll(aif->pll);
832 }
833
834 if (!aifs_active(&tscs454->aifs_status)) {
835 dev_dbg(component->dev, "Freeing pll %d from ir\n",
836 tscs454->internal_rate.pll->id);
837 free_pll(tscs454->internal_rate.pll);
838 }
839
840 mutex_unlock(&tscs454->aifs_status_lock);
841
842 return 0;
843 }
844
845 /* R_PLLCTL PG 0 ADDR 0x15 */
846 static char const * const bclk_sel_txt[] = {
847 "BCLK 1", "BCLK 2", "BCLK 3"};
848
849 static struct soc_enum const bclk_sel_enum =
850 SOC_ENUM_SINGLE(R_PLLCTL, FB_PLLCTL_BCLKSEL,
851 ARRAY_SIZE(bclk_sel_txt), bclk_sel_txt);
852
853 /* R_ISRC PG 0 ADDR 0x16 */
854 static char const * const isrc_br_txt[] = {
855 "44.1kHz", "48kHz"};
856
857 static struct soc_enum const isrc_br_enum =
858 SOC_ENUM_SINGLE(R_ISRC, FB_ISRC_IBR,
859 ARRAY_SIZE(isrc_br_txt), isrc_br_txt);
860
861 static char const * const isrc_bm_txt[] = {
862 "0.25x", "0.5x", "1.0x", "2.0x"};
863
864 static struct soc_enum const isrc_bm_enum =
865 SOC_ENUM_SINGLE(R_ISRC, FB_ISRC_IBM,
866 ARRAY_SIZE(isrc_bm_txt), isrc_bm_txt);
867
868 /* R_SCLKCTL PG 0 ADDR 0x18 */
869 static char const * const modular_rate_txt[] = {
870 "Reserved", "Half", "Full", "Auto",};
871
872 static struct soc_enum const adc_modular_rate_enum =
873 SOC_ENUM_SINGLE(R_SCLKCTL, FB_SCLKCTL_ASDM,
874 ARRAY_SIZE(modular_rate_txt), modular_rate_txt);
875
876 static struct soc_enum const dac_modular_rate_enum =
877 SOC_ENUM_SINGLE(R_SCLKCTL, FB_SCLKCTL_DSDM,
878 ARRAY_SIZE(modular_rate_txt), modular_rate_txt);
879
880 /* R_I2SIDCTL PG 0 ADDR 0x38 */
881 static char const * const data_ctrl_txt[] = {
882 "L/R", "L/L", "R/R", "R/L"};
883
884 static struct soc_enum const data_in_ctrl_enums[] = {
885 SOC_ENUM_SINGLE(R_I2SIDCTL, FB_I2SIDCTL_I2SI1DCTL,
886 ARRAY_SIZE(data_ctrl_txt), data_ctrl_txt),
887 SOC_ENUM_SINGLE(R_I2SIDCTL, FB_I2SIDCTL_I2SI2DCTL,
888 ARRAY_SIZE(data_ctrl_txt), data_ctrl_txt),
889 SOC_ENUM_SINGLE(R_I2SIDCTL, FB_I2SIDCTL_I2SI3DCTL,
890 ARRAY_SIZE(data_ctrl_txt), data_ctrl_txt),
891 };
892
893 /* R_I2SODCTL PG 0 ADDR 0x39 */
894 static struct soc_enum const data_out_ctrl_enums[] = {
895 SOC_ENUM_SINGLE(R_I2SODCTL, FB_I2SODCTL_I2SO1DCTL,
896 ARRAY_SIZE(data_ctrl_txt), data_ctrl_txt),
897 SOC_ENUM_SINGLE(R_I2SODCTL, FB_I2SODCTL_I2SO2DCTL,
898 ARRAY_SIZE(data_ctrl_txt), data_ctrl_txt),
899 SOC_ENUM_SINGLE(R_I2SODCTL, FB_I2SODCTL_I2SO3DCTL,
900 ARRAY_SIZE(data_ctrl_txt), data_ctrl_txt),
901 };
902
903 /* R_AUDIOMUX1 PG 0 ADDR 0x3A */
904 static char const * const asrc_mux_txt[] = {
905 "None", "DAI 1", "DAI 2", "DAI 3"};
906
907 static struct soc_enum const asrc_in_mux_enum =
908 SOC_ENUM_SINGLE(R_AUDIOMUX1, FB_AUDIOMUX1_ASRCIMUX,
909 ARRAY_SIZE(asrc_mux_txt), asrc_mux_txt);
910
911 static char const * const dai_mux_txt[] = {
912 "CH 0_1", "CH 2_3", "CH 4_5", "ADC/DMic 1",
913 "DMic 2", "ClassD", "DAC", "Sub"};
914
915 static struct soc_enum const dai2_mux_enum =
916 SOC_ENUM_SINGLE(R_AUDIOMUX1, FB_AUDIOMUX1_I2S2MUX,
917 ARRAY_SIZE(dai_mux_txt), dai_mux_txt);
918
919 static struct snd_kcontrol_new const dai2_mux_dapm_enum =
920 SOC_DAPM_ENUM("DAI 2 Mux", dai2_mux_enum);
921
922 static struct soc_enum const dai1_mux_enum =
923 SOC_ENUM_SINGLE(R_AUDIOMUX1, FB_AUDIOMUX1_I2S1MUX,
924 ARRAY_SIZE(dai_mux_txt), dai_mux_txt);
925
926 static struct snd_kcontrol_new const dai1_mux_dapm_enum =
927 SOC_DAPM_ENUM("DAI 1 Mux", dai1_mux_enum);
928
929 /* R_AUDIOMUX2 PG 0 ADDR 0x3B */
930 static struct soc_enum const asrc_out_mux_enum =
931 SOC_ENUM_SINGLE(R_AUDIOMUX2, FB_AUDIOMUX2_ASRCOMUX,
932 ARRAY_SIZE(asrc_mux_txt), asrc_mux_txt);
933
934 static struct soc_enum const dac_mux_enum =
935 SOC_ENUM_SINGLE(R_AUDIOMUX2, FB_AUDIOMUX2_DACMUX,
936 ARRAY_SIZE(dai_mux_txt), dai_mux_txt);
937
938 static struct snd_kcontrol_new const dac_mux_dapm_enum =
939 SOC_DAPM_ENUM("DAC Mux", dac_mux_enum);
940
941 static struct soc_enum const dai3_mux_enum =
942 SOC_ENUM_SINGLE(R_AUDIOMUX2, FB_AUDIOMUX2_I2S3MUX,
943 ARRAY_SIZE(dai_mux_txt), dai_mux_txt);
944
945 static struct snd_kcontrol_new const dai3_mux_dapm_enum =
946 SOC_DAPM_ENUM("DAI 3 Mux", dai3_mux_enum);
947
948 /* R_AUDIOMUX3 PG 0 ADDR 0x3C */
949 static char const * const sub_mux_txt[] = {
950 "CH 0", "CH 1", "CH 0 + 1",
951 "CH 2", "CH 3", "CH 2 + 3",
952 "CH 4", "CH 5", "CH 4 + 5",
953 "ADC/DMic 1 Left", "ADC/DMic 1 Right",
954 "ADC/DMic 1 Left Plus Right",
955 "DMic 2 Left", "DMic 2 Right", "DMic 2 Left Plus Right",
956 "ClassD Left", "ClassD Right", "ClassD Left Plus Right"};
957
958 static struct soc_enum const sub_mux_enum =
959 SOC_ENUM_SINGLE(R_AUDIOMUX3, FB_AUDIOMUX3_SUBMUX,
960 ARRAY_SIZE(sub_mux_txt), sub_mux_txt);
961
962 static struct snd_kcontrol_new const sub_mux_dapm_enum =
963 SOC_DAPM_ENUM("Sub Mux", sub_mux_enum);
964
965 static struct soc_enum const classd_mux_enum =
966 SOC_ENUM_SINGLE(R_AUDIOMUX3, FB_AUDIOMUX3_CLSSDMUX,
967 ARRAY_SIZE(dai_mux_txt), dai_mux_txt);
968
969 static struct snd_kcontrol_new const classd_mux_dapm_enum =
970 SOC_DAPM_ENUM("ClassD Mux", classd_mux_enum);
971
972 /* R_HSDCTL1 PG 1 ADDR 0x01 */
973 static char const * const jack_type_txt[] = {
974 "3 Terminal", "4 Terminal"};
975
976 static struct soc_enum const hp_jack_type_enum =
977 SOC_ENUM_SINGLE(R_HSDCTL1, FB_HSDCTL1_HPJKTYPE,
978 ARRAY_SIZE(jack_type_txt), jack_type_txt);
979
980 static char const * const hs_det_pol_txt[] = {
981 "Rising", "Falling"};
982
983 static struct soc_enum const hs_det_pol_enum =
984 SOC_ENUM_SINGLE(R_HSDCTL1, FB_HSDCTL1_HSDETPOL,
985 ARRAY_SIZE(hs_det_pol_txt), hs_det_pol_txt);
986
987 /* R_HSDCTL1 PG 1 ADDR 0x02 */
988 static char const * const hs_mic_bias_force_txt[] = {
989 "Off", "Ring", "Sleeve"};
990
991 static struct soc_enum const hs_mic_bias_force_enum =
992 SOC_ENUM_SINGLE(R_HSDCTL2, FB_HSDCTL2_FMICBIAS1,
993 ARRAY_SIZE(hs_mic_bias_force_txt),
994 hs_mic_bias_force_txt);
995
996 static char const * const plug_type_txt[] = {
997 "OMTP", "CTIA", "Reserved", "Headphone"};
998
999 static struct soc_enum const plug_type_force_enum =
1000 SOC_ENUM_SINGLE(R_HSDCTL2, FB_HSDCTL2_FPLUGTYPE,
1001 ARRAY_SIZE(plug_type_txt), plug_type_txt);
1002
1003
1004 /* R_CH0AIC PG 1 ADDR 0x06 */
1005 static char const * const in_bst_mux_txt[] = {
1006 "Input 1", "Input 2", "Input 3", "D2S"};
1007
1008 static struct soc_enum const in_bst_mux_ch0_enum =
1009 SOC_ENUM_SINGLE(R_CH0AIC, FB_CH0AIC_INSELL,
1010 ARRAY_SIZE(in_bst_mux_txt),
1011 in_bst_mux_txt);
1012 static struct snd_kcontrol_new const in_bst_mux_ch0_dapm_enum =
1013 SOC_DAPM_ENUM("Input Boost Channel 0 Enum",
1014 in_bst_mux_ch0_enum);
1015
1016 static DECLARE_TLV_DB_SCALE(in_bst_vol_tlv_arr, 0, 1000, 0);
1017
1018 static char const * const adc_mux_txt[] = {
1019 "Input 1 Boost Bypass", "Input 2 Boost Bypass",
1020 "Input 3 Boost Bypass", "Input Boost"};
1021
1022 static struct soc_enum const adc_mux_ch0_enum =
1023 SOC_ENUM_SINGLE(R_CH0AIC, FB_CH0AIC_LADCIN,
1024 ARRAY_SIZE(adc_mux_txt), adc_mux_txt);
1025 static struct snd_kcontrol_new const adc_mux_ch0_dapm_enum =
1026 SOC_DAPM_ENUM("ADC Channel 0 Enum", adc_mux_ch0_enum);
1027
1028 static char const * const in_proc_mux_txt[] = {
1029 "ADC", "DMic"};
1030
1031 static struct soc_enum const in_proc_ch0_enum =
1032 SOC_ENUM_SINGLE(R_CH0AIC, FB_CH0AIC_IPCH0S,
1033 ARRAY_SIZE(in_proc_mux_txt), in_proc_mux_txt);
1034 static struct snd_kcontrol_new const in_proc_mux_ch0_dapm_enum =
1035 SOC_DAPM_ENUM("Input Processor Channel 0 Enum",
1036 in_proc_ch0_enum);
1037
1038 /* R_CH1AIC PG 1 ADDR 0x07 */
1039 static struct soc_enum const in_bst_mux_ch1_enum =
1040 SOC_ENUM_SINGLE(R_CH1AIC, FB_CH1AIC_INSELR,
1041 ARRAY_SIZE(in_bst_mux_txt),
1042 in_bst_mux_txt);
1043 static struct snd_kcontrol_new const in_bst_mux_ch1_dapm_enum =
1044 SOC_DAPM_ENUM("Input Boost Channel 1 Enum",
1045 in_bst_mux_ch1_enum);
1046
1047 static struct soc_enum const adc_mux_ch1_enum =
1048 SOC_ENUM_SINGLE(R_CH1AIC, FB_CH1AIC_RADCIN,
1049 ARRAY_SIZE(adc_mux_txt), adc_mux_txt);
1050 static struct snd_kcontrol_new const adc_mux_ch1_dapm_enum =
1051 SOC_DAPM_ENUM("ADC Channel 1 Enum", adc_mux_ch1_enum);
1052
1053 static struct soc_enum const in_proc_ch1_enum =
1054 SOC_ENUM_SINGLE(R_CH1AIC, FB_CH1AIC_IPCH1S,
1055 ARRAY_SIZE(in_proc_mux_txt), in_proc_mux_txt);
1056 static struct snd_kcontrol_new const in_proc_mux_ch1_dapm_enum =
1057 SOC_DAPM_ENUM("Input Processor Channel 1 Enum",
1058 in_proc_ch1_enum);
1059
1060 /* R_ICTL0 PG 1 ADDR 0x0A */
1061 static char const * const pol_txt[] = {
1062 "Normal", "Invert"};
1063
1064 static struct soc_enum const in_pol_ch1_enum =
1065 SOC_ENUM_SINGLE(R_ICTL0, FB_ICTL0_IN0POL,
1066 ARRAY_SIZE(pol_txt), pol_txt);
1067
1068 static struct soc_enum const in_pol_ch0_enum =
1069 SOC_ENUM_SINGLE(R_ICTL0, FB_ICTL0_IN1POL,
1070 ARRAY_SIZE(pol_txt), pol_txt);
1071
1072 static char const * const in_proc_ch_sel_txt[] = {
1073 "Normal", "Mono Mix to Channel 0",
1074 "Mono Mix to Channel 1", "Add"};
1075
1076 static struct soc_enum const in_proc_ch01_sel_enum =
1077 SOC_ENUM_SINGLE(R_ICTL0, FB_ICTL0_INPCH10SEL,
1078 ARRAY_SIZE(in_proc_ch_sel_txt),
1079 in_proc_ch_sel_txt);
1080
1081 /* R_ICTL1 PG 1 ADDR 0x0B */
1082 static struct soc_enum const in_pol_ch3_enum =
1083 SOC_ENUM_SINGLE(R_ICTL1, FB_ICTL1_IN2POL,
1084 ARRAY_SIZE(pol_txt), pol_txt);
1085
1086 static struct soc_enum const in_pol_ch2_enum =
1087 SOC_ENUM_SINGLE(R_ICTL1, FB_ICTL1_IN3POL,
1088 ARRAY_SIZE(pol_txt), pol_txt);
1089
1090 static struct soc_enum const in_proc_ch23_sel_enum =
1091 SOC_ENUM_SINGLE(R_ICTL1, FB_ICTL1_INPCH32SEL,
1092 ARRAY_SIZE(in_proc_ch_sel_txt),
1093 in_proc_ch_sel_txt);
1094
1095 /* R_MICBIAS PG 1 ADDR 0x0C */
1096 static char const * const mic_bias_txt[] = {
1097 "2.5V", "2.1V", "1.8V", "Vdd"};
1098
1099 static struct soc_enum const mic_bias_2_enum =
1100 SOC_ENUM_SINGLE(R_MICBIAS, FB_MICBIAS_MICBOV2,
1101 ARRAY_SIZE(mic_bias_txt), mic_bias_txt);
1102
1103 static struct soc_enum const mic_bias_1_enum =
1104 SOC_ENUM_SINGLE(R_MICBIAS, FB_MICBIAS_MICBOV1,
1105 ARRAY_SIZE(mic_bias_txt), mic_bias_txt);
1106
1107 /* R_PGACTL0 PG 1 ADDR 0x0D */
1108 /* R_PGACTL1 PG 1 ADDR 0x0E */
1109 /* R_PGACTL2 PG 1 ADDR 0x0F */
1110 /* R_PGACTL3 PG 1 ADDR 0x10 */
1111 static DECLARE_TLV_DB_SCALE(in_pga_vol_tlv_arr, -1725, 75, 0);
1112
1113 /* R_ICH0VOL PG1 ADDR 0x12 */
1114 /* R_ICH1VOL PG1 ADDR 0x13 */
1115 /* R_ICH2VOL PG1 ADDR 0x14 */
1116 /* R_ICH3VOL PG1 ADDR 0x15 */
1117 static DECLARE_TLV_DB_MINMAX(in_vol_tlv_arr, -7125, 2400);
1118
1119 /* R_ASRCILVOL PG1 ADDR 0x16 */
1120 /* R_ASRCIRVOL PG1 ADDR 0x17 */
1121 /* R_ASRCOLVOL PG1 ADDR 0x18 */
1122 /* R_ASRCORVOL PG1 ADDR 0x19 */
1123 static DECLARE_TLV_DB_MINMAX(asrc_vol_tlv_arr, -9562, 600);
1124
1125 /* R_ALCCTL0 PG1 ADDR 0x1D */
1126 static char const * const alc_mode_txt[] = {
1127 "ALC", "Limiter"};
1128
1129 static struct soc_enum const alc_mode_enum =
1130 SOC_ENUM_SINGLE(R_ALCCTL0, FB_ALCCTL0_ALCMODE,
1131 ARRAY_SIZE(alc_mode_txt), alc_mode_txt);
1132
1133 static char const * const alc_ref_text[] = {
1134 "Channel 0", "Channel 1", "Channel 2", "Channel 3", "Peak"};
1135
1136 static struct soc_enum const alc_ref_enum =
1137 SOC_ENUM_SINGLE(R_ALCCTL0, FB_ALCCTL0_ALCREF,
1138 ARRAY_SIZE(alc_ref_text), alc_ref_text);
1139
1140 /* R_ALCCTL1 PG 1 ADDR 0x1E */
1141 static DECLARE_TLV_DB_SCALE(alc_max_gain_tlv_arr, -1200, 600, 0);
1142 static DECLARE_TLV_DB_SCALE(alc_target_tlv_arr, -2850, 150, 0);
1143
1144 /* R_ALCCTL2 PG 1 ADDR 0x1F */
1145 static DECLARE_TLV_DB_SCALE(alc_min_gain_tlv_arr, -1725, 600, 0);
1146
1147 /* R_NGATE PG 1 ADDR 0x21 */
1148 static DECLARE_TLV_DB_SCALE(ngth_tlv_arr, -7650, 150, 0);
1149
1150 static char const * const ngate_type_txt[] = {
1151 "PGA Constant", "ADC Mute"};
1152
1153 static struct soc_enum const ngate_type_enum =
1154 SOC_ENUM_SINGLE(R_NGATE, FB_NGATE_NGG,
1155 ARRAY_SIZE(ngate_type_txt), ngate_type_txt);
1156
1157 /* R_DMICCTL PG 1 ADDR 0x22 */
1158 static char const * const dmic_mono_sel_txt[] = {
1159 "Stereo", "Mono"};
1160
1161 static struct soc_enum const dmic_mono_sel_enum =
1162 SOC_ENUM_SINGLE(R_DMICCTL, FB_DMICCTL_DMONO,
1163 ARRAY_SIZE(dmic_mono_sel_txt), dmic_mono_sel_txt);
1164
1165 /* R_DACCTL PG 2 ADDR 0x01 */
1166 static struct soc_enum const dac_pol_r_enum =
1167 SOC_ENUM_SINGLE(R_DACCTL, FB_DACCTL_DACPOLR,
1168 ARRAY_SIZE(pol_txt), pol_txt);
1169
1170 static struct soc_enum const dac_pol_l_enum =
1171 SOC_ENUM_SINGLE(R_DACCTL, FB_DACCTL_DACPOLL,
1172 ARRAY_SIZE(pol_txt), pol_txt);
1173
1174 static char const * const dac_dith_txt[] = {
1175 "Half", "Full", "Disabled", "Static"};
1176
1177 static struct soc_enum const dac_dith_enum =
1178 SOC_ENUM_SINGLE(R_DACCTL, FB_DACCTL_DACDITH,
1179 ARRAY_SIZE(dac_dith_txt), dac_dith_txt);
1180
1181 /* R_SPKCTL PG 2 ADDR 0x02 */
1182 static struct soc_enum const spk_pol_r_enum =
1183 SOC_ENUM_SINGLE(R_SPKCTL, FB_SPKCTL_SPKPOLR,
1184 ARRAY_SIZE(pol_txt), pol_txt);
1185
1186 static struct soc_enum const spk_pol_l_enum =
1187 SOC_ENUM_SINGLE(R_SPKCTL, FB_SPKCTL_SPKPOLL,
1188 ARRAY_SIZE(pol_txt), pol_txt);
1189
1190 /* R_SUBCTL PG 2 ADDR 0x03 */
1191 static struct soc_enum const sub_pol_enum =
1192 SOC_ENUM_SINGLE(R_SUBCTL, FB_SUBCTL_SUBPOL,
1193 ARRAY_SIZE(pol_txt), pol_txt);
1194
1195 /* R_MVOLL PG 2 ADDR 0x08 */
1196 /* R_MVOLR PG 2 ADDR 0x09 */
1197 static DECLARE_TLV_DB_MINMAX(mvol_tlv_arr, -9562, 0);
1198
1199 /* R_HPVOLL PG 2 ADDR 0x0A */
1200 /* R_HPVOLR PG 2 ADDR 0x0B */
1201 static DECLARE_TLV_DB_SCALE(hp_vol_tlv_arr, -8850, 75, 0);
1202
1203 /* R_SPKVOLL PG 2 ADDR 0x0C */
1204 /* R_SPKVOLR PG 2 ADDR 0x0D */
1205 static DECLARE_TLV_DB_SCALE(spk_vol_tlv_arr, -7725, 75, 0);
1206
1207 /* R_SPKEQFILT PG 3 ADDR 0x01 */
1208 static char const * const eq_txt[] = {
1209 "Pre Scale",
1210 "Pre Scale + EQ Band 0",
1211 "Pre Scale + EQ Band 0 - 1",
1212 "Pre Scale + EQ Band 0 - 2",
1213 "Pre Scale + EQ Band 0 - 3",
1214 "Pre Scale + EQ Band 0 - 4",
1215 "Pre Scale + EQ Band 0 - 5",
1216 };
1217
1218 static struct soc_enum const spk_eq_enums[] = {
1219 SOC_ENUM_SINGLE(R_SPKEQFILT, FB_SPKEQFILT_EQ2BE,
1220 ARRAY_SIZE(eq_txt), eq_txt),
1221 SOC_ENUM_SINGLE(R_SPKEQFILT, FB_SPKEQFILT_EQ1BE,
1222 ARRAY_SIZE(eq_txt), eq_txt),
1223 };
1224
1225 /* R_SPKMBCCTL PG 3 ADDR 0x0B */
1226 static char const * const lvl_mode_txt[] = {
1227 "Average", "Peak"};
1228
1229 static struct soc_enum const spk_mbc3_lvl_det_mode_enum =
1230 SOC_ENUM_SINGLE(R_SPKMBCCTL, FB_SPKMBCCTL_LVLMODE3,
1231 ARRAY_SIZE(lvl_mode_txt), lvl_mode_txt);
1232
1233 static char const * const win_sel_txt[] = {
1234 "512", "64"};
1235
1236 static struct soc_enum const spk_mbc3_win_sel_enum =
1237 SOC_ENUM_SINGLE(R_SPKMBCCTL, FB_SPKMBCCTL_WINSEL3,
1238 ARRAY_SIZE(win_sel_txt), win_sel_txt);
1239
1240 static struct soc_enum const spk_mbc2_lvl_det_mode_enum =
1241 SOC_ENUM_SINGLE(R_SPKMBCCTL, FB_SPKMBCCTL_LVLMODE2,
1242 ARRAY_SIZE(lvl_mode_txt), lvl_mode_txt);
1243
1244 static struct soc_enum const spk_mbc2_win_sel_enum =
1245 SOC_ENUM_SINGLE(R_SPKMBCCTL, FB_SPKMBCCTL_WINSEL2,
1246 ARRAY_SIZE(win_sel_txt), win_sel_txt);
1247
1248 static struct soc_enum const spk_mbc1_lvl_det_mode_enum =
1249 SOC_ENUM_SINGLE(R_SPKMBCCTL, FB_SPKMBCCTL_LVLMODE1,
1250 ARRAY_SIZE(lvl_mode_txt), lvl_mode_txt);
1251
1252 static struct soc_enum const spk_mbc1_win_sel_enum =
1253 SOC_ENUM_SINGLE(R_SPKMBCCTL, FB_SPKMBCCTL_WINSEL1,
1254 ARRAY_SIZE(win_sel_txt), win_sel_txt);
1255
1256 /* R_SPKMBCMUG1 PG 3 ADDR 0x0C */
1257 static struct soc_enum const spk_mbc1_phase_pol_enum =
1258 SOC_ENUM_SINGLE(R_SPKMBCMUG1, FB_SPKMBCMUG_PHASE,
1259 ARRAY_SIZE(pol_txt), pol_txt);
1260
1261 static DECLARE_TLV_DB_MINMAX(mbc_mug_tlv_arr, -4650, 0);
1262
1263 /* R_SPKMBCTHR1 PG 3 ADDR 0x0D */
1264 static DECLARE_TLV_DB_MINMAX(thr_tlv_arr, -9562, 0);
1265
1266 /* R_SPKMBCRAT1 PG 3 ADDR 0x0E */
1267 static char const * const comp_rat_txt[] = {
1268 "Reserved", "1.5:1", "2:1", "3:1", "4:1", "5:1", "6:1",
1269 "7:1", "8:1", "9:1", "10:1", "11:1", "12:1", "13:1", "14:1",
1270 "15:1", "16:1", "17:1", "18:1", "19:1", "20:1"};
1271
1272 static struct soc_enum const spk_mbc1_comp_rat_enum =
1273 SOC_ENUM_SINGLE(R_SPKMBCRAT1, FB_SPKMBCRAT_RATIO,
1274 ARRAY_SIZE(comp_rat_txt), comp_rat_txt);
1275
1276 /* R_SPKMBCMUG2 PG 3 ADDR 0x13 */
1277 static struct soc_enum const spk_mbc2_phase_pol_enum =
1278 SOC_ENUM_SINGLE(R_SPKMBCMUG2, FB_SPKMBCMUG_PHASE,
1279 ARRAY_SIZE(pol_txt), pol_txt);
1280
1281 /* R_SPKMBCRAT2 PG 3 ADDR 0x15 */
1282 static struct soc_enum const spk_mbc2_comp_rat_enum =
1283 SOC_ENUM_SINGLE(R_SPKMBCRAT2, FB_SPKMBCRAT_RATIO,
1284 ARRAY_SIZE(comp_rat_txt), comp_rat_txt);
1285
1286 /* R_SPKMBCMUG3 PG 3 ADDR 0x1A */
1287 static struct soc_enum const spk_mbc3_phase_pol_enum =
1288 SOC_ENUM_SINGLE(R_SPKMBCMUG3, FB_SPKMBCMUG_PHASE,
1289 ARRAY_SIZE(pol_txt), pol_txt);
1290
1291 /* R_SPKMBCRAT3 PG 3 ADDR 0x1C */
1292 static struct soc_enum const spk_mbc3_comp_rat_enum =
1293 SOC_ENUM_SINGLE(R_SPKMBCRAT3, FB_SPKMBCRAT_RATIO,
1294 ARRAY_SIZE(comp_rat_txt), comp_rat_txt);
1295
1296 /* R_SPKCLECTL PG 3 ADDR 0x21 */
1297 static struct soc_enum const spk_cle_lvl_mode_enum =
1298 SOC_ENUM_SINGLE(R_SPKCLECTL, FB_SPKCLECTL_LVLMODE,
1299 ARRAY_SIZE(lvl_mode_txt), lvl_mode_txt);
1300
1301 static struct soc_enum const spk_cle_win_sel_enum =
1302 SOC_ENUM_SINGLE(R_SPKCLECTL, FB_SPKCLECTL_WINSEL,
1303 ARRAY_SIZE(win_sel_txt), win_sel_txt);
1304
1305 /* R_SPKCLEMUG PG 3 ADDR 0x22 */
1306 static DECLARE_TLV_DB_MINMAX(cle_mug_tlv_arr, 0, 4650);
1307
1308 /* R_SPKCOMPRAT PG 3 ADDR 0x24 */
1309 static struct soc_enum const spk_comp_rat_enum =
1310 SOC_ENUM_SINGLE(R_SPKCOMPRAT, FB_SPKCOMPRAT_RATIO,
1311 ARRAY_SIZE(comp_rat_txt), comp_rat_txt);
1312
1313 /* R_SPKEXPTHR PG 3 ADDR 0x2F */
1314 static char const * const exp_rat_txt[] = {
1315 "Reserved", "Reserved", "1:2", "1:3",
1316 "1:4", "1:5", "1:6", "1:7"};
1317
1318 static struct soc_enum const spk_exp_rat_enum =
1319 SOC_ENUM_SINGLE(R_SPKEXPRAT, FB_SPKEXPRAT_RATIO,
1320 ARRAY_SIZE(exp_rat_txt), exp_rat_txt);
1321
1322 /* R_DACEQFILT PG 4 ADDR 0x01 */
1323 static struct soc_enum const dac_eq_enums[] = {
1324 SOC_ENUM_SINGLE(R_DACEQFILT, FB_DACEQFILT_EQ2BE,
1325 ARRAY_SIZE(eq_txt), eq_txt),
1326 SOC_ENUM_SINGLE(R_DACEQFILT, FB_DACEQFILT_EQ1BE,
1327 ARRAY_SIZE(eq_txt), eq_txt),
1328 };
1329
1330 /* R_DACMBCCTL PG 4 ADDR 0x0B */
1331 static struct soc_enum const dac_mbc3_lvl_det_mode_enum =
1332 SOC_ENUM_SINGLE(R_DACMBCCTL, FB_DACMBCCTL_LVLMODE3,
1333 ARRAY_SIZE(lvl_mode_txt), lvl_mode_txt);
1334
1335 static struct soc_enum const dac_mbc3_win_sel_enum =
1336 SOC_ENUM_SINGLE(R_DACMBCCTL, FB_DACMBCCTL_WINSEL3,
1337 ARRAY_SIZE(win_sel_txt), win_sel_txt);
1338
1339 static struct soc_enum const dac_mbc2_lvl_det_mode_enum =
1340 SOC_ENUM_SINGLE(R_DACMBCCTL, FB_DACMBCCTL_LVLMODE2,
1341 ARRAY_SIZE(lvl_mode_txt), lvl_mode_txt);
1342
1343 static struct soc_enum const dac_mbc2_win_sel_enum =
1344 SOC_ENUM_SINGLE(R_DACMBCCTL, FB_DACMBCCTL_WINSEL2,
1345 ARRAY_SIZE(win_sel_txt), win_sel_txt);
1346
1347 static struct soc_enum const dac_mbc1_lvl_det_mode_enum =
1348 SOC_ENUM_SINGLE(R_DACMBCCTL, FB_DACMBCCTL_LVLMODE1,
1349 ARRAY_SIZE(lvl_mode_txt), lvl_mode_txt);
1350
1351 static struct soc_enum const dac_mbc1_win_sel_enum =
1352 SOC_ENUM_SINGLE(R_DACMBCCTL, FB_DACMBCCTL_WINSEL1,
1353 ARRAY_SIZE(win_sel_txt), win_sel_txt);
1354
1355 /* R_DACMBCMUG1 PG 4 ADDR 0x0C */
1356 static struct soc_enum const dac_mbc1_phase_pol_enum =
1357 SOC_ENUM_SINGLE(R_DACMBCMUG1, FB_DACMBCMUG_PHASE,
1358 ARRAY_SIZE(pol_txt), pol_txt);
1359
1360 /* R_DACMBCRAT1 PG 4 ADDR 0x0E */
1361 static struct soc_enum const dac_mbc1_comp_rat_enum =
1362 SOC_ENUM_SINGLE(R_DACMBCRAT1, FB_DACMBCRAT_RATIO,
1363 ARRAY_SIZE(comp_rat_txt), comp_rat_txt);
1364
1365 /* R_DACMBCMUG2 PG 4 ADDR 0x13 */
1366 static struct soc_enum const dac_mbc2_phase_pol_enum =
1367 SOC_ENUM_SINGLE(R_DACMBCMUG2, FB_DACMBCMUG_PHASE,
1368 ARRAY_SIZE(pol_txt), pol_txt);
1369
1370 /* R_DACMBCRAT2 PG 4 ADDR 0x15 */
1371 static struct soc_enum const dac_mbc2_comp_rat_enum =
1372 SOC_ENUM_SINGLE(R_DACMBCRAT2, FB_DACMBCRAT_RATIO,
1373 ARRAY_SIZE(comp_rat_txt), comp_rat_txt);
1374
1375 /* R_DACMBCMUG3 PG 4 ADDR 0x1A */
1376 static struct soc_enum const dac_mbc3_phase_pol_enum =
1377 SOC_ENUM_SINGLE(R_DACMBCMUG3, FB_DACMBCMUG_PHASE,
1378 ARRAY_SIZE(pol_txt), pol_txt);
1379
1380 /* R_DACMBCRAT3 PG 4 ADDR 0x1C */
1381 static struct soc_enum const dac_mbc3_comp_rat_enum =
1382 SOC_ENUM_SINGLE(R_DACMBCRAT3, FB_DACMBCRAT_RATIO,
1383 ARRAY_SIZE(comp_rat_txt), comp_rat_txt);
1384
1385 /* R_DACCLECTL PG 4 ADDR 0x21 */
1386 static struct soc_enum const dac_cle_lvl_mode_enum =
1387 SOC_ENUM_SINGLE(R_DACCLECTL, FB_DACCLECTL_LVLMODE,
1388 ARRAY_SIZE(lvl_mode_txt), lvl_mode_txt);
1389
1390 static struct soc_enum const dac_cle_win_sel_enum =
1391 SOC_ENUM_SINGLE(R_DACCLECTL, FB_DACCLECTL_WINSEL,
1392 ARRAY_SIZE(win_sel_txt), win_sel_txt);
1393
1394 /* R_DACCOMPRAT PG 4 ADDR 0x24 */
1395 static struct soc_enum const dac_comp_rat_enum =
1396 SOC_ENUM_SINGLE(R_DACCOMPRAT, FB_DACCOMPRAT_RATIO,
1397 ARRAY_SIZE(comp_rat_txt), comp_rat_txt);
1398
1399 /* R_DACEXPRAT PG 4 ADDR 0x30 */
1400 static struct soc_enum const dac_exp_rat_enum =
1401 SOC_ENUM_SINGLE(R_DACEXPRAT, FB_DACEXPRAT_RATIO,
1402 ARRAY_SIZE(exp_rat_txt), exp_rat_txt);
1403
1404 /* R_SUBEQFILT PG 5 ADDR 0x01 */
1405 static struct soc_enum const sub_eq_enums[] = {
1406 SOC_ENUM_SINGLE(R_SUBEQFILT, FB_SUBEQFILT_EQ2BE,
1407 ARRAY_SIZE(eq_txt), eq_txt),
1408 SOC_ENUM_SINGLE(R_SUBEQFILT, FB_SUBEQFILT_EQ1BE,
1409 ARRAY_SIZE(eq_txt), eq_txt),
1410 };
1411
1412 /* R_SUBMBCCTL PG 5 ADDR 0x0B */
1413 static struct soc_enum const sub_mbc3_lvl_det_mode_enum =
1414 SOC_ENUM_SINGLE(R_SUBMBCCTL, FB_SUBMBCCTL_LVLMODE3,
1415 ARRAY_SIZE(lvl_mode_txt), lvl_mode_txt);
1416
1417 static struct soc_enum const sub_mbc3_win_sel_enum =
1418 SOC_ENUM_SINGLE(R_SUBMBCCTL, FB_SUBMBCCTL_WINSEL3,
1419 ARRAY_SIZE(win_sel_txt), win_sel_txt);
1420
1421 static struct soc_enum const sub_mbc2_lvl_det_mode_enum =
1422 SOC_ENUM_SINGLE(R_SUBMBCCTL, FB_SUBMBCCTL_LVLMODE2,
1423 ARRAY_SIZE(lvl_mode_txt), lvl_mode_txt);
1424
1425 static struct soc_enum const sub_mbc2_win_sel_enum =
1426 SOC_ENUM_SINGLE(R_SUBMBCCTL, FB_SUBMBCCTL_WINSEL2,
1427 ARRAY_SIZE(win_sel_txt), win_sel_txt);
1428
1429 static struct soc_enum const sub_mbc1_lvl_det_mode_enum =
1430 SOC_ENUM_SINGLE(R_SUBMBCCTL, FB_SUBMBCCTL_LVLMODE1,
1431 ARRAY_SIZE(lvl_mode_txt), lvl_mode_txt);
1432
1433 static struct soc_enum const sub_mbc1_win_sel_enum =
1434 SOC_ENUM_SINGLE(R_SUBMBCCTL, FB_SUBMBCCTL_WINSEL1,
1435 ARRAY_SIZE(win_sel_txt), win_sel_txt);
1436
1437 /* R_SUBMBCMUG1 PG 5 ADDR 0x0C */
1438 static struct soc_enum const sub_mbc1_phase_pol_enum =
1439 SOC_ENUM_SINGLE(R_SUBMBCMUG1, FB_SUBMBCMUG_PHASE,
1440 ARRAY_SIZE(pol_txt), pol_txt);
1441
1442 /* R_SUBMBCRAT1 PG 5 ADDR 0x0E */
1443 static struct soc_enum const sub_mbc1_comp_rat_enum =
1444 SOC_ENUM_SINGLE(R_SUBMBCRAT1, FB_SUBMBCRAT_RATIO,
1445 ARRAY_SIZE(comp_rat_txt), comp_rat_txt);
1446
1447 /* R_SUBMBCMUG2 PG 5 ADDR 0x13 */
1448 static struct soc_enum const sub_mbc2_phase_pol_enum =
1449 SOC_ENUM_SINGLE(R_SUBMBCMUG2, FB_SUBMBCMUG_PHASE,
1450 ARRAY_SIZE(pol_txt), pol_txt);
1451
1452 /* R_SUBMBCRAT2 PG 5 ADDR 0x15 */
1453 static struct soc_enum const sub_mbc2_comp_rat_enum =
1454 SOC_ENUM_SINGLE(R_SUBMBCRAT2, FB_SUBMBCRAT_RATIO,
1455 ARRAY_SIZE(comp_rat_txt), comp_rat_txt);
1456
1457 /* R_SUBMBCMUG3 PG 5 ADDR 0x1A */
1458 static struct soc_enum const sub_mbc3_phase_pol_enum =
1459 SOC_ENUM_SINGLE(R_SUBMBCMUG3, FB_SUBMBCMUG_PHASE,
1460 ARRAY_SIZE(pol_txt), pol_txt);
1461
1462 /* R_SUBMBCRAT3 PG 5 ADDR 0x1C */
1463 static struct soc_enum const sub_mbc3_comp_rat_enum =
1464 SOC_ENUM_SINGLE(R_SUBMBCRAT3, FB_SUBMBCRAT_RATIO,
1465 ARRAY_SIZE(comp_rat_txt), comp_rat_txt);
1466
1467 /* R_SUBCLECTL PG 5 ADDR 0x21 */
1468 static struct soc_enum const sub_cle_lvl_mode_enum =
1469 SOC_ENUM_SINGLE(R_SUBCLECTL, FB_SUBCLECTL_LVLMODE,
1470 ARRAY_SIZE(lvl_mode_txt), lvl_mode_txt);
1471 static struct soc_enum const sub_cle_win_sel_enum =
1472 SOC_ENUM_SINGLE(R_SUBCLECTL, FB_SUBCLECTL_WINSEL,
1473 ARRAY_SIZE(win_sel_txt), win_sel_txt);
1474
1475 /* R_SUBCOMPRAT PG 5 ADDR 0x24 */
1476 static struct soc_enum const sub_comp_rat_enum =
1477 SOC_ENUM_SINGLE(R_SUBCOMPRAT, FB_SUBCOMPRAT_RATIO,
1478 ARRAY_SIZE(comp_rat_txt), comp_rat_txt);
1479
1480 /* R_SUBEXPRAT PG 5 ADDR 0x30 */
1481 static struct soc_enum const sub_exp_rat_enum =
1482 SOC_ENUM_SINGLE(R_SUBEXPRAT, FB_SUBEXPRAT_RATIO,
1483 ARRAY_SIZE(exp_rat_txt), exp_rat_txt);
1484
1485 static int bytes_info_ext(struct snd_kcontrol *kcontrol,
1486 struct snd_ctl_elem_info *ucontrol)
1487 {
1488 struct coeff_ram_ctl *ctl =
1489 (struct coeff_ram_ctl *)kcontrol->private_value;
1490 struct soc_bytes_ext *params = &ctl->bytes_ext;
1491
1492 ucontrol->type = SNDRV_CTL_ELEM_TYPE_BYTES;
1493 ucontrol->count = params->max;
1494
1495 return 0;
1496 }
1497
1498 /* CH 0_1 Input Mux */
1499 static char const * const ch_0_1_mux_txt[] = {"DAI 1", "TDM 0_1"};
1500
1501 static struct soc_enum const ch_0_1_mux_enum =
1502 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0,
1503 ARRAY_SIZE(ch_0_1_mux_txt), ch_0_1_mux_txt);
1504
1505 static struct snd_kcontrol_new const ch_0_1_mux_dapm_enum =
1506 SOC_DAPM_ENUM("CH 0_1 Input Mux", ch_0_1_mux_enum);
1507
1508 /* CH 2_3 Input Mux */
1509 static char const * const ch_2_3_mux_txt[] = {"DAI 2", "TDM 2_3"};
1510
1511 static struct soc_enum const ch_2_3_mux_enum =
1512 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0,
1513 ARRAY_SIZE(ch_2_3_mux_txt), ch_2_3_mux_txt);
1514
1515 static struct snd_kcontrol_new const ch_2_3_mux_dapm_enum =
1516 SOC_DAPM_ENUM("CH 2_3 Input Mux", ch_2_3_mux_enum);
1517
1518 /* CH 4_5 Input Mux */
1519 static char const * const ch_4_5_mux_txt[] = {"DAI 3", "TDM 4_5"};
1520
1521 static struct soc_enum const ch_4_5_mux_enum =
1522 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0,
1523 ARRAY_SIZE(ch_4_5_mux_txt), ch_4_5_mux_txt);
1524
1525 static struct snd_kcontrol_new const ch_4_5_mux_dapm_enum =
1526 SOC_DAPM_ENUM("CH 4_5 Input Mux", ch_4_5_mux_enum);
1527
1528 #define COEFF_RAM_CTL(xname, xcount, xaddr) \
1529 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1530 .info = bytes_info_ext, \
1531 .get = coeff_ram_get, .put = coeff_ram_put, \
1532 .private_value = (unsigned long)&(struct coeff_ram_ctl) { \
1533 .addr = xaddr, \
1534 .bytes_ext = {.max = xcount, }, \
1535 } \
1536 }
1537
1538 static struct snd_kcontrol_new const tscs454_snd_controls[] = {
1539 /* R_PLLCTL PG 0 ADDR 0x15 */
1540 SOC_ENUM("PLL BCLK Input", bclk_sel_enum),
1541 /* R_ISRC PG 0 ADDR 0x16 */
1542 SOC_ENUM("Internal Rate", isrc_br_enum),
1543 SOC_ENUM("Internal Rate Multiple", isrc_bm_enum),
1544 /* R_SCLKCTL PG 0 ADDR 0x18 */
1545 SOC_ENUM("ADC Modular Rate", adc_modular_rate_enum),
1546 SOC_ENUM("DAC Modular Rate", dac_modular_rate_enum),
1547 /* R_ASRC PG 0 ADDR 0x28 */
1548 SOC_SINGLE("ASRC Out High Bandwidth Switch",
1549 R_ASRC, FB_ASRC_ASRCOBW, 1, 0),
1550 SOC_SINGLE("ASRC In High Bandwidth Switch",
1551 R_ASRC, FB_ASRC_ASRCIBW, 1, 0),
1552 /* R_I2SIDCTL PG 0 ADDR 0x38 */
1553 SOC_ENUM("I2S 1 Data In Control", data_in_ctrl_enums[0]),
1554 SOC_ENUM("I2S 2 Data In Control", data_in_ctrl_enums[1]),
1555 SOC_ENUM("I2S 3 Data In Control", data_in_ctrl_enums[2]),
1556 /* R_I2SODCTL PG 0 ADDR 0x39 */
1557 SOC_ENUM("I2S 1 Data Out Control", data_out_ctrl_enums[0]),
1558 SOC_ENUM("I2S 2 Data Out Control", data_out_ctrl_enums[1]),
1559 SOC_ENUM("I2S 3 Data Out Control", data_out_ctrl_enums[2]),
1560 /* R_AUDIOMUX1 PG 0 ADDR 0x3A */
1561 SOC_ENUM("ASRC In", asrc_in_mux_enum),
1562 /* R_AUDIOMUX2 PG 0 ADDR 0x3B */
1563 SOC_ENUM("ASRC Out", asrc_out_mux_enum),
1564 /* R_HSDCTL1 PG 1 ADDR 0x01 */
1565 SOC_ENUM("Headphone Jack Type", hp_jack_type_enum),
1566 SOC_ENUM("Headset Detection Polarity", hs_det_pol_enum),
1567 SOC_SINGLE("Headphone Detection Switch",
1568 R_HSDCTL1, FB_HSDCTL1_HPID_EN, 1, 0),
1569 SOC_SINGLE("Headset OMTP/CTIA Switch",
1570 R_HSDCTL1, FB_HSDCTL1_GBLHS_EN, 1, 0),
1571 /* R_HSDCTL1 PG 1 ADDR 0x02 */
1572 SOC_ENUM("Headset Mic Bias Force", hs_mic_bias_force_enum),
1573 SOC_SINGLE("Manual Mic Bias Switch",
1574 R_HSDCTL2, FB_HSDCTL2_MB1MODE, 1, 0),
1575 SOC_SINGLE("Ring/Sleeve Auto Switch",
1576 R_HSDCTL2, FB_HSDCTL2_SWMODE, 1, 0),
1577 SOC_ENUM("Manual Mode Plug Type", plug_type_force_enum),
1578 /* R_CH0AIC PG 1 ADDR 0x06 */
1579 SOC_SINGLE_TLV("Input Boost Channel 0 Volume", R_CH0AIC,
1580 FB_CHAIC_MICBST, 0x3, 0, in_bst_vol_tlv_arr),
1581 /* R_CH1AIC PG 1 ADDR 0x07 */
1582 SOC_SINGLE_TLV("Input Boost Channel 1 Volume", R_CH1AIC,
1583 FB_CHAIC_MICBST, 0x3, 0, in_bst_vol_tlv_arr),
1584 /* R_CH2AIC PG 1 ADDR 0x08 */
1585 SOC_SINGLE_TLV("Input Boost Channel 2 Volume", R_CH2AIC,
1586 FB_CHAIC_MICBST, 0x3, 0, in_bst_vol_tlv_arr),
1587 /* R_CH3AIC PG 1 ADDR 0x09 */
1588 SOC_SINGLE_TLV("Input Boost Channel 3 Volume", R_CH3AIC,
1589 FB_CHAIC_MICBST, 0x3, 0, in_bst_vol_tlv_arr),
1590 /* R_ICTL0 PG 1 ADDR 0x0A */
1591 SOC_ENUM("Input Channel 1 Polarity", in_pol_ch1_enum),
1592 SOC_ENUM("Input Channel 0 Polarity", in_pol_ch0_enum),
1593 SOC_ENUM("Input Processor Channel 0/1 Operation",
1594 in_proc_ch01_sel_enum),
1595 SOC_SINGLE("Input Channel 1 Mute Switch",
1596 R_ICTL0, FB_ICTL0_IN1MUTE, 1, 0),
1597 SOC_SINGLE("Input Channel 0 Mute Switch",
1598 R_ICTL0, FB_ICTL0_IN0MUTE, 1, 0),
1599 SOC_SINGLE("Input Channel 1 HPF Disable Switch",
1600 R_ICTL0, FB_ICTL0_IN1HP, 1, 0),
1601 SOC_SINGLE("Input Channel 0 HPF Disable Switch",
1602 R_ICTL0, FB_ICTL0_IN0HP, 1, 0),
1603 /* R_ICTL1 PG 1 ADDR 0x0B */
1604 SOC_ENUM("Input Channel 3 Polarity", in_pol_ch3_enum),
1605 SOC_ENUM("Input Channel 2 Polarity", in_pol_ch2_enum),
1606 SOC_ENUM("Input Processor Channel 2/3 Operation",
1607 in_proc_ch23_sel_enum),
1608 SOC_SINGLE("Input Channel 3 Mute Switch",
1609 R_ICTL1, FB_ICTL1_IN3MUTE, 1, 0),
1610 SOC_SINGLE("Input Channel 2 Mute Switch",
1611 R_ICTL1, FB_ICTL1_IN2MUTE, 1, 0),
1612 SOC_SINGLE("Input Channel 3 HPF Disable Switch",
1613 R_ICTL1, FB_ICTL1_IN3HP, 1, 0),
1614 SOC_SINGLE("Input Channel 2 HPF Disable Switch",
1615 R_ICTL1, FB_ICTL1_IN2HP, 1, 0),
1616 /* R_MICBIAS PG 1 ADDR 0x0C */
1617 SOC_ENUM("Mic Bias 2 Voltage", mic_bias_2_enum),
1618 SOC_ENUM("Mic Bias 1 Voltage", mic_bias_1_enum),
1619 /* R_PGACTL0 PG 1 ADDR 0x0D */
1620 SOC_SINGLE("Input Channel 0 PGA Mute Switch",
1621 R_PGACTL0, FB_PGACTL_PGAMUTE, 1, 0),
1622 SOC_SINGLE_TLV("Input Channel 0 PGA Volume", R_PGACTL0,
1623 FB_PGACTL_PGAVOL,
1624 FM_PGACTL_PGAVOL, 0, in_pga_vol_tlv_arr),
1625 /* R_PGACTL1 PG 1 ADDR 0x0E */
1626 SOC_SINGLE("Input Channel 1 PGA Mute Switch",
1627 R_PGACTL1, FB_PGACTL_PGAMUTE, 1, 0),
1628 SOC_SINGLE_TLV("Input Channel 1 PGA Volume", R_PGACTL1,
1629 FB_PGACTL_PGAVOL,
1630 FM_PGACTL_PGAVOL, 0, in_pga_vol_tlv_arr),
1631 /* R_PGACTL2 PG 1 ADDR 0x0F */
1632 SOC_SINGLE("Input Channel 2 PGA Mute Switch",
1633 R_PGACTL2, FB_PGACTL_PGAMUTE, 1, 0),
1634 SOC_SINGLE_TLV("Input Channel 2 PGA Volume", R_PGACTL2,
1635 FB_PGACTL_PGAVOL,
1636 FM_PGACTL_PGAVOL, 0, in_pga_vol_tlv_arr),
1637 /* R_PGACTL3 PG 1 ADDR 0x10 */
1638 SOC_SINGLE("Input Channel 3 PGA Mute Switch",
1639 R_PGACTL3, FB_PGACTL_PGAMUTE, 1, 0),
1640 SOC_SINGLE_TLV("Input Channel 3 PGA Volume", R_PGACTL3,
1641 FB_PGACTL_PGAVOL,
1642 FM_PGACTL_PGAVOL, 0, in_pga_vol_tlv_arr),
1643 /* R_ICH0VOL PG 1 ADDR 0x12 */
1644 SOC_SINGLE_TLV("Input Channel 0 Volume", R_ICH0VOL,
1645 FB_ICHVOL_ICHVOL, FM_ICHVOL_ICHVOL, 0, in_vol_tlv_arr),
1646 /* R_ICH1VOL PG 1 ADDR 0x13 */
1647 SOC_SINGLE_TLV("Input Channel 1 Volume", R_ICH1VOL,
1648 FB_ICHVOL_ICHVOL, FM_ICHVOL_ICHVOL, 0, in_vol_tlv_arr),
1649 /* R_ICH2VOL PG 1 ADDR 0x14 */
1650 SOC_SINGLE_TLV("Input Channel 2 Volume", R_ICH2VOL,
1651 FB_ICHVOL_ICHVOL, FM_ICHVOL_ICHVOL, 0, in_vol_tlv_arr),
1652 /* R_ICH3VOL PG 1 ADDR 0x15 */
1653 SOC_SINGLE_TLV("Input Channel 3 Volume", R_ICH3VOL,
1654 FB_ICHVOL_ICHVOL, FM_ICHVOL_ICHVOL, 0, in_vol_tlv_arr),
1655 /* R_ASRCILVOL PG 1 ADDR 0x16 */
1656 SOC_SINGLE_TLV("ASRC Input Left Volume", R_ASRCILVOL,
1657 FB_ASRCILVOL_ASRCILVOL, FM_ASRCILVOL_ASRCILVOL,
1658 0, asrc_vol_tlv_arr),
1659 /* R_ASRCIRVOL PG 1 ADDR 0x17 */
1660 SOC_SINGLE_TLV("ASRC Input Right Volume", R_ASRCIRVOL,
1661 FB_ASRCIRVOL_ASRCIRVOL, FM_ASRCIRVOL_ASRCIRVOL,
1662 0, asrc_vol_tlv_arr),
1663 /* R_ASRCOLVOL PG 1 ADDR 0x18 */
1664 SOC_SINGLE_TLV("ASRC Output Left Volume", R_ASRCOLVOL,
1665 FB_ASRCOLVOL_ASRCOLVOL, FM_ASRCOLVOL_ASRCOLVOL,
1666 0, asrc_vol_tlv_arr),
1667 /* R_ASRCORVOL PG 1 ADDR 0x19 */
1668 SOC_SINGLE_TLV("ASRC Output Right Volume", R_ASRCORVOL,
1669 FB_ASRCORVOL_ASRCOLVOL, FM_ASRCORVOL_ASRCOLVOL,
1670 0, asrc_vol_tlv_arr),
1671 /* R_IVOLCTLU PG 1 ADDR 0x1C */
1672 /* R_ALCCTL0 PG 1 ADDR 0x1D */
1673 SOC_ENUM("ALC Mode", alc_mode_enum),
1674 SOC_ENUM("ALC Reference", alc_ref_enum),
1675 SOC_SINGLE("Input Channel 3 ALC Switch",
1676 R_ALCCTL0, FB_ALCCTL0_ALCEN3, 1, 0),
1677 SOC_SINGLE("Input Channel 2 ALC Switch",
1678 R_ALCCTL0, FB_ALCCTL0_ALCEN2, 1, 0),
1679 SOC_SINGLE("Input Channel 1 ALC Switch",
1680 R_ALCCTL0, FB_ALCCTL0_ALCEN1, 1, 0),
1681 SOC_SINGLE("Input Channel 0 ALC Switch",
1682 R_ALCCTL0, FB_ALCCTL0_ALCEN0, 1, 0),
1683 /* R_ALCCTL1 PG 1 ADDR 0x1E */
1684 SOC_SINGLE_TLV("ALC Max Gain Volume", R_ALCCTL1,
1685 FB_ALCCTL1_MAXGAIN, FM_ALCCTL1_MAXGAIN,
1686 0, alc_max_gain_tlv_arr),
1687 SOC_SINGLE_TLV("ALC Target Volume", R_ALCCTL1,
1688 FB_ALCCTL1_ALCL, FM_ALCCTL1_ALCL,
1689 0, alc_target_tlv_arr),
1690 /* R_ALCCTL2 PG 1 ADDR 0x1F */
1691 SOC_SINGLE("ALC Zero Cross Switch",
1692 R_ALCCTL2, FB_ALCCTL2_ALCZC, 1, 0),
1693 SOC_SINGLE_TLV("ALC Min Gain Volume", R_ALCCTL2,
1694 FB_ALCCTL2_MINGAIN, FM_ALCCTL2_MINGAIN,
1695 0, alc_min_gain_tlv_arr),
1696 SOC_SINGLE_RANGE("ALC Hold", R_ALCCTL2,
1697 FB_ALCCTL2_HLD, 0, FM_ALCCTL2_HLD, 0),
1698 /* R_ALCCTL3 PG 1 ADDR 0x20 */
1699 SOC_SINGLE_RANGE("ALC Decay", R_ALCCTL3,
1700 FB_ALCCTL3_DCY, 0, FM_ALCCTL3_DCY, 0),
1701 SOC_SINGLE_RANGE("ALC Attack", R_ALCCTL3,
1702 FB_ALCCTL3_ATK, 0, FM_ALCCTL3_ATK, 0),
1703 /* R_NGATE PG 1 ADDR 0x21 */
1704 SOC_SINGLE_TLV("Noise Gate Threshold Volume", R_NGATE,
1705 FB_NGATE_NGTH, FM_NGATE_NGTH, 0, ngth_tlv_arr),
1706 SOC_ENUM("Noise Gate Type", ngate_type_enum),
1707 SOC_SINGLE("Noise Gate Switch", R_NGATE, FB_NGATE_NGAT, 1, 0),
1708 /* R_DMICCTL PG 1 ADDR 0x22 */
1709 SOC_SINGLE("Digital Mic 2 Switch", R_DMICCTL, FB_DMICCTL_DMIC2EN, 1, 0),
1710 SOC_SINGLE("Digital Mic 1 Switch", R_DMICCTL, FB_DMICCTL_DMIC1EN, 1, 0),
1711 SOC_ENUM("Digital Mic Mono Select", dmic_mono_sel_enum),
1712 /* R_DACCTL PG 2 ADDR 0x01 */
1713 SOC_ENUM("DAC Polarity Left", dac_pol_r_enum),
1714 SOC_ENUM("DAC Polarity Right", dac_pol_l_enum),
1715 SOC_ENUM("DAC Dither", dac_dith_enum),
1716 SOC_SINGLE("DAC Mute Switch", R_DACCTL, FB_DACCTL_DACMUTE, 1, 0),
1717 SOC_SINGLE("DAC De-Emphasis Switch", R_DACCTL, FB_DACCTL_DACDEM, 1, 0),
1718 /* R_SPKCTL PG 2 ADDR 0x02 */
1719 SOC_ENUM("Speaker Polarity Right", spk_pol_r_enum),
1720 SOC_ENUM("Speaker Polarity Left", spk_pol_l_enum),
1721 SOC_SINGLE("Speaker Mute Switch", R_SPKCTL, FB_SPKCTL_SPKMUTE, 1, 0),
1722 SOC_SINGLE("Speaker De-Emphasis Switch",
1723 R_SPKCTL, FB_SPKCTL_SPKDEM, 1, 0),
1724 /* R_SUBCTL PG 2 ADDR 0x03 */
1725 SOC_ENUM("Sub Polarity", sub_pol_enum),
1726 SOC_SINGLE("SUB Mute Switch", R_SUBCTL, FB_SUBCTL_SUBMUTE, 1, 0),
1727 SOC_SINGLE("Sub De-Emphasis Switch", R_SUBCTL, FB_SUBCTL_SUBDEM, 1, 0),
1728 /* R_DCCTL PG 2 ADDR 0x04 */
1729 SOC_SINGLE("Sub DC Removal Switch", R_DCCTL, FB_DCCTL_SUBDCBYP, 1, 1),
1730 SOC_SINGLE("DAC DC Removal Switch", R_DCCTL, FB_DCCTL_DACDCBYP, 1, 1),
1731 SOC_SINGLE("Speaker DC Removal Switch",
1732 R_DCCTL, FB_DCCTL_SPKDCBYP, 1, 1),
1733 SOC_SINGLE("DC Removal Coefficient Switch", R_DCCTL, FB_DCCTL_DCCOEFSEL,
1734 FM_DCCTL_DCCOEFSEL, 0),
1735 /* R_OVOLCTLU PG 2 ADDR 0x06 */
1736 SOC_SINGLE("Output Fade Switch", R_OVOLCTLU, FB_OVOLCTLU_OFADE, 1, 0),
1737 /* R_MVOLL PG 2 ADDR 0x08 */
1738 /* R_MVOLR PG 2 ADDR 0x09 */
1739 SOC_DOUBLE_R_TLV("Master Volume", R_MVOLL, R_MVOLR,
1740 FB_MVOLL_MVOL_L, FM_MVOLL_MVOL_L, 0, mvol_tlv_arr),
1741 /* R_HPVOLL PG 2 ADDR 0x0A */
1742 /* R_HPVOLR PG 2 ADDR 0x0B */
1743 SOC_DOUBLE_R_TLV("Headphone Volume", R_HPVOLL, R_HPVOLR,
1744 FB_HPVOLL_HPVOL_L, FM_HPVOLL_HPVOL_L, 0,
1745 hp_vol_tlv_arr),
1746 /* R_SPKVOLL PG 2 ADDR 0x0C */
1747 /* R_SPKVOLR PG 2 ADDR 0x0D */
1748 SOC_DOUBLE_R_TLV("Speaker Volume", R_SPKVOLL, R_SPKVOLR,
1749 FB_SPKVOLL_SPKVOL_L, FM_SPKVOLL_SPKVOL_L, 0,
1750 spk_vol_tlv_arr),
1751 /* R_SUBVOL PG 2 ADDR 0x10 */
1752 SOC_SINGLE_TLV("Sub Volume", R_SUBVOL,
1753 FB_SUBVOL_SUBVOL, FM_SUBVOL_SUBVOL, 0, spk_vol_tlv_arr),
1754 /* R_SPKEQFILT PG 3 ADDR 0x01 */
1755 SOC_SINGLE("Speaker EQ 2 Switch",
1756 R_SPKEQFILT, FB_SPKEQFILT_EQ2EN, 1, 0),
1757 SOC_ENUM("Speaker EQ 2 Band", spk_eq_enums[0]),
1758 SOC_SINGLE("Speaker EQ 1 Switch",
1759 R_SPKEQFILT, FB_SPKEQFILT_EQ1EN, 1, 0),
1760 SOC_ENUM("Speaker EQ 1 Band", spk_eq_enums[1]),
1761 /* R_SPKMBCEN PG 3 ADDR 0x0A */
1762 SOC_SINGLE("Speaker MBC 3 Switch",
1763 R_SPKMBCEN, FB_SPKMBCEN_MBCEN3, 1, 0),
1764 SOC_SINGLE("Speaker MBC 2 Switch",
1765 R_SPKMBCEN, FB_SPKMBCEN_MBCEN2, 1, 0),
1766 SOC_SINGLE("Speaker MBC 1 Switch",
1767 R_SPKMBCEN, FB_SPKMBCEN_MBCEN1, 1, 0),
1768 /* R_SPKMBCCTL PG 3 ADDR 0x0B */
1769 SOC_ENUM("Speaker MBC 3 Mode", spk_mbc3_lvl_det_mode_enum),
1770 SOC_ENUM("Speaker MBC 3 Window", spk_mbc3_win_sel_enum),
1771 SOC_ENUM("Speaker MBC 2 Mode", spk_mbc2_lvl_det_mode_enum),
1772 SOC_ENUM("Speaker MBC 2 Window", spk_mbc2_win_sel_enum),
1773 SOC_ENUM("Speaker MBC 1 Mode", spk_mbc1_lvl_det_mode_enum),
1774 SOC_ENUM("Speaker MBC 1 Window", spk_mbc1_win_sel_enum),
1775 /* R_SPKMBCMUG1 PG 3 ADDR 0x0C */
1776 SOC_ENUM("Speaker MBC 1 Phase Polarity", spk_mbc1_phase_pol_enum),
1777 SOC_SINGLE_TLV("Speaker MBC1 Make-Up Gain Volume", R_SPKMBCMUG1,
1778 FB_SPKMBCMUG_MUGAIN, FM_SPKMBCMUG_MUGAIN,
1779 0, mbc_mug_tlv_arr),
1780 /* R_SPKMBCTHR1 PG 3 ADDR 0x0D */
1781 SOC_SINGLE_TLV("Speaker MBC 1 Compressor Threshold Volume",
1782 R_SPKMBCTHR1, FB_SPKMBCTHR_THRESH, FM_SPKMBCTHR_THRESH,
1783 0, thr_tlv_arr),
1784 /* R_SPKMBCRAT1 PG 3 ADDR 0x0E */
1785 SOC_ENUM("Speaker MBC 1 Compressor Ratio", spk_mbc1_comp_rat_enum),
1786 /* R_SPKMBCATK1L PG 3 ADDR 0x0F */
1787 /* R_SPKMBCATK1H PG 3 ADDR 0x10 */
1788 SND_SOC_BYTES("Speaker MBC 1 Attack", R_SPKMBCATK1L, 2),
1789 /* R_SPKMBCREL1L PG 3 ADDR 0x11 */
1790 /* R_SPKMBCREL1H PG 3 ADDR 0x12 */
1791 SND_SOC_BYTES("Speaker MBC 1 Release", R_SPKMBCREL1L, 2),
1792 /* R_SPKMBCMUG2 PG 3 ADDR 0x13 */
1793 SOC_ENUM("Speaker MBC 2 Phase Polarity", spk_mbc2_phase_pol_enum),
1794 SOC_SINGLE_TLV("Speaker MBC2 Make-Up Gain Volume", R_SPKMBCMUG2,
1795 FB_SPKMBCMUG_MUGAIN, FM_SPKMBCMUG_MUGAIN,
1796 0, mbc_mug_tlv_arr),
1797 /* R_SPKMBCTHR2 PG 3 ADDR 0x14 */
1798 SOC_SINGLE_TLV("Speaker MBC 2 Compressor Threshold Volume",
1799 R_SPKMBCTHR2, FB_SPKMBCTHR_THRESH, FM_SPKMBCTHR_THRESH,
1800 0, thr_tlv_arr),
1801 /* R_SPKMBCRAT2 PG 3 ADDR 0x15 */
1802 SOC_ENUM("Speaker MBC 2 Compressor Ratio", spk_mbc2_comp_rat_enum),
1803 /* R_SPKMBCATK2L PG 3 ADDR 0x16 */
1804 /* R_SPKMBCATK2H PG 3 ADDR 0x17 */
1805 SND_SOC_BYTES("Speaker MBC 2 Attack", R_SPKMBCATK2L, 2),
1806 /* R_SPKMBCREL2L PG 3 ADDR 0x18 */
1807 /* R_SPKMBCREL2H PG 3 ADDR 0x19 */
1808 SND_SOC_BYTES("Speaker MBC 2 Release", R_SPKMBCREL2L, 2),
1809 /* R_SPKMBCMUG3 PG 3 ADDR 0x1A */
1810 SOC_ENUM("Speaker MBC 3 Phase Polarity", spk_mbc3_phase_pol_enum),
1811 SOC_SINGLE_TLV("Speaker MBC 3 Make-Up Gain Volume", R_SPKMBCMUG3,
1812 FB_SPKMBCMUG_MUGAIN, FM_SPKMBCMUG_MUGAIN,
1813 0, mbc_mug_tlv_arr),
1814 /* R_SPKMBCTHR3 PG 3 ADDR 0x1B */
1815 SOC_SINGLE_TLV("Speaker MBC 3 Threshold Volume", R_SPKMBCTHR3,
1816 FB_SPKMBCTHR_THRESH, FM_SPKMBCTHR_THRESH,
1817 0, thr_tlv_arr),
1818 /* R_SPKMBCRAT3 PG 3 ADDR 0x1C */
1819 SOC_ENUM("Speaker MBC 3 Compressor Ratio", spk_mbc3_comp_rat_enum),
1820 /* R_SPKMBCATK3L PG 3 ADDR 0x1D */
1821 /* R_SPKMBCATK3H PG 3 ADDR 0x1E */
1822 SND_SOC_BYTES("Speaker MBC 3 Attack", R_SPKMBCATK3L, 3),
1823 /* R_SPKMBCREL3L PG 3 ADDR 0x1F */
1824 /* R_SPKMBCREL3H PG 3 ADDR 0x20 */
1825 SND_SOC_BYTES("Speaker MBC 3 Release", R_SPKMBCREL3L, 3),
1826 /* R_SPKCLECTL PG 3 ADDR 0x21 */
1827 SOC_ENUM("Speaker CLE Level Mode", spk_cle_lvl_mode_enum),
1828 SOC_ENUM("Speaker CLE Window", spk_cle_win_sel_enum),
1829 SOC_SINGLE("Speaker CLE Expander Switch",
1830 R_SPKCLECTL, FB_SPKCLECTL_EXPEN, 1, 0),
1831 SOC_SINGLE("Speaker CLE Limiter Switch",
1832 R_SPKCLECTL, FB_SPKCLECTL_LIMEN, 1, 0),
1833 SOC_SINGLE("Speaker CLE Compressor Switch",
1834 R_SPKCLECTL, FB_SPKCLECTL_COMPEN, 1, 0),
1835 /* R_SPKCLEMUG PG 3 ADDR 0x22 */
1836 SOC_SINGLE_TLV("Speaker CLE Make-Up Gain Volume", R_SPKCLEMUG,
1837 FB_SPKCLEMUG_MUGAIN, FM_SPKCLEMUG_MUGAIN,
1838 0, cle_mug_tlv_arr),
1839 /* R_SPKCOMPTHR PG 3 ADDR 0x23 */
1840 SOC_SINGLE_TLV("Speaker Compressor Threshold Volume", R_SPKCOMPTHR,
1841 FB_SPKCOMPTHR_THRESH, FM_SPKCOMPTHR_THRESH,
1842 0, thr_tlv_arr),
1843 /* R_SPKCOMPRAT PG 3 ADDR 0x24 */
1844 SOC_ENUM("Speaker Compressor Ratio", spk_comp_rat_enum),
1845 /* R_SPKCOMPATKL PG 3 ADDR 0x25 */
1846 /* R_SPKCOMPATKH PG 3 ADDR 0x26 */
1847 SND_SOC_BYTES("Speaker Compressor Attack", R_SPKCOMPATKL, 2),
1848 /* R_SPKCOMPRELL PG 3 ADDR 0x27 */
1849 /* R_SPKCOMPRELH PG 3 ADDR 0x28 */
1850 SND_SOC_BYTES("Speaker Compressor Release", R_SPKCOMPRELL, 2),
1851 /* R_SPKLIMTHR PG 3 ADDR 0x29 */
1852 SOC_SINGLE_TLV("Speaker Limiter Threshold Volume", R_SPKLIMTHR,
1853 FB_SPKLIMTHR_THRESH, FM_SPKLIMTHR_THRESH,
1854 0, thr_tlv_arr),
1855 /* R_SPKLIMTGT PG 3 ADDR 0x2A */
1856 SOC_SINGLE_TLV("Speaker Limiter Target Volume", R_SPKLIMTGT,
1857 FB_SPKLIMTGT_TARGET, FM_SPKLIMTGT_TARGET,
1858 0, thr_tlv_arr),
1859 /* R_SPKLIMATKL PG 3 ADDR 0x2B */
1860 /* R_SPKLIMATKH PG 3 ADDR 0x2C */
1861 SND_SOC_BYTES("Speaker Limiter Attack", R_SPKLIMATKL, 2),
1862 /* R_SPKLIMRELL PG 3 ADDR 0x2D */
1863 /* R_SPKLIMRELR PG 3 ADDR 0x2E */
1864 SND_SOC_BYTES("Speaker Limiter Release", R_SPKLIMRELL, 2),
1865 /* R_SPKEXPTHR PG 3 ADDR 0x2F */
1866 SOC_SINGLE_TLV("Speaker Expander Threshold Volume", R_SPKEXPTHR,
1867 FB_SPKEXPTHR_THRESH, FM_SPKEXPTHR_THRESH,
1868 0, thr_tlv_arr),
1869 /* R_SPKEXPRAT PG 3 ADDR 0x30 */
1870 SOC_ENUM("Speaker Expander Ratio", spk_exp_rat_enum),
1871 /* R_SPKEXPATKL PG 3 ADDR 0x31 */
1872 /* R_SPKEXPATKR PG 3 ADDR 0x32 */
1873 SND_SOC_BYTES("Speaker Expander Attack", R_SPKEXPATKL, 2),
1874 /* R_SPKEXPRELL PG 3 ADDR 0x33 */
1875 /* R_SPKEXPRELR PG 3 ADDR 0x34 */
1876 SND_SOC_BYTES("Speaker Expander Release", R_SPKEXPRELL, 2),
1877 /* R_SPKFXCTL PG 3 ADDR 0x35 */
1878 SOC_SINGLE("Speaker 3D Switch", R_SPKFXCTL, FB_SPKFXCTL_3DEN, 1, 0),
1879 SOC_SINGLE("Speaker Treble Enhancement Switch",
1880 R_SPKFXCTL, FB_SPKFXCTL_TEEN, 1, 0),
1881 SOC_SINGLE("Speaker Treble NLF Switch",
1882 R_SPKFXCTL, FB_SPKFXCTL_TNLFBYP, 1, 1),
1883 SOC_SINGLE("Speaker Bass Enhancement Switch",
1884 R_SPKFXCTL, FB_SPKFXCTL_BEEN, 1, 0),
1885 SOC_SINGLE("Speaker Bass NLF Switch",
1886 R_SPKFXCTL, FB_SPKFXCTL_BNLFBYP, 1, 1),
1887 /* R_DACEQFILT PG 4 ADDR 0x01 */
1888 SOC_SINGLE("DAC EQ 2 Switch",
1889 R_DACEQFILT, FB_DACEQFILT_EQ2EN, 1, 0),
1890 SOC_ENUM("DAC EQ 2 Band", dac_eq_enums[0]),
1891 SOC_SINGLE("DAC EQ 1 Switch", R_DACEQFILT, FB_DACEQFILT_EQ1EN, 1, 0),
1892 SOC_ENUM("DAC EQ 1 Band", dac_eq_enums[1]),
1893 /* R_DACMBCEN PG 4 ADDR 0x0A */
1894 SOC_SINGLE("DAC MBC 3 Switch", R_DACMBCEN, FB_DACMBCEN_MBCEN3, 1, 0),
1895 SOC_SINGLE("DAC MBC 2 Switch", R_DACMBCEN, FB_DACMBCEN_MBCEN2, 1, 0),
1896 SOC_SINGLE("DAC MBC 1 Switch", R_DACMBCEN, FB_DACMBCEN_MBCEN1, 1, 0),
1897 /* R_DACMBCCTL PG 4 ADDR 0x0B */
1898 SOC_ENUM("DAC MBC 3 Mode", dac_mbc3_lvl_det_mode_enum),
1899 SOC_ENUM("DAC MBC 3 Window", dac_mbc3_win_sel_enum),
1900 SOC_ENUM("DAC MBC 2 Mode", dac_mbc2_lvl_det_mode_enum),
1901 SOC_ENUM("DAC MBC 2 Window", dac_mbc2_win_sel_enum),
1902 SOC_ENUM("DAC MBC 1 Mode", dac_mbc1_lvl_det_mode_enum),
1903 SOC_ENUM("DAC MBC 1 Window", dac_mbc1_win_sel_enum),
1904 /* R_DACMBCMUG1 PG 4 ADDR 0x0C */
1905 SOC_ENUM("DAC MBC 1 Phase Polarity", dac_mbc1_phase_pol_enum),
1906 SOC_SINGLE_TLV("DAC MBC 1 Make-Up Gain Volume", R_DACMBCMUG1,
1907 FB_DACMBCMUG_MUGAIN, FM_DACMBCMUG_MUGAIN,
1908 0, mbc_mug_tlv_arr),
1909 /* R_DACMBCTHR1 PG 4 ADDR 0x0D */
1910 SOC_SINGLE_TLV("DAC MBC 1 Compressor Threshold Volume", R_DACMBCTHR1,
1911 FB_DACMBCTHR_THRESH, FM_DACMBCTHR_THRESH,
1912 0, thr_tlv_arr),
1913 /* R_DACMBCRAT1 PG 4 ADDR 0x0E */
1914 SOC_ENUM("DAC MBC 1 Compressor Ratio", dac_mbc1_comp_rat_enum),
1915 /* R_DACMBCATK1L PG 4 ADDR 0x0F */
1916 /* R_DACMBCATK1H PG 4 ADDR 0x10 */
1917 SND_SOC_BYTES("DAC MBC 1 Attack", R_DACMBCATK1L, 2),
1918 /* R_DACMBCREL1L PG 4 ADDR 0x11 */
1919 /* R_DACMBCREL1H PG 4 ADDR 0x12 */
1920 SND_SOC_BYTES("DAC MBC 1 Release", R_DACMBCREL1L, 2),
1921 /* R_DACMBCMUG2 PG 4 ADDR 0x13 */
1922 SOC_ENUM("DAC MBC 2 Phase Polarity", dac_mbc2_phase_pol_enum),
1923 SOC_SINGLE_TLV("DAC MBC 2 Make-Up Gain Volume", R_DACMBCMUG2,
1924 FB_DACMBCMUG_MUGAIN, FM_DACMBCMUG_MUGAIN,
1925 0, mbc_mug_tlv_arr),
1926 /* R_DACMBCTHR2 PG 4 ADDR 0x14 */
1927 SOC_SINGLE_TLV("DAC MBC 2 Compressor Threshold Volume", R_DACMBCTHR2,
1928 FB_DACMBCTHR_THRESH, FM_DACMBCTHR_THRESH,
1929 0, thr_tlv_arr),
1930 /* R_DACMBCRAT2 PG 4 ADDR 0x15 */
1931 SOC_ENUM("DAC MBC 2 Compressor Ratio", dac_mbc2_comp_rat_enum),
1932 /* R_DACMBCATK2L PG 4 ADDR 0x16 */
1933 /* R_DACMBCATK2H PG 4 ADDR 0x17 */
1934 SND_SOC_BYTES("DAC MBC 2 Attack", R_DACMBCATK2L, 2),
1935 /* R_DACMBCREL2L PG 4 ADDR 0x18 */
1936 /* R_DACMBCREL2H PG 4 ADDR 0x19 */
1937 SND_SOC_BYTES("DAC MBC 2 Release", R_DACMBCREL2L, 2),
1938 /* R_DACMBCMUG3 PG 4 ADDR 0x1A */
1939 SOC_ENUM("DAC MBC 3 Phase Polarity", dac_mbc3_phase_pol_enum),
1940 SOC_SINGLE_TLV("DAC MBC 3 Make-Up Gain Volume", R_DACMBCMUG3,
1941 FB_DACMBCMUG_MUGAIN, FM_DACMBCMUG_MUGAIN,
1942 0, mbc_mug_tlv_arr),
1943 /* R_DACMBCTHR3 PG 4 ADDR 0x1B */
1944 SOC_SINGLE_TLV("DAC MBC 3 Threshold Volume", R_DACMBCTHR3,
1945 FB_DACMBCTHR_THRESH, FM_DACMBCTHR_THRESH,
1946 0, thr_tlv_arr),
1947 /* R_DACMBCRAT3 PG 4 ADDR 0x1C */
1948 SOC_ENUM("DAC MBC 3 Compressor Ratio", dac_mbc3_comp_rat_enum),
1949 /* R_DACMBCATK3L PG 4 ADDR 0x1D */
1950 /* R_DACMBCATK3H PG 4 ADDR 0x1E */
1951 SND_SOC_BYTES("DAC MBC 3 Attack", R_DACMBCATK3L, 3),
1952 /* R_DACMBCREL3L PG 4 ADDR 0x1F */
1953 /* R_DACMBCREL3H PG 4 ADDR 0x20 */
1954 SND_SOC_BYTES("DAC MBC 3 Release", R_DACMBCREL3L, 3),
1955 /* R_DACCLECTL PG 4 ADDR 0x21 */
1956 SOC_ENUM("DAC CLE Level Mode", dac_cle_lvl_mode_enum),
1957 SOC_ENUM("DAC CLE Window", dac_cle_win_sel_enum),
1958 SOC_SINGLE("DAC CLE Expander Switch",
1959 R_DACCLECTL, FB_DACCLECTL_EXPEN, 1, 0),
1960 SOC_SINGLE("DAC CLE Limiter Switch",
1961 R_DACCLECTL, FB_DACCLECTL_LIMEN, 1, 0),
1962 SOC_SINGLE("DAC CLE Compressor Switch",
1963 R_DACCLECTL, FB_DACCLECTL_COMPEN, 1, 0),
1964 /* R_DACCLEMUG PG 4 ADDR 0x22 */
1965 SOC_SINGLE_TLV("DAC CLE Make-Up Gain Volume", R_DACCLEMUG,
1966 FB_DACCLEMUG_MUGAIN, FM_DACCLEMUG_MUGAIN,
1967 0, cle_mug_tlv_arr),
1968 /* R_DACCOMPTHR PG 4 ADDR 0x23 */
1969 SOC_SINGLE_TLV("DAC Compressor Threshold Volume", R_DACCOMPTHR,
1970 FB_DACCOMPTHR_THRESH, FM_DACCOMPTHR_THRESH,
1971 0, thr_tlv_arr),
1972 /* R_DACCOMPRAT PG 4 ADDR 0x24 */
1973 SOC_ENUM("DAC Compressor Ratio", dac_comp_rat_enum),
1974 /* R_DACCOMPATKL PG 4 ADDR 0x25 */
1975 /* R_DACCOMPATKH PG 4 ADDR 0x26 */
1976 SND_SOC_BYTES("DAC Compressor Attack", R_DACCOMPATKL, 2),
1977 /* R_DACCOMPRELL PG 4 ADDR 0x27 */
1978 /* R_DACCOMPRELH PG 4 ADDR 0x28 */
1979 SND_SOC_BYTES("DAC Compressor Release", R_DACCOMPRELL, 2),
1980 /* R_DACLIMTHR PG 4 ADDR 0x29 */
1981 SOC_SINGLE_TLV("DAC Limiter Threshold Volume", R_DACLIMTHR,
1982 FB_DACLIMTHR_THRESH, FM_DACLIMTHR_THRESH,
1983 0, thr_tlv_arr),
1984 /* R_DACLIMTGT PG 4 ADDR 0x2A */
1985 SOC_SINGLE_TLV("DAC Limiter Target Volume", R_DACLIMTGT,
1986 FB_DACLIMTGT_TARGET, FM_DACLIMTGT_TARGET,
1987 0, thr_tlv_arr),
1988 /* R_DACLIMATKL PG 4 ADDR 0x2B */
1989 /* R_DACLIMATKH PG 4 ADDR 0x2C */
1990 SND_SOC_BYTES("DAC Limiter Attack", R_DACLIMATKL, 2),
1991 /* R_DACLIMRELL PG 4 ADDR 0x2D */
1992 /* R_DACLIMRELR PG 4 ADDR 0x2E */
1993 SND_SOC_BYTES("DAC Limiter Release", R_DACLIMRELL, 2),
1994 /* R_DACEXPTHR PG 4 ADDR 0x2F */
1995 SOC_SINGLE_TLV("DAC Expander Threshold Volume", R_DACEXPTHR,
1996 FB_DACEXPTHR_THRESH, FM_DACEXPTHR_THRESH,
1997 0, thr_tlv_arr),
1998 /* R_DACEXPRAT PG 4 ADDR 0x30 */
1999 SOC_ENUM("DAC Expander Ratio", dac_exp_rat_enum),
2000 /* R_DACEXPATKL PG 4 ADDR 0x31 */
2001 /* R_DACEXPATKR PG 4 ADDR 0x32 */
2002 SND_SOC_BYTES("DAC Expander Attack", R_DACEXPATKL, 2),
2003 /* R_DACEXPRELL PG 4 ADDR 0x33 */
2004 /* R_DACEXPRELR PG 4 ADDR 0x34 */
2005 SND_SOC_BYTES("DAC Expander Release", R_DACEXPRELL, 2),
2006 /* R_DACFXCTL PG 4 ADDR 0x35 */
2007 SOC_SINGLE("DAC 3D Switch", R_DACFXCTL, FB_DACFXCTL_3DEN, 1, 0),
2008 SOC_SINGLE("DAC Treble Enhancement Switch",
2009 R_DACFXCTL, FB_DACFXCTL_TEEN, 1, 0),
2010 SOC_SINGLE("DAC Treble NLF Switch",
2011 R_DACFXCTL, FB_DACFXCTL_TNLFBYP, 1, 1),
2012 SOC_SINGLE("DAC Bass Enhancement Switch",
2013 R_DACFXCTL, FB_DACFXCTL_BEEN, 1, 0),
2014 SOC_SINGLE("DAC Bass NLF Switch",
2015 R_DACFXCTL, FB_DACFXCTL_BNLFBYP, 1, 1),
2016 /* R_SUBEQFILT PG 5 ADDR 0x01 */
2017 SOC_SINGLE("Sub EQ 2 Switch",
2018 R_SUBEQFILT, FB_SUBEQFILT_EQ2EN, 1, 0),
2019 SOC_ENUM("Sub EQ 2 Band", sub_eq_enums[0]),
2020 SOC_SINGLE("Sub EQ 1 Switch", R_SUBEQFILT, FB_SUBEQFILT_EQ1EN, 1, 0),
2021 SOC_ENUM("Sub EQ 1 Band", sub_eq_enums[1]),
2022 /* R_SUBMBCEN PG 5 ADDR 0x0A */
2023 SOC_SINGLE("Sub MBC 3 Switch", R_SUBMBCEN, FB_SUBMBCEN_MBCEN3, 1, 0),
2024 SOC_SINGLE("Sub MBC 2 Switch", R_SUBMBCEN, FB_SUBMBCEN_MBCEN2, 1, 0),
2025 SOC_SINGLE("Sub MBC 1 Switch", R_SUBMBCEN, FB_SUBMBCEN_MBCEN1, 1, 0),
2026 /* R_SUBMBCCTL PG 5 ADDR 0x0B */
2027 SOC_ENUM("Sub MBC 3 Mode", sub_mbc3_lvl_det_mode_enum),
2028 SOC_ENUM("Sub MBC 3 Window", sub_mbc3_win_sel_enum),
2029 SOC_ENUM("Sub MBC 2 Mode", sub_mbc2_lvl_det_mode_enum),
2030 SOC_ENUM("Sub MBC 2 Window", sub_mbc2_win_sel_enum),
2031 SOC_ENUM("Sub MBC 1 Mode", sub_mbc1_lvl_det_mode_enum),
2032 SOC_ENUM("Sub MBC 1 Window", sub_mbc1_win_sel_enum),
2033 /* R_SUBMBCMUG1 PG 5 ADDR 0x0C */
2034 SOC_ENUM("Sub MBC 1 Phase Polarity", sub_mbc1_phase_pol_enum),
2035 SOC_SINGLE_TLV("Sub MBC 1 Make-Up Gain Volume", R_SUBMBCMUG1,
2036 FB_SUBMBCMUG_MUGAIN, FM_SUBMBCMUG_MUGAIN,
2037 0, mbc_mug_tlv_arr),
2038 /* R_SUBMBCTHR1 PG 5 ADDR 0x0D */
2039 SOC_SINGLE_TLV("Sub MBC 1 Compressor Threshold Volume", R_SUBMBCTHR1,
2040 FB_SUBMBCTHR_THRESH, FM_SUBMBCTHR_THRESH,
2041 0, thr_tlv_arr),
2042 /* R_SUBMBCRAT1 PG 5 ADDR 0x0E */
2043 SOC_ENUM("Sub MBC 1 Compressor Ratio", sub_mbc1_comp_rat_enum),
2044 /* R_SUBMBCATK1L PG 5 ADDR 0x0F */
2045 /* R_SUBMBCATK1H PG 5 ADDR 0x10 */
2046 SND_SOC_BYTES("Sub MBC 1 Attack", R_SUBMBCATK1L, 2),
2047 /* R_SUBMBCREL1L PG 5 ADDR 0x11 */
2048 /* R_SUBMBCREL1H PG 5 ADDR 0x12 */
2049 SND_SOC_BYTES("Sub MBC 1 Release", R_SUBMBCREL1L, 2),
2050 /* R_SUBMBCMUG2 PG 5 ADDR 0x13 */
2051 SOC_ENUM("Sub MBC 2 Phase Polarity", sub_mbc2_phase_pol_enum),
2052 SOC_SINGLE_TLV("Sub MBC 2 Make-Up Gain Volume", R_SUBMBCMUG2,
2053 FB_SUBMBCMUG_MUGAIN, FM_SUBMBCMUG_MUGAIN,
2054 0, mbc_mug_tlv_arr),
2055 /* R_SUBMBCTHR2 PG 5 ADDR 0x14 */
2056 SOC_SINGLE_TLV("Sub MBC 2 Compressor Threshold Volume", R_SUBMBCTHR2,
2057 FB_SUBMBCTHR_THRESH, FM_SUBMBCTHR_THRESH,
2058 0, thr_tlv_arr),
2059 /* R_SUBMBCRAT2 PG 5 ADDR 0x15 */
2060 SOC_ENUM("Sub MBC 2 Compressor Ratio", sub_mbc2_comp_rat_enum),
2061 /* R_SUBMBCATK2L PG 5 ADDR 0x16 */
2062 /* R_SUBMBCATK2H PG 5 ADDR 0x17 */
2063 SND_SOC_BYTES("Sub MBC 2 Attack", R_SUBMBCATK2L, 2),
2064 /* R_SUBMBCREL2L PG 5 ADDR 0x18 */
2065 /* R_SUBMBCREL2H PG 5 ADDR 0x19 */
2066 SND_SOC_BYTES("Sub MBC 2 Release", R_SUBMBCREL2L, 2),
2067 /* R_SUBMBCMUG3 PG 5 ADDR 0x1A */
2068 SOC_ENUM("Sub MBC 3 Phase Polarity", sub_mbc3_phase_pol_enum),
2069 SOC_SINGLE_TLV("Sub MBC 3 Make-Up Gain Volume", R_SUBMBCMUG3,
2070 FB_SUBMBCMUG_MUGAIN, FM_SUBMBCMUG_MUGAIN,
2071 0, mbc_mug_tlv_arr),
2072 /* R_SUBMBCTHR3 PG 5 ADDR 0x1B */
2073 SOC_SINGLE_TLV("Sub MBC 3 Threshold Volume", R_SUBMBCTHR3,
2074 FB_SUBMBCTHR_THRESH, FM_SUBMBCTHR_THRESH,
2075 0, thr_tlv_arr),
2076 /* R_SUBMBCRAT3 PG 5 ADDR 0x1C */
2077 SOC_ENUM("Sub MBC 3 Compressor Ratio", sub_mbc3_comp_rat_enum),
2078 /* R_SUBMBCATK3L PG 5 ADDR 0x1D */
2079 /* R_SUBMBCATK3H PG 5 ADDR 0x1E */
2080 SND_SOC_BYTES("Sub MBC 3 Attack", R_SUBMBCATK3L, 3),
2081 /* R_SUBMBCREL3L PG 5 ADDR 0x1F */
2082 /* R_SUBMBCREL3H PG 5 ADDR 0x20 */
2083 SND_SOC_BYTES("Sub MBC 3 Release", R_SUBMBCREL3L, 3),
2084 /* R_SUBCLECTL PG 5 ADDR 0x21 */
2085 SOC_ENUM("Sub CLE Level Mode", sub_cle_lvl_mode_enum),
2086 SOC_ENUM("Sub CLE Window", sub_cle_win_sel_enum),
2087 SOC_SINGLE("Sub CLE Expander Switch",
2088 R_SUBCLECTL, FB_SUBCLECTL_EXPEN, 1, 0),
2089 SOC_SINGLE("Sub CLE Limiter Switch",
2090 R_SUBCLECTL, FB_SUBCLECTL_LIMEN, 1, 0),
2091 SOC_SINGLE("Sub CLE Compressor Switch",
2092 R_SUBCLECTL, FB_SUBCLECTL_COMPEN, 1, 0),
2093 /* R_SUBCLEMUG PG 5 ADDR 0x22 */
2094 SOC_SINGLE_TLV("Sub CLE Make-Up Gain Volume", R_SUBCLEMUG,
2095 FB_SUBCLEMUG_MUGAIN, FM_SUBCLEMUG_MUGAIN,
2096 0, cle_mug_tlv_arr),
2097 /* R_SUBCOMPTHR PG 5 ADDR 0x23 */
2098 SOC_SINGLE_TLV("Sub Compressor Threshold Volume", R_SUBCOMPTHR,
2099 FB_SUBCOMPTHR_THRESH, FM_SUBCOMPTHR_THRESH,
2100 0, thr_tlv_arr),
2101 /* R_SUBCOMPRAT PG 5 ADDR 0x24 */
2102 SOC_ENUM("Sub Compressor Ratio", sub_comp_rat_enum),
2103 /* R_SUBCOMPATKL PG 5 ADDR 0x25 */
2104 /* R_SUBCOMPATKH PG 5 ADDR 0x26 */
2105 SND_SOC_BYTES("Sub Compressor Attack", R_SUBCOMPATKL, 2),
2106 /* R_SUBCOMPRELL PG 5 ADDR 0x27 */
2107 /* R_SUBCOMPRELH PG 5 ADDR 0x28 */
2108 SND_SOC_BYTES("Sub Compressor Release", R_SUBCOMPRELL, 2),
2109 /* R_SUBLIMTHR PG 5 ADDR 0x29 */
2110 SOC_SINGLE_TLV("Sub Limiter Threshold Volume", R_SUBLIMTHR,
2111 FB_SUBLIMTHR_THRESH, FM_SUBLIMTHR_THRESH,
2112 0, thr_tlv_arr),
2113 /* R_SUBLIMTGT PG 5 ADDR 0x2A */
2114 SOC_SINGLE_TLV("Sub Limiter Target Volume", R_SUBLIMTGT,
2115 FB_SUBLIMTGT_TARGET, FM_SUBLIMTGT_TARGET,
2116 0, thr_tlv_arr),
2117 /* R_SUBLIMATKL PG 5 ADDR 0x2B */
2118 /* R_SUBLIMATKH PG 5 ADDR 0x2C */
2119 SND_SOC_BYTES("Sub Limiter Attack", R_SUBLIMATKL, 2),
2120 /* R_SUBLIMRELL PG 5 ADDR 0x2D */
2121 /* R_SUBLIMRELR PG 5 ADDR 0x2E */
2122 SND_SOC_BYTES("Sub Limiter Release", R_SUBLIMRELL, 2),
2123 /* R_SUBEXPTHR PG 5 ADDR 0x2F */
2124 SOC_SINGLE_TLV("Sub Expander Threshold Volume", R_SUBEXPTHR,
2125 FB_SUBEXPTHR_THRESH, FM_SUBEXPTHR_THRESH,
2126 0, thr_tlv_arr),
2127 /* R_SUBEXPRAT PG 5 ADDR 0x30 */
2128 SOC_ENUM("Sub Expander Ratio", sub_exp_rat_enum),
2129 /* R_SUBEXPATKL PG 5 ADDR 0x31 */
2130 /* R_SUBEXPATKR PG 5 ADDR 0x32 */
2131 SND_SOC_BYTES("Sub Expander Attack", R_SUBEXPATKL, 2),
2132 /* R_SUBEXPRELL PG 5 ADDR 0x33 */
2133 /* R_SUBEXPRELR PG 5 ADDR 0x34 */
2134 SND_SOC_BYTES("Sub Expander Release", R_SUBEXPRELL, 2),
2135 /* R_SUBFXCTL PG 5 ADDR 0x35 */
2136 SOC_SINGLE("Sub Treble Enhancement Switch",
2137 R_SUBFXCTL, FB_SUBFXCTL_TEEN, 1, 0),
2138 SOC_SINGLE("Sub Treble NLF Switch",
2139 R_SUBFXCTL, FB_SUBFXCTL_TNLFBYP, 1, 1),
2140 SOC_SINGLE("Sub Bass Enhancement Switch",
2141 R_SUBFXCTL, FB_SUBFXCTL_BEEN, 1, 0),
2142 SOC_SINGLE("Sub Bass NLF Switch",
2143 R_SUBFXCTL, FB_SUBFXCTL_BNLFBYP, 1, 1),
2144 COEFF_RAM_CTL("DAC Cascade 1 Left BiQuad 1", BIQUAD_SIZE, 0x00),
2145 COEFF_RAM_CTL("DAC Cascade 1 Left BiQuad 2", BIQUAD_SIZE, 0x05),
2146 COEFF_RAM_CTL("DAC Cascade 1 Left BiQuad 3", BIQUAD_SIZE, 0x0a),
2147 COEFF_RAM_CTL("DAC Cascade 1 Left BiQuad 4", BIQUAD_SIZE, 0x0f),
2148 COEFF_RAM_CTL("DAC Cascade 1 Left BiQuad 5", BIQUAD_SIZE, 0x14),
2149 COEFF_RAM_CTL("DAC Cascade 1 Left BiQuad 6", BIQUAD_SIZE, 0x19),
2150
2151 COEFF_RAM_CTL("DAC Cascade 1 Right BiQuad 1", BIQUAD_SIZE, 0x20),
2152 COEFF_RAM_CTL("DAC Cascade 1 Right BiQuad 2", BIQUAD_SIZE, 0x25),
2153 COEFF_RAM_CTL("DAC Cascade 1 Right BiQuad 3", BIQUAD_SIZE, 0x2a),
2154 COEFF_RAM_CTL("DAC Cascade 1 Right BiQuad 4", BIQUAD_SIZE, 0x2f),
2155 COEFF_RAM_CTL("DAC Cascade 1 Right BiQuad 5", BIQUAD_SIZE, 0x34),
2156 COEFF_RAM_CTL("DAC Cascade 1 Right BiQuad 6", BIQUAD_SIZE, 0x39),
2157
2158 COEFF_RAM_CTL("DAC Cascade 1 Left Prescale", COEFF_SIZE, 0x1f),
2159 COEFF_RAM_CTL("DAC Cascade 1 Right Prescale", COEFF_SIZE, 0x3f),
2160
2161 COEFF_RAM_CTL("DAC Cascade 2 Left BiQuad 1", BIQUAD_SIZE, 0x40),
2162 COEFF_RAM_CTL("DAC Cascade 2 Left BiQuad 2", BIQUAD_SIZE, 0x45),
2163 COEFF_RAM_CTL("DAC Cascade 2 Left BiQuad 3", BIQUAD_SIZE, 0x4a),
2164 COEFF_RAM_CTL("DAC Cascade 2 Left BiQuad 4", BIQUAD_SIZE, 0x4f),
2165 COEFF_RAM_CTL("DAC Cascade 2 Left BiQuad 5", BIQUAD_SIZE, 0x54),
2166 COEFF_RAM_CTL("DAC Cascade 2 Left BiQuad 6", BIQUAD_SIZE, 0x59),
2167
2168 COEFF_RAM_CTL("DAC Cascade 2 Right BiQuad 1", BIQUAD_SIZE, 0x60),
2169 COEFF_RAM_CTL("DAC Cascade 2 Right BiQuad 2", BIQUAD_SIZE, 0x65),
2170 COEFF_RAM_CTL("DAC Cascade 2 Right BiQuad 3", BIQUAD_SIZE, 0x6a),
2171 COEFF_RAM_CTL("DAC Cascade 2 Right BiQuad 4", BIQUAD_SIZE, 0x6f),
2172 COEFF_RAM_CTL("DAC Cascade 2 Right BiQuad 5", BIQUAD_SIZE, 0x74),
2173 COEFF_RAM_CTL("DAC Cascade 2 Right BiQuad 6", BIQUAD_SIZE, 0x79),
2174
2175 COEFF_RAM_CTL("DAC Cascade 2 Left Prescale", COEFF_SIZE, 0x5f),
2176 COEFF_RAM_CTL("DAC Cascade 2 Right Prescale", COEFF_SIZE, 0x7f),
2177
2178 COEFF_RAM_CTL("DAC Bass Extraction BiQuad 1", BIQUAD_SIZE, 0x80),
2179 COEFF_RAM_CTL("DAC Bass Extraction BiQuad 2", BIQUAD_SIZE, 0x85),
2180
2181 COEFF_RAM_CTL("DAC Bass Non Linear Function 1", COEFF_SIZE, 0x8a),
2182 COEFF_RAM_CTL("DAC Bass Non Linear Function 2", COEFF_SIZE, 0x8b),
2183
2184 COEFF_RAM_CTL("DAC Bass Limiter BiQuad", BIQUAD_SIZE, 0x8c),
2185
2186 COEFF_RAM_CTL("DAC Bass Cut Off BiQuad", BIQUAD_SIZE, 0x91),
2187
2188 COEFF_RAM_CTL("DAC Bass Mix", COEFF_SIZE, 0x96),
2189
2190 COEFF_RAM_CTL("DAC Treb Extraction BiQuad 1", BIQUAD_SIZE, 0x97),
2191 COEFF_RAM_CTL("DAC Treb Extraction BiQuad 2", BIQUAD_SIZE, 0x9c),
2192
2193 COEFF_RAM_CTL("DAC Treb Non Linear Function 1", COEFF_SIZE, 0xa1),
2194 COEFF_RAM_CTL("DAC Treb Non Linear Function 2", COEFF_SIZE, 0xa2),
2195
2196 COEFF_RAM_CTL("DAC Treb Limiter BiQuad", BIQUAD_SIZE, 0xa3),
2197
2198 COEFF_RAM_CTL("DAC Treb Cut Off BiQuad", BIQUAD_SIZE, 0xa8),
2199
2200 COEFF_RAM_CTL("DAC Treb Mix", COEFF_SIZE, 0xad),
2201
2202 COEFF_RAM_CTL("DAC 3D", COEFF_SIZE, 0xae),
2203
2204 COEFF_RAM_CTL("DAC 3D Mix", COEFF_SIZE, 0xaf),
2205
2206 COEFF_RAM_CTL("DAC MBC 1 BiQuad 1", BIQUAD_SIZE, 0xb0),
2207 COEFF_RAM_CTL("DAC MBC 1 BiQuad 2", BIQUAD_SIZE, 0xb5),
2208
2209 COEFF_RAM_CTL("DAC MBC 2 BiQuad 1", BIQUAD_SIZE, 0xba),
2210 COEFF_RAM_CTL("DAC MBC 2 BiQuad 2", BIQUAD_SIZE, 0xbf),
2211
2212 COEFF_RAM_CTL("DAC MBC 3 BiQuad 1", BIQUAD_SIZE, 0xc4),
2213 COEFF_RAM_CTL("DAC MBC 3 BiQuad 2", BIQUAD_SIZE, 0xc9),
2214
2215 COEFF_RAM_CTL("Speaker Cascade 1 Left BiQuad 1", BIQUAD_SIZE, 0x00),
2216 COEFF_RAM_CTL("Speaker Cascade 1 Left BiQuad 2", BIQUAD_SIZE, 0x05),
2217 COEFF_RAM_CTL("Speaker Cascade 1 Left BiQuad 3", BIQUAD_SIZE, 0x0a),
2218 COEFF_RAM_CTL("Speaker Cascade 1 Left BiQuad 4", BIQUAD_SIZE, 0x0f),
2219 COEFF_RAM_CTL("Speaker Cascade 1 Left BiQuad 5", BIQUAD_SIZE, 0x14),
2220 COEFF_RAM_CTL("Speaker Cascade 1 Left BiQuad 6", BIQUAD_SIZE, 0x19),
2221
2222 COEFF_RAM_CTL("Speaker Cascade 1 Right BiQuad 1", BIQUAD_SIZE, 0x20),
2223 COEFF_RAM_CTL("Speaker Cascade 1 Right BiQuad 2", BIQUAD_SIZE, 0x25),
2224 COEFF_RAM_CTL("Speaker Cascade 1 Right BiQuad 3", BIQUAD_SIZE, 0x2a),
2225 COEFF_RAM_CTL("Speaker Cascade 1 Right BiQuad 4", BIQUAD_SIZE, 0x2f),
2226 COEFF_RAM_CTL("Speaker Cascade 1 Right BiQuad 5", BIQUAD_SIZE, 0x34),
2227 COEFF_RAM_CTL("Speaker Cascade 1 Right BiQuad 6", BIQUAD_SIZE, 0x39),
2228
2229 COEFF_RAM_CTL("Speaker Cascade 1 Left Prescale", COEFF_SIZE, 0x1f),
2230 COEFF_RAM_CTL("Speaker Cascade 1 Right Prescale", COEFF_SIZE, 0x3f),
2231
2232 COEFF_RAM_CTL("Speaker Cascade 2 Left BiQuad 1", BIQUAD_SIZE, 0x40),
2233 COEFF_RAM_CTL("Speaker Cascade 2 Left BiQuad 2", BIQUAD_SIZE, 0x45),
2234 COEFF_RAM_CTL("Speaker Cascade 2 Left BiQuad 3", BIQUAD_SIZE, 0x4a),
2235 COEFF_RAM_CTL("Speaker Cascade 2 Left BiQuad 4", BIQUAD_SIZE, 0x4f),
2236 COEFF_RAM_CTL("Speaker Cascade 2 Left BiQuad 5", BIQUAD_SIZE, 0x54),
2237 COEFF_RAM_CTL("Speaker Cascade 2 Left BiQuad 6", BIQUAD_SIZE, 0x59),
2238
2239 COEFF_RAM_CTL("Speaker Cascade 2 Right BiQuad 1", BIQUAD_SIZE, 0x60),
2240 COEFF_RAM_CTL("Speaker Cascade 2 Right BiQuad 2", BIQUAD_SIZE, 0x65),
2241 COEFF_RAM_CTL("Speaker Cascade 2 Right BiQuad 3", BIQUAD_SIZE, 0x6a),
2242 COEFF_RAM_CTL("Speaker Cascade 2 Right BiQuad 4", BIQUAD_SIZE, 0x6f),
2243 COEFF_RAM_CTL("Speaker Cascade 2 Right BiQuad 5", BIQUAD_SIZE, 0x74),
2244 COEFF_RAM_CTL("Speaker Cascade 2 Right BiQuad 6", BIQUAD_SIZE, 0x79),
2245
2246 COEFF_RAM_CTL("Speaker Cascade 2 Left Prescale", COEFF_SIZE, 0x5f),
2247 COEFF_RAM_CTL("Speaker Cascade 2 Right Prescale", COEFF_SIZE, 0x7f),
2248
2249 COEFF_RAM_CTL("Speaker Bass Extraction BiQuad 1", BIQUAD_SIZE, 0x80),
2250 COEFF_RAM_CTL("Speaker Bass Extraction BiQuad 2", BIQUAD_SIZE, 0x85),
2251
2252 COEFF_RAM_CTL("Speaker Bass Non Linear Function 1", COEFF_SIZE, 0x8a),
2253 COEFF_RAM_CTL("Speaker Bass Non Linear Function 2", COEFF_SIZE, 0x8b),
2254
2255 COEFF_RAM_CTL("Speaker Bass Limiter BiQuad", BIQUAD_SIZE, 0x8c),
2256
2257 COEFF_RAM_CTL("Speaker Bass Cut Off BiQuad", BIQUAD_SIZE, 0x91),
2258
2259 COEFF_RAM_CTL("Speaker Bass Mix", COEFF_SIZE, 0x96),
2260
2261 COEFF_RAM_CTL("Speaker Treb Extraction BiQuad 1", BIQUAD_SIZE, 0x97),
2262 COEFF_RAM_CTL("Speaker Treb Extraction BiQuad 2", BIQUAD_SIZE, 0x9c),
2263
2264 COEFF_RAM_CTL("Speaker Treb Non Linear Function 1", COEFF_SIZE, 0xa1),
2265 COEFF_RAM_CTL("Speaker Treb Non Linear Function 2", COEFF_SIZE, 0xa2),
2266
2267 COEFF_RAM_CTL("Speaker Treb Limiter BiQuad", BIQUAD_SIZE, 0xa3),
2268
2269 COEFF_RAM_CTL("Speaker Treb Cut Off BiQuad", BIQUAD_SIZE, 0xa8),
2270
2271 COEFF_RAM_CTL("Speaker Treb Mix", COEFF_SIZE, 0xad),
2272
2273 COEFF_RAM_CTL("Speaker 3D", COEFF_SIZE, 0xae),
2274
2275 COEFF_RAM_CTL("Speaker 3D Mix", COEFF_SIZE, 0xaf),
2276
2277 COEFF_RAM_CTL("Speaker MBC 1 BiQuad 1", BIQUAD_SIZE, 0xb0),
2278 COEFF_RAM_CTL("Speaker MBC 1 BiQuad 2", BIQUAD_SIZE, 0xb5),
2279
2280 COEFF_RAM_CTL("Speaker MBC 2 BiQuad 1", BIQUAD_SIZE, 0xba),
2281 COEFF_RAM_CTL("Speaker MBC 2 BiQuad 2", BIQUAD_SIZE, 0xbf),
2282
2283 COEFF_RAM_CTL("Speaker MBC 3 BiQuad 1", BIQUAD_SIZE, 0xc4),
2284 COEFF_RAM_CTL("Speaker MBC 3 BiQuad 2", BIQUAD_SIZE, 0xc9),
2285
2286 COEFF_RAM_CTL("Sub Cascade 1 Left BiQuad 1", BIQUAD_SIZE, 0x00),
2287 COEFF_RAM_CTL("Sub Cascade 1 Left BiQuad 2", BIQUAD_SIZE, 0x05),
2288 COEFF_RAM_CTL("Sub Cascade 1 Left BiQuad 3", BIQUAD_SIZE, 0x0a),
2289 COEFF_RAM_CTL("Sub Cascade 1 Left BiQuad 4", BIQUAD_SIZE, 0x0f),
2290 COEFF_RAM_CTL("Sub Cascade 1 Left BiQuad 5", BIQUAD_SIZE, 0x14),
2291 COEFF_RAM_CTL("Sub Cascade 1 Left BiQuad 6", BIQUAD_SIZE, 0x19),
2292
2293 COEFF_RAM_CTL("Sub Cascade 1 Right BiQuad 1", BIQUAD_SIZE, 0x20),
2294 COEFF_RAM_CTL("Sub Cascade 1 Right BiQuad 2", BIQUAD_SIZE, 0x25),
2295 COEFF_RAM_CTL("Sub Cascade 1 Right BiQuad 3", BIQUAD_SIZE, 0x2a),
2296 COEFF_RAM_CTL("Sub Cascade 1 Right BiQuad 4", BIQUAD_SIZE, 0x2f),
2297 COEFF_RAM_CTL("Sub Cascade 1 Right BiQuad 5", BIQUAD_SIZE, 0x34),
2298 COEFF_RAM_CTL("Sub Cascade 1 Right BiQuad 6", BIQUAD_SIZE, 0x39),
2299
2300 COEFF_RAM_CTL("Sub Cascade 1 Left Prescale", COEFF_SIZE, 0x1f),
2301 COEFF_RAM_CTL("Sub Cascade 1 Right Prescale", COEFF_SIZE, 0x3f),
2302
2303 COEFF_RAM_CTL("Sub Cascade 2 Left BiQuad 1", BIQUAD_SIZE, 0x40),
2304 COEFF_RAM_CTL("Sub Cascade 2 Left BiQuad 2", BIQUAD_SIZE, 0x45),
2305 COEFF_RAM_CTL("Sub Cascade 2 Left BiQuad 3", BIQUAD_SIZE, 0x4a),
2306 COEFF_RAM_CTL("Sub Cascade 2 Left BiQuad 4", BIQUAD_SIZE, 0x4f),
2307 COEFF_RAM_CTL("Sub Cascade 2 Left BiQuad 5", BIQUAD_SIZE, 0x54),
2308 COEFF_RAM_CTL("Sub Cascade 2 Left BiQuad 6", BIQUAD_SIZE, 0x59),
2309
2310 COEFF_RAM_CTL("Sub Cascade 2 Right BiQuad 1", BIQUAD_SIZE, 0x60),
2311 COEFF_RAM_CTL("Sub Cascade 2 Right BiQuad 2", BIQUAD_SIZE, 0x65),
2312 COEFF_RAM_CTL("Sub Cascade 2 Right BiQuad 3", BIQUAD_SIZE, 0x6a),
2313 COEFF_RAM_CTL("Sub Cascade 2 Right BiQuad 4", BIQUAD_SIZE, 0x6f),
2314 COEFF_RAM_CTL("Sub Cascade 2 Right BiQuad 5", BIQUAD_SIZE, 0x74),
2315 COEFF_RAM_CTL("Sub Cascade 2 Right BiQuad 6", BIQUAD_SIZE, 0x79),
2316
2317 COEFF_RAM_CTL("Sub Cascade 2 Left Prescale", COEFF_SIZE, 0x5f),
2318 COEFF_RAM_CTL("Sub Cascade 2 Right Prescale", COEFF_SIZE, 0x7f),
2319
2320 COEFF_RAM_CTL("Sub Bass Extraction BiQuad 1", BIQUAD_SIZE, 0x80),
2321 COEFF_RAM_CTL("Sub Bass Extraction BiQuad 2", BIQUAD_SIZE, 0x85),
2322
2323 COEFF_RAM_CTL("Sub Bass Non Linear Function 1", COEFF_SIZE, 0x8a),
2324 COEFF_RAM_CTL("Sub Bass Non Linear Function 2", COEFF_SIZE, 0x8b),
2325
2326 COEFF_RAM_CTL("Sub Bass Limiter BiQuad", BIQUAD_SIZE, 0x8c),
2327
2328 COEFF_RAM_CTL("Sub Bass Cut Off BiQuad", BIQUAD_SIZE, 0x91),
2329
2330 COEFF_RAM_CTL("Sub Bass Mix", COEFF_SIZE, 0x96),
2331
2332 COEFF_RAM_CTL("Sub Treb Extraction BiQuad 1", BIQUAD_SIZE, 0x97),
2333 COEFF_RAM_CTL("Sub Treb Extraction BiQuad 2", BIQUAD_SIZE, 0x9c),
2334
2335 COEFF_RAM_CTL("Sub Treb Non Linear Function 1", COEFF_SIZE, 0xa1),
2336 COEFF_RAM_CTL("Sub Treb Non Linear Function 2", COEFF_SIZE, 0xa2),
2337
2338 COEFF_RAM_CTL("Sub Treb Limiter BiQuad", BIQUAD_SIZE, 0xa3),
2339
2340 COEFF_RAM_CTL("Sub Treb Cut Off BiQuad", BIQUAD_SIZE, 0xa8),
2341
2342 COEFF_RAM_CTL("Sub Treb Mix", COEFF_SIZE, 0xad),
2343
2344 COEFF_RAM_CTL("Sub 3D", COEFF_SIZE, 0xae),
2345
2346 COEFF_RAM_CTL("Sub 3D Mix", COEFF_SIZE, 0xaf),
2347
2348 COEFF_RAM_CTL("Sub MBC 1 BiQuad 1", BIQUAD_SIZE, 0xb0),
2349 COEFF_RAM_CTL("Sub MBC 1 BiQuad 2", BIQUAD_SIZE, 0xb5),
2350
2351 COEFF_RAM_CTL("Sub MBC 2 BiQuad 1", BIQUAD_SIZE, 0xba),
2352 COEFF_RAM_CTL("Sub MBC 2 BiQuad 2", BIQUAD_SIZE, 0xbf),
2353
2354 COEFF_RAM_CTL("Sub MBC 3 BiQuad 1", BIQUAD_SIZE, 0xc4),
2355 COEFF_RAM_CTL("Sub MBC 3 BiQuad 2", BIQUAD_SIZE, 0xc9),
2356 };
2357
2358 static struct snd_soc_dapm_widget const tscs454_dapm_widgets[] = {
2359 /* R_PLLCTL PG 0 ADDR 0x15 */
2360 SND_SOC_DAPM_SUPPLY("PLL 1 Power", R_PLLCTL, FB_PLLCTL_PU_PLL1, 0,
2361 pll_power_event,
2362 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_PRE_PMD),
2363 SND_SOC_DAPM_SUPPLY("PLL 2 Power", R_PLLCTL, FB_PLLCTL_PU_PLL2, 0,
2364 pll_power_event,
2365 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_PRE_PMD),
2366 /* R_I2SPINC0 PG 0 ADDR 0x22 */
2367 SND_SOC_DAPM_AIF_OUT("DAI 3 Out", "DAI 3 Capture", 0,
2368 R_I2SPINC0, FB_I2SPINC0_SDO3TRI, 1),
2369 SND_SOC_DAPM_AIF_OUT("DAI 2 Out", "DAI 2 Capture", 0,
2370 R_I2SPINC0, FB_I2SPINC0_SDO2TRI, 1),
2371 SND_SOC_DAPM_AIF_OUT("DAI 1 Out", "DAI 1 Capture", 0,
2372 R_I2SPINC0, FB_I2SPINC0_SDO1TRI, 1),
2373 /* R_PWRM0 PG 0 ADDR 0x33 */
2374 SND_SOC_DAPM_ADC("Input Processor Channel 3", NULL,
2375 R_PWRM0, FB_PWRM0_INPROC3PU, 0),
2376 SND_SOC_DAPM_ADC("Input Processor Channel 2", NULL,
2377 R_PWRM0, FB_PWRM0_INPROC2PU, 0),
2378 SND_SOC_DAPM_ADC("Input Processor Channel 1", NULL,
2379 R_PWRM0, FB_PWRM0_INPROC1PU, 0),
2380 SND_SOC_DAPM_ADC("Input Processor Channel 0", NULL,
2381 R_PWRM0, FB_PWRM0_INPROC0PU, 0),
2382 SND_SOC_DAPM_SUPPLY("Mic Bias 2",
2383 R_PWRM0, FB_PWRM0_MICB2PU, 0, NULL, 0),
2384 SND_SOC_DAPM_SUPPLY("Mic Bias 1", R_PWRM0,
2385 FB_PWRM0_MICB1PU, 0, NULL, 0),
2386 /* R_PWRM1 PG 0 ADDR 0x34 */
2387 SND_SOC_DAPM_SUPPLY("Sub Power", R_PWRM1, FB_PWRM1_SUBPU, 0, NULL, 0),
2388 SND_SOC_DAPM_SUPPLY("Headphone Left Power",
2389 R_PWRM1, FB_PWRM1_HPLPU, 0, NULL, 0),
2390 SND_SOC_DAPM_SUPPLY("Headphone Right Power",
2391 R_PWRM1, FB_PWRM1_HPRPU, 0, NULL, 0),
2392 SND_SOC_DAPM_SUPPLY("Speaker Left Power",
2393 R_PWRM1, FB_PWRM1_SPKLPU, 0, NULL, 0),
2394 SND_SOC_DAPM_SUPPLY("Speaker Right Power",
2395 R_PWRM1, FB_PWRM1_SPKRPU, 0, NULL, 0),
2396 SND_SOC_DAPM_SUPPLY("Differential Input 2 Power",
2397 R_PWRM1, FB_PWRM1_D2S2PU, 0, NULL, 0),
2398 SND_SOC_DAPM_SUPPLY("Differential Input 1 Power",
2399 R_PWRM1, FB_PWRM1_D2S1PU, 0, NULL, 0),
2400 /* R_PWRM2 PG 0 ADDR 0x35 */
2401 SND_SOC_DAPM_SUPPLY("DAI 3 Out Power",
2402 R_PWRM2, FB_PWRM2_I2S3OPU, 0, NULL, 0),
2403 SND_SOC_DAPM_SUPPLY("DAI 2 Out Power",
2404 R_PWRM2, FB_PWRM2_I2S2OPU, 0, NULL, 0),
2405 SND_SOC_DAPM_SUPPLY("DAI 1 Out Power",
2406 R_PWRM2, FB_PWRM2_I2S1OPU, 0, NULL, 0),
2407 SND_SOC_DAPM_SUPPLY("DAI 3 In Power",
2408 R_PWRM2, FB_PWRM2_I2S3IPU, 0, NULL, 0),
2409 SND_SOC_DAPM_SUPPLY("DAI 2 In Power",
2410 R_PWRM2, FB_PWRM2_I2S2IPU, 0, NULL, 0),
2411 SND_SOC_DAPM_SUPPLY("DAI 1 In Power",
2412 R_PWRM2, FB_PWRM2_I2S1IPU, 0, NULL, 0),
2413 /* R_PWRM3 PG 0 ADDR 0x36 */
2414 SND_SOC_DAPM_SUPPLY("Line Out Left Power",
2415 R_PWRM3, FB_PWRM3_LLINEPU, 0, NULL, 0),
2416 SND_SOC_DAPM_SUPPLY("Line Out Right Power",
2417 R_PWRM3, FB_PWRM3_RLINEPU, 0, NULL, 0),
2418 /* R_PWRM4 PG 0 ADDR 0x37 */
2419 SND_SOC_DAPM_DAC("Sub", NULL, R_PWRM4, FB_PWRM4_OPSUBPU, 0),
2420 SND_SOC_DAPM_DAC("DAC Left", NULL, R_PWRM4, FB_PWRM4_OPDACLPU, 0),
2421 SND_SOC_DAPM_DAC("DAC Right", NULL, R_PWRM4, FB_PWRM4_OPDACRPU, 0),
2422 SND_SOC_DAPM_DAC("ClassD Left", NULL, R_PWRM4, FB_PWRM4_OPSPKLPU, 0),
2423 SND_SOC_DAPM_DAC("ClassD Right", NULL, R_PWRM4, FB_PWRM4_OPSPKRPU, 0),
2424 /* R_AUDIOMUX1 PG 0 ADDR 0x3A */
2425 SND_SOC_DAPM_MUX("DAI 2 Out Mux", SND_SOC_NOPM, 0, 0,
2426 &dai2_mux_dapm_enum),
2427 SND_SOC_DAPM_MUX("DAI 1 Out Mux", SND_SOC_NOPM, 0, 0,
2428 &dai1_mux_dapm_enum),
2429 /* R_AUDIOMUX2 PG 0 ADDR 0x3B */
2430 SND_SOC_DAPM_MUX("DAC Mux", SND_SOC_NOPM, 0, 0,
2431 &dac_mux_dapm_enum),
2432 SND_SOC_DAPM_MUX("DAI 3 Out Mux", SND_SOC_NOPM, 0, 0,
2433 &dai3_mux_dapm_enum),
2434 /* R_AUDIOMUX3 PG 0 ADDR 0x3C */
2435 SND_SOC_DAPM_MUX("Sub Mux", SND_SOC_NOPM, 0, 0,
2436 &sub_mux_dapm_enum),
2437 SND_SOC_DAPM_MUX("Speaker Mux", SND_SOC_NOPM, 0, 0,
2438 &classd_mux_dapm_enum),
2439 /* R_HSDCTL1 PG 1 ADDR 0x01 */
2440 SND_SOC_DAPM_SUPPLY("GHS Detect Power", R_HSDCTL1,
2441 FB_HSDCTL1_CON_DET_PWD, 1, NULL, 0),
2442 /* R_CH0AIC PG 1 ADDR 0x06 */
2443 SND_SOC_DAPM_MUX("Input Boost Channel 0 Mux", SND_SOC_NOPM, 0, 0,
2444 &in_bst_mux_ch0_dapm_enum),
2445 SND_SOC_DAPM_MUX("ADC Channel 0 Mux", SND_SOC_NOPM, 0, 0,
2446 &adc_mux_ch0_dapm_enum),
2447 SND_SOC_DAPM_MUX("Input Processor Channel 0 Mux", SND_SOC_NOPM, 0, 0,
2448 &in_proc_mux_ch0_dapm_enum),
2449 /* R_CH1AIC PG 1 ADDR 0x07 */
2450 SND_SOC_DAPM_MUX("Input Boost Channel 1 Mux", SND_SOC_NOPM, 0, 0,
2451 &in_bst_mux_ch1_dapm_enum),
2452 SND_SOC_DAPM_MUX("ADC Channel 1 Mux", SND_SOC_NOPM, 0, 0,
2453 &adc_mux_ch1_dapm_enum),
2454 SND_SOC_DAPM_MUX("Input Processor Channel 1 Mux", SND_SOC_NOPM, 0, 0,
2455 &in_proc_mux_ch1_dapm_enum),
2456 /* Virtual */
2457 SND_SOC_DAPM_AIF_IN("DAI 3 In", "DAI 3 Playback", 0,
2458 SND_SOC_NOPM, 0, 0),
2459 SND_SOC_DAPM_AIF_IN("DAI 2 In", "DAI 2 Playback", 0,
2460 SND_SOC_NOPM, 0, 0),
2461 SND_SOC_DAPM_AIF_IN("DAI 1 In", "DAI 1 Playback", 0,
2462 SND_SOC_NOPM, 0, 0),
2463 SND_SOC_DAPM_SUPPLY("PLLs", SND_SOC_NOPM, 0, 0, NULL, 0),
2464 SND_SOC_DAPM_OUTPUT("Sub Out"),
2465 SND_SOC_DAPM_OUTPUT("Headphone Left"),
2466 SND_SOC_DAPM_OUTPUT("Headphone Right"),
2467 SND_SOC_DAPM_OUTPUT("Speaker Left"),
2468 SND_SOC_DAPM_OUTPUT("Speaker Right"),
2469 SND_SOC_DAPM_OUTPUT("Line Out Left"),
2470 SND_SOC_DAPM_OUTPUT("Line Out Right"),
2471 SND_SOC_DAPM_INPUT("D2S 2"),
2472 SND_SOC_DAPM_INPUT("D2S 1"),
2473 SND_SOC_DAPM_INPUT("Line In 1 Left"),
2474 SND_SOC_DAPM_INPUT("Line In 1 Right"),
2475 SND_SOC_DAPM_INPUT("Line In 2 Left"),
2476 SND_SOC_DAPM_INPUT("Line In 2 Right"),
2477 SND_SOC_DAPM_INPUT("Line In 3 Left"),
2478 SND_SOC_DAPM_INPUT("Line In 3 Right"),
2479 SND_SOC_DAPM_INPUT("DMic 1"),
2480 SND_SOC_DAPM_INPUT("DMic 2"),
2481
2482 SND_SOC_DAPM_MUX("CH 0_1 Mux", SND_SOC_NOPM, 0, 0,
2483 &ch_0_1_mux_dapm_enum),
2484 SND_SOC_DAPM_MUX("CH 2_3 Mux", SND_SOC_NOPM, 0, 0,
2485 &ch_2_3_mux_dapm_enum),
2486 SND_SOC_DAPM_MUX("CH 4_5 Mux", SND_SOC_NOPM, 0, 0,
2487 &ch_4_5_mux_dapm_enum),
2488 };
2489
2490 static struct snd_soc_dapm_route const tscs454_intercon[] = {
2491 /* PLLs */
2492 {"PLLs", NULL, "PLL 1 Power", pll_connected},
2493 {"PLLs", NULL, "PLL 2 Power", pll_connected},
2494 /* Inputs */
2495 {"DAI 3 In", NULL, "DAI 3 In Power"},
2496 {"DAI 2 In", NULL, "DAI 2 In Power"},
2497 {"DAI 1 In", NULL, "DAI 1 In Power"},
2498 /* Outputs */
2499 {"DAI 3 Out", NULL, "DAI 3 Out Power"},
2500 {"DAI 2 Out", NULL, "DAI 2 Out Power"},
2501 {"DAI 1 Out", NULL, "DAI 1 Out Power"},
2502 /* Ch Muxing */
2503 {"CH 0_1 Mux", "DAI 1", "DAI 1 In"},
2504 {"CH 0_1 Mux", "TDM 0_1", "DAI 1 In"},
2505 {"CH 2_3 Mux", "DAI 2", "DAI 2 In"},
2506 {"CH 2_3 Mux", "TDM 2_3", "DAI 1 In"},
2507 {"CH 4_5 Mux", "DAI 3", "DAI 2 In"},
2508 {"CH 4_5 Mux", "TDM 4_5", "DAI 1 In"},
2509 /* In/Out Muxing */
2510 {"DAI 1 Out Mux", "CH 0_1", "CH 0_1 Mux"},
2511 {"DAI 1 Out Mux", "CH 2_3", "CH 2_3 Mux"},
2512 {"DAI 1 Out Mux", "CH 4_5", "CH 4_5 Mux"},
2513 {"DAI 2 Out Mux", "CH 0_1", "CH 0_1 Mux"},
2514 {"DAI 2 Out Mux", "CH 2_3", "CH 2_3 Mux"},
2515 {"DAI 2 Out Mux", "CH 4_5", "CH 4_5 Mux"},
2516 {"DAI 3 Out Mux", "CH 0_1", "CH 0_1 Mux"},
2517 {"DAI 3 Out Mux", "CH 2_3", "CH 2_3 Mux"},
2518 {"DAI 3 Out Mux", "CH 4_5", "CH 4_5 Mux"},
2519 /******************
2520 * Playback Paths *
2521 ******************/
2522 /* DAC Path */
2523 {"DAC Mux", "CH 4_5", "CH 4_5 Mux"},
2524 {"DAC Mux", "CH 2_3", "CH 2_3 Mux"},
2525 {"DAC Mux", "CH 0_1", "CH 0_1 Mux"},
2526 {"DAC Left", NULL, "DAC Mux"},
2527 {"DAC Right", NULL, "DAC Mux"},
2528 {"DAC Left", NULL, "PLLs"},
2529 {"DAC Right", NULL, "PLLs"},
2530 {"Headphone Left", NULL, "Headphone Left Power"},
2531 {"Headphone Right", NULL, "Headphone Right Power"},
2532 {"Headphone Left", NULL, "DAC Left"},
2533 {"Headphone Right", NULL, "DAC Right"},
2534 /* Line Out */
2535 {"Line Out Left", NULL, "Line Out Left Power"},
2536 {"Line Out Right", NULL, "Line Out Right Power"},
2537 {"Line Out Left", NULL, "DAC Left"},
2538 {"Line Out Right", NULL, "DAC Right"},
2539 /* ClassD Path */
2540 {"Speaker Mux", "CH 4_5", "CH 4_5 Mux"},
2541 {"Speaker Mux", "CH 2_3", "CH 2_3 Mux"},
2542 {"Speaker Mux", "CH 0_1", "CH 0_1 Mux"},
2543 {"ClassD Left", NULL, "Speaker Mux"},
2544 {"ClassD Right", NULL, "Speaker Mux"},
2545 {"ClassD Left", NULL, "PLLs"},
2546 {"ClassD Right", NULL, "PLLs"},
2547 {"Speaker Left", NULL, "Speaker Left Power"},
2548 {"Speaker Right", NULL, "Speaker Right Power"},
2549 {"Speaker Left", NULL, "ClassD Left"},
2550 {"Speaker Right", NULL, "ClassD Right"},
2551 /* Sub Path */
2552 {"Sub Mux", "CH 4", "CH 4_5 Mux"},
2553 {"Sub Mux", "CH 5", "CH 4_5 Mux"},
2554 {"Sub Mux", "CH 4 + 5", "CH 4_5 Mux"},
2555 {"Sub Mux", "CH 2", "CH 2_3 Mux"},
2556 {"Sub Mux", "CH 3", "CH 2_3 Mux"},
2557 {"Sub Mux", "CH 2 + 3", "CH 2_3 Mux"},
2558 {"Sub Mux", "CH 0", "CH 0_1 Mux"},
2559 {"Sub Mux", "CH 1", "CH 0_1 Mux"},
2560 {"Sub Mux", "CH 0 + 1", "CH 0_1 Mux"},
2561 {"Sub Mux", "ADC/DMic 1 Left", "Input Processor Channel 0"},
2562 {"Sub Mux", "ADC/DMic 1 Right", "Input Processor Channel 1"},
2563 {"Sub Mux", "ADC/DMic 1 Left Plus Right", "Input Processor Channel 0"},
2564 {"Sub Mux", "ADC/DMic 1 Left Plus Right", "Input Processor Channel 1"},
2565 {"Sub Mux", "DMic 2 Left", "DMic 2"},
2566 {"Sub Mux", "DMic 2 Right", "DMic 2"},
2567 {"Sub Mux", "DMic 2 Left Plus Right", "DMic 2"},
2568 {"Sub Mux", "ClassD Left", "ClassD Left"},
2569 {"Sub Mux", "ClassD Right", "ClassD Right"},
2570 {"Sub Mux", "ClassD Left Plus Right", "ClassD Left"},
2571 {"Sub Mux", "ClassD Left Plus Right", "ClassD Right"},
2572 {"Sub", NULL, "Sub Mux"},
2573 {"Sub", NULL, "PLLs"},
2574 {"Sub Out", NULL, "Sub Power"},
2575 {"Sub Out", NULL, "Sub"},
2576 /*****************
2577 * Capture Paths *
2578 *****************/
2579 {"Input Boost Channel 0 Mux", "Input 3", "Line In 3 Left"},
2580 {"Input Boost Channel 0 Mux", "Input 2", "Line In 2 Left"},
2581 {"Input Boost Channel 0 Mux", "Input 1", "Line In 1 Left"},
2582 {"Input Boost Channel 0 Mux", "D2S", "D2S 1"},
2583
2584 {"Input Boost Channel 1 Mux", "Input 3", "Line In 3 Right"},
2585 {"Input Boost Channel 1 Mux", "Input 2", "Line In 2 Right"},
2586 {"Input Boost Channel 1 Mux", "Input 1", "Line In 1 Right"},
2587 {"Input Boost Channel 1 Mux", "D2S", "D2S 2"},
2588
2589 {"ADC Channel 0 Mux", "Input 3 Boost Bypass", "Line In 3 Left"},
2590 {"ADC Channel 0 Mux", "Input 2 Boost Bypass", "Line In 2 Left"},
2591 {"ADC Channel 0 Mux", "Input 1 Boost Bypass", "Line In 1 Left"},
2592 {"ADC Channel 0 Mux", "Input Boost", "Input Boost Channel 0 Mux"},
2593
2594 {"ADC Channel 1 Mux", "Input 3 Boost Bypass", "Line In 3 Right"},
2595 {"ADC Channel 1 Mux", "Input 2 Boost Bypass", "Line In 2 Right"},
2596 {"ADC Channel 1 Mux", "Input 1 Boost Bypass", "Line In 1 Right"},
2597 {"ADC Channel 1 Mux", "Input Boost", "Input Boost Channel 1 Mux"},
2598
2599 {"Input Processor Channel 0 Mux", "ADC", "ADC Channel 0 Mux"},
2600 {"Input Processor Channel 0 Mux", "DMic", "DMic 1"},
2601
2602 {"Input Processor Channel 0", NULL, "PLLs"},
2603 {"Input Processor Channel 0", NULL, "Input Processor Channel 0 Mux"},
2604
2605 {"Input Processor Channel 1 Mux", "ADC", "ADC Channel 1 Mux"},
2606 {"Input Processor Channel 1 Mux", "DMic", "DMic 1"},
2607
2608 {"Input Processor Channel 1", NULL, "PLLs"},
2609 {"Input Processor Channel 1", NULL, "Input Processor Channel 1 Mux"},
2610
2611 {"Input Processor Channel 2", NULL, "PLLs"},
2612 {"Input Processor Channel 2", NULL, "DMic 2"},
2613
2614 {"Input Processor Channel 3", NULL, "PLLs"},
2615 {"Input Processor Channel 3", NULL, "DMic 2"},
2616
2617 {"DAI 1 Out Mux", "ADC/DMic 1", "Input Processor Channel 0"},
2618 {"DAI 1 Out Mux", "ADC/DMic 1", "Input Processor Channel 1"},
2619 {"DAI 1 Out Mux", "DMic 2", "Input Processor Channel 2"},
2620 {"DAI 1 Out Mux", "DMic 2", "Input Processor Channel 3"},
2621
2622 {"DAI 2 Out Mux", "ADC/DMic 1", "Input Processor Channel 0"},
2623 {"DAI 2 Out Mux", "ADC/DMic 1", "Input Processor Channel 1"},
2624 {"DAI 2 Out Mux", "DMic 2", "Input Processor Channel 2"},
2625 {"DAI 2 Out Mux", "DMic 2", "Input Processor Channel 3"},
2626
2627 {"DAI 3 Out Mux", "ADC/DMic 1", "Input Processor Channel 0"},
2628 {"DAI 3 Out Mux", "ADC/DMic 1", "Input Processor Channel 1"},
2629 {"DAI 3 Out Mux", "DMic 2", "Input Processor Channel 2"},
2630 {"DAI 3 Out Mux", "DMic 2", "Input Processor Channel 3"},
2631
2632 {"DAI 1 Out", NULL, "DAI 1 Out Mux"},
2633 {"DAI 2 Out", NULL, "DAI 2 Out Mux"},
2634 {"DAI 3 Out", NULL, "DAI 3 Out Mux"},
2635 };
2636
2637 /* This is used when BCLK is sourcing the PLLs */
2638 static int tscs454_set_sysclk(struct snd_soc_dai *dai,
2639 int clk_id, unsigned int freq, int dir)
2640 {
2641 struct snd_soc_component *component = dai->component;
2642 struct tscs454 *tscs454 = snd_soc_component_get_drvdata(component);
2643 unsigned int val;
2644 int bclk_dai;
2645 int ret;
2646
2647 dev_dbg(component->dev, "%s(): freq = %u\n", __func__, freq);
2648
2649 ret = snd_soc_component_read(component, R_PLLCTL, &val);
2650 if (ret < 0)
2651 return ret;
2652
2653 bclk_dai = (val & FM_PLLCTL_BCLKSEL) >> FB_PLLCTL_BCLKSEL;
2654 if (bclk_dai != dai->id)
2655 return 0;
2656
2657 tscs454->bclk_freq = freq;
2658 return set_sysclk(component);
2659 }
2660
2661 static int tscs454_set_bclk_ratio(struct snd_soc_dai *dai,
2662 unsigned int ratio)
2663 {
2664 unsigned int mask;
2665 int ret;
2666 struct snd_soc_component *component = dai->component;
2667 unsigned int val;
2668 int shift;
2669
2670 dev_dbg(component->dev, "set_bclk_ratio() id = %d ratio = %u\n",
2671 dai->id, ratio);
2672
2673 switch (dai->id) {
2674 case TSCS454_DAI1_ID:
2675 mask = FM_I2SCMC_BCMP1;
2676 shift = FB_I2SCMC_BCMP1;
2677 break;
2678 case TSCS454_DAI2_ID:
2679 mask = FM_I2SCMC_BCMP2;
2680 shift = FB_I2SCMC_BCMP2;
2681 break;
2682 case TSCS454_DAI3_ID:
2683 mask = FM_I2SCMC_BCMP3;
2684 shift = FB_I2SCMC_BCMP3;
2685 break;
2686 default:
2687 ret = -EINVAL;
2688 dev_err(component->dev, "Unknown audio interface (%d)\n", ret);
2689 return ret;
2690 }
2691
2692 switch (ratio) {
2693 case 32:
2694 val = I2SCMC_BCMP_32X;
2695 break;
2696 case 40:
2697 val = I2SCMC_BCMP_40X;
2698 break;
2699 case 64:
2700 val = I2SCMC_BCMP_64X;
2701 break;
2702 default:
2703 ret = -EINVAL;
2704 dev_err(component->dev, "Unsupported bclk ratio (%d)\n", ret);
2705 return ret;
2706 }
2707
2708 ret = snd_soc_component_update_bits(component,
2709 R_I2SCMC, mask, val << shift);
2710 if (ret < 0) {
2711 dev_err(component->dev,
2712 "Failed to set DAI BCLK ratio (%d)\n", ret);
2713 return ret;
2714 }
2715
2716 return 0;
2717 }
2718
2719 static inline int set_aif_master_from_fmt(struct snd_soc_component *component,
2720 struct aif *aif, unsigned int fmt)
2721 {
2722 int ret;
2723
2724 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
2725 case SND_SOC_DAIFMT_CBM_CFM:
2726 aif->master = true;
2727 break;
2728 case SND_SOC_DAIFMT_CBS_CFS:
2729 aif->master = false;
2730 break;
2731 default:
2732 ret = -EINVAL;
2733 dev_err(component->dev, "Unsupported format (%d)\n", ret);
2734 return ret;
2735 }
2736
2737 return 0;
2738 }
2739
2740 static inline int set_aif_tdm_delay(struct snd_soc_component *component,
2741 unsigned int dai_id, bool delay)
2742 {
2743 unsigned int reg;
2744 int ret;
2745
2746 switch (dai_id) {
2747 case TSCS454_DAI1_ID:
2748 reg = R_TDMCTL0;
2749 break;
2750 case TSCS454_DAI2_ID:
2751 reg = R_PCMP2CTL0;
2752 break;
2753 case TSCS454_DAI3_ID:
2754 reg = R_PCMP3CTL0;
2755 break;
2756 default:
2757 ret = -EINVAL;
2758 dev_err(component->dev,
2759 "DAI %d unknown (%d)\n", dai_id + 1, ret);
2760 return ret;
2761 }
2762 ret = snd_soc_component_update_bits(component,
2763 reg, FM_TDMCTL0_BDELAY, delay);
2764 if (ret < 0) {
2765 dev_err(component->dev, "Failed to setup tdm format (%d)\n",
2766 ret);
2767 return ret;
2768 }
2769
2770 return 0;
2771 }
2772
2773 static inline int set_aif_format_from_fmt(struct snd_soc_component *component,
2774 unsigned int dai_id, unsigned int fmt)
2775 {
2776 unsigned int reg;
2777 unsigned int val;
2778 int ret;
2779
2780 switch (dai_id) {
2781 case TSCS454_DAI1_ID:
2782 reg = R_I2SP1CTL;
2783 break;
2784 case TSCS454_DAI2_ID:
2785 reg = R_I2SP2CTL;
2786 break;
2787 case TSCS454_DAI3_ID:
2788 reg = R_I2SP3CTL;
2789 break;
2790 default:
2791 ret = -EINVAL;
2792 dev_err(component->dev,
2793 "DAI %d unknown (%d)\n", dai_id + 1, ret);
2794 return ret;
2795 }
2796
2797 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2798 case SND_SOC_DAIFMT_RIGHT_J:
2799 val = FV_FORMAT_RIGHT;
2800 break;
2801 case SND_SOC_DAIFMT_LEFT_J:
2802 val = FV_FORMAT_LEFT;
2803 break;
2804 case SND_SOC_DAIFMT_I2S:
2805 val = FV_FORMAT_I2S;
2806 break;
2807 case SND_SOC_DAIFMT_DSP_A:
2808 ret = set_aif_tdm_delay(component, dai_id, true);
2809 if (ret < 0)
2810 return ret;
2811 val = FV_FORMAT_TDM;
2812 break;
2813 case SND_SOC_DAIFMT_DSP_B:
2814 ret = set_aif_tdm_delay(component, dai_id, false);
2815 if (ret < 0)
2816 return ret;
2817 val = FV_FORMAT_TDM;
2818 break;
2819 default:
2820 ret = -EINVAL;
2821 dev_err(component->dev, "Format unsupported (%d)\n", ret);
2822 return ret;
2823 }
2824
2825 ret = snd_soc_component_update_bits(component,
2826 reg, FM_I2SPCTL_FORMAT, val);
2827 if (ret < 0) {
2828 dev_err(component->dev, "Failed to set DAI %d format (%d)\n",
2829 dai_id + 1, ret);
2830 return ret;
2831 }
2832
2833 return 0;
2834 }
2835
2836 static inline int
2837 set_aif_clock_format_from_fmt(struct snd_soc_component *component,
2838 unsigned int dai_id, unsigned int fmt)
2839 {
2840 unsigned int reg;
2841 unsigned int val;
2842 int ret;
2843
2844 switch (dai_id) {
2845 case TSCS454_DAI1_ID:
2846 reg = R_I2SP1CTL;
2847 break;
2848 case TSCS454_DAI2_ID:
2849 reg = R_I2SP2CTL;
2850 break;
2851 case TSCS454_DAI3_ID:
2852 reg = R_I2SP3CTL;
2853 break;
2854 default:
2855 ret = -EINVAL;
2856 dev_err(component->dev,
2857 "DAI %d unknown (%d)\n", dai_id + 1, ret);
2858 return ret;
2859 }
2860
2861 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2862 case SND_SOC_DAIFMT_NB_NF:
2863 val = FV_BCLKP_NOT_INVERTED | FV_LRCLKP_NOT_INVERTED;
2864 break;
2865 case SND_SOC_DAIFMT_NB_IF:
2866 val = FV_BCLKP_NOT_INVERTED | FV_LRCLKP_INVERTED;
2867 break;
2868 case SND_SOC_DAIFMT_IB_NF:
2869 val = FV_BCLKP_INVERTED | FV_LRCLKP_NOT_INVERTED;
2870 break;
2871 case SND_SOC_DAIFMT_IB_IF:
2872 val = FV_BCLKP_INVERTED | FV_LRCLKP_INVERTED;
2873 break;
2874 default:
2875 ret = -EINVAL;
2876 dev_err(component->dev, "Format unknown (%d)\n", ret);
2877 return ret;
2878 }
2879
2880 ret = snd_soc_component_update_bits(component, reg,
2881 FM_I2SPCTL_BCLKP | FM_I2SPCTL_LRCLKP, val);
2882 if (ret < 0) {
2883 dev_err(component->dev,
2884 "Failed to set clock polarity for DAI%d (%d)\n",
2885 dai_id + 1, ret);
2886 return ret;
2887 }
2888
2889 return 0;
2890 }
2891
2892 static int tscs454_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
2893 {
2894 struct snd_soc_component *component = dai->component;
2895 struct tscs454 *tscs454 = snd_soc_component_get_drvdata(component);
2896 struct aif *aif = &tscs454->aifs[dai->id];
2897 int ret;
2898
2899 ret = set_aif_master_from_fmt(component, aif, fmt);
2900 if (ret < 0)
2901 return ret;
2902
2903 ret = set_aif_format_from_fmt(component, dai->id, fmt);
2904 if (ret < 0)
2905 return ret;
2906
2907 ret = set_aif_clock_format_from_fmt(component, dai->id, fmt);
2908 if (ret < 0)
2909 return ret;
2910
2911 return 0;
2912 }
2913
2914 static int tscs454_dai1_set_tdm_slot(struct snd_soc_dai *dai,
2915 unsigned int tx_mask, unsigned int rx_mask, int slots,
2916 int slot_width)
2917 {
2918 struct snd_soc_component *component = dai->component;
2919 unsigned int val;
2920 int ret;
2921
2922 if (!slots)
2923 return 0;
2924
2925 if (tx_mask >= (1 << slots) || rx_mask >= (1 << slots)) {
2926 ret = -EINVAL;
2927 dev_err(component->dev, "Invalid TDM slot mask (%d)\n", ret);
2928 return ret;
2929 }
2930
2931 switch (slots) {
2932 case 2:
2933 val = FV_TDMSO_2 | FV_TDMSI_2;
2934 break;
2935 case 4:
2936 val = FV_TDMSO_4 | FV_TDMSI_4;
2937 break;
2938 case 6:
2939 val = FV_TDMSO_6 | FV_TDMSI_6;
2940 break;
2941 default:
2942 ret = -EINVAL;
2943 dev_err(component->dev, "Invalid number of slots (%d)\n", ret);
2944 return ret;
2945 }
2946
2947 switch (slot_width) {
2948 case 16:
2949 val = val | FV_TDMDSS_16;
2950 break;
2951 case 24:
2952 val = val | FV_TDMDSS_24;
2953 break;
2954 case 32:
2955 val = val | FV_TDMDSS_32;
2956 break;
2957 default:
2958 ret = -EINVAL;
2959 dev_err(component->dev, "Invalid TDM slot width (%d)\n", ret);
2960 return ret;
2961 }
2962 ret = snd_soc_component_write(component, R_TDMCTL1, val);
2963 if (ret < 0) {
2964 dev_err(component->dev, "Failed to set slots (%d)\n", ret);
2965 return ret;
2966 }
2967
2968 return 0;
2969 }
2970
2971 static int tscs454_dai23_set_tdm_slot(struct snd_soc_dai *dai,
2972 unsigned int tx_mask, unsigned int rx_mask, int slots,
2973 int slot_width)
2974 {
2975 struct snd_soc_component *component = dai->component;
2976 unsigned int reg;
2977 unsigned int val;
2978 int ret;
2979
2980 if (!slots)
2981 return 0;
2982
2983 if (tx_mask >= (1 << slots) || rx_mask >= (1 << slots)) {
2984 ret = -EINVAL;
2985 dev_err(component->dev, "Invalid TDM slot mask (%d)\n", ret);
2986 return ret;
2987 }
2988
2989 switch (dai->id) {
2990 case TSCS454_DAI2_ID:
2991 reg = R_PCMP2CTL1;
2992 break;
2993 case TSCS454_DAI3_ID:
2994 reg = R_PCMP3CTL1;
2995 break;
2996 default:
2997 ret = -EINVAL;
2998 dev_err(component->dev, "Unrecognized interface %d (%d)\n",
2999 dai->id, ret);
3000 return ret;
3001 }
3002
3003 switch (slots) {
3004 case 1:
3005 val = FV_PCMSOP_1 | FV_PCMSIP_1;
3006 break;
3007 case 2:
3008 val = FV_PCMSOP_2 | FV_PCMSIP_2;
3009 break;
3010 default:
3011 ret = -EINVAL;
3012 dev_err(component->dev, "Invalid number of slots (%d)\n", ret);
3013 return ret;
3014 }
3015
3016 switch (slot_width) {
3017 case 16:
3018 val = val | FV_PCMDSSP_16;
3019 break;
3020 case 24:
3021 val = val | FV_PCMDSSP_24;
3022 break;
3023 case 32:
3024 val = val | FV_PCMDSSP_32;
3025 break;
3026 default:
3027 ret = -EINVAL;
3028 dev_err(component->dev, "Invalid TDM slot width (%d)\n", ret);
3029 return ret;
3030 }
3031 ret = snd_soc_component_write(component, reg, val);
3032 if (ret < 0) {
3033 dev_err(component->dev, "Failed to set slots (%d)\n", ret);
3034 return ret;
3035 }
3036
3037 return 0;
3038 }
3039
3040 static int set_aif_fs(struct snd_soc_component *component,
3041 unsigned int id,
3042 unsigned int rate)
3043 {
3044 unsigned int reg;
3045 unsigned int br;
3046 unsigned int bm;
3047 int ret;
3048
3049 switch (rate) {
3050 case 8000:
3051 br = FV_I2SMBR_32;
3052 bm = FV_I2SMBM_0PT25;
3053 break;
3054 case 16000:
3055 br = FV_I2SMBR_32;
3056 bm = FV_I2SMBM_0PT5;
3057 break;
3058 case 24000:
3059 br = FV_I2SMBR_48;
3060 bm = FV_I2SMBM_0PT5;
3061 break;
3062 case 32000:
3063 br = FV_I2SMBR_32;
3064 bm = FV_I2SMBM_1;
3065 break;
3066 case 48000:
3067 br = FV_I2SMBR_48;
3068 bm = FV_I2SMBM_1;
3069 break;
3070 case 96000:
3071 br = FV_I2SMBR_48;
3072 bm = FV_I2SMBM_2;
3073 break;
3074 case 11025:
3075 br = FV_I2SMBR_44PT1;
3076 bm = FV_I2SMBM_0PT25;
3077 break;
3078 case 22050:
3079 br = FV_I2SMBR_44PT1;
3080 bm = FV_I2SMBM_0PT5;
3081 break;
3082 case 44100:
3083 br = FV_I2SMBR_44PT1;
3084 bm = FV_I2SMBM_1;
3085 break;
3086 case 88200:
3087 br = FV_I2SMBR_44PT1;
3088 bm = FV_I2SMBM_2;
3089 break;
3090 default:
3091 ret = -EINVAL;
3092 dev_err(component->dev, "Unsupported sample rate (%d)\n", ret);
3093 return ret;
3094 }
3095
3096 switch (id) {
3097 case TSCS454_DAI1_ID:
3098 reg = R_I2S1MRATE;
3099 break;
3100 case TSCS454_DAI2_ID:
3101 reg = R_I2S2MRATE;
3102 break;
3103 case TSCS454_DAI3_ID:
3104 reg = R_I2S3MRATE;
3105 break;
3106 default:
3107 ret = -EINVAL;
3108 dev_err(component->dev, "DAI ID not recognized (%d)\n", ret);
3109 return ret;
3110 }
3111
3112 ret = snd_soc_component_update_bits(component, reg,
3113 FM_I2SMRATE_I2SMBR | FM_I2SMRATE_I2SMBM, br|bm);
3114 if (ret < 0) {
3115 dev_err(component->dev,
3116 "Failed to update register (%d)\n", ret);
3117 return ret;
3118 }
3119
3120 return 0;
3121 }
3122
3123 static int set_aif_sample_format(struct snd_soc_component *component,
3124 snd_pcm_format_t format,
3125 int aif_id)
3126 {
3127 unsigned int reg;
3128 unsigned int width;
3129 int ret;
3130
3131 switch (format) {
3132 case SNDRV_PCM_FORMAT_S16_LE:
3133 width = FV_WL_16;
3134 break;
3135 case SNDRV_PCM_FORMAT_S20_3LE:
3136 width = FV_WL_20;
3137 break;
3138 case SNDRV_PCM_FORMAT_S24_3LE:
3139 width = FV_WL_24;
3140 break;
3141 case SNDRV_PCM_FORMAT_S24_LE:
3142 case SNDRV_PCM_FORMAT_S32_LE:
3143 width = FV_WL_32;
3144 break;
3145 default:
3146 ret = -EINVAL;
3147 dev_err(component->dev, "Unsupported format width (%d)\n", ret);
3148 return ret;
3149 }
3150
3151 switch (aif_id) {
3152 case TSCS454_DAI1_ID:
3153 reg = R_I2SP1CTL;
3154 break;
3155 case TSCS454_DAI2_ID:
3156 reg = R_I2SP2CTL;
3157 break;
3158 case TSCS454_DAI3_ID:
3159 reg = R_I2SP3CTL;
3160 break;
3161 default:
3162 ret = -EINVAL;
3163 dev_err(component->dev, "AIF ID not recognized (%d)\n", ret);
3164 return ret;
3165 }
3166
3167 ret = snd_soc_component_update_bits(component,
3168 reg, FM_I2SPCTL_WL, width);
3169 if (ret < 0) {
3170 dev_err(component->dev,
3171 "Failed to set sample width (%d)\n", ret);
3172 return ret;
3173 }
3174
3175 return 0;
3176 }
3177
3178 static int tscs454_hw_params(struct snd_pcm_substream *substream,
3179 struct snd_pcm_hw_params *params,
3180 struct snd_soc_dai *dai)
3181 {
3182 struct snd_soc_component *component = dai->component;
3183 struct tscs454 *tscs454 = snd_soc_component_get_drvdata(component);
3184 unsigned int fs = params_rate(params);
3185 struct aif *aif = &tscs454->aifs[dai->id];
3186 unsigned int val;
3187 int ret;
3188
3189 mutex_lock(&tscs454->aifs_status_lock);
3190
3191 dev_dbg(component->dev, "%s(): aif %d fs = %u\n", __func__,
3192 aif->id, fs);
3193
3194 if (!aif_active(&tscs454->aifs_status, aif->id)) {
3195 if (PLL_44_1K_RATE % fs)
3196 aif->pll = &tscs454->pll1;
3197 else
3198 aif->pll = &tscs454->pll2;
3199
3200 dev_dbg(component->dev, "Reserving pll %d for aif %d\n",
3201 aif->pll->id, aif->id);
3202
3203 reserve_pll(aif->pll);
3204 }
3205
3206 if (!aifs_active(&tscs454->aifs_status)) { /* First active aif */
3207 ret = snd_soc_component_read(component, R_ISRC, &val);
3208 if (ret < 0)
3209 goto exit;
3210
3211 if ((val & FM_ISRC_IBR) == FV_IBR_48)
3212 tscs454->internal_rate.pll = &tscs454->pll1;
3213 else
3214 tscs454->internal_rate.pll = &tscs454->pll2;
3215
3216 dev_dbg(component->dev, "Reserving pll %d for ir\n",
3217 tscs454->internal_rate.pll->id);
3218
3219 reserve_pll(tscs454->internal_rate.pll);
3220 }
3221
3222 ret = set_aif_fs(component, aif->id, fs);
3223 if (ret < 0) {
3224 dev_err(component->dev, "Failed to set aif fs (%d)\n", ret);
3225 goto exit;
3226 }
3227
3228 ret = set_aif_sample_format(component, params_format(params), aif->id);
3229 if (ret < 0) {
3230 dev_err(component->dev,
3231 "Failed to set aif sample format (%d)\n", ret);
3232 goto exit;
3233 }
3234
3235 set_aif_status_active(&tscs454->aifs_status, aif->id,
3236 substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
3237
3238 dev_dbg(component->dev, "Set aif %d active. Streams status is 0x%x\n",
3239 aif->id, tscs454->aifs_status.streams);
3240
3241 ret = 0;
3242 exit:
3243 mutex_unlock(&tscs454->aifs_status_lock);
3244
3245 return ret;
3246 }
3247
3248 static int tscs454_hw_free(struct snd_pcm_substream *substream,
3249 struct snd_soc_dai *dai)
3250 {
3251 struct snd_soc_component *component = dai->component;
3252 struct tscs454 *tscs454 = snd_soc_component_get_drvdata(component);
3253 struct aif *aif = &tscs454->aifs[dai->id];
3254
3255 return aif_free(component, aif,
3256 substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
3257 }
3258
3259 static int tscs454_prepare(struct snd_pcm_substream *substream,
3260 struct snd_soc_dai *dai)
3261 {
3262 int ret;
3263 struct snd_soc_component *component = dai->component;
3264 struct tscs454 *tscs454 = snd_soc_component_get_drvdata(component);
3265 struct aif *aif = &tscs454->aifs[dai->id];
3266
3267 ret = aif_prepare(component, aif);
3268 if (ret < 0)
3269 return ret;
3270
3271 return 0;
3272 }
3273
3274 static struct snd_soc_dai_ops const tscs454_dai1_ops = {
3275 .set_sysclk = tscs454_set_sysclk,
3276 .set_bclk_ratio = tscs454_set_bclk_ratio,
3277 .set_fmt = tscs454_set_dai_fmt,
3278 .set_tdm_slot = tscs454_dai1_set_tdm_slot,
3279 .hw_params = tscs454_hw_params,
3280 .hw_free = tscs454_hw_free,
3281 .prepare = tscs454_prepare,
3282 };
3283
3284 static struct snd_soc_dai_ops const tscs454_dai23_ops = {
3285 .set_sysclk = tscs454_set_sysclk,
3286 .set_bclk_ratio = tscs454_set_bclk_ratio,
3287 .set_fmt = tscs454_set_dai_fmt,
3288 .set_tdm_slot = tscs454_dai23_set_tdm_slot,
3289 .hw_params = tscs454_hw_params,
3290 .hw_free = tscs454_hw_free,
3291 .prepare = tscs454_prepare,
3292 };
3293
3294 static int tscs454_probe(struct snd_soc_component *component)
3295 {
3296 struct tscs454 *tscs454 = snd_soc_component_get_drvdata(component);
3297 unsigned int val;
3298 int ret = 0;
3299
3300 switch (tscs454->sysclk_src_id) {
3301 case PLL_INPUT_XTAL:
3302 val = FV_PLLISEL_XTAL;
3303 break;
3304 case PLL_INPUT_MCLK1:
3305 val = FV_PLLISEL_MCLK1;
3306 break;
3307 case PLL_INPUT_MCLK2:
3308 val = FV_PLLISEL_MCLK2;
3309 break;
3310 case PLL_INPUT_BCLK:
3311 val = FV_PLLISEL_BCLK;
3312 break;
3313 default:
3314 ret = -EINVAL;
3315 dev_err(component->dev, "Invalid sysclk src id (%d)\n", ret);
3316 return ret;
3317 }
3318
3319 ret = snd_soc_component_update_bits(component, R_PLLCTL,
3320 FM_PLLCTL_PLLISEL, val);
3321 if (ret < 0) {
3322 dev_err(component->dev, "Failed to set PLL input (%d)\n", ret);
3323 return ret;
3324 }
3325
3326 if (tscs454->sysclk_src_id < PLL_INPUT_BCLK)
3327 ret = set_sysclk(component);
3328
3329 return ret;
3330 }
3331
3332 static const struct snd_soc_component_driver soc_component_dev_tscs454 = {
3333 .probe = tscs454_probe,
3334 .dapm_widgets = tscs454_dapm_widgets,
3335 .num_dapm_widgets = ARRAY_SIZE(tscs454_dapm_widgets),
3336 .dapm_routes = tscs454_intercon,
3337 .num_dapm_routes = ARRAY_SIZE(tscs454_intercon),
3338 .controls = tscs454_snd_controls,
3339 .num_controls = ARRAY_SIZE(tscs454_snd_controls),
3340 };
3341
3342 #define TSCS454_RATES SNDRV_PCM_RATE_8000_96000
3343
3344 #define TSCS454_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE \
3345 | SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S24_LE \
3346 | SNDRV_PCM_FMTBIT_S32_LE)
3347
3348 static struct snd_soc_dai_driver tscs454_dais[] = {
3349 {
3350 .name = "tscs454-dai1",
3351 .id = TSCS454_DAI1_ID,
3352 .playback = {
3353 .stream_name = "DAI 1 Playback",
3354 .channels_min = 1,
3355 .channels_max = 6,
3356 .rates = TSCS454_RATES,
3357 .formats = TSCS454_FORMATS,},
3358 .capture = {
3359 .stream_name = "DAI 1 Capture",
3360 .channels_min = 1,
3361 .channels_max = 6,
3362 .rates = TSCS454_RATES,
3363 .formats = TSCS454_FORMATS,},
3364 .ops = &tscs454_dai1_ops,
3365 .symmetric_rates = 1,
3366 .symmetric_channels = 1,
3367 .symmetric_samplebits = 1,
3368 },
3369 {
3370 .name = "tscs454-dai2",
3371 .id = TSCS454_DAI2_ID,
3372 .playback = {
3373 .stream_name = "DAI 2 Playback",
3374 .channels_min = 1,
3375 .channels_max = 2,
3376 .rates = TSCS454_RATES,
3377 .formats = TSCS454_FORMATS,},
3378 .capture = {
3379 .stream_name = "DAI 2 Capture",
3380 .channels_min = 1,
3381 .channels_max = 2,
3382 .rates = TSCS454_RATES,
3383 .formats = TSCS454_FORMATS,},
3384 .ops = &tscs454_dai23_ops,
3385 .symmetric_rates = 1,
3386 .symmetric_channels = 1,
3387 .symmetric_samplebits = 1,
3388 },
3389 {
3390 .name = "tscs454-dai3",
3391 .id = TSCS454_DAI3_ID,
3392 .playback = {
3393 .stream_name = "DAI 3 Playback",
3394 .channels_min = 1,
3395 .channels_max = 2,
3396 .rates = TSCS454_RATES,
3397 .formats = TSCS454_FORMATS,},
3398 .capture = {
3399 .stream_name = "DAI 3 Capture",
3400 .channels_min = 1,
3401 .channels_max = 2,
3402 .rates = TSCS454_RATES,
3403 .formats = TSCS454_FORMATS,},
3404 .ops = &tscs454_dai23_ops,
3405 .symmetric_rates = 1,
3406 .symmetric_channels = 1,
3407 .symmetric_samplebits = 1,
3408 },
3409 };
3410
3411 static char const * const src_names[] = {
3412 "xtal", "mclk1", "mclk2", "bclk"};
3413
3414 static int tscs454_i2c_probe(struct i2c_client *i2c,
3415 const struct i2c_device_id *id)
3416 {
3417 struct tscs454 *tscs454;
3418 int src;
3419 int ret;
3420
3421 tscs454 = devm_kzalloc(&i2c->dev, sizeof(*tscs454), GFP_KERNEL);
3422 if (!tscs454)
3423 return -ENOMEM;
3424
3425 ret = tscs454_data_init(tscs454, i2c);
3426 if (ret < 0)
3427 return ret;
3428
3429 i2c_set_clientdata(i2c, tscs454);
3430
3431 for (src = PLL_INPUT_XTAL; src < PLL_INPUT_BCLK; src++) {
3432 tscs454->sysclk = devm_clk_get(&i2c->dev, src_names[src]);
3433 if (!IS_ERR(tscs454->sysclk)) {
3434 break;
3435 } else if (PTR_ERR(tscs454->sysclk) != -ENOENT) {
3436 ret = PTR_ERR(tscs454->sysclk);
3437 dev_err(&i2c->dev, "Failed to get sysclk (%d)\n", ret);
3438 return ret;
3439 }
3440 }
3441 dev_dbg(&i2c->dev, "PLL input is %s\n", src_names[src]);
3442 tscs454->sysclk_src_id = src;
3443
3444 ret = regmap_write(tscs454->regmap,
3445 R_RESET, FV_RESET_PWR_ON_DEFAULTS);
3446 if (ret < 0) {
3447 dev_err(&i2c->dev, "Failed to reset the component (%d)\n", ret);
3448 return ret;
3449 }
3450 regcache_mark_dirty(tscs454->regmap);
3451
3452 ret = regmap_register_patch(tscs454->regmap, tscs454_patch,
3453 ARRAY_SIZE(tscs454_patch));
3454 if (ret < 0) {
3455 dev_err(&i2c->dev, "Failed to apply patch (%d)\n", ret);
3456 return ret;
3457 }
3458 /* Sync pg sel reg with cache */
3459 regmap_write(tscs454->regmap, R_PAGESEL, 0x00);
3460
3461 ret = devm_snd_soc_register_component(&i2c->dev, &soc_component_dev_tscs454,
3462 tscs454_dais, ARRAY_SIZE(tscs454_dais));
3463 if (ret) {
3464 dev_err(&i2c->dev, "Failed to register component (%d)\n", ret);
3465 return ret;
3466 }
3467
3468 return 0;
3469 }
3470
3471 static const struct i2c_device_id tscs454_i2c_id[] = {
3472 { "tscs454", 0 },
3473 { }
3474 };
3475 MODULE_DEVICE_TABLE(i2c, tscs454_i2c_id);
3476
3477 static const struct of_device_id tscs454_of_match[] = {
3478 { .compatible = "tempo,tscs454", },
3479 { }
3480 };
3481 MODULE_DEVICE_TABLE(of, tscs454_of_match);
3482
3483 static struct i2c_driver tscs454_i2c_driver = {
3484 .driver = {
3485 .name = "tscs454",
3486 .of_match_table = tscs454_of_match,
3487 },
3488 .probe = tscs454_i2c_probe,
3489 .id_table = tscs454_i2c_id,
3490 };
3491
3492 module_i2c_driver(tscs454_i2c_driver);
3493
3494 MODULE_AUTHOR("Tempo Semiconductor <steven.eckhoff.opensource@gmail.com");
3495 MODULE_DESCRIPTION("ASoC TSCS454 driver");
3496 MODULE_LICENSE("GPL v2");
Linux with added FPC-III support