sound/soc/codecs/wm8753.h

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2 /*
   3  * wm8753.h  --  audio driver for WM8753
   4  *
   5  * Copyright 2003 Wolfson Microelectronics PLC.
   6  * Author: Liam Girdwood <lrg@slimlogic.co.uk>
   7  */
   8
   9 #ifndef _WM8753_H
  10 #define _WM8753_H
  11
  12 /* WM8753 register space */
  13
  14 #define WM8753_DAC              0x01
  15 #define WM8753_ADC              0x02
  16 #define WM8753_PCM              0x03
  17 #define WM8753_HIFI             0x04
  18 #define WM8753_IOCTL            0x05
  19 #define WM8753_SRATE1           0x06
  20 #define WM8753_SRATE2           0x07
  21 #define WM8753_LDAC             0x08
  22 #define WM8753_RDAC             0x09
  23 #define WM8753_BASS             0x0a
  24 #define WM8753_TREBLE           0x0b
  25 #define WM8753_ALC1             0x0c
  26 #define WM8753_ALC2             0x0d
  27 #define WM8753_ALC3             0x0e
  28 #define WM8753_NGATE            0x0f
  29 #define WM8753_LADC             0x10
  30 #define WM8753_RADC             0x11
  31 #define WM8753_ADCTL1           0x12
  32 #define WM8753_3D               0x13
  33 #define WM8753_PWR1             0x14
  34 #define WM8753_PWR2             0x15
  35 #define WM8753_PWR3             0x16
  36 #define WM8753_PWR4             0x17
  37 #define WM8753_ID               0x18
  38 #define WM8753_INTPOL           0x19
  39 #define WM8753_INTEN            0x1a
  40 #define WM8753_GPIO1            0x1b
  41 #define WM8753_GPIO2            0x1c
  42 #define WM8753_RESET            0x1f
  43 #define WM8753_RECMIX1          0x20
  44 #define WM8753_RECMIX2          0x21
  45 #define WM8753_LOUTM1           0x22
  46 #define WM8753_LOUTM2           0x23
  47 #define WM8753_ROUTM1           0x24
  48 #define WM8753_ROUTM2           0x25
  49 #define WM8753_MOUTM1           0x26
  50 #define WM8753_MOUTM2           0x27
  51 #define WM8753_LOUT1V           0x28
  52 #define WM8753_ROUT1V           0x29
  53 #define WM8753_LOUT2V           0x2a
  54 #define WM8753_ROUT2V           0x2b
  55 #define WM8753_MOUTV            0x2c
  56 #define WM8753_OUTCTL           0x2d
  57 #define WM8753_ADCIN            0x2e
  58 #define WM8753_INCTL1           0x2f
  59 #define WM8753_INCTL2           0x30
  60 #define WM8753_LINVOL           0x31
  61 #define WM8753_RINVOL           0x32
  62 #define WM8753_MICBIAS          0x33
  63 #define WM8753_CLOCK            0x34
  64 #define WM8753_PLL1CTL1         0x35
  65 #define WM8753_PLL1CTL2         0x36
  66 #define WM8753_PLL1CTL3         0x37
  67 #define WM8753_PLL1CTL4         0x38
  68 #define WM8753_PLL2CTL1         0x39
  69 #define WM8753_PLL2CTL2         0x3a
  70 #define WM8753_PLL2CTL3         0x3b
  71 #define WM8753_PLL2CTL4         0x3c
  72 #define WM8753_BIASCTL          0x3d
  73 #define WM8753_ADCTL2           0x3f
  74
  75 #define WM8753_PLL1                     0
  76 #define WM8753_PLL2                     1
  77
  78 /* clock inputs */
  79 #define WM8753_MCLK             0
  80 #define WM8753_PCMCLK           1
  81
  82 /* clock divider id's */
  83 #define WM8753_PCMDIV           0
  84 #define WM8753_BCLKDIV          1
  85 #define WM8753_VXCLKDIV         2
  86
  87 /* PCM clock dividers */
  88 #define WM8753_PCM_DIV_1        (0 << 6)
  89 #define WM8753_PCM_DIV_3        (2 << 6)
  90 #define WM8753_PCM_DIV_5_5      (3 << 6)
  91 #define WM8753_PCM_DIV_2        (4 << 6)
  92 #define WM8753_PCM_DIV_4        (5 << 6)
  93 #define WM8753_PCM_DIV_6        (6 << 6)
  94 #define WM8753_PCM_DIV_8        (7 << 6)
  95
  96 /* BCLK clock dividers */
  97 #define WM8753_BCLK_DIV_1       (0 << 3)
  98 #define WM8753_BCLK_DIV_2       (1 << 3)
  99 #define WM8753_BCLK_DIV_4       (2 << 3)
 100 #define WM8753_BCLK_DIV_8       (3 << 3)
 101 #define WM8753_BCLK_DIV_16      (4 << 3)
 102
 103 /* VXCLK clock dividers */
 104 #define WM8753_VXCLK_DIV_1      (0 << 6)
 105 #define WM8753_VXCLK_DIV_2      (1 << 6)
 106 #define WM8753_VXCLK_DIV_4      (2 << 6)
 107 #define WM8753_VXCLK_DIV_8      (3 << 6)
 108 #define WM8753_VXCLK_DIV_16     (4 << 6)
 109
 110 #endif