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ARM: dts: omap5: Add bus_dma_limit for L3 bus
[linux/fpc-iii.git] / sound / soc / codecs / wm8900.c
blob271235a69c016815adda27ca1e8ee97473bdac64
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * wm8900.c -- WM8900 ALSA Soc Audio driver
4 *
5 * Copyright 2007, 2008 Wolfson Microelectronics PLC.
6 *
7 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
8 *
9 * TODO:
10 * - Tristating.
11 * - TDM.
12 * - Jack detect.
13 * - FLL source configuration, currently only MCLK is supported.
14 */
15
16 #include <linux/module.h>
17 #include <linux/moduleparam.h>
18 #include <linux/kernel.h>
19 #include <linux/init.h>
20 #include <linux/delay.h>
21 #include <linux/pm.h>
22 #include <linux/i2c.h>
23 #include <linux/regmap.h>
24 #include <linux/spi/spi.h>
25 #include <linux/slab.h>
26 #include <sound/core.h>
27 #include <sound/pcm.h>
28 #include <sound/pcm_params.h>
29 #include <sound/soc.h>
30 #include <sound/initval.h>
31 #include <sound/tlv.h>
32
33 #include "wm8900.h"
34
35 /* WM8900 register space */
36 #define WM8900_REG_RESET 0x0
37 #define WM8900_REG_ID 0x0
38 #define WM8900_REG_POWER1 0x1
39 #define WM8900_REG_POWER2 0x2
40 #define WM8900_REG_POWER3 0x3
41 #define WM8900_REG_AUDIO1 0x4
42 #define WM8900_REG_AUDIO2 0x5
43 #define WM8900_REG_CLOCKING1 0x6
44 #define WM8900_REG_CLOCKING2 0x7
45 #define WM8900_REG_AUDIO3 0x8
46 #define WM8900_REG_AUDIO4 0x9
47 #define WM8900_REG_DACCTRL 0xa
48 #define WM8900_REG_LDAC_DV 0xb
49 #define WM8900_REG_RDAC_DV 0xc
50 #define WM8900_REG_SIDETONE 0xd
51 #define WM8900_REG_ADCCTRL 0xe
52 #define WM8900_REG_LADC_DV 0xf
53 #define WM8900_REG_RADC_DV 0x10
54 #define WM8900_REG_GPIO 0x12
55 #define WM8900_REG_INCTL 0x15
56 #define WM8900_REG_LINVOL 0x16
57 #define WM8900_REG_RINVOL 0x17
58 #define WM8900_REG_INBOOSTMIX1 0x18
59 #define WM8900_REG_INBOOSTMIX2 0x19
60 #define WM8900_REG_ADCPATH 0x1a
61 #define WM8900_REG_AUXBOOST 0x1b
62 #define WM8900_REG_ADDCTL 0x1e
63 #define WM8900_REG_FLLCTL1 0x24
64 #define WM8900_REG_FLLCTL2 0x25
65 #define WM8900_REG_FLLCTL3 0x26
66 #define WM8900_REG_FLLCTL4 0x27
67 #define WM8900_REG_FLLCTL5 0x28
68 #define WM8900_REG_FLLCTL6 0x29
69 #define WM8900_REG_LOUTMIXCTL1 0x2c
70 #define WM8900_REG_ROUTMIXCTL1 0x2d
71 #define WM8900_REG_BYPASS1 0x2e
72 #define WM8900_REG_BYPASS2 0x2f
73 #define WM8900_REG_AUXOUT_CTL 0x30
74 #define WM8900_REG_LOUT1CTL 0x33
75 #define WM8900_REG_ROUT1CTL 0x34
76 #define WM8900_REG_LOUT2CTL 0x35
77 #define WM8900_REG_ROUT2CTL 0x36
78 #define WM8900_REG_HPCTL1 0x3a
79 #define WM8900_REG_OUTBIASCTL 0x73
80
81 #define WM8900_MAXREG 0x80
82
83 #define WM8900_REG_ADDCTL_OUT1_DIS 0x80
84 #define WM8900_REG_ADDCTL_OUT2_DIS 0x40
85 #define WM8900_REG_ADDCTL_VMID_DIS 0x20
86 #define WM8900_REG_ADDCTL_BIAS_SRC 0x10
87 #define WM8900_REG_ADDCTL_VMID_SOFTST 0x04
88 #define WM8900_REG_ADDCTL_TEMP_SD 0x02
89
90 #define WM8900_REG_GPIO_TEMP_ENA 0x2
91
92 #define WM8900_REG_POWER1_STARTUP_BIAS_ENA 0x0100
93 #define WM8900_REG_POWER1_BIAS_ENA 0x0008
94 #define WM8900_REG_POWER1_VMID_BUF_ENA 0x0004
95 #define WM8900_REG_POWER1_FLL_ENA 0x0040
96
97 #define WM8900_REG_POWER2_SYSCLK_ENA 0x8000
98 #define WM8900_REG_POWER2_ADCL_ENA 0x0002
99 #define WM8900_REG_POWER2_ADCR_ENA 0x0001
100
101 #define WM8900_REG_POWER3_DACL_ENA 0x0002
102 #define WM8900_REG_POWER3_DACR_ENA 0x0001
103
104 #define WM8900_REG_AUDIO1_AIF_FMT_MASK 0x0018
105 #define WM8900_REG_AUDIO1_LRCLK_INV 0x0080
106 #define WM8900_REG_AUDIO1_BCLK_INV 0x0100
107
108 #define WM8900_REG_CLOCKING1_BCLK_DIR 0x1
109 #define WM8900_REG_CLOCKING1_MCLK_SRC 0x100
110 #define WM8900_REG_CLOCKING1_BCLK_MASK 0x01e
111 #define WM8900_REG_CLOCKING1_OPCLK_MASK 0x7000
112
113 #define WM8900_REG_CLOCKING2_ADC_CLKDIV 0xe0
114 #define WM8900_REG_CLOCKING2_DAC_CLKDIV 0x1c
115
116 #define WM8900_REG_DACCTRL_MUTE 0x004
117 #define WM8900_REG_DACCTRL_DAC_SB_FILT 0x100
118 #define WM8900_REG_DACCTRL_AIF_LRCLKRATE 0x400
119
120 #define WM8900_REG_AUDIO3_ADCLRC_DIR 0x0800
121
122 #define WM8900_REG_AUDIO4_DACLRC_DIR 0x0800
123
124 #define WM8900_REG_FLLCTL1_OSC_ENA 0x100
125
126 #define WM8900_REG_FLLCTL6_FLL_SLOW_LOCK_REF 0x100
127
128 #define WM8900_REG_HPCTL1_HP_IPSTAGE_ENA 0x80
129 #define WM8900_REG_HPCTL1_HP_OPSTAGE_ENA 0x40
130 #define WM8900_REG_HPCTL1_HP_CLAMP_IP 0x20
131 #define WM8900_REG_HPCTL1_HP_CLAMP_OP 0x10
132 #define WM8900_REG_HPCTL1_HP_SHORT 0x08
133 #define WM8900_REG_HPCTL1_HP_SHORT2 0x04
134
135 #define WM8900_LRC_MASK 0x03ff
136
137 struct wm8900_priv {
138 struct regmap *regmap;
139
140 u32 fll_in; /* FLL input frequency */
141 u32 fll_out; /* FLL output frequency */
142 };
143
144 /*
145 * wm8900 register cache. We can't read the entire register space and we
146 * have slow control buses so we cache the registers.
147 */
148 static const struct reg_default wm8900_reg_defaults[] = {
149 { 1, 0x0000 },
150 { 2, 0xc000 },
151 { 3, 0x0000 },
152 { 4, 0x4050 },
153 { 5, 0x4000 },
154 { 6, 0x0008 },
155 { 7, 0x0000 },
156 { 8, 0x0040 },
157 { 9, 0x0040 },
158 { 10, 0x1004 },
159 { 11, 0x00c0 },
160 { 12, 0x00c0 },
161 { 13, 0x0000 },
162 { 14, 0x0100 },
163 { 15, 0x00c0 },
164 { 16, 0x00c0 },
165 { 17, 0x0000 },
166 { 18, 0xb001 },
167 { 19, 0x0000 },
168 { 20, 0x0000 },
169 { 21, 0x0044 },
170 { 22, 0x004c },
171 { 23, 0x004c },
172 { 24, 0x0044 },
173 { 25, 0x0044 },
174 { 26, 0x0000 },
175 { 27, 0x0044 },
176 { 28, 0x0000 },
177 { 29, 0x0000 },
178 { 30, 0x0002 },
179 { 31, 0x0000 },
180 { 32, 0x0000 },
181 { 33, 0x0000 },
182 { 34, 0x0000 },
183 { 35, 0x0000 },
184 { 36, 0x0008 },
185 { 37, 0x0000 },
186 { 38, 0x0000 },
187 { 39, 0x0008 },
188 { 40, 0x0097 },
189 { 41, 0x0100 },
190 { 42, 0x0000 },
191 { 43, 0x0000 },
192 { 44, 0x0050 },
193 { 45, 0x0050 },
194 { 46, 0x0055 },
195 { 47, 0x0055 },
196 { 48, 0x0055 },
197 { 49, 0x0000 },
198 { 50, 0x0000 },
199 { 51, 0x0079 },
200 { 52, 0x0079 },
201 { 53, 0x0079 },
202 { 54, 0x0079 },
203 { 55, 0x0000 },
204 };
205
206 static bool wm8900_volatile_register(struct device *dev, unsigned int reg)
207 {
208 switch (reg) {
209 case WM8900_REG_ID:
210 return true;
211 default:
212 return false;
213 }
214 }
215
216 static void wm8900_reset(struct snd_soc_component *component)
217 {
218 snd_soc_component_write(component, WM8900_REG_RESET, 0);
219 }
220
221 static int wm8900_hp_event(struct snd_soc_dapm_widget *w,
222 struct snd_kcontrol *kcontrol, int event)
223 {
224 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
225 u16 hpctl1 = snd_soc_component_read32(component, WM8900_REG_HPCTL1);
226
227 switch (event) {
228 case SND_SOC_DAPM_PRE_PMU:
229 /* Clamp headphone outputs */
230 hpctl1 = WM8900_REG_HPCTL1_HP_CLAMP_IP |
231 WM8900_REG_HPCTL1_HP_CLAMP_OP;
232 snd_soc_component_write(component, WM8900_REG_HPCTL1, hpctl1);
233 break;
234
235 case SND_SOC_DAPM_POST_PMU:
236 /* Enable the input stage */
237 hpctl1 &= ~WM8900_REG_HPCTL1_HP_CLAMP_IP;
238 hpctl1 |= WM8900_REG_HPCTL1_HP_SHORT |
239 WM8900_REG_HPCTL1_HP_SHORT2 |
240 WM8900_REG_HPCTL1_HP_IPSTAGE_ENA;
241 snd_soc_component_write(component, WM8900_REG_HPCTL1, hpctl1);
242
243 msleep(400);
244
245 /* Enable the output stage */
246 hpctl1 &= ~WM8900_REG_HPCTL1_HP_CLAMP_OP;
247 hpctl1 |= WM8900_REG_HPCTL1_HP_OPSTAGE_ENA;
248 snd_soc_component_write(component, WM8900_REG_HPCTL1, hpctl1);
249
250 /* Remove the shorts */
251 hpctl1 &= ~WM8900_REG_HPCTL1_HP_SHORT2;
252 snd_soc_component_write(component, WM8900_REG_HPCTL1, hpctl1);
253 hpctl1 &= ~WM8900_REG_HPCTL1_HP_SHORT;
254 snd_soc_component_write(component, WM8900_REG_HPCTL1, hpctl1);
255 break;
256
257 case SND_SOC_DAPM_PRE_PMD:
258 /* Short the output */
259 hpctl1 |= WM8900_REG_HPCTL1_HP_SHORT;
260 snd_soc_component_write(component, WM8900_REG_HPCTL1, hpctl1);
261
262 /* Disable the output stage */
263 hpctl1 &= ~WM8900_REG_HPCTL1_HP_OPSTAGE_ENA;
264 snd_soc_component_write(component, WM8900_REG_HPCTL1, hpctl1);
265
266 /* Clamp the outputs and power down input */
267 hpctl1 |= WM8900_REG_HPCTL1_HP_CLAMP_IP |
268 WM8900_REG_HPCTL1_HP_CLAMP_OP;
269 hpctl1 &= ~WM8900_REG_HPCTL1_HP_IPSTAGE_ENA;
270 snd_soc_component_write(component, WM8900_REG_HPCTL1, hpctl1);
271 break;
272
273 case SND_SOC_DAPM_POST_PMD:
274 /* Disable everything */
275 snd_soc_component_write(component, WM8900_REG_HPCTL1, 0);
276 break;
277
278 default:
279 WARN(1, "Invalid event %d\n", event);
280 break;
281 }
282
283 return 0;
284 }
285
286 static const DECLARE_TLV_DB_SCALE(out_pga_tlv, -5700, 100, 0);
287
288 static const DECLARE_TLV_DB_SCALE(out_mix_tlv, -1500, 300, 0);
289
290 static const DECLARE_TLV_DB_SCALE(in_boost_tlv, -1200, 600, 0);
291
292 static const DECLARE_TLV_DB_SCALE(in_pga_tlv, -1200, 100, 0);
293
294 static const DECLARE_TLV_DB_SCALE(dac_boost_tlv, 0, 600, 0);
295
296 static const DECLARE_TLV_DB_SCALE(dac_tlv, -7200, 75, 1);
297
298 static const DECLARE_TLV_DB_SCALE(adc_svol_tlv, -3600, 300, 0);
299
300 static const DECLARE_TLV_DB_SCALE(adc_tlv, -7200, 75, 1);
301
302 static const char *mic_bias_level_txt[] = { "0.9*AVDD", "0.65*AVDD" };
303
304 static SOC_ENUM_SINGLE_DECL(mic_bias_level,
305 WM8900_REG_INCTL, 8, mic_bias_level_txt);
306
307 static const char *dac_mute_rate_txt[] = { "Fast", "Slow" };
308
309 static SOC_ENUM_SINGLE_DECL(dac_mute_rate,
310 WM8900_REG_DACCTRL, 7, dac_mute_rate_txt);
311
312 static const char *dac_deemphasis_txt[] = {
313 "Disabled", "32kHz", "44.1kHz", "48kHz"
314 };
315
316 static SOC_ENUM_SINGLE_DECL(dac_deemphasis,
317 WM8900_REG_DACCTRL, 4, dac_deemphasis_txt);
318
319 static const char *adc_hpf_cut_txt[] = {
320 "Hi-fi mode", "Voice mode 1", "Voice mode 2", "Voice mode 3"
321 };
322
323 static SOC_ENUM_SINGLE_DECL(adc_hpf_cut,
324 WM8900_REG_ADCCTRL, 5, adc_hpf_cut_txt);
325
326 static const char *lr_txt[] = {
327 "Left", "Right"
328 };
329
330 static SOC_ENUM_SINGLE_DECL(aifl_src,
331 WM8900_REG_AUDIO1, 15, lr_txt);
332
333 static SOC_ENUM_SINGLE_DECL(aifr_src,
334 WM8900_REG_AUDIO1, 14, lr_txt);
335
336 static SOC_ENUM_SINGLE_DECL(dacl_src,
337 WM8900_REG_AUDIO2, 15, lr_txt);
338
339 static SOC_ENUM_SINGLE_DECL(dacr_src,
340 WM8900_REG_AUDIO2, 14, lr_txt);
341
342 static const char *sidetone_txt[] = {
343 "Disabled", "Left ADC", "Right ADC"
344 };
345
346 static SOC_ENUM_SINGLE_DECL(dacl_sidetone,
347 WM8900_REG_SIDETONE, 2, sidetone_txt);
348
349 static SOC_ENUM_SINGLE_DECL(dacr_sidetone,
350 WM8900_REG_SIDETONE, 0, sidetone_txt);
351
352 static const struct snd_kcontrol_new wm8900_snd_controls[] = {
353 SOC_ENUM("Mic Bias Level", mic_bias_level),
354
355 SOC_SINGLE_TLV("Left Input PGA Volume", WM8900_REG_LINVOL, 0, 31, 0,
356 in_pga_tlv),
357 SOC_SINGLE("Left Input PGA Switch", WM8900_REG_LINVOL, 6, 1, 1),
358 SOC_SINGLE("Left Input PGA ZC Switch", WM8900_REG_LINVOL, 7, 1, 0),
359
360 SOC_SINGLE_TLV("Right Input PGA Volume", WM8900_REG_RINVOL, 0, 31, 0,
361 in_pga_tlv),
362 SOC_SINGLE("Right Input PGA Switch", WM8900_REG_RINVOL, 6, 1, 1),
363 SOC_SINGLE("Right Input PGA ZC Switch", WM8900_REG_RINVOL, 7, 1, 0),
364
365 SOC_SINGLE("DAC Soft Mute Switch", WM8900_REG_DACCTRL, 6, 1, 1),
366 SOC_ENUM("DAC Mute Rate", dac_mute_rate),
367 SOC_SINGLE("DAC Mono Switch", WM8900_REG_DACCTRL, 9, 1, 0),
368 SOC_ENUM("DAC Deemphasis", dac_deemphasis),
369 SOC_SINGLE("DAC Sigma-Delta Modulator Clock Switch", WM8900_REG_DACCTRL,
370 12, 1, 0),
371
372 SOC_SINGLE("ADC HPF Switch", WM8900_REG_ADCCTRL, 8, 1, 0),
373 SOC_ENUM("ADC HPF Cut-Off", adc_hpf_cut),
374 SOC_DOUBLE("ADC Invert Switch", WM8900_REG_ADCCTRL, 1, 0, 1, 0),
375 SOC_SINGLE_TLV("Left ADC Sidetone Volume", WM8900_REG_SIDETONE, 9, 12, 0,
376 adc_svol_tlv),
377 SOC_SINGLE_TLV("Right ADC Sidetone Volume", WM8900_REG_SIDETONE, 5, 12, 0,
378 adc_svol_tlv),
379 SOC_ENUM("Left Digital Audio Source", aifl_src),
380 SOC_ENUM("Right Digital Audio Source", aifr_src),
381
382 SOC_SINGLE_TLV("DAC Input Boost Volume", WM8900_REG_AUDIO2, 10, 4, 0,
383 dac_boost_tlv),
384 SOC_ENUM("Left DAC Source", dacl_src),
385 SOC_ENUM("Right DAC Source", dacr_src),
386 SOC_ENUM("Left DAC Sidetone", dacl_sidetone),
387 SOC_ENUM("Right DAC Sidetone", dacr_sidetone),
388 SOC_DOUBLE("DAC Invert Switch", WM8900_REG_DACCTRL, 1, 0, 1, 0),
389
390 SOC_DOUBLE_R_TLV("Digital Playback Volume",
391 WM8900_REG_LDAC_DV, WM8900_REG_RDAC_DV,
392 1, 96, 0, dac_tlv),
393 SOC_DOUBLE_R_TLV("Digital Capture Volume",
394 WM8900_REG_LADC_DV, WM8900_REG_RADC_DV, 1, 119, 0, adc_tlv),
395
396 SOC_SINGLE_TLV("LINPUT3 Bypass Volume", WM8900_REG_LOUTMIXCTL1, 4, 7, 0,
397 out_mix_tlv),
398 SOC_SINGLE_TLV("RINPUT3 Bypass Volume", WM8900_REG_ROUTMIXCTL1, 4, 7, 0,
399 out_mix_tlv),
400 SOC_SINGLE_TLV("Left AUX Bypass Volume", WM8900_REG_AUXOUT_CTL, 4, 7, 0,
401 out_mix_tlv),
402 SOC_SINGLE_TLV("Right AUX Bypass Volume", WM8900_REG_AUXOUT_CTL, 0, 7, 0,
403 out_mix_tlv),
404
405 SOC_SINGLE_TLV("LeftIn to RightOut Mixer Volume", WM8900_REG_BYPASS1, 0, 7, 0,
406 out_mix_tlv),
407 SOC_SINGLE_TLV("LeftIn to LeftOut Mixer Volume", WM8900_REG_BYPASS1, 4, 7, 0,
408 out_mix_tlv),
409 SOC_SINGLE_TLV("RightIn to LeftOut Mixer Volume", WM8900_REG_BYPASS2, 0, 7, 0,
410 out_mix_tlv),
411 SOC_SINGLE_TLV("RightIn to RightOut Mixer Volume", WM8900_REG_BYPASS2, 4, 7, 0,
412 out_mix_tlv),
413
414 SOC_SINGLE_TLV("IN2L Boost Volume", WM8900_REG_INBOOSTMIX1, 0, 3, 0,
415 in_boost_tlv),
416 SOC_SINGLE_TLV("IN3L Boost Volume", WM8900_REG_INBOOSTMIX1, 4, 3, 0,
417 in_boost_tlv),
418 SOC_SINGLE_TLV("IN2R Boost Volume", WM8900_REG_INBOOSTMIX2, 0, 3, 0,
419 in_boost_tlv),
420 SOC_SINGLE_TLV("IN3R Boost Volume", WM8900_REG_INBOOSTMIX2, 4, 3, 0,
421 in_boost_tlv),
422 SOC_SINGLE_TLV("Left AUX Boost Volume", WM8900_REG_AUXBOOST, 4, 3, 0,
423 in_boost_tlv),
424 SOC_SINGLE_TLV("Right AUX Boost Volume", WM8900_REG_AUXBOOST, 0, 3, 0,
425 in_boost_tlv),
426
427 SOC_DOUBLE_R_TLV("LINEOUT1 Volume", WM8900_REG_LOUT1CTL, WM8900_REG_ROUT1CTL,
428 0, 63, 0, out_pga_tlv),
429 SOC_DOUBLE_R("LINEOUT1 Switch", WM8900_REG_LOUT1CTL, WM8900_REG_ROUT1CTL,
430 6, 1, 1),
431 SOC_DOUBLE_R("LINEOUT1 ZC Switch", WM8900_REG_LOUT1CTL, WM8900_REG_ROUT1CTL,
432 7, 1, 0),
433
434 SOC_DOUBLE_R_TLV("LINEOUT2 Volume",
435 WM8900_REG_LOUT2CTL, WM8900_REG_ROUT2CTL,
436 0, 63, 0, out_pga_tlv),
437 SOC_DOUBLE_R("LINEOUT2 Switch",
438 WM8900_REG_LOUT2CTL, WM8900_REG_ROUT2CTL, 6, 1, 1),
439 SOC_DOUBLE_R("LINEOUT2 ZC Switch",
440 WM8900_REG_LOUT2CTL, WM8900_REG_ROUT2CTL, 7, 1, 0),
441 SOC_SINGLE("LINEOUT2 LP -12dB", WM8900_REG_LOUTMIXCTL1,
442 0, 1, 1),
443
444 };
445
446 static const struct snd_kcontrol_new wm8900_dapm_loutput2_control =
447 SOC_DAPM_SINGLE("LINEOUT2L Switch", WM8900_REG_POWER3, 6, 1, 0);
448
449 static const struct snd_kcontrol_new wm8900_dapm_routput2_control =
450 SOC_DAPM_SINGLE("LINEOUT2R Switch", WM8900_REG_POWER3, 5, 1, 0);
451
452 static const struct snd_kcontrol_new wm8900_loutmix_controls[] = {
453 SOC_DAPM_SINGLE("LINPUT3 Bypass Switch", WM8900_REG_LOUTMIXCTL1, 7, 1, 0),
454 SOC_DAPM_SINGLE("AUX Bypass Switch", WM8900_REG_AUXOUT_CTL, 7, 1, 0),
455 SOC_DAPM_SINGLE("Left Input Mixer Switch", WM8900_REG_BYPASS1, 7, 1, 0),
456 SOC_DAPM_SINGLE("Right Input Mixer Switch", WM8900_REG_BYPASS2, 3, 1, 0),
457 SOC_DAPM_SINGLE("DACL Switch", WM8900_REG_LOUTMIXCTL1, 8, 1, 0),
458 };
459
460 static const struct snd_kcontrol_new wm8900_routmix_controls[] = {
461 SOC_DAPM_SINGLE("RINPUT3 Bypass Switch", WM8900_REG_ROUTMIXCTL1, 7, 1, 0),
462 SOC_DAPM_SINGLE("AUX Bypass Switch", WM8900_REG_AUXOUT_CTL, 3, 1, 0),
463 SOC_DAPM_SINGLE("Left Input Mixer Switch", WM8900_REG_BYPASS1, 3, 1, 0),
464 SOC_DAPM_SINGLE("Right Input Mixer Switch", WM8900_REG_BYPASS2, 7, 1, 0),
465 SOC_DAPM_SINGLE("DACR Switch", WM8900_REG_ROUTMIXCTL1, 8, 1, 0),
466 };
467
468 static const struct snd_kcontrol_new wm8900_linmix_controls[] = {
469 SOC_DAPM_SINGLE("LINPUT2 Switch", WM8900_REG_INBOOSTMIX1, 2, 1, 1),
470 SOC_DAPM_SINGLE("LINPUT3 Switch", WM8900_REG_INBOOSTMIX1, 6, 1, 1),
471 SOC_DAPM_SINGLE("AUX Switch", WM8900_REG_AUXBOOST, 6, 1, 1),
472 SOC_DAPM_SINGLE("Input PGA Switch", WM8900_REG_ADCPATH, 6, 1, 0),
473 };
474
475 static const struct snd_kcontrol_new wm8900_rinmix_controls[] = {
476 SOC_DAPM_SINGLE("RINPUT2 Switch", WM8900_REG_INBOOSTMIX2, 2, 1, 1),
477 SOC_DAPM_SINGLE("RINPUT3 Switch", WM8900_REG_INBOOSTMIX2, 6, 1, 1),
478 SOC_DAPM_SINGLE("AUX Switch", WM8900_REG_AUXBOOST, 2, 1, 1),
479 SOC_DAPM_SINGLE("Input PGA Switch", WM8900_REG_ADCPATH, 2, 1, 0),
480 };
481
482 static const struct snd_kcontrol_new wm8900_linpga_controls[] = {
483 SOC_DAPM_SINGLE("LINPUT1 Switch", WM8900_REG_INCTL, 6, 1, 0),
484 SOC_DAPM_SINGLE("LINPUT2 Switch", WM8900_REG_INCTL, 5, 1, 0),
485 SOC_DAPM_SINGLE("LINPUT3 Switch", WM8900_REG_INCTL, 4, 1, 0),
486 };
487
488 static const struct snd_kcontrol_new wm8900_rinpga_controls[] = {
489 SOC_DAPM_SINGLE("RINPUT1 Switch", WM8900_REG_INCTL, 2, 1, 0),
490 SOC_DAPM_SINGLE("RINPUT2 Switch", WM8900_REG_INCTL, 1, 1, 0),
491 SOC_DAPM_SINGLE("RINPUT3 Switch", WM8900_REG_INCTL, 0, 1, 0),
492 };
493
494 static const char *wm8900_lp_mux[] = { "Disabled", "Enabled" };
495
496 static SOC_ENUM_SINGLE_DECL(wm8900_lineout2_lp_mux,
497 WM8900_REG_LOUTMIXCTL1, 1, wm8900_lp_mux);
498
499 static const struct snd_kcontrol_new wm8900_lineout2_lp =
500 SOC_DAPM_ENUM("Route", wm8900_lineout2_lp_mux);
501
502 static const struct snd_soc_dapm_widget wm8900_dapm_widgets[] = {
503
504 /* Externally visible pins */
505 SND_SOC_DAPM_OUTPUT("LINEOUT1L"),
506 SND_SOC_DAPM_OUTPUT("LINEOUT1R"),
507 SND_SOC_DAPM_OUTPUT("LINEOUT2L"),
508 SND_SOC_DAPM_OUTPUT("LINEOUT2R"),
509 SND_SOC_DAPM_OUTPUT("HP_L"),
510 SND_SOC_DAPM_OUTPUT("HP_R"),
511
512 SND_SOC_DAPM_INPUT("RINPUT1"),
513 SND_SOC_DAPM_INPUT("LINPUT1"),
514 SND_SOC_DAPM_INPUT("RINPUT2"),
515 SND_SOC_DAPM_INPUT("LINPUT2"),
516 SND_SOC_DAPM_INPUT("RINPUT3"),
517 SND_SOC_DAPM_INPUT("LINPUT3"),
518 SND_SOC_DAPM_INPUT("AUX"),
519
520 SND_SOC_DAPM_VMID("VMID"),
521
522 /* Input */
523 SND_SOC_DAPM_MIXER("Left Input PGA", WM8900_REG_POWER2, 3, 0,
524 wm8900_linpga_controls,
525 ARRAY_SIZE(wm8900_linpga_controls)),
526 SND_SOC_DAPM_MIXER("Right Input PGA", WM8900_REG_POWER2, 2, 0,
527 wm8900_rinpga_controls,
528 ARRAY_SIZE(wm8900_rinpga_controls)),
529
530 SND_SOC_DAPM_MIXER("Left Input Mixer", WM8900_REG_POWER2, 5, 0,
531 wm8900_linmix_controls,
532 ARRAY_SIZE(wm8900_linmix_controls)),
533 SND_SOC_DAPM_MIXER("Right Input Mixer", WM8900_REG_POWER2, 4, 0,
534 wm8900_rinmix_controls,
535 ARRAY_SIZE(wm8900_rinmix_controls)),
536
537 SND_SOC_DAPM_SUPPLY("Mic Bias", WM8900_REG_POWER1, 4, 0, NULL, 0),
538
539 SND_SOC_DAPM_ADC("ADCL", "Left HiFi Capture", WM8900_REG_POWER2, 1, 0),
540 SND_SOC_DAPM_ADC("ADCR", "Right HiFi Capture", WM8900_REG_POWER2, 0, 0),
541
542 /* Output */
543 SND_SOC_DAPM_DAC("DACL", "Left HiFi Playback", WM8900_REG_POWER3, 1, 0),
544 SND_SOC_DAPM_DAC("DACR", "Right HiFi Playback", WM8900_REG_POWER3, 0, 0),
545
546 SND_SOC_DAPM_PGA_E("Headphone Amplifier", WM8900_REG_POWER3, 7, 0, NULL, 0,
547 wm8900_hp_event,
548 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
549 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
550
551 SND_SOC_DAPM_PGA("LINEOUT1L PGA", WM8900_REG_POWER2, 8, 0, NULL, 0),
552 SND_SOC_DAPM_PGA("LINEOUT1R PGA", WM8900_REG_POWER2, 7, 0, NULL, 0),
553
554 SND_SOC_DAPM_MUX("LINEOUT2 LP", SND_SOC_NOPM, 0, 0, &wm8900_lineout2_lp),
555 SND_SOC_DAPM_PGA("LINEOUT2L PGA", WM8900_REG_POWER3, 6, 0, NULL, 0),
556 SND_SOC_DAPM_PGA("LINEOUT2R PGA", WM8900_REG_POWER3, 5, 0, NULL, 0),
557
558 SND_SOC_DAPM_MIXER("Left Output Mixer", WM8900_REG_POWER3, 3, 0,
559 wm8900_loutmix_controls,
560 ARRAY_SIZE(wm8900_loutmix_controls)),
561 SND_SOC_DAPM_MIXER("Right Output Mixer", WM8900_REG_POWER3, 2, 0,
562 wm8900_routmix_controls,
563 ARRAY_SIZE(wm8900_routmix_controls)),
564 };
565
566 /* Target, Path, Source */
567 static const struct snd_soc_dapm_route wm8900_dapm_routes[] = {
568 /* Inputs */
569 {"Left Input PGA", "LINPUT1 Switch", "LINPUT1"},
570 {"Left Input PGA", "LINPUT2 Switch", "LINPUT2"},
571 {"Left Input PGA", "LINPUT3 Switch", "LINPUT3"},
572
573 {"Right Input PGA", "RINPUT1 Switch", "RINPUT1"},
574 {"Right Input PGA", "RINPUT2 Switch", "RINPUT2"},
575 {"Right Input PGA", "RINPUT3 Switch", "RINPUT3"},
576
577 {"Left Input Mixer", "LINPUT2 Switch", "LINPUT2"},
578 {"Left Input Mixer", "LINPUT3 Switch", "LINPUT3"},
579 {"Left Input Mixer", "AUX Switch", "AUX"},
580 {"Left Input Mixer", "Input PGA Switch", "Left Input PGA"},
581
582 {"Right Input Mixer", "RINPUT2 Switch", "RINPUT2"},
583 {"Right Input Mixer", "RINPUT3 Switch", "RINPUT3"},
584 {"Right Input Mixer", "AUX Switch", "AUX"},
585 {"Right Input Mixer", "Input PGA Switch", "Right Input PGA"},
586
587 {"ADCL", NULL, "Left Input Mixer"},
588 {"ADCR", NULL, "Right Input Mixer"},
589
590 /* Outputs */
591 {"LINEOUT1L", NULL, "LINEOUT1L PGA"},
592 {"LINEOUT1L PGA", NULL, "Left Output Mixer"},
593 {"LINEOUT1R", NULL, "LINEOUT1R PGA"},
594 {"LINEOUT1R PGA", NULL, "Right Output Mixer"},
595
596 {"LINEOUT2L PGA", NULL, "Left Output Mixer"},
597 {"LINEOUT2 LP", "Disabled", "LINEOUT2L PGA"},
598 {"LINEOUT2 LP", "Enabled", "Left Output Mixer"},
599 {"LINEOUT2L", NULL, "LINEOUT2 LP"},
600
601 {"LINEOUT2R PGA", NULL, "Right Output Mixer"},
602 {"LINEOUT2 LP", "Disabled", "LINEOUT2R PGA"},
603 {"LINEOUT2 LP", "Enabled", "Right Output Mixer"},
604 {"LINEOUT2R", NULL, "LINEOUT2 LP"},
605
606 {"Left Output Mixer", "LINPUT3 Bypass Switch", "LINPUT3"},
607 {"Left Output Mixer", "AUX Bypass Switch", "AUX"},
608 {"Left Output Mixer", "Left Input Mixer Switch", "Left Input Mixer"},
609 {"Left Output Mixer", "Right Input Mixer Switch", "Right Input Mixer"},
610 {"Left Output Mixer", "DACL Switch", "DACL"},
611
612 {"Right Output Mixer", "RINPUT3 Bypass Switch", "RINPUT3"},
613 {"Right Output Mixer", "AUX Bypass Switch", "AUX"},
614 {"Right Output Mixer", "Left Input Mixer Switch", "Left Input Mixer"},
615 {"Right Output Mixer", "Right Input Mixer Switch", "Right Input Mixer"},
616 {"Right Output Mixer", "DACR Switch", "DACR"},
617
618 /* Note that the headphone output stage needs to be connected
619 * externally to LINEOUT2 via DC blocking capacitors. Other
620 * configurations are not supported.
621 *
622 * Note also that left and right headphone paths are treated as a
623 * mono path.
624 */
625 {"Headphone Amplifier", NULL, "LINEOUT2 LP"},
626 {"Headphone Amplifier", NULL, "LINEOUT2 LP"},
627 {"HP_L", NULL, "Headphone Amplifier"},
628 {"HP_R", NULL, "Headphone Amplifier"},
629 };
630
631 static int wm8900_hw_params(struct snd_pcm_substream *substream,
632 struct snd_pcm_hw_params *params,
633 struct snd_soc_dai *dai)
634 {
635 struct snd_soc_component *component = dai->component;
636 u16 reg;
637
638 reg = snd_soc_component_read32(component, WM8900_REG_AUDIO1) & ~0x60;
639
640 switch (params_width(params)) {
641 case 16:
642 break;
643 case 20:
644 reg |= 0x20;
645 break;
646 case 24:
647 reg |= 0x40;
648 break;
649 case 32:
650 reg |= 0x60;
651 break;
652 default:
653 return -EINVAL;
654 }
655
656 snd_soc_component_write(component, WM8900_REG_AUDIO1, reg);
657
658 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
659 reg = snd_soc_component_read32(component, WM8900_REG_DACCTRL);
660
661 if (params_rate(params) <= 24000)
662 reg |= WM8900_REG_DACCTRL_DAC_SB_FILT;
663 else
664 reg &= ~WM8900_REG_DACCTRL_DAC_SB_FILT;
665
666 snd_soc_component_write(component, WM8900_REG_DACCTRL, reg);
667 }
668
669 return 0;
670 }
671
672 /* FLL divisors */
673 struct _fll_div {
674 u16 fll_ratio;
675 u16 fllclk_div;
676 u16 fll_slow_lock_ref;
677 u16 n;
678 u16 k;
679 };
680
681 /* The size in bits of the FLL divide multiplied by 10
682 * to allow rounding later */
683 #define FIXED_FLL_SIZE ((1 << 16) * 10)
684
685 static int fll_factors(struct _fll_div *fll_div, unsigned int Fref,
686 unsigned int Fout)
687 {
688 u64 Kpart;
689 unsigned int K, Ndiv, Nmod, target;
690 unsigned int div;
691
692 if (WARN_ON(!Fout))
693 return -EINVAL;
694
695 /* The FLL must run at 90-100MHz which is then scaled down to
696 * the output value by FLLCLK_DIV. */
697 target = Fout;
698 div = 1;
699 while (target < 90000000) {
700 div *= 2;
701 target *= 2;
702 }
703
704 if (target > 100000000)
705 printk(KERN_WARNING "wm8900: FLL rate %u out of range, Fref=%u"
706 " Fout=%u\n", target, Fref, Fout);
707 if (div > 32) {
708 printk(KERN_ERR "wm8900: Invalid FLL division rate %u, "
709 "Fref=%u, Fout=%u, target=%u\n",
710 div, Fref, Fout, target);
711 return -EINVAL;
712 }
713
714 fll_div->fllclk_div = div >> 2;
715
716 if (Fref < 48000)
717 fll_div->fll_slow_lock_ref = 1;
718 else
719 fll_div->fll_slow_lock_ref = 0;
720
721 Ndiv = target / Fref;
722
723 if (Fref < 1000000)
724 fll_div->fll_ratio = 8;
725 else
726 fll_div->fll_ratio = 1;
727
728 fll_div->n = Ndiv / fll_div->fll_ratio;
729 Nmod = (target / fll_div->fll_ratio) % Fref;
730
731 /* Calculate fractional part - scale up so we can round. */
732 Kpart = FIXED_FLL_SIZE * (long long)Nmod;
733
734 do_div(Kpart, Fref);
735
736 K = Kpart & 0xFFFFFFFF;
737
738 if ((K % 10) >= 5)
739 K += 5;
740
741 /* Move down to proper range now rounding is done */
742 fll_div->k = K / 10;
743
744 if (WARN_ON(target != Fout * (fll_div->fllclk_div << 2)) ||
745 WARN_ON(!K && target != Fref * fll_div->fll_ratio * fll_div->n))
746 return -EINVAL;
747
748 return 0;
749 }
750
751 static int wm8900_set_fll(struct snd_soc_component *component,
752 int fll_id, unsigned int freq_in, unsigned int freq_out)
753 {
754 struct wm8900_priv *wm8900 = snd_soc_component_get_drvdata(component);
755 struct _fll_div fll_div;
756
757 if (wm8900->fll_in == freq_in && wm8900->fll_out == freq_out)
758 return 0;
759
760 /* The digital side should be disabled during any change. */
761 snd_soc_component_update_bits(component, WM8900_REG_POWER1,
762 WM8900_REG_POWER1_FLL_ENA, 0);
763
764 /* Disable the FLL? */
765 if (!freq_in || !freq_out) {
766 snd_soc_component_update_bits(component, WM8900_REG_CLOCKING1,
767 WM8900_REG_CLOCKING1_MCLK_SRC, 0);
768 snd_soc_component_update_bits(component, WM8900_REG_FLLCTL1,
769 WM8900_REG_FLLCTL1_OSC_ENA, 0);
770 wm8900->fll_in = freq_in;
771 wm8900->fll_out = freq_out;
772
773 return 0;
774 }
775
776 if (fll_factors(&fll_div, freq_in, freq_out) != 0)
777 goto reenable;
778
779 wm8900->fll_in = freq_in;
780 wm8900->fll_out = freq_out;
781
782 /* The osclilator *MUST* be enabled before we enable the
783 * digital circuit. */
784 snd_soc_component_write(component, WM8900_REG_FLLCTL1,
785 fll_div.fll_ratio | WM8900_REG_FLLCTL1_OSC_ENA);
786
787 snd_soc_component_write(component, WM8900_REG_FLLCTL4, fll_div.n >> 5);
788 snd_soc_component_write(component, WM8900_REG_FLLCTL5,
789 (fll_div.fllclk_div << 6) | (fll_div.n & 0x1f));
790
791 if (fll_div.k) {
792 snd_soc_component_write(component, WM8900_REG_FLLCTL2,
793 (fll_div.k >> 8) | 0x100);
794 snd_soc_component_write(component, WM8900_REG_FLLCTL3, fll_div.k & 0xff);
795 } else
796 snd_soc_component_write(component, WM8900_REG_FLLCTL2, 0);
797
798 if (fll_div.fll_slow_lock_ref)
799 snd_soc_component_write(component, WM8900_REG_FLLCTL6,
800 WM8900_REG_FLLCTL6_FLL_SLOW_LOCK_REF);
801 else
802 snd_soc_component_write(component, WM8900_REG_FLLCTL6, 0);
803
804 snd_soc_component_update_bits(component, WM8900_REG_POWER1,
805 WM8900_REG_POWER1_FLL_ENA,
806 WM8900_REG_POWER1_FLL_ENA);
807
808 reenable:
809 snd_soc_component_update_bits(component, WM8900_REG_CLOCKING1,
810 WM8900_REG_CLOCKING1_MCLK_SRC,
811 WM8900_REG_CLOCKING1_MCLK_SRC);
812 return 0;
813 }
814
815 static int wm8900_set_dai_pll(struct snd_soc_dai *codec_dai, int pll_id,
816 int source, unsigned int freq_in, unsigned int freq_out)
817 {
818 return wm8900_set_fll(codec_dai->component, pll_id, freq_in, freq_out);
819 }
820
821 static int wm8900_set_dai_clkdiv(struct snd_soc_dai *codec_dai,
822 int div_id, int div)
823 {
824 struct snd_soc_component *component = codec_dai->component;
825
826 switch (div_id) {
827 case WM8900_BCLK_DIV:
828 snd_soc_component_update_bits(component, WM8900_REG_CLOCKING1,
829 WM8900_REG_CLOCKING1_BCLK_MASK, div);
830 break;
831 case WM8900_OPCLK_DIV:
832 snd_soc_component_update_bits(component, WM8900_REG_CLOCKING1,
833 WM8900_REG_CLOCKING1_OPCLK_MASK, div);
834 break;
835 case WM8900_DAC_LRCLK:
836 snd_soc_component_update_bits(component, WM8900_REG_AUDIO4,
837 WM8900_LRC_MASK, div);
838 break;
839 case WM8900_ADC_LRCLK:
840 snd_soc_component_update_bits(component, WM8900_REG_AUDIO3,
841 WM8900_LRC_MASK, div);
842 break;
843 case WM8900_DAC_CLKDIV:
844 snd_soc_component_update_bits(component, WM8900_REG_CLOCKING2,
845 WM8900_REG_CLOCKING2_DAC_CLKDIV, div);
846 break;
847 case WM8900_ADC_CLKDIV:
848 snd_soc_component_update_bits(component, WM8900_REG_CLOCKING2,
849 WM8900_REG_CLOCKING2_ADC_CLKDIV, div);
850 break;
851 case WM8900_LRCLK_MODE:
852 snd_soc_component_update_bits(component, WM8900_REG_DACCTRL,
853 WM8900_REG_DACCTRL_AIF_LRCLKRATE, div);
854 break;
855 default:
856 return -EINVAL;
857 }
858
859 return 0;
860 }
861
862
863 static int wm8900_set_dai_fmt(struct snd_soc_dai *codec_dai,
864 unsigned int fmt)
865 {
866 struct snd_soc_component *component = codec_dai->component;
867 unsigned int clocking1, aif1, aif3, aif4;
868
869 clocking1 = snd_soc_component_read32(component, WM8900_REG_CLOCKING1);
870 aif1 = snd_soc_component_read32(component, WM8900_REG_AUDIO1);
871 aif3 = snd_soc_component_read32(component, WM8900_REG_AUDIO3);
872 aif4 = snd_soc_component_read32(component, WM8900_REG_AUDIO4);
873
874 /* set master/slave audio interface */
875 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
876 case SND_SOC_DAIFMT_CBS_CFS:
877 clocking1 &= ~WM8900_REG_CLOCKING1_BCLK_DIR;
878 aif3 &= ~WM8900_REG_AUDIO3_ADCLRC_DIR;
879 aif4 &= ~WM8900_REG_AUDIO4_DACLRC_DIR;
880 break;
881 case SND_SOC_DAIFMT_CBS_CFM:
882 clocking1 &= ~WM8900_REG_CLOCKING1_BCLK_DIR;
883 aif3 |= WM8900_REG_AUDIO3_ADCLRC_DIR;
884 aif4 |= WM8900_REG_AUDIO4_DACLRC_DIR;
885 break;
886 case SND_SOC_DAIFMT_CBM_CFM:
887 clocking1 |= WM8900_REG_CLOCKING1_BCLK_DIR;
888 aif3 |= WM8900_REG_AUDIO3_ADCLRC_DIR;
889 aif4 |= WM8900_REG_AUDIO4_DACLRC_DIR;
890 break;
891 case SND_SOC_DAIFMT_CBM_CFS:
892 clocking1 |= WM8900_REG_CLOCKING1_BCLK_DIR;
893 aif3 &= ~WM8900_REG_AUDIO3_ADCLRC_DIR;
894 aif4 &= ~WM8900_REG_AUDIO4_DACLRC_DIR;
895 break;
896 default:
897 return -EINVAL;
898 }
899
900 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
901 case SND_SOC_DAIFMT_DSP_A:
902 aif1 |= WM8900_REG_AUDIO1_AIF_FMT_MASK;
903 aif1 &= ~WM8900_REG_AUDIO1_LRCLK_INV;
904 break;
905 case SND_SOC_DAIFMT_DSP_B:
906 aif1 |= WM8900_REG_AUDIO1_AIF_FMT_MASK;
907 aif1 |= WM8900_REG_AUDIO1_LRCLK_INV;
908 break;
909 case SND_SOC_DAIFMT_I2S:
910 aif1 &= ~WM8900_REG_AUDIO1_AIF_FMT_MASK;
911 aif1 |= 0x10;
912 break;
913 case SND_SOC_DAIFMT_RIGHT_J:
914 aif1 &= ~WM8900_REG_AUDIO1_AIF_FMT_MASK;
915 break;
916 case SND_SOC_DAIFMT_LEFT_J:
917 aif1 &= ~WM8900_REG_AUDIO1_AIF_FMT_MASK;
918 aif1 |= 0x8;
919 break;
920 default:
921 return -EINVAL;
922 }
923
924 /* Clock inversion */
925 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
926 case SND_SOC_DAIFMT_DSP_A:
927 case SND_SOC_DAIFMT_DSP_B:
928 /* frame inversion not valid for DSP modes */
929 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
930 case SND_SOC_DAIFMT_NB_NF:
931 aif1 &= ~WM8900_REG_AUDIO1_BCLK_INV;
932 break;
933 case SND_SOC_DAIFMT_IB_NF:
934 aif1 |= WM8900_REG_AUDIO1_BCLK_INV;
935 break;
936 default:
937 return -EINVAL;
938 }
939 break;
940 case SND_SOC_DAIFMT_I2S:
941 case SND_SOC_DAIFMT_RIGHT_J:
942 case SND_SOC_DAIFMT_LEFT_J:
943 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
944 case SND_SOC_DAIFMT_NB_NF:
945 aif1 &= ~WM8900_REG_AUDIO1_BCLK_INV;
946 aif1 &= ~WM8900_REG_AUDIO1_LRCLK_INV;
947 break;
948 case SND_SOC_DAIFMT_IB_IF:
949 aif1 |= WM8900_REG_AUDIO1_BCLK_INV;
950 aif1 |= WM8900_REG_AUDIO1_LRCLK_INV;
951 break;
952 case SND_SOC_DAIFMT_IB_NF:
953 aif1 |= WM8900_REG_AUDIO1_BCLK_INV;
954 aif1 &= ~WM8900_REG_AUDIO1_LRCLK_INV;
955 break;
956 case SND_SOC_DAIFMT_NB_IF:
957 aif1 &= ~WM8900_REG_AUDIO1_BCLK_INV;
958 aif1 |= WM8900_REG_AUDIO1_LRCLK_INV;
959 break;
960 default:
961 return -EINVAL;
962 }
963 break;
964 default:
965 return -EINVAL;
966 }
967
968 snd_soc_component_write(component, WM8900_REG_CLOCKING1, clocking1);
969 snd_soc_component_write(component, WM8900_REG_AUDIO1, aif1);
970 snd_soc_component_write(component, WM8900_REG_AUDIO3, aif3);
971 snd_soc_component_write(component, WM8900_REG_AUDIO4, aif4);
972
973 return 0;
974 }
975
976 static int wm8900_digital_mute(struct snd_soc_dai *codec_dai, int mute)
977 {
978 struct snd_soc_component *component = codec_dai->component;
979 u16 reg;
980
981 reg = snd_soc_component_read32(component, WM8900_REG_DACCTRL);
982
983 if (mute)
984 reg |= WM8900_REG_DACCTRL_MUTE;
985 else
986 reg &= ~WM8900_REG_DACCTRL_MUTE;
987
988 snd_soc_component_write(component, WM8900_REG_DACCTRL, reg);
989
990 return 0;
991 }
992
993 #define WM8900_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\
994 SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 |\
995 SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000)
996
997 #define WM8900_PCM_FORMATS \
998 (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
999 SNDRV_PCM_FMTBIT_S24_LE)
1000
1001 static const struct snd_soc_dai_ops wm8900_dai_ops = {
1002 .hw_params = wm8900_hw_params,
1003 .set_clkdiv = wm8900_set_dai_clkdiv,
1004 .set_pll = wm8900_set_dai_pll,
1005 .set_fmt = wm8900_set_dai_fmt,
1006 .digital_mute = wm8900_digital_mute,
1007 };
1008
1009 static struct snd_soc_dai_driver wm8900_dai = {
1010 .name = "wm8900-hifi",
1011 .playback = {
1012 .stream_name = "HiFi Playback",
1013 .channels_min = 1,
1014 .channels_max = 2,
1015 .rates = WM8900_RATES,
1016 .formats = WM8900_PCM_FORMATS,
1017 },
1018 .capture = {
1019 .stream_name = "HiFi Capture",
1020 .channels_min = 1,
1021 .channels_max = 2,
1022 .rates = WM8900_RATES,
1023 .formats = WM8900_PCM_FORMATS,
1024 },
1025 .ops = &wm8900_dai_ops,
1026 };
1027
1028 static int wm8900_set_bias_level(struct snd_soc_component *component,
1029 enum snd_soc_bias_level level)
1030 {
1031 u16 reg;
1032
1033 switch (level) {
1034 case SND_SOC_BIAS_ON:
1035 /* Enable thermal shutdown */
1036 snd_soc_component_update_bits(component, WM8900_REG_GPIO,
1037 WM8900_REG_GPIO_TEMP_ENA,
1038 WM8900_REG_GPIO_TEMP_ENA);
1039 snd_soc_component_update_bits(component, WM8900_REG_ADDCTL,
1040 WM8900_REG_ADDCTL_TEMP_SD,
1041 WM8900_REG_ADDCTL_TEMP_SD);
1042 break;
1043
1044 case SND_SOC_BIAS_PREPARE:
1045 break;
1046
1047 case SND_SOC_BIAS_STANDBY:
1048 /* Charge capacitors if initial power up */
1049 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
1050 /* STARTUP_BIAS_ENA on */
1051 snd_soc_component_write(component, WM8900_REG_POWER1,
1052 WM8900_REG_POWER1_STARTUP_BIAS_ENA);
1053
1054 /* Startup bias mode */
1055 snd_soc_component_write(component, WM8900_REG_ADDCTL,
1056 WM8900_REG_ADDCTL_BIAS_SRC |
1057 WM8900_REG_ADDCTL_VMID_SOFTST);
1058
1059 /* VMID 2x50k */
1060 snd_soc_component_write(component, WM8900_REG_POWER1,
1061 WM8900_REG_POWER1_STARTUP_BIAS_ENA | 0x1);
1062
1063 /* Allow capacitors to charge */
1064 schedule_timeout_interruptible(msecs_to_jiffies(400));
1065
1066 /* Enable bias */
1067 snd_soc_component_write(component, WM8900_REG_POWER1,
1068 WM8900_REG_POWER1_STARTUP_BIAS_ENA |
1069 WM8900_REG_POWER1_BIAS_ENA | 0x1);
1070
1071 snd_soc_component_write(component, WM8900_REG_ADDCTL, 0);
1072
1073 snd_soc_component_write(component, WM8900_REG_POWER1,
1074 WM8900_REG_POWER1_BIAS_ENA | 0x1);
1075 }
1076
1077 reg = snd_soc_component_read32(component, WM8900_REG_POWER1);
1078 snd_soc_component_write(component, WM8900_REG_POWER1,
1079 (reg & WM8900_REG_POWER1_FLL_ENA) |
1080 WM8900_REG_POWER1_BIAS_ENA | 0x1);
1081 snd_soc_component_write(component, WM8900_REG_POWER2,
1082 WM8900_REG_POWER2_SYSCLK_ENA);
1083 snd_soc_component_write(component, WM8900_REG_POWER3, 0);
1084 break;
1085
1086 case SND_SOC_BIAS_OFF:
1087 /* Startup bias enable */
1088 reg = snd_soc_component_read32(component, WM8900_REG_POWER1);
1089 snd_soc_component_write(component, WM8900_REG_POWER1,
1090 reg & WM8900_REG_POWER1_STARTUP_BIAS_ENA);
1091 snd_soc_component_write(component, WM8900_REG_ADDCTL,
1092 WM8900_REG_ADDCTL_BIAS_SRC |
1093 WM8900_REG_ADDCTL_VMID_SOFTST);
1094
1095 /* Discharge caps */
1096 snd_soc_component_write(component, WM8900_REG_POWER1,
1097 WM8900_REG_POWER1_STARTUP_BIAS_ENA);
1098 schedule_timeout_interruptible(msecs_to_jiffies(500));
1099
1100 /* Remove clamp */
1101 snd_soc_component_write(component, WM8900_REG_HPCTL1, 0);
1102
1103 /* Power down */
1104 snd_soc_component_write(component, WM8900_REG_ADDCTL, 0);
1105 snd_soc_component_write(component, WM8900_REG_POWER1, 0);
1106 snd_soc_component_write(component, WM8900_REG_POWER2, 0);
1107 snd_soc_component_write(component, WM8900_REG_POWER3, 0);
1108
1109 /* Need to let things settle before stopping the clock
1110 * to ensure that restart works, see "Stopping the
1111 * master clock" in the datasheet. */
1112 schedule_timeout_interruptible(msecs_to_jiffies(1));
1113 snd_soc_component_write(component, WM8900_REG_POWER2,
1114 WM8900_REG_POWER2_SYSCLK_ENA);
1115 break;
1116 }
1117 return 0;
1118 }
1119
1120 static int wm8900_suspend(struct snd_soc_component *component)
1121 {
1122 struct wm8900_priv *wm8900 = snd_soc_component_get_drvdata(component);
1123 int fll_out = wm8900->fll_out;
1124 int fll_in = wm8900->fll_in;
1125 int ret;
1126
1127 /* Stop the FLL in an orderly fashion */
1128 ret = wm8900_set_fll(component, 0, 0, 0);
1129 if (ret != 0) {
1130 dev_err(component->dev, "Failed to stop FLL\n");
1131 return ret;
1132 }
1133
1134 wm8900->fll_out = fll_out;
1135 wm8900->fll_in = fll_in;
1136
1137 snd_soc_component_force_bias_level(component, SND_SOC_BIAS_OFF);
1138
1139 return 0;
1140 }
1141
1142 static int wm8900_resume(struct snd_soc_component *component)
1143 {
1144 struct wm8900_priv *wm8900 = snd_soc_component_get_drvdata(component);
1145 int ret;
1146
1147 wm8900_reset(component);
1148
1149 ret = regcache_sync(wm8900->regmap);
1150 if (ret != 0) {
1151 dev_err(component->dev, "Failed to restore cache: %d\n", ret);
1152 return ret;
1153 }
1154
1155 snd_soc_component_force_bias_level(component, SND_SOC_BIAS_STANDBY);
1156
1157 /* Restart the FLL? */
1158 if (wm8900->fll_out) {
1159 int fll_out = wm8900->fll_out;
1160 int fll_in = wm8900->fll_in;
1161
1162 wm8900->fll_in = 0;
1163 wm8900->fll_out = 0;
1164
1165 ret = wm8900_set_fll(component, 0, fll_in, fll_out);
1166 if (ret != 0) {
1167 dev_err(component->dev, "Failed to restart FLL\n");
1168 return ret;
1169 }
1170 }
1171
1172 return 0;
1173 }
1174
1175 static int wm8900_probe(struct snd_soc_component *component)
1176 {
1177 int reg;
1178
1179 reg = snd_soc_component_read32(component, WM8900_REG_ID);
1180 if (reg != 0x8900) {
1181 dev_err(component->dev, "Device is not a WM8900 - ID %x\n", reg);
1182 return -ENODEV;
1183 }
1184
1185 wm8900_reset(component);
1186
1187 /* Turn the chip on */
1188 snd_soc_component_force_bias_level(component, SND_SOC_BIAS_STANDBY);
1189
1190 /* Latch the volume update bits */
1191 snd_soc_component_update_bits(component, WM8900_REG_LINVOL, 0x100, 0x100);
1192 snd_soc_component_update_bits(component, WM8900_REG_RINVOL, 0x100, 0x100);
1193 snd_soc_component_update_bits(component, WM8900_REG_LOUT1CTL, 0x100, 0x100);
1194 snd_soc_component_update_bits(component, WM8900_REG_ROUT1CTL, 0x100, 0x100);
1195 snd_soc_component_update_bits(component, WM8900_REG_LOUT2CTL, 0x100, 0x100);
1196 snd_soc_component_update_bits(component, WM8900_REG_ROUT2CTL, 0x100, 0x100);
1197 snd_soc_component_update_bits(component, WM8900_REG_LDAC_DV, 0x100, 0x100);
1198 snd_soc_component_update_bits(component, WM8900_REG_RDAC_DV, 0x100, 0x100);
1199 snd_soc_component_update_bits(component, WM8900_REG_LADC_DV, 0x100, 0x100);
1200 snd_soc_component_update_bits(component, WM8900_REG_RADC_DV, 0x100, 0x100);
1201
1202 /* Set the DAC and mixer output bias */
1203 snd_soc_component_write(component, WM8900_REG_OUTBIASCTL, 0x81);
1204
1205 return 0;
1206 }
1207
1208 static const struct snd_soc_component_driver soc_component_dev_wm8900 = {
1209 .probe = wm8900_probe,
1210 .suspend = wm8900_suspend,
1211 .resume = wm8900_resume,
1212 .set_bias_level = wm8900_set_bias_level,
1213 .controls = wm8900_snd_controls,
1214 .num_controls = ARRAY_SIZE(wm8900_snd_controls),
1215 .dapm_widgets = wm8900_dapm_widgets,
1216 .num_dapm_widgets = ARRAY_SIZE(wm8900_dapm_widgets),
1217 .dapm_routes = wm8900_dapm_routes,
1218 .num_dapm_routes = ARRAY_SIZE(wm8900_dapm_routes),
1219 .idle_bias_on = 1,
1220 .use_pmdown_time = 1,
1221 .endianness = 1,
1222 .non_legacy_dai_naming = 1,
1223 };
1224
1225 static const struct regmap_config wm8900_regmap = {
1226 .reg_bits = 8,
1227 .val_bits = 16,
1228 .max_register = WM8900_MAXREG,
1229
1230 .reg_defaults = wm8900_reg_defaults,
1231 .num_reg_defaults = ARRAY_SIZE(wm8900_reg_defaults),
1232 .cache_type = REGCACHE_RBTREE,
1233
1234 .volatile_reg = wm8900_volatile_register,
1235 };
1236
1237 #if defined(CONFIG_SPI_MASTER)
1238 static int wm8900_spi_probe(struct spi_device *spi)
1239 {
1240 struct wm8900_priv *wm8900;
1241 int ret;
1242
1243 wm8900 = devm_kzalloc(&spi->dev, sizeof(struct wm8900_priv),
1244 GFP_KERNEL);
1245 if (wm8900 == NULL)
1246 return -ENOMEM;
1247
1248 wm8900->regmap = devm_regmap_init_spi(spi, &wm8900_regmap);
1249 if (IS_ERR(wm8900->regmap))
1250 return PTR_ERR(wm8900->regmap);
1251
1252 spi_set_drvdata(spi, wm8900);
1253
1254 ret = devm_snd_soc_register_component(&spi->dev,
1255 &soc_component_dev_wm8900, &wm8900_dai, 1);
1256
1257 return ret;
1258 }
1259
1260 static int wm8900_spi_remove(struct spi_device *spi)
1261 {
1262 return 0;
1263 }
1264
1265 static struct spi_driver wm8900_spi_driver = {
1266 .driver = {
1267 .name = "wm8900",
1268 },
1269 .probe = wm8900_spi_probe,
1270 .remove = wm8900_spi_remove,
1271 };
1272 #endif /* CONFIG_SPI_MASTER */
1273
1274 #if IS_ENABLED(CONFIG_I2C)
1275 static int wm8900_i2c_probe(struct i2c_client *i2c,
1276 const struct i2c_device_id *id)
1277 {
1278 struct wm8900_priv *wm8900;
1279 int ret;
1280
1281 wm8900 = devm_kzalloc(&i2c->dev, sizeof(struct wm8900_priv),
1282 GFP_KERNEL);
1283 if (wm8900 == NULL)
1284 return -ENOMEM;
1285
1286 wm8900->regmap = devm_regmap_init_i2c(i2c, &wm8900_regmap);
1287 if (IS_ERR(wm8900->regmap))
1288 return PTR_ERR(wm8900->regmap);
1289
1290 i2c_set_clientdata(i2c, wm8900);
1291
1292 ret = devm_snd_soc_register_component(&i2c->dev,
1293 &soc_component_dev_wm8900, &wm8900_dai, 1);
1294
1295 return ret;
1296 }
1297
1298 static int wm8900_i2c_remove(struct i2c_client *client)
1299 {
1300 return 0;
1301 }
1302
1303 static const struct i2c_device_id wm8900_i2c_id[] = {
1304 { "wm8900", 0 },
1305 { }
1306 };
1307 MODULE_DEVICE_TABLE(i2c, wm8900_i2c_id);
1308
1309 static struct i2c_driver wm8900_i2c_driver = {
1310 .driver = {
1311 .name = "wm8900",
1312 },
1313 .probe = wm8900_i2c_probe,
1314 .remove = wm8900_i2c_remove,
1315 .id_table = wm8900_i2c_id,
1316 };
1317 #endif
1318
1319 static int __init wm8900_modinit(void)
1320 {
1321 int ret = 0;
1322 #if IS_ENABLED(CONFIG_I2C)
1323 ret = i2c_add_driver(&wm8900_i2c_driver);
1324 if (ret != 0) {
1325 printk(KERN_ERR "Failed to register wm8900 I2C driver: %d\n",
1326 ret);
1327 }
1328 #endif
1329 #if defined(CONFIG_SPI_MASTER)
1330 ret = spi_register_driver(&wm8900_spi_driver);
1331 if (ret != 0) {
1332 printk(KERN_ERR "Failed to register wm8900 SPI driver: %d\n",
1333 ret);
1334 }
1335 #endif
1336 return ret;
1337 }
1338 module_init(wm8900_modinit);
1339
1340 static void __exit wm8900_exit(void)
1341 {
1342 #if IS_ENABLED(CONFIG_I2C)
1343 i2c_del_driver(&wm8900_i2c_driver);
1344 #endif
1345 #if defined(CONFIG_SPI_MASTER)
1346 spi_unregister_driver(&wm8900_spi_driver);
1347 #endif
1348 }
1349 module_exit(wm8900_exit);
1350
1351 MODULE_DESCRIPTION("ASoC WM8900 driver");
1352 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfonmicro.com>");
1353 MODULE_LICENSE("GPL");
Linux with added FPC-III support