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ARM: dts: omap5: Add bus_dma_limit for L3 bus
[linux/fpc-iii.git] / sound / soc / codecs / wm8990.c
blobcfe7892696ddc7e1ee136f773e046d0cfd5c0f7d
1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * wm8990.c -- WM8990 ALSA Soc Audio driver
4 *
5 * Copyright 2008 Wolfson Microelectronics PLC.
6 * Author: Liam Girdwood <lrg@slimlogic.co.uk>
7 */
8
9 #include <linux/module.h>
10 #include <linux/moduleparam.h>
11 #include <linux/kernel.h>
12 #include <linux/init.h>
13 #include <linux/delay.h>
14 #include <linux/pm.h>
15 #include <linux/i2c.h>
16 #include <linux/regmap.h>
17 #include <linux/slab.h>
18 #include <sound/core.h>
19 #include <sound/pcm.h>
20 #include <sound/pcm_params.h>
21 #include <sound/soc.h>
22 #include <sound/initval.h>
23 #include <sound/tlv.h>
24 #include <asm/div64.h>
25
26 #include "wm8990.h"
27
28 /* codec private data */
29 struct wm8990_priv {
30 struct regmap *regmap;
31 unsigned int sysclk;
32 unsigned int pcmclk;
33 };
34
35 static bool wm8990_volatile_register(struct device *dev, unsigned int reg)
36 {
37 switch (reg) {
38 case WM8990_RESET:
39 return true;
40 default:
41 return false;
42 }
43 }
44
45 static const struct reg_default wm8990_reg_defaults[] = {
46 { 1, 0x0000 }, /* R1 - Power Management (1) */
47 { 2, 0x6000 }, /* R2 - Power Management (2) */
48 { 3, 0x0000 }, /* R3 - Power Management (3) */
49 { 4, 0x4050 }, /* R4 - Audio Interface (1) */
50 { 5, 0x4000 }, /* R5 - Audio Interface (2) */
51 { 6, 0x01C8 }, /* R6 - Clocking (1) */
52 { 7, 0x0000 }, /* R7 - Clocking (2) */
53 { 8, 0x0040 }, /* R8 - Audio Interface (3) */
54 { 9, 0x0040 }, /* R9 - Audio Interface (4) */
55 { 10, 0x0004 }, /* R10 - DAC CTRL */
56 { 11, 0x00C0 }, /* R11 - Left DAC Digital Volume */
57 { 12, 0x00C0 }, /* R12 - Right DAC Digital Volume */
58 { 13, 0x0000 }, /* R13 - Digital Side Tone */
59 { 14, 0x0100 }, /* R14 - ADC CTRL */
60 { 15, 0x00C0 }, /* R15 - Left ADC Digital Volume */
61 { 16, 0x00C0 }, /* R16 - Right ADC Digital Volume */
62
63 { 18, 0x0000 }, /* R18 - GPIO CTRL 1 */
64 { 19, 0x1000 }, /* R19 - GPIO1 & GPIO2 */
65 { 20, 0x1010 }, /* R20 - GPIO3 & GPIO4 */
66 { 21, 0x1010 }, /* R21 - GPIO5 & GPIO6 */
67 { 22, 0x8000 }, /* R22 - GPIOCTRL 2 */
68 { 23, 0x0800 }, /* R23 - GPIO_POL */
69 { 24, 0x008B }, /* R24 - Left Line Input 1&2 Volume */
70 { 25, 0x008B }, /* R25 - Left Line Input 3&4 Volume */
71 { 26, 0x008B }, /* R26 - Right Line Input 1&2 Volume */
72 { 27, 0x008B }, /* R27 - Right Line Input 3&4 Volume */
73 { 28, 0x0000 }, /* R28 - Left Output Volume */
74 { 29, 0x0000 }, /* R29 - Right Output Volume */
75 { 30, 0x0066 }, /* R30 - Line Outputs Volume */
76 { 31, 0x0022 }, /* R31 - Out3/4 Volume */
77 { 32, 0x0079 }, /* R32 - Left OPGA Volume */
78 { 33, 0x0079 }, /* R33 - Right OPGA Volume */
79 { 34, 0x0003 }, /* R34 - Speaker Volume */
80 { 35, 0x0003 }, /* R35 - ClassD1 */
81
82 { 37, 0x0100 }, /* R37 - ClassD3 */
83 { 38, 0x0079 }, /* R38 - ClassD4 */
84 { 39, 0x0000 }, /* R39 - Input Mixer1 */
85 { 40, 0x0000 }, /* R40 - Input Mixer2 */
86 { 41, 0x0000 }, /* R41 - Input Mixer3 */
87 { 42, 0x0000 }, /* R42 - Input Mixer4 */
88 { 43, 0x0000 }, /* R43 - Input Mixer5 */
89 { 44, 0x0000 }, /* R44 - Input Mixer6 */
90 { 45, 0x0000 }, /* R45 - Output Mixer1 */
91 { 46, 0x0000 }, /* R46 - Output Mixer2 */
92 { 47, 0x0000 }, /* R47 - Output Mixer3 */
93 { 48, 0x0000 }, /* R48 - Output Mixer4 */
94 { 49, 0x0000 }, /* R49 - Output Mixer5 */
95 { 50, 0x0000 }, /* R50 - Output Mixer6 */
96 { 51, 0x0180 }, /* R51 - Out3/4 Mixer */
97 { 52, 0x0000 }, /* R52 - Line Mixer1 */
98 { 53, 0x0000 }, /* R53 - Line Mixer2 */
99 { 54, 0x0000 }, /* R54 - Speaker Mixer */
100 { 55, 0x0000 }, /* R55 - Additional Control */
101 { 56, 0x0000 }, /* R56 - AntiPOP1 */
102 { 57, 0x0000 }, /* R57 - AntiPOP2 */
103 { 58, 0x0000 }, /* R58 - MICBIAS */
104
105 { 60, 0x0008 }, /* R60 - PLL1 */
106 { 61, 0x0031 }, /* R61 - PLL2 */
107 { 62, 0x0026 }, /* R62 - PLL3 */
108 };
109
110 #define wm8990_reset(c) snd_soc_component_write(c, WM8990_RESET, 0)
111
112 static const DECLARE_TLV_DB_SCALE(rec_mix_tlv, -1500, 600, 0);
113
114 static const DECLARE_TLV_DB_SCALE(in_pga_tlv, -1650, 3000, 0);
115
116 static const DECLARE_TLV_DB_SCALE(out_mix_tlv, 0, -2100, 0);
117
118 static const DECLARE_TLV_DB_SCALE(out_pga_tlv, -7300, 600, 0);
119
120 static const DECLARE_TLV_DB_SCALE(out_omix_tlv, -600, 0, 0);
121
122 static const DECLARE_TLV_DB_SCALE(out_dac_tlv, -7163, 0, 0);
123
124 static const DECLARE_TLV_DB_SCALE(in_adc_tlv, -7163, 1763, 0);
125
126 static const DECLARE_TLV_DB_SCALE(out_sidetone_tlv, -3600, 0, 0);
127
128 static int wm899x_outpga_put_volsw_vu(struct snd_kcontrol *kcontrol,
129 struct snd_ctl_elem_value *ucontrol)
130 {
131 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
132 struct soc_mixer_control *mc =
133 (struct soc_mixer_control *)kcontrol->private_value;
134 int reg = mc->reg;
135 int ret;
136 u16 val;
137
138 ret = snd_soc_put_volsw(kcontrol, ucontrol);
139 if (ret < 0)
140 return ret;
141
142 /* now hit the volume update bits (always bit 8) */
143 val = snd_soc_component_read32(component, reg);
144 return snd_soc_component_write(component, reg, val | 0x0100);
145 }
146
147 #define SOC_WM899X_OUTPGA_SINGLE_R_TLV(xname, reg, shift, max, invert,\
148 tlv_array) \
149 SOC_SINGLE_EXT_TLV(xname, reg, shift, max, invert, \
150 snd_soc_get_volsw, wm899x_outpga_put_volsw_vu, tlv_array)
151
152
153 static const char *wm8990_digital_sidetone[] =
154 {"None", "Left ADC", "Right ADC", "Reserved"};
155
156 static SOC_ENUM_SINGLE_DECL(wm8990_left_digital_sidetone_enum,
157 WM8990_DIGITAL_SIDE_TONE,
158 WM8990_ADC_TO_DACL_SHIFT,
159 wm8990_digital_sidetone);
160
161 static SOC_ENUM_SINGLE_DECL(wm8990_right_digital_sidetone_enum,
162 WM8990_DIGITAL_SIDE_TONE,
163 WM8990_ADC_TO_DACR_SHIFT,
164 wm8990_digital_sidetone);
165
166 static const char *wm8990_adcmode[] =
167 {"Hi-fi mode", "Voice mode 1", "Voice mode 2", "Voice mode 3"};
168
169 static SOC_ENUM_SINGLE_DECL(wm8990_right_adcmode_enum,
170 WM8990_ADC_CTRL,
171 WM8990_ADC_HPF_CUT_SHIFT,
172 wm8990_adcmode);
173
174 static const struct snd_kcontrol_new wm8990_snd_controls[] = {
175 /* INMIXL */
176 SOC_SINGLE("LIN12 PGA Boost", WM8990_INPUT_MIXER3, WM8990_L12MNBST_BIT, 1, 0),
177 SOC_SINGLE("LIN34 PGA Boost", WM8990_INPUT_MIXER3, WM8990_L34MNBST_BIT, 1, 0),
178 /* INMIXR */
179 SOC_SINGLE("RIN12 PGA Boost", WM8990_INPUT_MIXER3, WM8990_R12MNBST_BIT, 1, 0),
180 SOC_SINGLE("RIN34 PGA Boost", WM8990_INPUT_MIXER3, WM8990_R34MNBST_BIT, 1, 0),
181
182 /* LOMIX */
183 SOC_SINGLE_TLV("LOMIX LIN3 Bypass Volume", WM8990_OUTPUT_MIXER3,
184 WM8990_LLI3LOVOL_SHIFT, WM8990_LLI3LOVOL_MASK, 1, out_mix_tlv),
185 SOC_SINGLE_TLV("LOMIX RIN12 PGA Bypass Volume", WM8990_OUTPUT_MIXER3,
186 WM8990_LR12LOVOL_SHIFT, WM8990_LR12LOVOL_MASK, 1, out_mix_tlv),
187 SOC_SINGLE_TLV("LOMIX LIN12 PGA Bypass Volume", WM8990_OUTPUT_MIXER3,
188 WM8990_LL12LOVOL_SHIFT, WM8990_LL12LOVOL_MASK, 1, out_mix_tlv),
189 SOC_SINGLE_TLV("LOMIX RIN3 Bypass Volume", WM8990_OUTPUT_MIXER5,
190 WM8990_LRI3LOVOL_SHIFT, WM8990_LRI3LOVOL_MASK, 1, out_mix_tlv),
191 SOC_SINGLE_TLV("LOMIX AINRMUX Bypass Volume", WM8990_OUTPUT_MIXER5,
192 WM8990_LRBLOVOL_SHIFT, WM8990_LRBLOVOL_MASK, 1, out_mix_tlv),
193 SOC_SINGLE_TLV("LOMIX AINLMUX Bypass Volume", WM8990_OUTPUT_MIXER5,
194 WM8990_LRBLOVOL_SHIFT, WM8990_LRBLOVOL_MASK, 1, out_mix_tlv),
195
196 /* ROMIX */
197 SOC_SINGLE_TLV("ROMIX RIN3 Bypass Volume", WM8990_OUTPUT_MIXER4,
198 WM8990_RRI3ROVOL_SHIFT, WM8990_RRI3ROVOL_MASK, 1, out_mix_tlv),
199 SOC_SINGLE_TLV("ROMIX LIN12 PGA Bypass Volume", WM8990_OUTPUT_MIXER4,
200 WM8990_RL12ROVOL_SHIFT, WM8990_RL12ROVOL_MASK, 1, out_mix_tlv),
201 SOC_SINGLE_TLV("ROMIX RIN12 PGA Bypass Volume", WM8990_OUTPUT_MIXER4,
202 WM8990_RR12ROVOL_SHIFT, WM8990_RR12ROVOL_MASK, 1, out_mix_tlv),
203 SOC_SINGLE_TLV("ROMIX LIN3 Bypass Volume", WM8990_OUTPUT_MIXER6,
204 WM8990_RLI3ROVOL_SHIFT, WM8990_RLI3ROVOL_MASK, 1, out_mix_tlv),
205 SOC_SINGLE_TLV("ROMIX AINLMUX Bypass Volume", WM8990_OUTPUT_MIXER6,
206 WM8990_RLBROVOL_SHIFT, WM8990_RLBROVOL_MASK, 1, out_mix_tlv),
207 SOC_SINGLE_TLV("ROMIX AINRMUX Bypass Volume", WM8990_OUTPUT_MIXER6,
208 WM8990_RRBROVOL_SHIFT, WM8990_RRBROVOL_MASK, 1, out_mix_tlv),
209
210 /* LOUT */
211 SOC_WM899X_OUTPGA_SINGLE_R_TLV("LOUT Volume", WM8990_LEFT_OUTPUT_VOLUME,
212 WM8990_LOUTVOL_SHIFT, WM8990_LOUTVOL_MASK, 0, out_pga_tlv),
213 SOC_SINGLE("LOUT ZC", WM8990_LEFT_OUTPUT_VOLUME, WM8990_LOZC_BIT, 1, 0),
214
215 /* ROUT */
216 SOC_WM899X_OUTPGA_SINGLE_R_TLV("ROUT Volume", WM8990_RIGHT_OUTPUT_VOLUME,
217 WM8990_ROUTVOL_SHIFT, WM8990_ROUTVOL_MASK, 0, out_pga_tlv),
218 SOC_SINGLE("ROUT ZC", WM8990_RIGHT_OUTPUT_VOLUME, WM8990_ROZC_BIT, 1, 0),
219
220 /* LOPGA */
221 SOC_WM899X_OUTPGA_SINGLE_R_TLV("LOPGA Volume", WM8990_LEFT_OPGA_VOLUME,
222 WM8990_LOPGAVOL_SHIFT, WM8990_LOPGAVOL_MASK, 0, out_pga_tlv),
223 SOC_SINGLE("LOPGA ZC Switch", WM8990_LEFT_OPGA_VOLUME,
224 WM8990_LOPGAZC_BIT, 1, 0),
225
226 /* ROPGA */
227 SOC_WM899X_OUTPGA_SINGLE_R_TLV("ROPGA Volume", WM8990_RIGHT_OPGA_VOLUME,
228 WM8990_ROPGAVOL_SHIFT, WM8990_ROPGAVOL_MASK, 0, out_pga_tlv),
229 SOC_SINGLE("ROPGA ZC Switch", WM8990_RIGHT_OPGA_VOLUME,
230 WM8990_ROPGAZC_BIT, 1, 0),
231
232 SOC_SINGLE("LON Mute Switch", WM8990_LINE_OUTPUTS_VOLUME,
233 WM8990_LONMUTE_BIT, 1, 0),
234 SOC_SINGLE("LOP Mute Switch", WM8990_LINE_OUTPUTS_VOLUME,
235 WM8990_LOPMUTE_BIT, 1, 0),
236 SOC_SINGLE("LOP Attenuation Switch", WM8990_LINE_OUTPUTS_VOLUME,
237 WM8990_LOATTN_BIT, 1, 0),
238 SOC_SINGLE("RON Mute Switch", WM8990_LINE_OUTPUTS_VOLUME,
239 WM8990_RONMUTE_BIT, 1, 0),
240 SOC_SINGLE("ROP Mute Switch", WM8990_LINE_OUTPUTS_VOLUME,
241 WM8990_ROPMUTE_BIT, 1, 0),
242 SOC_SINGLE("ROP Attenuation Switch", WM8990_LINE_OUTPUTS_VOLUME,
243 WM8990_ROATTN_BIT, 1, 0),
244
245 SOC_SINGLE("OUT3 Mute Switch", WM8990_OUT3_4_VOLUME,
246 WM8990_OUT3MUTE_BIT, 1, 0),
247 SOC_SINGLE("OUT3 Attenuation Switch", WM8990_OUT3_4_VOLUME,
248 WM8990_OUT3ATTN_BIT, 1, 0),
249
250 SOC_SINGLE("OUT4 Mute Switch", WM8990_OUT3_4_VOLUME,
251 WM8990_OUT4MUTE_BIT, 1, 0),
252 SOC_SINGLE("OUT4 Attenuation Switch", WM8990_OUT3_4_VOLUME,
253 WM8990_OUT4ATTN_BIT, 1, 0),
254
255 SOC_SINGLE("Speaker Mode Switch", WM8990_CLASSD1,
256 WM8990_CDMODE_BIT, 1, 0),
257
258 SOC_SINGLE("Speaker Output Attenuation Volume", WM8990_SPEAKER_VOLUME,
259 WM8990_SPKATTN_SHIFT, WM8990_SPKATTN_MASK, 0),
260 SOC_SINGLE("Speaker DC Boost Volume", WM8990_CLASSD3,
261 WM8990_DCGAIN_SHIFT, WM8990_DCGAIN_MASK, 0),
262 SOC_SINGLE("Speaker AC Boost Volume", WM8990_CLASSD3,
263 WM8990_ACGAIN_SHIFT, WM8990_ACGAIN_MASK, 0),
264 SOC_SINGLE_TLV("Speaker Volume", WM8990_CLASSD4,
265 WM8990_SPKVOL_SHIFT, WM8990_SPKVOL_MASK, 0, out_pga_tlv),
266 SOC_SINGLE("Speaker ZC Switch", WM8990_CLASSD4,
267 WM8990_SPKZC_SHIFT, WM8990_SPKZC_MASK, 0),
268
269 SOC_WM899X_OUTPGA_SINGLE_R_TLV("Left DAC Digital Volume",
270 WM8990_LEFT_DAC_DIGITAL_VOLUME,
271 WM8990_DACL_VOL_SHIFT,
272 WM8990_DACL_VOL_MASK,
273 0,
274 out_dac_tlv),
275
276 SOC_WM899X_OUTPGA_SINGLE_R_TLV("Right DAC Digital Volume",
277 WM8990_RIGHT_DAC_DIGITAL_VOLUME,
278 WM8990_DACR_VOL_SHIFT,
279 WM8990_DACR_VOL_MASK,
280 0,
281 out_dac_tlv),
282
283 SOC_ENUM("Left Digital Sidetone", wm8990_left_digital_sidetone_enum),
284 SOC_ENUM("Right Digital Sidetone", wm8990_right_digital_sidetone_enum),
285
286 SOC_SINGLE_TLV("Left Digital Sidetone Volume", WM8990_DIGITAL_SIDE_TONE,
287 WM8990_ADCL_DAC_SVOL_SHIFT, WM8990_ADCL_DAC_SVOL_MASK, 0,
288 out_sidetone_tlv),
289 SOC_SINGLE_TLV("Right Digital Sidetone Volume", WM8990_DIGITAL_SIDE_TONE,
290 WM8990_ADCR_DAC_SVOL_SHIFT, WM8990_ADCR_DAC_SVOL_MASK, 0,
291 out_sidetone_tlv),
292
293 SOC_SINGLE("ADC Digital High Pass Filter Switch", WM8990_ADC_CTRL,
294 WM8990_ADC_HPF_ENA_BIT, 1, 0),
295
296 SOC_ENUM("ADC HPF Mode", wm8990_right_adcmode_enum),
297
298 SOC_WM899X_OUTPGA_SINGLE_R_TLV("Left ADC Digital Volume",
299 WM8990_LEFT_ADC_DIGITAL_VOLUME,
300 WM8990_ADCL_VOL_SHIFT,
301 WM8990_ADCL_VOL_MASK,
302 0,
303 in_adc_tlv),
304
305 SOC_WM899X_OUTPGA_SINGLE_R_TLV("Right ADC Digital Volume",
306 WM8990_RIGHT_ADC_DIGITAL_VOLUME,
307 WM8990_ADCR_VOL_SHIFT,
308 WM8990_ADCR_VOL_MASK,
309 0,
310 in_adc_tlv),
311
312 SOC_WM899X_OUTPGA_SINGLE_R_TLV("LIN12 Volume",
313 WM8990_LEFT_LINE_INPUT_1_2_VOLUME,
314 WM8990_LIN12VOL_SHIFT,
315 WM8990_LIN12VOL_MASK,
316 0,
317 in_pga_tlv),
318
319 SOC_SINGLE("LIN12 ZC Switch", WM8990_LEFT_LINE_INPUT_1_2_VOLUME,
320 WM8990_LI12ZC_BIT, 1, 0),
321
322 SOC_SINGLE("LIN12 Mute Switch", WM8990_LEFT_LINE_INPUT_1_2_VOLUME,
323 WM8990_LI12MUTE_BIT, 1, 0),
324
325 SOC_WM899X_OUTPGA_SINGLE_R_TLV("LIN34 Volume",
326 WM8990_LEFT_LINE_INPUT_3_4_VOLUME,
327 WM8990_LIN34VOL_SHIFT,
328 WM8990_LIN34VOL_MASK,
329 0,
330 in_pga_tlv),
331
332 SOC_SINGLE("LIN34 ZC Switch", WM8990_LEFT_LINE_INPUT_3_4_VOLUME,
333 WM8990_LI34ZC_BIT, 1, 0),
334
335 SOC_SINGLE("LIN34 Mute Switch", WM8990_LEFT_LINE_INPUT_3_4_VOLUME,
336 WM8990_LI34MUTE_BIT, 1, 0),
337
338 SOC_WM899X_OUTPGA_SINGLE_R_TLV("RIN12 Volume",
339 WM8990_RIGHT_LINE_INPUT_1_2_VOLUME,
340 WM8990_RIN12VOL_SHIFT,
341 WM8990_RIN12VOL_MASK,
342 0,
343 in_pga_tlv),
344
345 SOC_SINGLE("RIN12 ZC Switch", WM8990_RIGHT_LINE_INPUT_1_2_VOLUME,
346 WM8990_RI12ZC_BIT, 1, 0),
347
348 SOC_SINGLE("RIN12 Mute Switch", WM8990_RIGHT_LINE_INPUT_1_2_VOLUME,
349 WM8990_RI12MUTE_BIT, 1, 0),
350
351 SOC_WM899X_OUTPGA_SINGLE_R_TLV("RIN34 Volume",
352 WM8990_RIGHT_LINE_INPUT_3_4_VOLUME,
353 WM8990_RIN34VOL_SHIFT,
354 WM8990_RIN34VOL_MASK,
355 0,
356 in_pga_tlv),
357
358 SOC_SINGLE("RIN34 ZC Switch", WM8990_RIGHT_LINE_INPUT_3_4_VOLUME,
359 WM8990_RI34ZC_BIT, 1, 0),
360
361 SOC_SINGLE("RIN34 Mute Switch", WM8990_RIGHT_LINE_INPUT_3_4_VOLUME,
362 WM8990_RI34MUTE_BIT, 1, 0),
363
364 };
365
366 /*
367 * _DAPM_ Controls
368 */
369
370 static int outmixer_event(struct snd_soc_dapm_widget *w,
371 struct snd_kcontrol *kcontrol, int event)
372 {
373 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
374 u32 reg_shift = kcontrol->private_value & 0xfff;
375 int ret = 0;
376 u16 reg;
377
378 switch (reg_shift) {
379 case WM8990_SPEAKER_MIXER | (WM8990_LDSPK_BIT << 8) :
380 reg = snd_soc_component_read32(component, WM8990_OUTPUT_MIXER1);
381 if (reg & WM8990_LDLO) {
382 printk(KERN_WARNING
383 "Cannot set as Output Mixer 1 LDLO Set\n");
384 ret = -1;
385 }
386 break;
387 case WM8990_SPEAKER_MIXER | (WM8990_RDSPK_BIT << 8):
388 reg = snd_soc_component_read32(component, WM8990_OUTPUT_MIXER2);
389 if (reg & WM8990_RDRO) {
390 printk(KERN_WARNING
391 "Cannot set as Output Mixer 2 RDRO Set\n");
392 ret = -1;
393 }
394 break;
395 case WM8990_OUTPUT_MIXER1 | (WM8990_LDLO_BIT << 8):
396 reg = snd_soc_component_read32(component, WM8990_SPEAKER_MIXER);
397 if (reg & WM8990_LDSPK) {
398 printk(KERN_WARNING
399 "Cannot set as Speaker Mixer LDSPK Set\n");
400 ret = -1;
401 }
402 break;
403 case WM8990_OUTPUT_MIXER2 | (WM8990_RDRO_BIT << 8):
404 reg = snd_soc_component_read32(component, WM8990_SPEAKER_MIXER);
405 if (reg & WM8990_RDSPK) {
406 printk(KERN_WARNING
407 "Cannot set as Speaker Mixer RDSPK Set\n");
408 ret = -1;
409 }
410 break;
411 }
412
413 return ret;
414 }
415
416 /* INMIX dB values */
417 static const DECLARE_TLV_DB_SCALE(in_mix_tlv, -1200, 600, 0);
418
419 /* Left In PGA Connections */
420 static const struct snd_kcontrol_new wm8990_dapm_lin12_pga_controls[] = {
421 SOC_DAPM_SINGLE("LIN1 Switch", WM8990_INPUT_MIXER2, WM8990_LMN1_BIT, 1, 0),
422 SOC_DAPM_SINGLE("LIN2 Switch", WM8990_INPUT_MIXER2, WM8990_LMP2_BIT, 1, 0),
423 };
424
425 static const struct snd_kcontrol_new wm8990_dapm_lin34_pga_controls[] = {
426 SOC_DAPM_SINGLE("LIN3 Switch", WM8990_INPUT_MIXER2, WM8990_LMN3_BIT, 1, 0),
427 SOC_DAPM_SINGLE("LIN4 Switch", WM8990_INPUT_MIXER2, WM8990_LMP4_BIT, 1, 0),
428 };
429
430 /* Right In PGA Connections */
431 static const struct snd_kcontrol_new wm8990_dapm_rin12_pga_controls[] = {
432 SOC_DAPM_SINGLE("RIN1 Switch", WM8990_INPUT_MIXER2, WM8990_RMN1_BIT, 1, 0),
433 SOC_DAPM_SINGLE("RIN2 Switch", WM8990_INPUT_MIXER2, WM8990_RMP2_BIT, 1, 0),
434 };
435
436 static const struct snd_kcontrol_new wm8990_dapm_rin34_pga_controls[] = {
437 SOC_DAPM_SINGLE("RIN3 Switch", WM8990_INPUT_MIXER2, WM8990_RMN3_BIT, 1, 0),
438 SOC_DAPM_SINGLE("RIN4 Switch", WM8990_INPUT_MIXER2, WM8990_RMP4_BIT, 1, 0),
439 };
440
441 /* INMIXL */
442 static const struct snd_kcontrol_new wm8990_dapm_inmixl_controls[] = {
443 SOC_DAPM_SINGLE_TLV("Record Left Volume", WM8990_INPUT_MIXER3,
444 WM8990_LDBVOL_SHIFT, WM8990_LDBVOL_MASK, 0, in_mix_tlv),
445 SOC_DAPM_SINGLE_TLV("LIN2 Volume", WM8990_INPUT_MIXER5, WM8990_LI2BVOL_SHIFT,
446 7, 0, in_mix_tlv),
447 SOC_DAPM_SINGLE("LINPGA12 Switch", WM8990_INPUT_MIXER3, WM8990_L12MNB_BIT,
448 1, 0),
449 SOC_DAPM_SINGLE("LINPGA34 Switch", WM8990_INPUT_MIXER3, WM8990_L34MNB_BIT,
450 1, 0),
451 };
452
453 /* INMIXR */
454 static const struct snd_kcontrol_new wm8990_dapm_inmixr_controls[] = {
455 SOC_DAPM_SINGLE_TLV("Record Right Volume", WM8990_INPUT_MIXER4,
456 WM8990_RDBVOL_SHIFT, WM8990_RDBVOL_MASK, 0, in_mix_tlv),
457 SOC_DAPM_SINGLE_TLV("RIN2 Volume", WM8990_INPUT_MIXER6, WM8990_RI2BVOL_SHIFT,
458 7, 0, in_mix_tlv),
459 SOC_DAPM_SINGLE("RINPGA12 Switch", WM8990_INPUT_MIXER3, WM8990_L12MNB_BIT,
460 1, 0),
461 SOC_DAPM_SINGLE("RINPGA34 Switch", WM8990_INPUT_MIXER3, WM8990_L34MNB_BIT,
462 1, 0),
463 };
464
465 /* AINLMUX */
466 static const char *wm8990_ainlmux[] =
467 {"INMIXL Mix", "RXVOICE Mix", "DIFFINL Mix"};
468
469 static SOC_ENUM_SINGLE_DECL(wm8990_ainlmux_enum,
470 WM8990_INPUT_MIXER1, WM8990_AINLMODE_SHIFT,
471 wm8990_ainlmux);
472
473 static const struct snd_kcontrol_new wm8990_dapm_ainlmux_controls =
474 SOC_DAPM_ENUM("Route", wm8990_ainlmux_enum);
475
476 /* DIFFINL */
477
478 /* AINRMUX */
479 static const char *wm8990_ainrmux[] =
480 {"INMIXR Mix", "RXVOICE Mix", "DIFFINR Mix"};
481
482 static SOC_ENUM_SINGLE_DECL(wm8990_ainrmux_enum,
483 WM8990_INPUT_MIXER1, WM8990_AINRMODE_SHIFT,
484 wm8990_ainrmux);
485
486 static const struct snd_kcontrol_new wm8990_dapm_ainrmux_controls =
487 SOC_DAPM_ENUM("Route", wm8990_ainrmux_enum);
488
489 /* RXVOICE */
490 static const struct snd_kcontrol_new wm8990_dapm_rxvoice_controls[] = {
491 SOC_DAPM_SINGLE_TLV("LIN4/RXN", WM8990_INPUT_MIXER5, WM8990_LR4BVOL_SHIFT,
492 WM8990_LR4BVOL_MASK, 0, in_mix_tlv),
493 SOC_DAPM_SINGLE_TLV("RIN4/RXP", WM8990_INPUT_MIXER6, WM8990_RL4BVOL_SHIFT,
494 WM8990_RL4BVOL_MASK, 0, in_mix_tlv),
495 };
496
497 /* LOMIX */
498 static const struct snd_kcontrol_new wm8990_dapm_lomix_controls[] = {
499 SOC_DAPM_SINGLE("LOMIX Right ADC Bypass Switch", WM8990_OUTPUT_MIXER1,
500 WM8990_LRBLO_BIT, 1, 0),
501 SOC_DAPM_SINGLE("LOMIX Left ADC Bypass Switch", WM8990_OUTPUT_MIXER1,
502 WM8990_LLBLO_BIT, 1, 0),
503 SOC_DAPM_SINGLE("LOMIX RIN3 Bypass Switch", WM8990_OUTPUT_MIXER1,
504 WM8990_LRI3LO_BIT, 1, 0),
505 SOC_DAPM_SINGLE("LOMIX LIN3 Bypass Switch", WM8990_OUTPUT_MIXER1,
506 WM8990_LLI3LO_BIT, 1, 0),
507 SOC_DAPM_SINGLE("LOMIX RIN12 PGA Bypass Switch", WM8990_OUTPUT_MIXER1,
508 WM8990_LR12LO_BIT, 1, 0),
509 SOC_DAPM_SINGLE("LOMIX LIN12 PGA Bypass Switch", WM8990_OUTPUT_MIXER1,
510 WM8990_LL12LO_BIT, 1, 0),
511 SOC_DAPM_SINGLE("LOMIX Left DAC Switch", WM8990_OUTPUT_MIXER1,
512 WM8990_LDLO_BIT, 1, 0),
513 };
514
515 /* ROMIX */
516 static const struct snd_kcontrol_new wm8990_dapm_romix_controls[] = {
517 SOC_DAPM_SINGLE("ROMIX Left ADC Bypass Switch", WM8990_OUTPUT_MIXER2,
518 WM8990_RLBRO_BIT, 1, 0),
519 SOC_DAPM_SINGLE("ROMIX Right ADC Bypass Switch", WM8990_OUTPUT_MIXER2,
520 WM8990_RRBRO_BIT, 1, 0),
521 SOC_DAPM_SINGLE("ROMIX LIN3 Bypass Switch", WM8990_OUTPUT_MIXER2,
522 WM8990_RLI3RO_BIT, 1, 0),
523 SOC_DAPM_SINGLE("ROMIX RIN3 Bypass Switch", WM8990_OUTPUT_MIXER2,
524 WM8990_RRI3RO_BIT, 1, 0),
525 SOC_DAPM_SINGLE("ROMIX LIN12 PGA Bypass Switch", WM8990_OUTPUT_MIXER2,
526 WM8990_RL12RO_BIT, 1, 0),
527 SOC_DAPM_SINGLE("ROMIX RIN12 PGA Bypass Switch", WM8990_OUTPUT_MIXER2,
528 WM8990_RR12RO_BIT, 1, 0),
529 SOC_DAPM_SINGLE("ROMIX Right DAC Switch", WM8990_OUTPUT_MIXER2,
530 WM8990_RDRO_BIT, 1, 0),
531 };
532
533 /* LONMIX */
534 static const struct snd_kcontrol_new wm8990_dapm_lonmix_controls[] = {
535 SOC_DAPM_SINGLE("LONMIX Left Mixer PGA Switch", WM8990_LINE_MIXER1,
536 WM8990_LLOPGALON_BIT, 1, 0),
537 SOC_DAPM_SINGLE("LONMIX Right Mixer PGA Switch", WM8990_LINE_MIXER1,
538 WM8990_LROPGALON_BIT, 1, 0),
539 SOC_DAPM_SINGLE("LONMIX Inverted LOP Switch", WM8990_LINE_MIXER1,
540 WM8990_LOPLON_BIT, 1, 0),
541 };
542
543 /* LOPMIX */
544 static const struct snd_kcontrol_new wm8990_dapm_lopmix_controls[] = {
545 SOC_DAPM_SINGLE("LOPMIX Right Mic Bypass Switch", WM8990_LINE_MIXER1,
546 WM8990_LR12LOP_BIT, 1, 0),
547 SOC_DAPM_SINGLE("LOPMIX Left Mic Bypass Switch", WM8990_LINE_MIXER1,
548 WM8990_LL12LOP_BIT, 1, 0),
549 SOC_DAPM_SINGLE("LOPMIX Left Mixer PGA Switch", WM8990_LINE_MIXER1,
550 WM8990_LLOPGALOP_BIT, 1, 0),
551 };
552
553 /* RONMIX */
554 static const struct snd_kcontrol_new wm8990_dapm_ronmix_controls[] = {
555 SOC_DAPM_SINGLE("RONMIX Right Mixer PGA Switch", WM8990_LINE_MIXER2,
556 WM8990_RROPGARON_BIT, 1, 0),
557 SOC_DAPM_SINGLE("RONMIX Left Mixer PGA Switch", WM8990_LINE_MIXER2,
558 WM8990_RLOPGARON_BIT, 1, 0),
559 SOC_DAPM_SINGLE("RONMIX Inverted ROP Switch", WM8990_LINE_MIXER2,
560 WM8990_ROPRON_BIT, 1, 0),
561 };
562
563 /* ROPMIX */
564 static const struct snd_kcontrol_new wm8990_dapm_ropmix_controls[] = {
565 SOC_DAPM_SINGLE("ROPMIX Left Mic Bypass Switch", WM8990_LINE_MIXER2,
566 WM8990_RL12ROP_BIT, 1, 0),
567 SOC_DAPM_SINGLE("ROPMIX Right Mic Bypass Switch", WM8990_LINE_MIXER2,
568 WM8990_RR12ROP_BIT, 1, 0),
569 SOC_DAPM_SINGLE("ROPMIX Right Mixer PGA Switch", WM8990_LINE_MIXER2,
570 WM8990_RROPGAROP_BIT, 1, 0),
571 };
572
573 /* OUT3MIX */
574 static const struct snd_kcontrol_new wm8990_dapm_out3mix_controls[] = {
575 SOC_DAPM_SINGLE("OUT3MIX LIN4/RXP Bypass Switch", WM8990_OUT3_4_MIXER,
576 WM8990_LI4O3_BIT, 1, 0),
577 SOC_DAPM_SINGLE("OUT3MIX Left Out PGA Switch", WM8990_OUT3_4_MIXER,
578 WM8990_LPGAO3_BIT, 1, 0),
579 };
580
581 /* OUT4MIX */
582 static const struct snd_kcontrol_new wm8990_dapm_out4mix_controls[] = {
583 SOC_DAPM_SINGLE("OUT4MIX Right Out PGA Switch", WM8990_OUT3_4_MIXER,
584 WM8990_RPGAO4_BIT, 1, 0),
585 SOC_DAPM_SINGLE("OUT4MIX RIN4/RXP Bypass Switch", WM8990_OUT3_4_MIXER,
586 WM8990_RI4O4_BIT, 1, 0),
587 };
588
589 /* SPKMIX */
590 static const struct snd_kcontrol_new wm8990_dapm_spkmix_controls[] = {
591 SOC_DAPM_SINGLE("SPKMIX LIN2 Bypass Switch", WM8990_SPEAKER_MIXER,
592 WM8990_LI2SPK_BIT, 1, 0),
593 SOC_DAPM_SINGLE("SPKMIX LADC Bypass Switch", WM8990_SPEAKER_MIXER,
594 WM8990_LB2SPK_BIT, 1, 0),
595 SOC_DAPM_SINGLE("SPKMIX Left Mixer PGA Switch", WM8990_SPEAKER_MIXER,
596 WM8990_LOPGASPK_BIT, 1, 0),
597 SOC_DAPM_SINGLE("SPKMIX Left DAC Switch", WM8990_SPEAKER_MIXER,
598 WM8990_LDSPK_BIT, 1, 0),
599 SOC_DAPM_SINGLE("SPKMIX Right DAC Switch", WM8990_SPEAKER_MIXER,
600 WM8990_RDSPK_BIT, 1, 0),
601 SOC_DAPM_SINGLE("SPKMIX Right Mixer PGA Switch", WM8990_SPEAKER_MIXER,
602 WM8990_ROPGASPK_BIT, 1, 0),
603 SOC_DAPM_SINGLE("SPKMIX RADC Bypass Switch", WM8990_SPEAKER_MIXER,
604 WM8990_RL12ROP_BIT, 1, 0),
605 SOC_DAPM_SINGLE("SPKMIX RIN2 Bypass Switch", WM8990_SPEAKER_MIXER,
606 WM8990_RI2SPK_BIT, 1, 0),
607 };
608
609 static const struct snd_soc_dapm_widget wm8990_dapm_widgets[] = {
610 /* Input Side */
611 /* Input Lines */
612 SND_SOC_DAPM_INPUT("LIN1"),
613 SND_SOC_DAPM_INPUT("LIN2"),
614 SND_SOC_DAPM_INPUT("LIN3"),
615 SND_SOC_DAPM_INPUT("LIN4/RXN"),
616 SND_SOC_DAPM_INPUT("RIN3"),
617 SND_SOC_DAPM_INPUT("RIN4/RXP"),
618 SND_SOC_DAPM_INPUT("RIN1"),
619 SND_SOC_DAPM_INPUT("RIN2"),
620 SND_SOC_DAPM_INPUT("Internal ADC Source"),
621
622 SND_SOC_DAPM_SUPPLY("INL", WM8990_POWER_MANAGEMENT_2, WM8990_AINL_ENA_BIT, 0,
623 NULL, 0),
624 SND_SOC_DAPM_SUPPLY("INR", WM8990_POWER_MANAGEMENT_2, WM8990_AINR_ENA_BIT, 0,
625 NULL, 0),
626
627 /* DACs */
628 SND_SOC_DAPM_ADC("Left ADC", "Left Capture", WM8990_POWER_MANAGEMENT_2,
629 WM8990_ADCL_ENA_BIT, 0),
630 SND_SOC_DAPM_ADC("Right ADC", "Right Capture", WM8990_POWER_MANAGEMENT_2,
631 WM8990_ADCR_ENA_BIT, 0),
632
633 /* Input PGAs */
634 SND_SOC_DAPM_MIXER("LIN12 PGA", WM8990_POWER_MANAGEMENT_2, WM8990_LIN12_ENA_BIT,
635 0, &wm8990_dapm_lin12_pga_controls[0],
636 ARRAY_SIZE(wm8990_dapm_lin12_pga_controls)),
637 SND_SOC_DAPM_MIXER("LIN34 PGA", WM8990_POWER_MANAGEMENT_2, WM8990_LIN34_ENA_BIT,
638 0, &wm8990_dapm_lin34_pga_controls[0],
639 ARRAY_SIZE(wm8990_dapm_lin34_pga_controls)),
640 SND_SOC_DAPM_MIXER("RIN12 PGA", WM8990_POWER_MANAGEMENT_2, WM8990_RIN12_ENA_BIT,
641 0, &wm8990_dapm_rin12_pga_controls[0],
642 ARRAY_SIZE(wm8990_dapm_rin12_pga_controls)),
643 SND_SOC_DAPM_MIXER("RIN34 PGA", WM8990_POWER_MANAGEMENT_2, WM8990_RIN34_ENA_BIT,
644 0, &wm8990_dapm_rin34_pga_controls[0],
645 ARRAY_SIZE(wm8990_dapm_rin34_pga_controls)),
646
647 /* INMIXL */
648 SND_SOC_DAPM_MIXER("INMIXL", SND_SOC_NOPM, 0, 0,
649 &wm8990_dapm_inmixl_controls[0],
650 ARRAY_SIZE(wm8990_dapm_inmixl_controls)),
651
652 /* AINLMUX */
653 SND_SOC_DAPM_MUX("AINLMUX", SND_SOC_NOPM, 0, 0, &wm8990_dapm_ainlmux_controls),
654
655 /* INMIXR */
656 SND_SOC_DAPM_MIXER("INMIXR", SND_SOC_NOPM, 0, 0,
657 &wm8990_dapm_inmixr_controls[0],
658 ARRAY_SIZE(wm8990_dapm_inmixr_controls)),
659
660 /* AINRMUX */
661 SND_SOC_DAPM_MUX("AINRMUX", SND_SOC_NOPM, 0, 0, &wm8990_dapm_ainrmux_controls),
662
663 /* Output Side */
664 /* DACs */
665 SND_SOC_DAPM_DAC("Left DAC", "Left Playback", WM8990_POWER_MANAGEMENT_3,
666 WM8990_DACL_ENA_BIT, 0),
667 SND_SOC_DAPM_DAC("Right DAC", "Right Playback", WM8990_POWER_MANAGEMENT_3,
668 WM8990_DACR_ENA_BIT, 0),
669
670 /* LOMIX */
671 SND_SOC_DAPM_MIXER_E("LOMIX", WM8990_POWER_MANAGEMENT_3, WM8990_LOMIX_ENA_BIT,
672 0, &wm8990_dapm_lomix_controls[0],
673 ARRAY_SIZE(wm8990_dapm_lomix_controls),
674 outmixer_event, SND_SOC_DAPM_PRE_REG),
675
676 /* LONMIX */
677 SND_SOC_DAPM_MIXER("LONMIX", WM8990_POWER_MANAGEMENT_3, WM8990_LON_ENA_BIT, 0,
678 &wm8990_dapm_lonmix_controls[0],
679 ARRAY_SIZE(wm8990_dapm_lonmix_controls)),
680
681 /* LOPMIX */
682 SND_SOC_DAPM_MIXER("LOPMIX", WM8990_POWER_MANAGEMENT_3, WM8990_LOP_ENA_BIT, 0,
683 &wm8990_dapm_lopmix_controls[0],
684 ARRAY_SIZE(wm8990_dapm_lopmix_controls)),
685
686 /* OUT3MIX */
687 SND_SOC_DAPM_MIXER("OUT3MIX", WM8990_POWER_MANAGEMENT_1, WM8990_OUT3_ENA_BIT, 0,
688 &wm8990_dapm_out3mix_controls[0],
689 ARRAY_SIZE(wm8990_dapm_out3mix_controls)),
690
691 /* SPKMIX */
692 SND_SOC_DAPM_MIXER_E("SPKMIX", WM8990_POWER_MANAGEMENT_1, WM8990_SPK_ENA_BIT, 0,
693 &wm8990_dapm_spkmix_controls[0],
694 ARRAY_SIZE(wm8990_dapm_spkmix_controls), outmixer_event,
695 SND_SOC_DAPM_PRE_REG),
696
697 /* OUT4MIX */
698 SND_SOC_DAPM_MIXER("OUT4MIX", WM8990_POWER_MANAGEMENT_1, WM8990_OUT4_ENA_BIT, 0,
699 &wm8990_dapm_out4mix_controls[0],
700 ARRAY_SIZE(wm8990_dapm_out4mix_controls)),
701
702 /* ROPMIX */
703 SND_SOC_DAPM_MIXER("ROPMIX", WM8990_POWER_MANAGEMENT_3, WM8990_ROP_ENA_BIT, 0,
704 &wm8990_dapm_ropmix_controls[0],
705 ARRAY_SIZE(wm8990_dapm_ropmix_controls)),
706
707 /* RONMIX */
708 SND_SOC_DAPM_MIXER("RONMIX", WM8990_POWER_MANAGEMENT_3, WM8990_RON_ENA_BIT, 0,
709 &wm8990_dapm_ronmix_controls[0],
710 ARRAY_SIZE(wm8990_dapm_ronmix_controls)),
711
712 /* ROMIX */
713 SND_SOC_DAPM_MIXER_E("ROMIX", WM8990_POWER_MANAGEMENT_3, WM8990_ROMIX_ENA_BIT,
714 0, &wm8990_dapm_romix_controls[0],
715 ARRAY_SIZE(wm8990_dapm_romix_controls),
716 outmixer_event, SND_SOC_DAPM_PRE_REG),
717
718 /* LOUT PGA */
719 SND_SOC_DAPM_PGA("LOUT PGA", WM8990_POWER_MANAGEMENT_1, WM8990_LOUT_ENA_BIT, 0,
720 NULL, 0),
721
722 /* ROUT PGA */
723 SND_SOC_DAPM_PGA("ROUT PGA", WM8990_POWER_MANAGEMENT_1, WM8990_ROUT_ENA_BIT, 0,
724 NULL, 0),
725
726 /* LOPGA */
727 SND_SOC_DAPM_PGA("LOPGA", WM8990_POWER_MANAGEMENT_3, WM8990_LOPGA_ENA_BIT, 0,
728 NULL, 0),
729
730 /* ROPGA */
731 SND_SOC_DAPM_PGA("ROPGA", WM8990_POWER_MANAGEMENT_3, WM8990_ROPGA_ENA_BIT, 0,
732 NULL, 0),
733
734 /* MICBIAS */
735 SND_SOC_DAPM_SUPPLY("MICBIAS", WM8990_POWER_MANAGEMENT_1,
736 WM8990_MICBIAS_ENA_BIT, 0, NULL, 0),
737
738 SND_SOC_DAPM_OUTPUT("LON"),
739 SND_SOC_DAPM_OUTPUT("LOP"),
740 SND_SOC_DAPM_OUTPUT("OUT3"),
741 SND_SOC_DAPM_OUTPUT("LOUT"),
742 SND_SOC_DAPM_OUTPUT("SPKN"),
743 SND_SOC_DAPM_OUTPUT("SPKP"),
744 SND_SOC_DAPM_OUTPUT("ROUT"),
745 SND_SOC_DAPM_OUTPUT("OUT4"),
746 SND_SOC_DAPM_OUTPUT("ROP"),
747 SND_SOC_DAPM_OUTPUT("RON"),
748
749 SND_SOC_DAPM_OUTPUT("Internal DAC Sink"),
750 };
751
752 static const struct snd_soc_dapm_route wm8990_dapm_routes[] = {
753 /* Make DACs turn on when playing even if not mixed into any outputs */
754 {"Internal DAC Sink", NULL, "Left DAC"},
755 {"Internal DAC Sink", NULL, "Right DAC"},
756
757 /* Make ADCs turn on when recording even if not mixed from any inputs */
758 {"Left ADC", NULL, "Internal ADC Source"},
759 {"Right ADC", NULL, "Internal ADC Source"},
760
761 {"AINLMUX", NULL, "INL"},
762 {"INMIXL", NULL, "INL"},
763 {"AINRMUX", NULL, "INR"},
764 {"INMIXR", NULL, "INR"},
765
766 /* Input Side */
767 /* LIN12 PGA */
768 {"LIN12 PGA", "LIN1 Switch", "LIN1"},
769 {"LIN12 PGA", "LIN2 Switch", "LIN2"},
770 /* LIN34 PGA */
771 {"LIN34 PGA", "LIN3 Switch", "LIN3"},
772 {"LIN34 PGA", "LIN4 Switch", "LIN4/RXN"},
773 /* INMIXL */
774 {"INMIXL", "Record Left Volume", "LOMIX"},
775 {"INMIXL", "LIN2 Volume", "LIN2"},
776 {"INMIXL", "LINPGA12 Switch", "LIN12 PGA"},
777 {"INMIXL", "LINPGA34 Switch", "LIN34 PGA"},
778 /* AINLMUX */
779 {"AINLMUX", "INMIXL Mix", "INMIXL"},
780 {"AINLMUX", "DIFFINL Mix", "LIN12 PGA"},
781 {"AINLMUX", "DIFFINL Mix", "LIN34 PGA"},
782 {"AINLMUX", "RXVOICE Mix", "LIN4/RXN"},
783 {"AINLMUX", "RXVOICE Mix", "RIN4/RXP"},
784 /* ADC */
785 {"Left ADC", NULL, "AINLMUX"},
786
787 /* RIN12 PGA */
788 {"RIN12 PGA", "RIN1 Switch", "RIN1"},
789 {"RIN12 PGA", "RIN2 Switch", "RIN2"},
790 /* RIN34 PGA */
791 {"RIN34 PGA", "RIN3 Switch", "RIN3"},
792 {"RIN34 PGA", "RIN4 Switch", "RIN4/RXP"},
793 /* INMIXL */
794 {"INMIXR", "Record Right Volume", "ROMIX"},
795 {"INMIXR", "RIN2 Volume", "RIN2"},
796 {"INMIXR", "RINPGA12 Switch", "RIN12 PGA"},
797 {"INMIXR", "RINPGA34 Switch", "RIN34 PGA"},
798 /* AINRMUX */
799 {"AINRMUX", "INMIXR Mix", "INMIXR"},
800 {"AINRMUX", "DIFFINR Mix", "RIN12 PGA"},
801 {"AINRMUX", "DIFFINR Mix", "RIN34 PGA"},
802 {"AINRMUX", "RXVOICE Mix", "LIN4/RXN"},
803 {"AINRMUX", "RXVOICE Mix", "RIN4/RXP"},
804 /* ADC */
805 {"Right ADC", NULL, "AINRMUX"},
806
807 /* LOMIX */
808 {"LOMIX", "LOMIX RIN3 Bypass Switch", "RIN3"},
809 {"LOMIX", "LOMIX LIN3 Bypass Switch", "LIN3"},
810 {"LOMIX", "LOMIX LIN12 PGA Bypass Switch", "LIN12 PGA"},
811 {"LOMIX", "LOMIX RIN12 PGA Bypass Switch", "RIN12 PGA"},
812 {"LOMIX", "LOMIX Right ADC Bypass Switch", "AINRMUX"},
813 {"LOMIX", "LOMIX Left ADC Bypass Switch", "AINLMUX"},
814 {"LOMIX", "LOMIX Left DAC Switch", "Left DAC"},
815
816 /* ROMIX */
817 {"ROMIX", "ROMIX RIN3 Bypass Switch", "RIN3"},
818 {"ROMIX", "ROMIX LIN3 Bypass Switch", "LIN3"},
819 {"ROMIX", "ROMIX LIN12 PGA Bypass Switch", "LIN12 PGA"},
820 {"ROMIX", "ROMIX RIN12 PGA Bypass Switch", "RIN12 PGA"},
821 {"ROMIX", "ROMIX Right ADC Bypass Switch", "AINRMUX"},
822 {"ROMIX", "ROMIX Left ADC Bypass Switch", "AINLMUX"},
823 {"ROMIX", "ROMIX Right DAC Switch", "Right DAC"},
824
825 /* SPKMIX */
826 {"SPKMIX", "SPKMIX LIN2 Bypass Switch", "LIN2"},
827 {"SPKMIX", "SPKMIX RIN2 Bypass Switch", "RIN2"},
828 {"SPKMIX", "SPKMIX LADC Bypass Switch", "AINLMUX"},
829 {"SPKMIX", "SPKMIX RADC Bypass Switch", "AINRMUX"},
830 {"SPKMIX", "SPKMIX Left Mixer PGA Switch", "LOPGA"},
831 {"SPKMIX", "SPKMIX Right Mixer PGA Switch", "ROPGA"},
832 {"SPKMIX", "SPKMIX Right DAC Switch", "Right DAC"},
833 {"SPKMIX", "SPKMIX Left DAC Switch", "Left DAC"},
834
835 /* LONMIX */
836 {"LONMIX", "LONMIX Left Mixer PGA Switch", "LOPGA"},
837 {"LONMIX", "LONMIX Right Mixer PGA Switch", "ROPGA"},
838 {"LONMIX", "LONMIX Inverted LOP Switch", "LOPMIX"},
839
840 /* LOPMIX */
841 {"LOPMIX", "LOPMIX Right Mic Bypass Switch", "RIN12 PGA"},
842 {"LOPMIX", "LOPMIX Left Mic Bypass Switch", "LIN12 PGA"},
843 {"LOPMIX", "LOPMIX Left Mixer PGA Switch", "LOPGA"},
844
845 /* OUT3MIX */
846 {"OUT3MIX", "OUT3MIX LIN4/RXP Bypass Switch", "LIN4/RXN"},
847 {"OUT3MIX", "OUT3MIX Left Out PGA Switch", "LOPGA"},
848
849 /* OUT4MIX */
850 {"OUT4MIX", "OUT4MIX Right Out PGA Switch", "ROPGA"},
851 {"OUT4MIX", "OUT4MIX RIN4/RXP Bypass Switch", "RIN4/RXP"},
852
853 /* RONMIX */
854 {"RONMIX", "RONMIX Right Mixer PGA Switch", "ROPGA"},
855 {"RONMIX", "RONMIX Left Mixer PGA Switch", "LOPGA"},
856 {"RONMIX", "RONMIX Inverted ROP Switch", "ROPMIX"},
857
858 /* ROPMIX */
859 {"ROPMIX", "ROPMIX Left Mic Bypass Switch", "LIN12 PGA"},
860 {"ROPMIX", "ROPMIX Right Mic Bypass Switch", "RIN12 PGA"},
861 {"ROPMIX", "ROPMIX Right Mixer PGA Switch", "ROPGA"},
862
863 /* Out Mixer PGAs */
864 {"LOPGA", NULL, "LOMIX"},
865 {"ROPGA", NULL, "ROMIX"},
866
867 {"LOUT PGA", NULL, "LOMIX"},
868 {"ROUT PGA", NULL, "ROMIX"},
869
870 /* Output Pins */
871 {"LON", NULL, "LONMIX"},
872 {"LOP", NULL, "LOPMIX"},
873 {"OUT3", NULL, "OUT3MIX"},
874 {"LOUT", NULL, "LOUT PGA"},
875 {"SPKN", NULL, "SPKMIX"},
876 {"ROUT", NULL, "ROUT PGA"},
877 {"OUT4", NULL, "OUT4MIX"},
878 {"ROP", NULL, "ROPMIX"},
879 {"RON", NULL, "RONMIX"},
880 };
881
882 /* PLL divisors */
883 struct _pll_div {
884 u32 div2;
885 u32 n;
886 u32 k;
887 };
888
889 /* The size in bits of the pll divide multiplied by 10
890 * to allow rounding later */
891 #define FIXED_PLL_SIZE ((1 << 16) * 10)
892
893 static void pll_factors(struct _pll_div *pll_div, unsigned int target,
894 unsigned int source)
895 {
896 u64 Kpart;
897 unsigned int K, Ndiv, Nmod;
898
899
900 Ndiv = target / source;
901 if (Ndiv < 6) {
902 source >>= 1;
903 pll_div->div2 = 1;
904 Ndiv = target / source;
905 } else
906 pll_div->div2 = 0;
907
908 if ((Ndiv < 6) || (Ndiv > 12))
909 printk(KERN_WARNING
910 "WM8990 N value outwith recommended range! N = %u\n", Ndiv);
911
912 pll_div->n = Ndiv;
913 Nmod = target % source;
914 Kpart = FIXED_PLL_SIZE * (long long)Nmod;
915
916 do_div(Kpart, source);
917
918 K = Kpart & 0xFFFFFFFF;
919
920 /* Check if we need to round */
921 if ((K % 10) >= 5)
922 K += 5;
923
924 /* Move down to proper range now rounding is done */
925 K /= 10;
926
927 pll_div->k = K;
928 }
929
930 static int wm8990_set_dai_pll(struct snd_soc_dai *codec_dai, int pll_id,
931 int source, unsigned int freq_in, unsigned int freq_out)
932 {
933 struct snd_soc_component *component = codec_dai->component;
934 struct _pll_div pll_div;
935
936 if (freq_in && freq_out) {
937 pll_factors(&pll_div, freq_out * 4, freq_in);
938
939 /* Turn on PLL */
940 snd_soc_component_update_bits(component, WM8990_POWER_MANAGEMENT_2,
941 WM8990_PLL_ENA, WM8990_PLL_ENA);
942
943 /* sysclk comes from PLL */
944 snd_soc_component_update_bits(component, WM8990_CLOCKING_2,
945 WM8990_SYSCLK_SRC, WM8990_SYSCLK_SRC);
946
947 /* set up N , fractional mode and pre-divisor if necessary */
948 snd_soc_component_write(component, WM8990_PLL1, pll_div.n | WM8990_SDM |
949 (pll_div.div2?WM8990_PRESCALE:0));
950 snd_soc_component_write(component, WM8990_PLL2, (u8)(pll_div.k>>8));
951 snd_soc_component_write(component, WM8990_PLL3, (u8)(pll_div.k & 0xFF));
952 } else {
953 /* Turn off PLL */
954 snd_soc_component_update_bits(component, WM8990_POWER_MANAGEMENT_2,
955 WM8990_PLL_ENA, 0);
956 }
957 return 0;
958 }
959
960 /*
961 * Clock after PLL and dividers
962 */
963 static int wm8990_set_dai_sysclk(struct snd_soc_dai *codec_dai,
964 int clk_id, unsigned int freq, int dir)
965 {
966 struct snd_soc_component *component = codec_dai->component;
967 struct wm8990_priv *wm8990 = snd_soc_component_get_drvdata(component);
968
969 wm8990->sysclk = freq;
970 return 0;
971 }
972
973 /*
974 * Set's ADC and Voice DAC format.
975 */
976 static int wm8990_set_dai_fmt(struct snd_soc_dai *codec_dai,
977 unsigned int fmt)
978 {
979 struct snd_soc_component *component = codec_dai->component;
980 u16 audio1, audio3;
981
982 audio1 = snd_soc_component_read32(component, WM8990_AUDIO_INTERFACE_1);
983 audio3 = snd_soc_component_read32(component, WM8990_AUDIO_INTERFACE_3);
984
985 /* set master/slave audio interface */
986 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
987 case SND_SOC_DAIFMT_CBS_CFS:
988 audio3 &= ~WM8990_AIF_MSTR1;
989 break;
990 case SND_SOC_DAIFMT_CBM_CFM:
991 audio3 |= WM8990_AIF_MSTR1;
992 break;
993 default:
994 return -EINVAL;
995 }
996
997 audio1 &= ~WM8990_AIF_FMT_MASK;
998
999 /* interface format */
1000 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1001 case SND_SOC_DAIFMT_I2S:
1002 audio1 |= WM8990_AIF_TMF_I2S;
1003 audio1 &= ~WM8990_AIF_LRCLK_INV;
1004 break;
1005 case SND_SOC_DAIFMT_RIGHT_J:
1006 audio1 |= WM8990_AIF_TMF_RIGHTJ;
1007 audio1 &= ~WM8990_AIF_LRCLK_INV;
1008 break;
1009 case SND_SOC_DAIFMT_LEFT_J:
1010 audio1 |= WM8990_AIF_TMF_LEFTJ;
1011 audio1 &= ~WM8990_AIF_LRCLK_INV;
1012 break;
1013 case SND_SOC_DAIFMT_DSP_A:
1014 audio1 |= WM8990_AIF_TMF_DSP;
1015 audio1 &= ~WM8990_AIF_LRCLK_INV;
1016 break;
1017 case SND_SOC_DAIFMT_DSP_B:
1018 audio1 |= WM8990_AIF_TMF_DSP | WM8990_AIF_LRCLK_INV;
1019 break;
1020 default:
1021 return -EINVAL;
1022 }
1023
1024 snd_soc_component_write(component, WM8990_AUDIO_INTERFACE_1, audio1);
1025 snd_soc_component_write(component, WM8990_AUDIO_INTERFACE_3, audio3);
1026 return 0;
1027 }
1028
1029 static int wm8990_set_dai_clkdiv(struct snd_soc_dai *codec_dai,
1030 int div_id, int div)
1031 {
1032 struct snd_soc_component *component = codec_dai->component;
1033
1034 switch (div_id) {
1035 case WM8990_MCLK_DIV:
1036 snd_soc_component_update_bits(component, WM8990_CLOCKING_2,
1037 WM8990_MCLK_DIV_MASK, div);
1038 break;
1039 case WM8990_DACCLK_DIV:
1040 snd_soc_component_update_bits(component, WM8990_CLOCKING_2,
1041 WM8990_DAC_CLKDIV_MASK, div);
1042 break;
1043 case WM8990_ADCCLK_DIV:
1044 snd_soc_component_update_bits(component, WM8990_CLOCKING_2,
1045 WM8990_ADC_CLKDIV_MASK, div);
1046 break;
1047 case WM8990_BCLK_DIV:
1048 snd_soc_component_update_bits(component, WM8990_CLOCKING_1,
1049 WM8990_BCLK_DIV_MASK, div);
1050 break;
1051 default:
1052 return -EINVAL;
1053 }
1054
1055 return 0;
1056 }
1057
1058 /*
1059 * Set PCM DAI bit size and sample rate.
1060 */
1061 static int wm8990_hw_params(struct snd_pcm_substream *substream,
1062 struct snd_pcm_hw_params *params,
1063 struct snd_soc_dai *dai)
1064 {
1065 struct snd_soc_component *component = dai->component;
1066 u16 audio1 = snd_soc_component_read32(component, WM8990_AUDIO_INTERFACE_1);
1067
1068 audio1 &= ~WM8990_AIF_WL_MASK;
1069 /* bit size */
1070 switch (params_width(params)) {
1071 case 16:
1072 break;
1073 case 20:
1074 audio1 |= WM8990_AIF_WL_20BITS;
1075 break;
1076 case 24:
1077 audio1 |= WM8990_AIF_WL_24BITS;
1078 break;
1079 case 32:
1080 audio1 |= WM8990_AIF_WL_32BITS;
1081 break;
1082 }
1083
1084 snd_soc_component_write(component, WM8990_AUDIO_INTERFACE_1, audio1);
1085 return 0;
1086 }
1087
1088 static int wm8990_mute(struct snd_soc_dai *dai, int mute)
1089 {
1090 struct snd_soc_component *component = dai->component;
1091 u16 val;
1092
1093 val = snd_soc_component_read32(component, WM8990_DAC_CTRL) & ~WM8990_DAC_MUTE;
1094
1095 if (mute)
1096 snd_soc_component_write(component, WM8990_DAC_CTRL, val | WM8990_DAC_MUTE);
1097 else
1098 snd_soc_component_write(component, WM8990_DAC_CTRL, val);
1099
1100 return 0;
1101 }
1102
1103 static int wm8990_set_bias_level(struct snd_soc_component *component,
1104 enum snd_soc_bias_level level)
1105 {
1106 struct wm8990_priv *wm8990 = snd_soc_component_get_drvdata(component);
1107 int ret;
1108
1109 switch (level) {
1110 case SND_SOC_BIAS_ON:
1111 break;
1112
1113 case SND_SOC_BIAS_PREPARE:
1114 /* VMID=2*50k */
1115 snd_soc_component_update_bits(component, WM8990_POWER_MANAGEMENT_1,
1116 WM8990_VMID_MODE_MASK, 0x2);
1117 break;
1118
1119 case SND_SOC_BIAS_STANDBY:
1120 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
1121 ret = regcache_sync(wm8990->regmap);
1122 if (ret < 0) {
1123 dev_err(component->dev, "Failed to sync cache: %d\n", ret);
1124 return ret;
1125 }
1126
1127 /* Enable all output discharge bits */
1128 snd_soc_component_write(component, WM8990_ANTIPOP1, WM8990_DIS_LLINE |
1129 WM8990_DIS_RLINE | WM8990_DIS_OUT3 |
1130 WM8990_DIS_OUT4 | WM8990_DIS_LOUT |
1131 WM8990_DIS_ROUT);
1132
1133 /* Enable POBCTRL, SOFT_ST, VMIDTOG and BUFDCOPEN */
1134 snd_soc_component_write(component, WM8990_ANTIPOP2, WM8990_SOFTST |
1135 WM8990_BUFDCOPEN | WM8990_POBCTRL |
1136 WM8990_VMIDTOG);
1137
1138 /* Delay to allow output caps to discharge */
1139 msleep(300);
1140
1141 /* Disable VMIDTOG */
1142 snd_soc_component_write(component, WM8990_ANTIPOP2, WM8990_SOFTST |
1143 WM8990_BUFDCOPEN | WM8990_POBCTRL);
1144
1145 /* disable all output discharge bits */
1146 snd_soc_component_write(component, WM8990_ANTIPOP1, 0);
1147
1148 /* Enable outputs */
1149 snd_soc_component_write(component, WM8990_POWER_MANAGEMENT_1, 0x1b00);
1150
1151 msleep(50);
1152
1153 /* Enable VMID at 2x50k */
1154 snd_soc_component_write(component, WM8990_POWER_MANAGEMENT_1, 0x1f02);
1155
1156 msleep(100);
1157
1158 /* Enable VREF */
1159 snd_soc_component_write(component, WM8990_POWER_MANAGEMENT_1, 0x1f03);
1160
1161 msleep(600);
1162
1163 /* Enable BUFIOEN */
1164 snd_soc_component_write(component, WM8990_ANTIPOP2, WM8990_SOFTST |
1165 WM8990_BUFDCOPEN | WM8990_POBCTRL |
1166 WM8990_BUFIOEN);
1167
1168 /* Disable outputs */
1169 snd_soc_component_write(component, WM8990_POWER_MANAGEMENT_1, 0x3);
1170
1171 /* disable POBCTRL, SOFT_ST and BUFDCOPEN */
1172 snd_soc_component_write(component, WM8990_ANTIPOP2, WM8990_BUFIOEN);
1173
1174 /* Enable workaround for ADC clocking issue. */
1175 snd_soc_component_write(component, WM8990_EXT_ACCESS_ENA, 0x2);
1176 snd_soc_component_write(component, WM8990_EXT_CTL1, 0xa003);
1177 snd_soc_component_write(component, WM8990_EXT_ACCESS_ENA, 0);
1178 }
1179
1180 /* VMID=2*250k */
1181 snd_soc_component_update_bits(component, WM8990_POWER_MANAGEMENT_1,
1182 WM8990_VMID_MODE_MASK, 0x4);
1183 break;
1184
1185 case SND_SOC_BIAS_OFF:
1186 /* Enable POBCTRL and SOFT_ST */
1187 snd_soc_component_write(component, WM8990_ANTIPOP2, WM8990_SOFTST |
1188 WM8990_POBCTRL | WM8990_BUFIOEN);
1189
1190 /* Enable POBCTRL, SOFT_ST and BUFDCOPEN */
1191 snd_soc_component_write(component, WM8990_ANTIPOP2, WM8990_SOFTST |
1192 WM8990_BUFDCOPEN | WM8990_POBCTRL |
1193 WM8990_BUFIOEN);
1194
1195 /* mute DAC */
1196 snd_soc_component_update_bits(component, WM8990_DAC_CTRL,
1197 WM8990_DAC_MUTE, WM8990_DAC_MUTE);
1198
1199 /* Enable any disabled outputs */
1200 snd_soc_component_write(component, WM8990_POWER_MANAGEMENT_1, 0x1f03);
1201
1202 /* Disable VMID */
1203 snd_soc_component_write(component, WM8990_POWER_MANAGEMENT_1, 0x1f01);
1204
1205 msleep(300);
1206
1207 /* Enable all output discharge bits */
1208 snd_soc_component_write(component, WM8990_ANTIPOP1, WM8990_DIS_LLINE |
1209 WM8990_DIS_RLINE | WM8990_DIS_OUT3 |
1210 WM8990_DIS_OUT4 | WM8990_DIS_LOUT |
1211 WM8990_DIS_ROUT);
1212
1213 /* Disable VREF */
1214 snd_soc_component_write(component, WM8990_POWER_MANAGEMENT_1, 0x0);
1215
1216 /* disable POBCTRL, SOFT_ST and BUFDCOPEN */
1217 snd_soc_component_write(component, WM8990_ANTIPOP2, 0x0);
1218
1219 regcache_mark_dirty(wm8990->regmap);
1220 break;
1221 }
1222
1223 return 0;
1224 }
1225
1226 #define WM8990_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\
1227 SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 | SNDRV_PCM_RATE_44100 | \
1228 SNDRV_PCM_RATE_48000)
1229
1230 #define WM8990_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
1231 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
1232
1233 /*
1234 * The WM8990 supports 2 different and mutually exclusive DAI
1235 * configurations.
1236 *
1237 * 1. ADC/DAC on Primary Interface
1238 * 2. ADC on Primary Interface/DAC on secondary
1239 */
1240 static const struct snd_soc_dai_ops wm8990_dai_ops = {
1241 .hw_params = wm8990_hw_params,
1242 .digital_mute = wm8990_mute,
1243 .set_fmt = wm8990_set_dai_fmt,
1244 .set_clkdiv = wm8990_set_dai_clkdiv,
1245 .set_pll = wm8990_set_dai_pll,
1246 .set_sysclk = wm8990_set_dai_sysclk,
1247 };
1248
1249 static struct snd_soc_dai_driver wm8990_dai = {
1250 /* ADC/DAC on primary */
1251 .name = "wm8990-hifi",
1252 .playback = {
1253 .stream_name = "Playback",
1254 .channels_min = 1,
1255 .channels_max = 2,
1256 .rates = WM8990_RATES,
1257 .formats = WM8990_FORMATS,},
1258 .capture = {
1259 .stream_name = "Capture",
1260 .channels_min = 1,
1261 .channels_max = 2,
1262 .rates = WM8990_RATES,
1263 .formats = WM8990_FORMATS,},
1264 .ops = &wm8990_dai_ops,
1265 };
1266
1267 /*
1268 * initialise the WM8990 driver
1269 * register the mixer and dsp interfaces with the kernel
1270 */
1271 static int wm8990_probe(struct snd_soc_component *component)
1272 {
1273 wm8990_reset(component);
1274
1275 /* charge output caps */
1276 snd_soc_component_force_bias_level(component, SND_SOC_BIAS_STANDBY);
1277
1278 snd_soc_component_update_bits(component, WM8990_AUDIO_INTERFACE_4,
1279 WM8990_ALRCGPIO1, WM8990_ALRCGPIO1);
1280
1281 snd_soc_component_update_bits(component, WM8990_GPIO1_GPIO2,
1282 WM8990_GPIO1_SEL_MASK, 1);
1283
1284 snd_soc_component_update_bits(component, WM8990_POWER_MANAGEMENT_2,
1285 WM8990_OPCLK_ENA, WM8990_OPCLK_ENA);
1286
1287 snd_soc_component_write(component, WM8990_LEFT_OUTPUT_VOLUME, 0x50 | (1<<8));
1288 snd_soc_component_write(component, WM8990_RIGHT_OUTPUT_VOLUME, 0x50 | (1<<8));
1289
1290 return 0;
1291 }
1292
1293 static const struct snd_soc_component_driver soc_component_dev_wm8990 = {
1294 .probe = wm8990_probe,
1295 .set_bias_level = wm8990_set_bias_level,
1296 .controls = wm8990_snd_controls,
1297 .num_controls = ARRAY_SIZE(wm8990_snd_controls),
1298 .dapm_widgets = wm8990_dapm_widgets,
1299 .num_dapm_widgets = ARRAY_SIZE(wm8990_dapm_widgets),
1300 .dapm_routes = wm8990_dapm_routes,
1301 .num_dapm_routes = ARRAY_SIZE(wm8990_dapm_routes),
1302 .suspend_bias_off = 1,
1303 .idle_bias_on = 1,
1304 .use_pmdown_time = 1,
1305 .endianness = 1,
1306 .non_legacy_dai_naming = 1,
1307 };
1308
1309 static const struct regmap_config wm8990_regmap = {
1310 .reg_bits = 8,
1311 .val_bits = 16,
1312
1313 .max_register = WM8990_PLL3,
1314 .volatile_reg = wm8990_volatile_register,
1315 .reg_defaults = wm8990_reg_defaults,
1316 .num_reg_defaults = ARRAY_SIZE(wm8990_reg_defaults),
1317 .cache_type = REGCACHE_RBTREE,
1318 };
1319
1320 static int wm8990_i2c_probe(struct i2c_client *i2c,
1321 const struct i2c_device_id *id)
1322 {
1323 struct wm8990_priv *wm8990;
1324 int ret;
1325
1326 wm8990 = devm_kzalloc(&i2c->dev, sizeof(struct wm8990_priv),
1327 GFP_KERNEL);
1328 if (wm8990 == NULL)
1329 return -ENOMEM;
1330
1331 i2c_set_clientdata(i2c, wm8990);
1332
1333 ret = devm_snd_soc_register_component(&i2c->dev,
1334 &soc_component_dev_wm8990, &wm8990_dai, 1);
1335
1336 return ret;
1337 }
1338
1339 static const struct i2c_device_id wm8990_i2c_id[] = {
1340 { "wm8990", 0 },
1341 { }
1342 };
1343 MODULE_DEVICE_TABLE(i2c, wm8990_i2c_id);
1344
1345 static struct i2c_driver wm8990_i2c_driver = {
1346 .driver = {
1347 .name = "wm8990",
1348 },
1349 .probe = wm8990_i2c_probe,
1350 .id_table = wm8990_i2c_id,
1351 };
1352
1353 module_i2c_driver(wm8990_i2c_driver);
1354
1355 MODULE_DESCRIPTION("ASoC WM8990 driver");
1356 MODULE_AUTHOR("Liam Girdwood");
1357 MODULE_LICENSE("GPL");
Linux with added FPC-III support