?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
ARM: dts: omap5: Add bus_dma_limit for L3 bus
[linux/fpc-iii.git] / sound / soc / codecs / wm8994.c
blob15ce64a48a87438672678f128be57f05f91eaa6d
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * wm8994.c -- WM8994 ALSA SoC Audio driver
4 *
5 * Copyright 2009-12 Wolfson Microelectronics plc
6 *
7 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
8 */
9
10 #include <linux/module.h>
11 #include <linux/moduleparam.h>
12 #include <linux/init.h>
13 #include <linux/delay.h>
14 #include <linux/pm.h>
15 #include <linux/gcd.h>
16 #include <linux/i2c.h>
17 #include <linux/platform_device.h>
18 #include <linux/pm_runtime.h>
19 #include <linux/regulator/consumer.h>
20 #include <linux/slab.h>
21 #include <sound/core.h>
22 #include <sound/jack.h>
23 #include <sound/pcm.h>
24 #include <sound/pcm_params.h>
25 #include <sound/soc.h>
26 #include <sound/initval.h>
27 #include <sound/tlv.h>
28 #include <trace/events/asoc.h>
29
30 #include <linux/mfd/wm8994/core.h>
31 #include <linux/mfd/wm8994/registers.h>
32 #include <linux/mfd/wm8994/pdata.h>
33 #include <linux/mfd/wm8994/gpio.h>
34
35 #include "wm8994.h"
36 #include "wm_hubs.h"
37
38 #define WM1811_JACKDET_MODE_NONE 0x0000
39 #define WM1811_JACKDET_MODE_JACK 0x0100
40 #define WM1811_JACKDET_MODE_MIC 0x0080
41 #define WM1811_JACKDET_MODE_AUDIO 0x0180
42
43 #define WM8994_NUM_DRC 3
44 #define WM8994_NUM_EQ 3
45
46 static struct {
47 unsigned int reg;
48 unsigned int mask;
49 } wm8994_vu_bits[] = {
50 { WM8994_LEFT_LINE_INPUT_1_2_VOLUME, WM8994_IN1_VU },
51 { WM8994_RIGHT_LINE_INPUT_1_2_VOLUME, WM8994_IN1_VU },
52 { WM8994_LEFT_LINE_INPUT_3_4_VOLUME, WM8994_IN2_VU },
53 { WM8994_RIGHT_LINE_INPUT_3_4_VOLUME, WM8994_IN2_VU },
54 { WM8994_SPEAKER_VOLUME_LEFT, WM8994_SPKOUT_VU },
55 { WM8994_SPEAKER_VOLUME_RIGHT, WM8994_SPKOUT_VU },
56 { WM8994_LEFT_OUTPUT_VOLUME, WM8994_HPOUT1_VU },
57 { WM8994_RIGHT_OUTPUT_VOLUME, WM8994_HPOUT1_VU },
58 { WM8994_LEFT_OPGA_VOLUME, WM8994_MIXOUT_VU },
59 { WM8994_RIGHT_OPGA_VOLUME, WM8994_MIXOUT_VU },
60
61 { WM8994_AIF1_DAC1_LEFT_VOLUME, WM8994_AIF1DAC1_VU },
62 { WM8994_AIF1_DAC1_RIGHT_VOLUME, WM8994_AIF1DAC1_VU },
63 { WM8994_AIF1_DAC2_LEFT_VOLUME, WM8994_AIF1DAC2_VU },
64 { WM8994_AIF1_DAC2_RIGHT_VOLUME, WM8994_AIF1DAC2_VU },
65 { WM8994_AIF2_DAC_LEFT_VOLUME, WM8994_AIF2DAC_VU },
66 { WM8994_AIF2_DAC_RIGHT_VOLUME, WM8994_AIF2DAC_VU },
67 { WM8994_AIF1_ADC1_LEFT_VOLUME, WM8994_AIF1ADC1_VU },
68 { WM8994_AIF1_ADC1_RIGHT_VOLUME, WM8994_AIF1ADC1_VU },
69 { WM8994_AIF1_ADC2_LEFT_VOLUME, WM8994_AIF1ADC2_VU },
70 { WM8994_AIF1_ADC2_RIGHT_VOLUME, WM8994_AIF1ADC2_VU },
71 { WM8994_AIF2_ADC_LEFT_VOLUME, WM8994_AIF2ADC_VU },
72 { WM8994_AIF2_ADC_RIGHT_VOLUME, WM8994_AIF1ADC2_VU },
73 { WM8994_DAC1_LEFT_VOLUME, WM8994_DAC1_VU },
74 { WM8994_DAC1_RIGHT_VOLUME, WM8994_DAC1_VU },
75 { WM8994_DAC2_LEFT_VOLUME, WM8994_DAC2_VU },
76 { WM8994_DAC2_RIGHT_VOLUME, WM8994_DAC2_VU },
77 };
78
79 static int wm8994_drc_base[] = {
80 WM8994_AIF1_DRC1_1,
81 WM8994_AIF1_DRC2_1,
82 WM8994_AIF2_DRC_1,
83 };
84
85 static int wm8994_retune_mobile_base[] = {
86 WM8994_AIF1_DAC1_EQ_GAINS_1,
87 WM8994_AIF1_DAC2_EQ_GAINS_1,
88 WM8994_AIF2_EQ_GAINS_1,
89 };
90
91 static const struct wm8958_micd_rate micdet_rates[] = {
92 { 32768, true, 1, 4 },
93 { 32768, false, 1, 1 },
94 { 44100 * 256, true, 7, 10 },
95 { 44100 * 256, false, 7, 10 },
96 };
97
98 static const struct wm8958_micd_rate jackdet_rates[] = {
99 { 32768, true, 0, 1 },
100 { 32768, false, 0, 1 },
101 { 44100 * 256, true, 10, 10 },
102 { 44100 * 256, false, 7, 8 },
103 };
104
105 static void wm8958_micd_set_rate(struct snd_soc_component *component)
106 {
107 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
108 struct wm8994 *control = wm8994->wm8994;
109 int best, i, sysclk, val;
110 bool idle;
111 const struct wm8958_micd_rate *rates;
112 int num_rates;
113
114 idle = !wm8994->jack_mic;
115
116 sysclk = snd_soc_component_read32(component, WM8994_CLOCKING_1);
117 if (sysclk & WM8994_SYSCLK_SRC)
118 sysclk = wm8994->aifclk[1];
119 else
120 sysclk = wm8994->aifclk[0];
121
122 if (control->pdata.micd_rates) {
123 rates = control->pdata.micd_rates;
124 num_rates = control->pdata.num_micd_rates;
125 } else if (wm8994->jackdet) {
126 rates = jackdet_rates;
127 num_rates = ARRAY_SIZE(jackdet_rates);
128 } else {
129 rates = micdet_rates;
130 num_rates = ARRAY_SIZE(micdet_rates);
131 }
132
133 best = 0;
134 for (i = 0; i < num_rates; i++) {
135 if (rates[i].idle != idle)
136 continue;
137 if (abs(rates[i].sysclk - sysclk) <
138 abs(rates[best].sysclk - sysclk))
139 best = i;
140 else if (rates[best].idle != idle)
141 best = i;
142 }
143
144 val = rates[best].start << WM8958_MICD_BIAS_STARTTIME_SHIFT
145 | rates[best].rate << WM8958_MICD_RATE_SHIFT;
146
147 dev_dbg(component->dev, "MICD rate %d,%d for %dHz %s\n",
148 rates[best].start, rates[best].rate, sysclk,
149 idle ? "idle" : "active");
150
151 snd_soc_component_update_bits(component, WM8958_MIC_DETECT_1,
152 WM8958_MICD_BIAS_STARTTIME_MASK |
153 WM8958_MICD_RATE_MASK, val);
154 }
155
156 static int configure_aif_clock(struct snd_soc_component *component, int aif)
157 {
158 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
159 int rate;
160 int reg1 = 0;
161 int offset;
162
163 if (aif)
164 offset = 4;
165 else
166 offset = 0;
167
168 switch (wm8994->sysclk[aif]) {
169 case WM8994_SYSCLK_MCLK1:
170 rate = wm8994->mclk_rate[0];
171 break;
172
173 case WM8994_SYSCLK_MCLK2:
174 reg1 |= 0x8;
175 rate = wm8994->mclk_rate[1];
176 break;
177
178 case WM8994_SYSCLK_FLL1:
179 reg1 |= 0x10;
180 rate = wm8994->fll[0].out;
181 break;
182
183 case WM8994_SYSCLK_FLL2:
184 reg1 |= 0x18;
185 rate = wm8994->fll[1].out;
186 break;
187
188 default:
189 return -EINVAL;
190 }
191
192 if (rate >= 13500000) {
193 rate /= 2;
194 reg1 |= WM8994_AIF1CLK_DIV;
195
196 dev_dbg(component->dev, "Dividing AIF%d clock to %dHz\n",
197 aif + 1, rate);
198 }
199
200 wm8994->aifclk[aif] = rate;
201
202 snd_soc_component_update_bits(component, WM8994_AIF1_CLOCKING_1 + offset,
203 WM8994_AIF1CLK_SRC_MASK | WM8994_AIF1CLK_DIV,
204 reg1);
205
206 return 0;
207 }
208
209 static int configure_clock(struct snd_soc_component *component)
210 {
211 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
212 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
213 int change, new;
214
215 /* Bring up the AIF clocks first */
216 configure_aif_clock(component, 0);
217 configure_aif_clock(component, 1);
218
219 /* Then switch CLK_SYS over to the higher of them; a change
220 * can only happen as a result of a clocking change which can
221 * only be made outside of DAPM so we can safely redo the
222 * clocking.
223 */
224
225 /* If they're equal it doesn't matter which is used */
226 if (wm8994->aifclk[0] == wm8994->aifclk[1]) {
227 wm8958_micd_set_rate(component);
228 return 0;
229 }
230
231 if (wm8994->aifclk[0] < wm8994->aifclk[1])
232 new = WM8994_SYSCLK_SRC;
233 else
234 new = 0;
235
236 change = snd_soc_component_update_bits(component, WM8994_CLOCKING_1,
237 WM8994_SYSCLK_SRC, new);
238 if (change)
239 snd_soc_dapm_sync(dapm);
240
241 wm8958_micd_set_rate(component);
242
243 return 0;
244 }
245
246 static int check_clk_sys(struct snd_soc_dapm_widget *source,
247 struct snd_soc_dapm_widget *sink)
248 {
249 struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm);
250 int reg = snd_soc_component_read32(component, WM8994_CLOCKING_1);
251 const char *clk;
252
253 /* Check what we're currently using for CLK_SYS */
254 if (reg & WM8994_SYSCLK_SRC)
255 clk = "AIF2CLK";
256 else
257 clk = "AIF1CLK";
258
259 return strcmp(source->name, clk) == 0;
260 }
261
262 static const char *sidetone_hpf_text[] = {
263 "2.7kHz", "1.35kHz", "675Hz", "370Hz", "180Hz", "90Hz", "45Hz"
264 };
265
266 static SOC_ENUM_SINGLE_DECL(sidetone_hpf,
267 WM8994_SIDETONE, 7, sidetone_hpf_text);
268
269 static const char *adc_hpf_text[] = {
270 "HiFi", "Voice 1", "Voice 2", "Voice 3"
271 };
272
273 static SOC_ENUM_SINGLE_DECL(aif1adc1_hpf,
274 WM8994_AIF1_ADC1_FILTERS, 13, adc_hpf_text);
275
276 static SOC_ENUM_SINGLE_DECL(aif1adc2_hpf,
277 WM8994_AIF1_ADC2_FILTERS, 13, adc_hpf_text);
278
279 static SOC_ENUM_SINGLE_DECL(aif2adc_hpf,
280 WM8994_AIF2_ADC_FILTERS, 13, adc_hpf_text);
281
282 static const DECLARE_TLV_DB_SCALE(aif_tlv, 0, 600, 0);
283 static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
284 static const DECLARE_TLV_DB_SCALE(st_tlv, -3600, 300, 0);
285 static const DECLARE_TLV_DB_SCALE(wm8994_3d_tlv, -1600, 183, 0);
286 static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
287 static const DECLARE_TLV_DB_SCALE(ng_tlv, -10200, 600, 0);
288 static const DECLARE_TLV_DB_SCALE(mixin_boost_tlv, 0, 900, 0);
289
290 #define WM8994_DRC_SWITCH(xname, reg, shift) \
291 SOC_SINGLE_EXT(xname, reg, shift, 1, 0, \
292 snd_soc_get_volsw, wm8994_put_drc_sw)
293
294 static int wm8994_put_drc_sw(struct snd_kcontrol *kcontrol,
295 struct snd_ctl_elem_value *ucontrol)
296 {
297 struct soc_mixer_control *mc =
298 (struct soc_mixer_control *)kcontrol->private_value;
299 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
300 int mask, ret;
301
302 /* Can't enable both ADC and DAC paths simultaneously */
303 if (mc->shift == WM8994_AIF1DAC1_DRC_ENA_SHIFT)
304 mask = WM8994_AIF1ADC1L_DRC_ENA_MASK |
305 WM8994_AIF1ADC1R_DRC_ENA_MASK;
306 else
307 mask = WM8994_AIF1DAC1_DRC_ENA_MASK;
308
309 ret = snd_soc_component_read32(component, mc->reg);
310 if (ret < 0)
311 return ret;
312 if (ret & mask)
313 return -EINVAL;
314
315 return snd_soc_put_volsw(kcontrol, ucontrol);
316 }
317
318 static void wm8994_set_drc(struct snd_soc_component *component, int drc)
319 {
320 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
321 struct wm8994 *control = wm8994->wm8994;
322 struct wm8994_pdata *pdata = &control->pdata;
323 int base = wm8994_drc_base[drc];
324 int cfg = wm8994->drc_cfg[drc];
325 int save, i;
326
327 /* Save any enables; the configuration should clear them. */
328 save = snd_soc_component_read32(component, base);
329 save &= WM8994_AIF1DAC1_DRC_ENA | WM8994_AIF1ADC1L_DRC_ENA |
330 WM8994_AIF1ADC1R_DRC_ENA;
331
332 for (i = 0; i < WM8994_DRC_REGS; i++)
333 snd_soc_component_update_bits(component, base + i, 0xffff,
334 pdata->drc_cfgs[cfg].regs[i]);
335
336 snd_soc_component_update_bits(component, base, WM8994_AIF1DAC1_DRC_ENA |
337 WM8994_AIF1ADC1L_DRC_ENA |
338 WM8994_AIF1ADC1R_DRC_ENA, save);
339 }
340
341 /* Icky as hell but saves code duplication */
342 static int wm8994_get_drc(const char *name)
343 {
344 if (strcmp(name, "AIF1DRC1 Mode") == 0)
345 return 0;
346 if (strcmp(name, "AIF1DRC2 Mode") == 0)
347 return 1;
348 if (strcmp(name, "AIF2DRC Mode") == 0)
349 return 2;
350 return -EINVAL;
351 }
352
353 static int wm8994_put_drc_enum(struct snd_kcontrol *kcontrol,
354 struct snd_ctl_elem_value *ucontrol)
355 {
356 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
357 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
358 struct wm8994 *control = wm8994->wm8994;
359 struct wm8994_pdata *pdata = &control->pdata;
360 int drc = wm8994_get_drc(kcontrol->id.name);
361 int value = ucontrol->value.enumerated.item[0];
362
363 if (drc < 0)
364 return drc;
365
366 if (value >= pdata->num_drc_cfgs)
367 return -EINVAL;
368
369 wm8994->drc_cfg[drc] = value;
370
371 wm8994_set_drc(component, drc);
372
373 return 0;
374 }
375
376 static int wm8994_get_drc_enum(struct snd_kcontrol *kcontrol,
377 struct snd_ctl_elem_value *ucontrol)
378 {
379 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
380 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
381 int drc = wm8994_get_drc(kcontrol->id.name);
382
383 if (drc < 0)
384 return drc;
385 ucontrol->value.enumerated.item[0] = wm8994->drc_cfg[drc];
386
387 return 0;
388 }
389
390 static void wm8994_set_retune_mobile(struct snd_soc_component *component, int block)
391 {
392 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
393 struct wm8994 *control = wm8994->wm8994;
394 struct wm8994_pdata *pdata = &control->pdata;
395 int base = wm8994_retune_mobile_base[block];
396 int iface, best, best_val, save, i, cfg;
397
398 if (!pdata || !wm8994->num_retune_mobile_texts)
399 return;
400
401 switch (block) {
402 case 0:
403 case 1:
404 iface = 0;
405 break;
406 case 2:
407 iface = 1;
408 break;
409 default:
410 return;
411 }
412
413 /* Find the version of the currently selected configuration
414 * with the nearest sample rate. */
415 cfg = wm8994->retune_mobile_cfg[block];
416 best = 0;
417 best_val = INT_MAX;
418 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
419 if (strcmp(pdata->retune_mobile_cfgs[i].name,
420 wm8994->retune_mobile_texts[cfg]) == 0 &&
421 abs(pdata->retune_mobile_cfgs[i].rate
422 - wm8994->dac_rates[iface]) < best_val) {
423 best = i;
424 best_val = abs(pdata->retune_mobile_cfgs[i].rate
425 - wm8994->dac_rates[iface]);
426 }
427 }
428
429 dev_dbg(component->dev, "ReTune Mobile %d %s/%dHz for %dHz sample rate\n",
430 block,
431 pdata->retune_mobile_cfgs[best].name,
432 pdata->retune_mobile_cfgs[best].rate,
433 wm8994->dac_rates[iface]);
434
435 /* The EQ will be disabled while reconfiguring it, remember the
436 * current configuration.
437 */
438 save = snd_soc_component_read32(component, base);
439 save &= WM8994_AIF1DAC1_EQ_ENA;
440
441 for (i = 0; i < WM8994_EQ_REGS; i++)
442 snd_soc_component_update_bits(component, base + i, 0xffff,
443 pdata->retune_mobile_cfgs[best].regs[i]);
444
445 snd_soc_component_update_bits(component, base, WM8994_AIF1DAC1_EQ_ENA, save);
446 }
447
448 /* Icky as hell but saves code duplication */
449 static int wm8994_get_retune_mobile_block(const char *name)
450 {
451 if (strcmp(name, "AIF1.1 EQ Mode") == 0)
452 return 0;
453 if (strcmp(name, "AIF1.2 EQ Mode") == 0)
454 return 1;
455 if (strcmp(name, "AIF2 EQ Mode") == 0)
456 return 2;
457 return -EINVAL;
458 }
459
460 static int wm8994_put_retune_mobile_enum(struct snd_kcontrol *kcontrol,
461 struct snd_ctl_elem_value *ucontrol)
462 {
463 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
464 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
465 struct wm8994 *control = wm8994->wm8994;
466 struct wm8994_pdata *pdata = &control->pdata;
467 int block = wm8994_get_retune_mobile_block(kcontrol->id.name);
468 int value = ucontrol->value.enumerated.item[0];
469
470 if (block < 0)
471 return block;
472
473 if (value >= pdata->num_retune_mobile_cfgs)
474 return -EINVAL;
475
476 wm8994->retune_mobile_cfg[block] = value;
477
478 wm8994_set_retune_mobile(component, block);
479
480 return 0;
481 }
482
483 static int wm8994_get_retune_mobile_enum(struct snd_kcontrol *kcontrol,
484 struct snd_ctl_elem_value *ucontrol)
485 {
486 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
487 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
488 int block = wm8994_get_retune_mobile_block(kcontrol->id.name);
489
490 if (block < 0)
491 return block;
492
493 ucontrol->value.enumerated.item[0] = wm8994->retune_mobile_cfg[block];
494
495 return 0;
496 }
497
498 static const char *aif_chan_src_text[] = {
499 "Left", "Right"
500 };
501
502 static SOC_ENUM_SINGLE_DECL(aif1adcl_src,
503 WM8994_AIF1_CONTROL_1, 15, aif_chan_src_text);
504
505 static SOC_ENUM_SINGLE_DECL(aif1adcr_src,
506 WM8994_AIF1_CONTROL_1, 14, aif_chan_src_text);
507
508 static SOC_ENUM_SINGLE_DECL(aif2adcl_src,
509 WM8994_AIF2_CONTROL_1, 15, aif_chan_src_text);
510
511 static SOC_ENUM_SINGLE_DECL(aif2adcr_src,
512 WM8994_AIF2_CONTROL_1, 14, aif_chan_src_text);
513
514 static SOC_ENUM_SINGLE_DECL(aif1dacl_src,
515 WM8994_AIF1_CONTROL_2, 15, aif_chan_src_text);
516
517 static SOC_ENUM_SINGLE_DECL(aif1dacr_src,
518 WM8994_AIF1_CONTROL_2, 14, aif_chan_src_text);
519
520 static SOC_ENUM_SINGLE_DECL(aif2dacl_src,
521 WM8994_AIF2_CONTROL_2, 15, aif_chan_src_text);
522
523 static SOC_ENUM_SINGLE_DECL(aif2dacr_src,
524 WM8994_AIF2_CONTROL_2, 14, aif_chan_src_text);
525
526 static const char *osr_text[] = {
527 "Low Power", "High Performance",
528 };
529
530 static SOC_ENUM_SINGLE_DECL(dac_osr,
531 WM8994_OVERSAMPLING, 0, osr_text);
532
533 static SOC_ENUM_SINGLE_DECL(adc_osr,
534 WM8994_OVERSAMPLING, 1, osr_text);
535
536 static const struct snd_kcontrol_new wm8994_common_snd_controls[] = {
537 SOC_DOUBLE_R_TLV("AIF1ADC1 Volume", WM8994_AIF1_ADC1_LEFT_VOLUME,
538 WM8994_AIF1_ADC1_RIGHT_VOLUME,
539 1, 119, 0, digital_tlv),
540 SOC_DOUBLE_R_TLV("AIF2ADC Volume", WM8994_AIF2_ADC_LEFT_VOLUME,
541 WM8994_AIF2_ADC_RIGHT_VOLUME,
542 1, 119, 0, digital_tlv),
543
544 SOC_ENUM("AIF1ADCL Source", aif1adcl_src),
545 SOC_ENUM("AIF1ADCR Source", aif1adcr_src),
546 SOC_ENUM("AIF2ADCL Source", aif2adcl_src),
547 SOC_ENUM("AIF2ADCR Source", aif2adcr_src),
548
549 SOC_ENUM("AIF1DACL Source", aif1dacl_src),
550 SOC_ENUM("AIF1DACR Source", aif1dacr_src),
551 SOC_ENUM("AIF2DACL Source", aif2dacl_src),
552 SOC_ENUM("AIF2DACR Source", aif2dacr_src),
553
554 SOC_DOUBLE_R_TLV("AIF1DAC1 Volume", WM8994_AIF1_DAC1_LEFT_VOLUME,
555 WM8994_AIF1_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
556 SOC_DOUBLE_R_TLV("AIF2DAC Volume", WM8994_AIF2_DAC_LEFT_VOLUME,
557 WM8994_AIF2_DAC_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
558
559 SOC_SINGLE_TLV("AIF1 Boost Volume", WM8994_AIF1_CONTROL_2, 10, 3, 0, aif_tlv),
560 SOC_SINGLE_TLV("AIF2 Boost Volume", WM8994_AIF2_CONTROL_2, 10, 3, 0, aif_tlv),
561
562 SOC_SINGLE("AIF1DAC1 EQ Switch", WM8994_AIF1_DAC1_EQ_GAINS_1, 0, 1, 0),
563 SOC_SINGLE("AIF2 EQ Switch", WM8994_AIF2_EQ_GAINS_1, 0, 1, 0),
564
565 WM8994_DRC_SWITCH("AIF1DAC1 DRC Switch", WM8994_AIF1_DRC1_1, 2),
566 WM8994_DRC_SWITCH("AIF1ADC1L DRC Switch", WM8994_AIF1_DRC1_1, 1),
567 WM8994_DRC_SWITCH("AIF1ADC1R DRC Switch", WM8994_AIF1_DRC1_1, 0),
568
569 WM8994_DRC_SWITCH("AIF2DAC DRC Switch", WM8994_AIF2_DRC_1, 2),
570 WM8994_DRC_SWITCH("AIF2ADCL DRC Switch", WM8994_AIF2_DRC_1, 1),
571 WM8994_DRC_SWITCH("AIF2ADCR DRC Switch", WM8994_AIF2_DRC_1, 0),
572
573 SOC_SINGLE_TLV("DAC1 Right Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES,
574 5, 12, 0, st_tlv),
575 SOC_SINGLE_TLV("DAC1 Left Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES,
576 0, 12, 0, st_tlv),
577 SOC_SINGLE_TLV("DAC2 Right Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
578 5, 12, 0, st_tlv),
579 SOC_SINGLE_TLV("DAC2 Left Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
580 0, 12, 0, st_tlv),
581 SOC_ENUM("Sidetone HPF Mux", sidetone_hpf),
582 SOC_SINGLE("Sidetone HPF Switch", WM8994_SIDETONE, 6, 1, 0),
583
584 SOC_ENUM("AIF1ADC1 HPF Mode", aif1adc1_hpf),
585 SOC_DOUBLE("AIF1ADC1 HPF Switch", WM8994_AIF1_ADC1_FILTERS, 12, 11, 1, 0),
586
587 SOC_ENUM("AIF2ADC HPF Mode", aif2adc_hpf),
588 SOC_DOUBLE("AIF2ADC HPF Switch", WM8994_AIF2_ADC_FILTERS, 12, 11, 1, 0),
589
590 SOC_ENUM("ADC OSR", adc_osr),
591 SOC_ENUM("DAC OSR", dac_osr),
592
593 SOC_DOUBLE_R_TLV("DAC1 Volume", WM8994_DAC1_LEFT_VOLUME,
594 WM8994_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
595 SOC_DOUBLE_R("DAC1 Switch", WM8994_DAC1_LEFT_VOLUME,
596 WM8994_DAC1_RIGHT_VOLUME, 9, 1, 1),
597
598 SOC_DOUBLE_R_TLV("DAC2 Volume", WM8994_DAC2_LEFT_VOLUME,
599 WM8994_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
600 SOC_DOUBLE_R("DAC2 Switch", WM8994_DAC2_LEFT_VOLUME,
601 WM8994_DAC2_RIGHT_VOLUME, 9, 1, 1),
602
603 SOC_SINGLE_TLV("SPKL DAC2 Volume", WM8994_SPKMIXL_ATTENUATION,
604 6, 1, 1, wm_hubs_spkmix_tlv),
605 SOC_SINGLE_TLV("SPKL DAC1 Volume", WM8994_SPKMIXL_ATTENUATION,
606 2, 1, 1, wm_hubs_spkmix_tlv),
607
608 SOC_SINGLE_TLV("SPKR DAC2 Volume", WM8994_SPKMIXR_ATTENUATION,
609 6, 1, 1, wm_hubs_spkmix_tlv),
610 SOC_SINGLE_TLV("SPKR DAC1 Volume", WM8994_SPKMIXR_ATTENUATION,
611 2, 1, 1, wm_hubs_spkmix_tlv),
612
613 SOC_SINGLE_TLV("AIF1DAC1 3D Stereo Volume", WM8994_AIF1_DAC1_FILTERS_2,
614 10, 15, 0, wm8994_3d_tlv),
615 SOC_SINGLE("AIF1DAC1 3D Stereo Switch", WM8994_AIF1_DAC1_FILTERS_2,
616 8, 1, 0),
617 SOC_SINGLE_TLV("AIF1DAC2 3D Stereo Volume", WM8994_AIF1_DAC2_FILTERS_2,
618 10, 15, 0, wm8994_3d_tlv),
619 SOC_SINGLE("AIF1DAC2 3D Stereo Switch", WM8994_AIF1_DAC2_FILTERS_2,
620 8, 1, 0),
621 SOC_SINGLE_TLV("AIF2DAC 3D Stereo Volume", WM8994_AIF2_DAC_FILTERS_2,
622 10, 15, 0, wm8994_3d_tlv),
623 SOC_SINGLE("AIF2DAC 3D Stereo Switch", WM8994_AIF2_DAC_FILTERS_2,
624 8, 1, 0),
625 };
626
627 /* Controls not available on WM1811 */
628 static const struct snd_kcontrol_new wm8994_snd_controls[] = {
629 SOC_DOUBLE_R_TLV("AIF1ADC2 Volume", WM8994_AIF1_ADC2_LEFT_VOLUME,
630 WM8994_AIF1_ADC2_RIGHT_VOLUME,
631 1, 119, 0, digital_tlv),
632 SOC_DOUBLE_R_TLV("AIF1DAC2 Volume", WM8994_AIF1_DAC2_LEFT_VOLUME,
633 WM8994_AIF1_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
634
635 SOC_SINGLE("AIF1DAC2 EQ Switch", WM8994_AIF1_DAC2_EQ_GAINS_1, 0, 1, 0),
636
637 WM8994_DRC_SWITCH("AIF1DAC2 DRC Switch", WM8994_AIF1_DRC2_1, 2),
638 WM8994_DRC_SWITCH("AIF1ADC2L DRC Switch", WM8994_AIF1_DRC2_1, 1),
639 WM8994_DRC_SWITCH("AIF1ADC2R DRC Switch", WM8994_AIF1_DRC2_1, 0),
640
641 SOC_ENUM("AIF1ADC2 HPF Mode", aif1adc2_hpf),
642 SOC_DOUBLE("AIF1ADC2 HPF Switch", WM8994_AIF1_ADC2_FILTERS, 12, 11, 1, 0),
643 };
644
645 static const struct snd_kcontrol_new wm8994_eq_controls[] = {
646 SOC_SINGLE_TLV("AIF1DAC1 EQ1 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 11, 31, 0,
647 eq_tlv),
648 SOC_SINGLE_TLV("AIF1DAC1 EQ2 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 6, 31, 0,
649 eq_tlv),
650 SOC_SINGLE_TLV("AIF1DAC1 EQ3 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 1, 31, 0,
651 eq_tlv),
652 SOC_SINGLE_TLV("AIF1DAC1 EQ4 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 11, 31, 0,
653 eq_tlv),
654 SOC_SINGLE_TLV("AIF1DAC1 EQ5 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 6, 31, 0,
655 eq_tlv),
656
657 SOC_SINGLE_TLV("AIF1DAC2 EQ1 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 11, 31, 0,
658 eq_tlv),
659 SOC_SINGLE_TLV("AIF1DAC2 EQ2 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 6, 31, 0,
660 eq_tlv),
661 SOC_SINGLE_TLV("AIF1DAC2 EQ3 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 1, 31, 0,
662 eq_tlv),
663 SOC_SINGLE_TLV("AIF1DAC2 EQ4 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 11, 31, 0,
664 eq_tlv),
665 SOC_SINGLE_TLV("AIF1DAC2 EQ5 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 6, 31, 0,
666 eq_tlv),
667
668 SOC_SINGLE_TLV("AIF2 EQ1 Volume", WM8994_AIF2_EQ_GAINS_1, 11, 31, 0,
669 eq_tlv),
670 SOC_SINGLE_TLV("AIF2 EQ2 Volume", WM8994_AIF2_EQ_GAINS_1, 6, 31, 0,
671 eq_tlv),
672 SOC_SINGLE_TLV("AIF2 EQ3 Volume", WM8994_AIF2_EQ_GAINS_1, 1, 31, 0,
673 eq_tlv),
674 SOC_SINGLE_TLV("AIF2 EQ4 Volume", WM8994_AIF2_EQ_GAINS_2, 11, 31, 0,
675 eq_tlv),
676 SOC_SINGLE_TLV("AIF2 EQ5 Volume", WM8994_AIF2_EQ_GAINS_2, 6, 31, 0,
677 eq_tlv),
678 };
679
680 static const struct snd_kcontrol_new wm8994_drc_controls[] = {
681 SND_SOC_BYTES_MASK("AIF1.1 DRC", WM8994_AIF1_DRC1_1, 5,
682 WM8994_AIF1DAC1_DRC_ENA | WM8994_AIF1ADC1L_DRC_ENA |
683 WM8994_AIF1ADC1R_DRC_ENA),
684 SND_SOC_BYTES_MASK("AIF1.2 DRC", WM8994_AIF1_DRC2_1, 5,
685 WM8994_AIF1DAC2_DRC_ENA | WM8994_AIF1ADC2L_DRC_ENA |
686 WM8994_AIF1ADC2R_DRC_ENA),
687 SND_SOC_BYTES_MASK("AIF2 DRC", WM8994_AIF2_DRC_1, 5,
688 WM8994_AIF2DAC_DRC_ENA | WM8994_AIF2ADCL_DRC_ENA |
689 WM8994_AIF2ADCR_DRC_ENA),
690 };
691
692 static const char *wm8958_ng_text[] = {
693 "30ms", "125ms", "250ms", "500ms",
694 };
695
696 static SOC_ENUM_SINGLE_DECL(wm8958_aif1dac1_ng_hold,
697 WM8958_AIF1_DAC1_NOISE_GATE,
698 WM8958_AIF1DAC1_NG_THR_SHIFT,
699 wm8958_ng_text);
700
701 static SOC_ENUM_SINGLE_DECL(wm8958_aif1dac2_ng_hold,
702 WM8958_AIF1_DAC2_NOISE_GATE,
703 WM8958_AIF1DAC2_NG_THR_SHIFT,
704 wm8958_ng_text);
705
706 static SOC_ENUM_SINGLE_DECL(wm8958_aif2dac_ng_hold,
707 WM8958_AIF2_DAC_NOISE_GATE,
708 WM8958_AIF2DAC_NG_THR_SHIFT,
709 wm8958_ng_text);
710
711 static const struct snd_kcontrol_new wm8958_snd_controls[] = {
712 SOC_SINGLE_TLV("AIF3 Boost Volume", WM8958_AIF3_CONTROL_2, 10, 3, 0, aif_tlv),
713
714 SOC_SINGLE("AIF1DAC1 Noise Gate Switch", WM8958_AIF1_DAC1_NOISE_GATE,
715 WM8958_AIF1DAC1_NG_ENA_SHIFT, 1, 0),
716 SOC_ENUM("AIF1DAC1 Noise Gate Hold Time", wm8958_aif1dac1_ng_hold),
717 SOC_SINGLE_TLV("AIF1DAC1 Noise Gate Threshold Volume",
718 WM8958_AIF1_DAC1_NOISE_GATE, WM8958_AIF1DAC1_NG_THR_SHIFT,
719 7, 1, ng_tlv),
720
721 SOC_SINGLE("AIF1DAC2 Noise Gate Switch", WM8958_AIF1_DAC2_NOISE_GATE,
722 WM8958_AIF1DAC2_NG_ENA_SHIFT, 1, 0),
723 SOC_ENUM("AIF1DAC2 Noise Gate Hold Time", wm8958_aif1dac2_ng_hold),
724 SOC_SINGLE_TLV("AIF1DAC2 Noise Gate Threshold Volume",
725 WM8958_AIF1_DAC2_NOISE_GATE, WM8958_AIF1DAC2_NG_THR_SHIFT,
726 7, 1, ng_tlv),
727
728 SOC_SINGLE("AIF2DAC Noise Gate Switch", WM8958_AIF2_DAC_NOISE_GATE,
729 WM8958_AIF2DAC_NG_ENA_SHIFT, 1, 0),
730 SOC_ENUM("AIF2DAC Noise Gate Hold Time", wm8958_aif2dac_ng_hold),
731 SOC_SINGLE_TLV("AIF2DAC Noise Gate Threshold Volume",
732 WM8958_AIF2_DAC_NOISE_GATE, WM8958_AIF2DAC_NG_THR_SHIFT,
733 7, 1, ng_tlv),
734 };
735
736 static const struct snd_kcontrol_new wm1811_snd_controls[] = {
737 SOC_SINGLE_TLV("MIXINL IN1LP Boost Volume", WM8994_INPUT_MIXER_1, 7, 1, 0,
738 mixin_boost_tlv),
739 SOC_SINGLE_TLV("MIXINL IN1RP Boost Volume", WM8994_INPUT_MIXER_1, 8, 1, 0,
740 mixin_boost_tlv),
741 };
742
743 /* We run all mode setting through a function to enforce audio mode */
744 static void wm1811_jackdet_set_mode(struct snd_soc_component *component, u16 mode)
745 {
746 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
747
748 if (!wm8994->jackdet || !wm8994->micdet[0].jack)
749 return;
750
751 if (wm8994->active_refcount)
752 mode = WM1811_JACKDET_MODE_AUDIO;
753
754 if (mode == wm8994->jackdet_mode)
755 return;
756
757 wm8994->jackdet_mode = mode;
758
759 /* Always use audio mode to detect while the system is active */
760 if (mode != WM1811_JACKDET_MODE_NONE)
761 mode = WM1811_JACKDET_MODE_AUDIO;
762
763 snd_soc_component_update_bits(component, WM8994_ANTIPOP_2,
764 WM1811_JACKDET_MODE_MASK, mode);
765 }
766
767 static void active_reference(struct snd_soc_component *component)
768 {
769 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
770
771 mutex_lock(&wm8994->accdet_lock);
772
773 wm8994->active_refcount++;
774
775 dev_dbg(component->dev, "Active refcount incremented, now %d\n",
776 wm8994->active_refcount);
777
778 /* If we're using jack detection go into audio mode */
779 wm1811_jackdet_set_mode(component, WM1811_JACKDET_MODE_AUDIO);
780
781 mutex_unlock(&wm8994->accdet_lock);
782 }
783
784 static void active_dereference(struct snd_soc_component *component)
785 {
786 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
787 u16 mode;
788
789 mutex_lock(&wm8994->accdet_lock);
790
791 wm8994->active_refcount--;
792
793 dev_dbg(component->dev, "Active refcount decremented, now %d\n",
794 wm8994->active_refcount);
795
796 if (wm8994->active_refcount == 0) {
797 /* Go into appropriate detection only mode */
798 if (wm8994->jack_mic || wm8994->mic_detecting)
799 mode = WM1811_JACKDET_MODE_MIC;
800 else
801 mode = WM1811_JACKDET_MODE_JACK;
802
803 wm1811_jackdet_set_mode(component, mode);
804 }
805
806 mutex_unlock(&wm8994->accdet_lock);
807 }
808
809 static int clk_sys_event(struct snd_soc_dapm_widget *w,
810 struct snd_kcontrol *kcontrol, int event)
811 {
812 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
813 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
814
815 switch (event) {
816 case SND_SOC_DAPM_PRE_PMU:
817 return configure_clock(component);
818
819 case SND_SOC_DAPM_POST_PMU:
820 /*
821 * JACKDET won't run until we start the clock and it
822 * only reports deltas, make sure we notify the state
823 * up the stack on startup. Use a *very* generous
824 * timeout for paranoia, there's no urgency and we
825 * don't want false reports.
826 */
827 if (wm8994->jackdet && !wm8994->clk_has_run) {
828 queue_delayed_work(system_power_efficient_wq,
829 &wm8994->jackdet_bootstrap,
830 msecs_to_jiffies(1000));
831 wm8994->clk_has_run = true;
832 }
833 break;
834
835 case SND_SOC_DAPM_POST_PMD:
836 configure_clock(component);
837 break;
838 }
839
840 return 0;
841 }
842
843 static void vmid_reference(struct snd_soc_component *component)
844 {
845 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
846
847 pm_runtime_get_sync(component->dev);
848
849 wm8994->vmid_refcount++;
850
851 dev_dbg(component->dev, "Referencing VMID, refcount is now %d\n",
852 wm8994->vmid_refcount);
853
854 if (wm8994->vmid_refcount == 1) {
855 snd_soc_component_update_bits(component, WM8994_ANTIPOP_1,
856 WM8994_LINEOUT1_DISCH |
857 WM8994_LINEOUT2_DISCH, 0);
858
859 wm_hubs_vmid_ena(component);
860
861 switch (wm8994->vmid_mode) {
862 default:
863 WARN_ON(NULL == "Invalid VMID mode");
864 /* fall through */
865 case WM8994_VMID_NORMAL:
866 /* Startup bias, VMID ramp & buffer */
867 snd_soc_component_update_bits(component, WM8994_ANTIPOP_2,
868 WM8994_BIAS_SRC |
869 WM8994_VMID_DISCH |
870 WM8994_STARTUP_BIAS_ENA |
871 WM8994_VMID_BUF_ENA |
872 WM8994_VMID_RAMP_MASK,
873 WM8994_BIAS_SRC |
874 WM8994_STARTUP_BIAS_ENA |
875 WM8994_VMID_BUF_ENA |
876 (0x2 << WM8994_VMID_RAMP_SHIFT));
877
878 /* Main bias enable, VMID=2x40k */
879 snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_1,
880 WM8994_BIAS_ENA |
881 WM8994_VMID_SEL_MASK,
882 WM8994_BIAS_ENA | 0x2);
883
884 msleep(300);
885
886 snd_soc_component_update_bits(component, WM8994_ANTIPOP_2,
887 WM8994_VMID_RAMP_MASK |
888 WM8994_BIAS_SRC,
889 0);
890 break;
891
892 case WM8994_VMID_FORCE:
893 /* Startup bias, slow VMID ramp & buffer */
894 snd_soc_component_update_bits(component, WM8994_ANTIPOP_2,
895 WM8994_BIAS_SRC |
896 WM8994_VMID_DISCH |
897 WM8994_STARTUP_BIAS_ENA |
898 WM8994_VMID_BUF_ENA |
899 WM8994_VMID_RAMP_MASK,
900 WM8994_BIAS_SRC |
901 WM8994_STARTUP_BIAS_ENA |
902 WM8994_VMID_BUF_ENA |
903 (0x2 << WM8994_VMID_RAMP_SHIFT));
904
905 /* Main bias enable, VMID=2x40k */
906 snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_1,
907 WM8994_BIAS_ENA |
908 WM8994_VMID_SEL_MASK,
909 WM8994_BIAS_ENA | 0x2);
910
911 msleep(400);
912
913 snd_soc_component_update_bits(component, WM8994_ANTIPOP_2,
914 WM8994_VMID_RAMP_MASK |
915 WM8994_BIAS_SRC,
916 0);
917 break;
918 }
919 }
920 }
921
922 static void vmid_dereference(struct snd_soc_component *component)
923 {
924 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
925
926 wm8994->vmid_refcount--;
927
928 dev_dbg(component->dev, "Dereferencing VMID, refcount is now %d\n",
929 wm8994->vmid_refcount);
930
931 if (wm8994->vmid_refcount == 0) {
932 if (wm8994->hubs.lineout1_se)
933 snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_3,
934 WM8994_LINEOUT1N_ENA |
935 WM8994_LINEOUT1P_ENA,
936 WM8994_LINEOUT1N_ENA |
937 WM8994_LINEOUT1P_ENA);
938
939 if (wm8994->hubs.lineout2_se)
940 snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_3,
941 WM8994_LINEOUT2N_ENA |
942 WM8994_LINEOUT2P_ENA,
943 WM8994_LINEOUT2N_ENA |
944 WM8994_LINEOUT2P_ENA);
945
946 /* Start discharging VMID */
947 snd_soc_component_update_bits(component, WM8994_ANTIPOP_2,
948 WM8994_BIAS_SRC |
949 WM8994_VMID_DISCH,
950 WM8994_BIAS_SRC |
951 WM8994_VMID_DISCH);
952
953 snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_1,
954 WM8994_VMID_SEL_MASK, 0);
955
956 msleep(400);
957
958 /* Active discharge */
959 snd_soc_component_update_bits(component, WM8994_ANTIPOP_1,
960 WM8994_LINEOUT1_DISCH |
961 WM8994_LINEOUT2_DISCH,
962 WM8994_LINEOUT1_DISCH |
963 WM8994_LINEOUT2_DISCH);
964
965 snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_3,
966 WM8994_LINEOUT1N_ENA |
967 WM8994_LINEOUT1P_ENA |
968 WM8994_LINEOUT2N_ENA |
969 WM8994_LINEOUT2P_ENA, 0);
970
971 /* Switch off startup biases */
972 snd_soc_component_update_bits(component, WM8994_ANTIPOP_2,
973 WM8994_BIAS_SRC |
974 WM8994_STARTUP_BIAS_ENA |
975 WM8994_VMID_BUF_ENA |
976 WM8994_VMID_RAMP_MASK, 0);
977
978 snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_1,
979 WM8994_VMID_SEL_MASK, 0);
980 }
981
982 pm_runtime_put(component->dev);
983 }
984
985 static int vmid_event(struct snd_soc_dapm_widget *w,
986 struct snd_kcontrol *kcontrol, int event)
987 {
988 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
989
990 switch (event) {
991 case SND_SOC_DAPM_PRE_PMU:
992 vmid_reference(component);
993 break;
994
995 case SND_SOC_DAPM_POST_PMD:
996 vmid_dereference(component);
997 break;
998 }
999
1000 return 0;
1001 }
1002
1003 static bool wm8994_check_class_w_digital(struct snd_soc_component *component)
1004 {
1005 int source = 0; /* GCC flow analysis can't track enable */
1006 int reg, reg_r;
1007
1008 /* We also need the same AIF source for L/R and only one path */
1009 reg = snd_soc_component_read32(component, WM8994_DAC1_LEFT_MIXER_ROUTING);
1010 switch (reg) {
1011 case WM8994_AIF2DACL_TO_DAC1L:
1012 dev_vdbg(component->dev, "Class W source AIF2DAC\n");
1013 source = 2 << WM8994_CP_DYN_SRC_SEL_SHIFT;
1014 break;
1015 case WM8994_AIF1DAC2L_TO_DAC1L:
1016 dev_vdbg(component->dev, "Class W source AIF1DAC2\n");
1017 source = 1 << WM8994_CP_DYN_SRC_SEL_SHIFT;
1018 break;
1019 case WM8994_AIF1DAC1L_TO_DAC1L:
1020 dev_vdbg(component->dev, "Class W source AIF1DAC1\n");
1021 source = 0 << WM8994_CP_DYN_SRC_SEL_SHIFT;
1022 break;
1023 default:
1024 dev_vdbg(component->dev, "DAC mixer setting: %x\n", reg);
1025 return false;
1026 }
1027
1028 reg_r = snd_soc_component_read32(component, WM8994_DAC1_RIGHT_MIXER_ROUTING);
1029 if (reg_r != reg) {
1030 dev_vdbg(component->dev, "Left and right DAC mixers different\n");
1031 return false;
1032 }
1033
1034 /* Set the source up */
1035 snd_soc_component_update_bits(component, WM8994_CLASS_W_1,
1036 WM8994_CP_DYN_SRC_SEL_MASK, source);
1037
1038 return true;
1039 }
1040
1041 static int aif_mclk_set(struct snd_soc_component *component, int aif, bool enable)
1042 {
1043 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
1044 unsigned int offset, val, clk_idx;
1045 int ret;
1046
1047 if (aif)
1048 offset = 4;
1049 else
1050 offset = 0;
1051
1052 val = snd_soc_component_read32(component, WM8994_AIF1_CLOCKING_1 + offset);
1053 val &= WM8994_AIF1CLK_SRC_MASK;
1054
1055 switch (val) {
1056 case 0:
1057 clk_idx = WM8994_MCLK1;
1058 break;
1059 case 1:
1060 clk_idx = WM8994_MCLK2;
1061 break;
1062 default:
1063 return 0;
1064 }
1065
1066 if (enable) {
1067 ret = clk_prepare_enable(wm8994->mclk[clk_idx].clk);
1068 if (ret < 0) {
1069 dev_err(component->dev, "Failed to enable MCLK%d\n",
1070 clk_idx);
1071 return ret;
1072 }
1073 } else {
1074 clk_disable_unprepare(wm8994->mclk[clk_idx].clk);
1075 }
1076
1077 return 0;
1078 }
1079
1080 static int aif1clk_ev(struct snd_soc_dapm_widget *w,
1081 struct snd_kcontrol *kcontrol, int event)
1082 {
1083 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1084 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
1085 struct wm8994 *control = wm8994->wm8994;
1086 int mask = WM8994_AIF1DAC1L_ENA | WM8994_AIF1DAC1R_ENA;
1087 int ret, i;
1088 int dac;
1089 int adc;
1090 int val;
1091
1092 switch (control->type) {
1093 case WM8994:
1094 case WM8958:
1095 mask |= WM8994_AIF1DAC2L_ENA | WM8994_AIF1DAC2R_ENA;
1096 break;
1097 default:
1098 break;
1099 }
1100
1101 switch (event) {
1102 case SND_SOC_DAPM_PRE_PMU:
1103 ret = aif_mclk_set(component, 0, true);
1104 if (ret < 0)
1105 return ret;
1106
1107 /* Don't enable timeslot 2 if not in use */
1108 if (wm8994->channels[0] <= 2)
1109 mask &= ~(WM8994_AIF1DAC2L_ENA | WM8994_AIF1DAC2R_ENA);
1110
1111 val = snd_soc_component_read32(component, WM8994_AIF1_CONTROL_1);
1112 if ((val & WM8994_AIF1ADCL_SRC) &&
1113 (val & WM8994_AIF1ADCR_SRC))
1114 adc = WM8994_AIF1ADC1R_ENA | WM8994_AIF1ADC2R_ENA;
1115 else if (!(val & WM8994_AIF1ADCL_SRC) &&
1116 !(val & WM8994_AIF1ADCR_SRC))
1117 adc = WM8994_AIF1ADC1L_ENA | WM8994_AIF1ADC2L_ENA;
1118 else
1119 adc = WM8994_AIF1ADC1R_ENA | WM8994_AIF1ADC2R_ENA |
1120 WM8994_AIF1ADC1L_ENA | WM8994_AIF1ADC2L_ENA;
1121
1122 val = snd_soc_component_read32(component, WM8994_AIF1_CONTROL_2);
1123 if ((val & WM8994_AIF1DACL_SRC) &&
1124 (val & WM8994_AIF1DACR_SRC))
1125 dac = WM8994_AIF1DAC1R_ENA | WM8994_AIF1DAC2R_ENA;
1126 else if (!(val & WM8994_AIF1DACL_SRC) &&
1127 !(val & WM8994_AIF1DACR_SRC))
1128 dac = WM8994_AIF1DAC1L_ENA | WM8994_AIF1DAC2L_ENA;
1129 else
1130 dac = WM8994_AIF1DAC1R_ENA | WM8994_AIF1DAC2R_ENA |
1131 WM8994_AIF1DAC1L_ENA | WM8994_AIF1DAC2L_ENA;
1132
1133 snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_4,
1134 mask, adc);
1135 snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_5,
1136 mask, dac);
1137 snd_soc_component_update_bits(component, WM8994_CLOCKING_1,
1138 WM8994_AIF1DSPCLK_ENA |
1139 WM8994_SYSDSPCLK_ENA,
1140 WM8994_AIF1DSPCLK_ENA |
1141 WM8994_SYSDSPCLK_ENA);
1142 snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_4, mask,
1143 WM8994_AIF1ADC1R_ENA |
1144 WM8994_AIF1ADC1L_ENA |
1145 WM8994_AIF1ADC2R_ENA |
1146 WM8994_AIF1ADC2L_ENA);
1147 snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_5, mask,
1148 WM8994_AIF1DAC1R_ENA |
1149 WM8994_AIF1DAC1L_ENA |
1150 WM8994_AIF1DAC2R_ENA |
1151 WM8994_AIF1DAC2L_ENA);
1152 break;
1153
1154 case SND_SOC_DAPM_POST_PMU:
1155 for (i = 0; i < ARRAY_SIZE(wm8994_vu_bits); i++)
1156 snd_soc_component_write(component, wm8994_vu_bits[i].reg,
1157 snd_soc_component_read32(component,
1158 wm8994_vu_bits[i].reg));
1159 break;
1160
1161 case SND_SOC_DAPM_PRE_PMD:
1162 case SND_SOC_DAPM_POST_PMD:
1163 snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_5,
1164 mask, 0);
1165 snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_4,
1166 mask, 0);
1167
1168 val = snd_soc_component_read32(component, WM8994_CLOCKING_1);
1169 if (val & WM8994_AIF2DSPCLK_ENA)
1170 val = WM8994_SYSDSPCLK_ENA;
1171 else
1172 val = 0;
1173 snd_soc_component_update_bits(component, WM8994_CLOCKING_1,
1174 WM8994_SYSDSPCLK_ENA |
1175 WM8994_AIF1DSPCLK_ENA, val);
1176 break;
1177 }
1178
1179 switch (event) {
1180 case SND_SOC_DAPM_POST_PMD:
1181 aif_mclk_set(component, 0, false);
1182 break;
1183 }
1184
1185 return 0;
1186 }
1187
1188 static int aif2clk_ev(struct snd_soc_dapm_widget *w,
1189 struct snd_kcontrol *kcontrol, int event)
1190 {
1191 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1192 int ret, i;
1193 int dac;
1194 int adc;
1195 int val;
1196
1197 switch (event) {
1198 case SND_SOC_DAPM_PRE_PMU:
1199 ret = aif_mclk_set(component, 1, true);
1200 if (ret < 0)
1201 return ret;
1202
1203 val = snd_soc_component_read32(component, WM8994_AIF2_CONTROL_1);
1204 if ((val & WM8994_AIF2ADCL_SRC) &&
1205 (val & WM8994_AIF2ADCR_SRC))
1206 adc = WM8994_AIF2ADCR_ENA;
1207 else if (!(val & WM8994_AIF2ADCL_SRC) &&
1208 !(val & WM8994_AIF2ADCR_SRC))
1209 adc = WM8994_AIF2ADCL_ENA;
1210 else
1211 adc = WM8994_AIF2ADCL_ENA | WM8994_AIF2ADCR_ENA;
1212
1213
1214 val = snd_soc_component_read32(component, WM8994_AIF2_CONTROL_2);
1215 if ((val & WM8994_AIF2DACL_SRC) &&
1216 (val & WM8994_AIF2DACR_SRC))
1217 dac = WM8994_AIF2DACR_ENA;
1218 else if (!(val & WM8994_AIF2DACL_SRC) &&
1219 !(val & WM8994_AIF2DACR_SRC))
1220 dac = WM8994_AIF2DACL_ENA;
1221 else
1222 dac = WM8994_AIF2DACL_ENA | WM8994_AIF2DACR_ENA;
1223
1224 snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_4,
1225 WM8994_AIF2ADCL_ENA |
1226 WM8994_AIF2ADCR_ENA, adc);
1227 snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_5,
1228 WM8994_AIF2DACL_ENA |
1229 WM8994_AIF2DACR_ENA, dac);
1230 snd_soc_component_update_bits(component, WM8994_CLOCKING_1,
1231 WM8994_AIF2DSPCLK_ENA |
1232 WM8994_SYSDSPCLK_ENA,
1233 WM8994_AIF2DSPCLK_ENA |
1234 WM8994_SYSDSPCLK_ENA);
1235 snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_4,
1236 WM8994_AIF2ADCL_ENA |
1237 WM8994_AIF2ADCR_ENA,
1238 WM8994_AIF2ADCL_ENA |
1239 WM8994_AIF2ADCR_ENA);
1240 snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_5,
1241 WM8994_AIF2DACL_ENA |
1242 WM8994_AIF2DACR_ENA,
1243 WM8994_AIF2DACL_ENA |
1244 WM8994_AIF2DACR_ENA);
1245 break;
1246
1247 case SND_SOC_DAPM_POST_PMU:
1248 for (i = 0; i < ARRAY_SIZE(wm8994_vu_bits); i++)
1249 snd_soc_component_write(component, wm8994_vu_bits[i].reg,
1250 snd_soc_component_read32(component,
1251 wm8994_vu_bits[i].reg));
1252 break;
1253
1254 case SND_SOC_DAPM_PRE_PMD:
1255 case SND_SOC_DAPM_POST_PMD:
1256 snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_5,
1257 WM8994_AIF2DACL_ENA |
1258 WM8994_AIF2DACR_ENA, 0);
1259 snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_4,
1260 WM8994_AIF2ADCL_ENA |
1261 WM8994_AIF2ADCR_ENA, 0);
1262
1263 val = snd_soc_component_read32(component, WM8994_CLOCKING_1);
1264 if (val & WM8994_AIF1DSPCLK_ENA)
1265 val = WM8994_SYSDSPCLK_ENA;
1266 else
1267 val = 0;
1268 snd_soc_component_update_bits(component, WM8994_CLOCKING_1,
1269 WM8994_SYSDSPCLK_ENA |
1270 WM8994_AIF2DSPCLK_ENA, val);
1271 break;
1272 }
1273
1274 switch (event) {
1275 case SND_SOC_DAPM_POST_PMD:
1276 aif_mclk_set(component, 1, false);
1277 break;
1278 }
1279
1280 return 0;
1281 }
1282
1283 static int aif1clk_late_ev(struct snd_soc_dapm_widget *w,
1284 struct snd_kcontrol *kcontrol, int event)
1285 {
1286 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1287 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
1288
1289 switch (event) {
1290 case SND_SOC_DAPM_PRE_PMU:
1291 wm8994->aif1clk_enable = 1;
1292 break;
1293 case SND_SOC_DAPM_POST_PMD:
1294 wm8994->aif1clk_disable = 1;
1295 break;
1296 }
1297
1298 return 0;
1299 }
1300
1301 static int aif2clk_late_ev(struct snd_soc_dapm_widget *w,
1302 struct snd_kcontrol *kcontrol, int event)
1303 {
1304 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1305 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
1306
1307 switch (event) {
1308 case SND_SOC_DAPM_PRE_PMU:
1309 wm8994->aif2clk_enable = 1;
1310 break;
1311 case SND_SOC_DAPM_POST_PMD:
1312 wm8994->aif2clk_disable = 1;
1313 break;
1314 }
1315
1316 return 0;
1317 }
1318
1319 static int late_enable_ev(struct snd_soc_dapm_widget *w,
1320 struct snd_kcontrol *kcontrol, int event)
1321 {
1322 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1323 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
1324
1325 switch (event) {
1326 case SND_SOC_DAPM_PRE_PMU:
1327 if (wm8994->aif1clk_enable) {
1328 aif1clk_ev(w, kcontrol, SND_SOC_DAPM_PRE_PMU);
1329 snd_soc_component_update_bits(component, WM8994_AIF1_CLOCKING_1,
1330 WM8994_AIF1CLK_ENA_MASK,
1331 WM8994_AIF1CLK_ENA);
1332 aif1clk_ev(w, kcontrol, SND_SOC_DAPM_POST_PMU);
1333 wm8994->aif1clk_enable = 0;
1334 }
1335 if (wm8994->aif2clk_enable) {
1336 aif2clk_ev(w, kcontrol, SND_SOC_DAPM_PRE_PMU);
1337 snd_soc_component_update_bits(component, WM8994_AIF2_CLOCKING_1,
1338 WM8994_AIF2CLK_ENA_MASK,
1339 WM8994_AIF2CLK_ENA);
1340 aif2clk_ev(w, kcontrol, SND_SOC_DAPM_POST_PMU);
1341 wm8994->aif2clk_enable = 0;
1342 }
1343 break;
1344 }
1345
1346 /* We may also have postponed startup of DSP, handle that. */
1347 wm8958_aif_ev(w, kcontrol, event);
1348
1349 return 0;
1350 }
1351
1352 static int late_disable_ev(struct snd_soc_dapm_widget *w,
1353 struct snd_kcontrol *kcontrol, int event)
1354 {
1355 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1356 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
1357
1358 switch (event) {
1359 case SND_SOC_DAPM_POST_PMD:
1360 if (wm8994->aif1clk_disable) {
1361 aif1clk_ev(w, kcontrol, SND_SOC_DAPM_PRE_PMD);
1362 snd_soc_component_update_bits(component, WM8994_AIF1_CLOCKING_1,
1363 WM8994_AIF1CLK_ENA_MASK, 0);
1364 aif1clk_ev(w, kcontrol, SND_SOC_DAPM_POST_PMD);
1365 wm8994->aif1clk_disable = 0;
1366 }
1367 if (wm8994->aif2clk_disable) {
1368 aif2clk_ev(w, kcontrol, SND_SOC_DAPM_PRE_PMD);
1369 snd_soc_component_update_bits(component, WM8994_AIF2_CLOCKING_1,
1370 WM8994_AIF2CLK_ENA_MASK, 0);
1371 aif2clk_ev(w, kcontrol, SND_SOC_DAPM_POST_PMD);
1372 wm8994->aif2clk_disable = 0;
1373 }
1374 break;
1375 }
1376
1377 return 0;
1378 }
1379
1380 static int adc_mux_ev(struct snd_soc_dapm_widget *w,
1381 struct snd_kcontrol *kcontrol, int event)
1382 {
1383 late_enable_ev(w, kcontrol, event);
1384 return 0;
1385 }
1386
1387 static int micbias_ev(struct snd_soc_dapm_widget *w,
1388 struct snd_kcontrol *kcontrol, int event)
1389 {
1390 late_enable_ev(w, kcontrol, event);
1391 return 0;
1392 }
1393
1394 static int dac_ev(struct snd_soc_dapm_widget *w,
1395 struct snd_kcontrol *kcontrol, int event)
1396 {
1397 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1398 unsigned int mask = 1 << w->shift;
1399
1400 snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_5,
1401 mask, mask);
1402 return 0;
1403 }
1404
1405 static const char *adc_mux_text[] = {
1406 "ADC",
1407 "DMIC",
1408 };
1409
1410 static SOC_ENUM_SINGLE_VIRT_DECL(adc_enum, adc_mux_text);
1411
1412 static const struct snd_kcontrol_new adcl_mux =
1413 SOC_DAPM_ENUM("ADCL Mux", adc_enum);
1414
1415 static const struct snd_kcontrol_new adcr_mux =
1416 SOC_DAPM_ENUM("ADCR Mux", adc_enum);
1417
1418 static const struct snd_kcontrol_new left_speaker_mixer[] = {
1419 SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 9, 1, 0),
1420 SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 7, 1, 0),
1421 SOC_DAPM_SINGLE("IN1LP Switch", WM8994_SPEAKER_MIXER, 5, 1, 0),
1422 SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 3, 1, 0),
1423 SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 1, 1, 0),
1424 };
1425
1426 static const struct snd_kcontrol_new right_speaker_mixer[] = {
1427 SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 8, 1, 0),
1428 SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 6, 1, 0),
1429 SOC_DAPM_SINGLE("IN1RP Switch", WM8994_SPEAKER_MIXER, 4, 1, 0),
1430 SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 2, 1, 0),
1431 SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 0, 1, 0),
1432 };
1433
1434 /* Debugging; dump chip status after DAPM transitions */
1435 static int post_ev(struct snd_soc_dapm_widget *w,
1436 struct snd_kcontrol *kcontrol, int event)
1437 {
1438 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1439 dev_dbg(component->dev, "SRC status: %x\n",
1440 snd_soc_component_read32(component,
1441 WM8994_RATE_STATUS));
1442 return 0;
1443 }
1444
1445 static const struct snd_kcontrol_new aif1adc1l_mix[] = {
1446 SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING,
1447 1, 1, 0),
1448 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING,
1449 0, 1, 0),
1450 };
1451
1452 static const struct snd_kcontrol_new aif1adc1r_mix[] = {
1453 SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING,
1454 1, 1, 0),
1455 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING,
1456 0, 1, 0),
1457 };
1458
1459 static const struct snd_kcontrol_new aif1adc2l_mix[] = {
1460 SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING,
1461 1, 1, 0),
1462 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING,
1463 0, 1, 0),
1464 };
1465
1466 static const struct snd_kcontrol_new aif1adc2r_mix[] = {
1467 SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING,
1468 1, 1, 0),
1469 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING,
1470 0, 1, 0),
1471 };
1472
1473 static const struct snd_kcontrol_new aif2dac2l_mix[] = {
1474 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1475 5, 1, 0),
1476 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1477 4, 1, 0),
1478 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1479 2, 1, 0),
1480 SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1481 1, 1, 0),
1482 SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1483 0, 1, 0),
1484 };
1485
1486 static const struct snd_kcontrol_new aif2dac2r_mix[] = {
1487 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1488 5, 1, 0),
1489 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1490 4, 1, 0),
1491 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1492 2, 1, 0),
1493 SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1494 1, 1, 0),
1495 SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1496 0, 1, 0),
1497 };
1498
1499 #define WM8994_CLASS_W_SWITCH(xname, reg, shift, max, invert) \
1500 SOC_SINGLE_EXT(xname, reg, shift, max, invert, \
1501 snd_soc_dapm_get_volsw, wm8994_put_class_w)
1502
1503 static int wm8994_put_class_w(struct snd_kcontrol *kcontrol,
1504 struct snd_ctl_elem_value *ucontrol)
1505 {
1506 struct snd_soc_component *component = snd_soc_dapm_kcontrol_component(kcontrol);
1507 int ret;
1508
1509 ret = snd_soc_dapm_put_volsw(kcontrol, ucontrol);
1510
1511 wm_hubs_update_class_w(component);
1512
1513 return ret;
1514 }
1515
1516 static const struct snd_kcontrol_new dac1l_mix[] = {
1517 WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1518 5, 1, 0),
1519 WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1520 4, 1, 0),
1521 WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1522 2, 1, 0),
1523 WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1524 1, 1, 0),
1525 WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1526 0, 1, 0),
1527 };
1528
1529 static const struct snd_kcontrol_new dac1r_mix[] = {
1530 WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1531 5, 1, 0),
1532 WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1533 4, 1, 0),
1534 WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1535 2, 1, 0),
1536 WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1537 1, 1, 0),
1538 WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1539 0, 1, 0),
1540 };
1541
1542 static const char *sidetone_text[] = {
1543 "ADC/DMIC1", "DMIC2",
1544 };
1545
1546 static SOC_ENUM_SINGLE_DECL(sidetone1_enum,
1547 WM8994_SIDETONE, 0, sidetone_text);
1548
1549 static const struct snd_kcontrol_new sidetone1_mux =
1550 SOC_DAPM_ENUM("Left Sidetone Mux", sidetone1_enum);
1551
1552 static SOC_ENUM_SINGLE_DECL(sidetone2_enum,
1553 WM8994_SIDETONE, 1, sidetone_text);
1554
1555 static const struct snd_kcontrol_new sidetone2_mux =
1556 SOC_DAPM_ENUM("Right Sidetone Mux", sidetone2_enum);
1557
1558 static const char *aif1dac_text[] = {
1559 "AIF1DACDAT", "AIF3DACDAT",
1560 };
1561
1562 static const char *loopback_text[] = {
1563 "None", "ADCDAT",
1564 };
1565
1566 static SOC_ENUM_SINGLE_DECL(aif1_loopback_enum,
1567 WM8994_AIF1_CONTROL_2,
1568 WM8994_AIF1_LOOPBACK_SHIFT,
1569 loopback_text);
1570
1571 static const struct snd_kcontrol_new aif1_loopback =
1572 SOC_DAPM_ENUM("AIF1 Loopback", aif1_loopback_enum);
1573
1574 static SOC_ENUM_SINGLE_DECL(aif2_loopback_enum,
1575 WM8994_AIF2_CONTROL_2,
1576 WM8994_AIF2_LOOPBACK_SHIFT,
1577 loopback_text);
1578
1579 static const struct snd_kcontrol_new aif2_loopback =
1580 SOC_DAPM_ENUM("AIF2 Loopback", aif2_loopback_enum);
1581
1582 static SOC_ENUM_SINGLE_DECL(aif1dac_enum,
1583 WM8994_POWER_MANAGEMENT_6, 0, aif1dac_text);
1584
1585 static const struct snd_kcontrol_new aif1dac_mux =
1586 SOC_DAPM_ENUM("AIF1DAC Mux", aif1dac_enum);
1587
1588 static const char *aif2dac_text[] = {
1589 "AIF2DACDAT", "AIF3DACDAT",
1590 };
1591
1592 static SOC_ENUM_SINGLE_DECL(aif2dac_enum,
1593 WM8994_POWER_MANAGEMENT_6, 1, aif2dac_text);
1594
1595 static const struct snd_kcontrol_new aif2dac_mux =
1596 SOC_DAPM_ENUM("AIF2DAC Mux", aif2dac_enum);
1597
1598 static const char *aif2adc_text[] = {
1599 "AIF2ADCDAT", "AIF3DACDAT",
1600 };
1601
1602 static SOC_ENUM_SINGLE_DECL(aif2adc_enum,
1603 WM8994_POWER_MANAGEMENT_6, 2, aif2adc_text);
1604
1605 static const struct snd_kcontrol_new aif2adc_mux =
1606 SOC_DAPM_ENUM("AIF2ADC Mux", aif2adc_enum);
1607
1608 static const char *aif3adc_text[] = {
1609 "AIF1ADCDAT", "AIF2ADCDAT", "AIF2DACDAT", "Mono PCM",
1610 };
1611
1612 static SOC_ENUM_SINGLE_DECL(wm8994_aif3adc_enum,
1613 WM8994_POWER_MANAGEMENT_6, 3, aif3adc_text);
1614
1615 static const struct snd_kcontrol_new wm8994_aif3adc_mux =
1616 SOC_DAPM_ENUM("AIF3ADC Mux", wm8994_aif3adc_enum);
1617
1618 static SOC_ENUM_SINGLE_DECL(wm8958_aif3adc_enum,
1619 WM8994_POWER_MANAGEMENT_6, 3, aif3adc_text);
1620
1621 static const struct snd_kcontrol_new wm8958_aif3adc_mux =
1622 SOC_DAPM_ENUM("AIF3ADC Mux", wm8958_aif3adc_enum);
1623
1624 static const char *mono_pcm_out_text[] = {
1625 "None", "AIF2ADCL", "AIF2ADCR",
1626 };
1627
1628 static SOC_ENUM_SINGLE_DECL(mono_pcm_out_enum,
1629 WM8994_POWER_MANAGEMENT_6, 9, mono_pcm_out_text);
1630
1631 static const struct snd_kcontrol_new mono_pcm_out_mux =
1632 SOC_DAPM_ENUM("Mono PCM Out Mux", mono_pcm_out_enum);
1633
1634 static const char *aif2dac_src_text[] = {
1635 "AIF2", "AIF3",
1636 };
1637
1638 /* Note that these two control shouldn't be simultaneously switched to AIF3 */
1639 static SOC_ENUM_SINGLE_DECL(aif2dacl_src_enum,
1640 WM8994_POWER_MANAGEMENT_6, 7, aif2dac_src_text);
1641
1642 static const struct snd_kcontrol_new aif2dacl_src_mux =
1643 SOC_DAPM_ENUM("AIF2DACL Mux", aif2dacl_src_enum);
1644
1645 static SOC_ENUM_SINGLE_DECL(aif2dacr_src_enum,
1646 WM8994_POWER_MANAGEMENT_6, 8, aif2dac_src_text);
1647
1648 static const struct snd_kcontrol_new aif2dacr_src_mux =
1649 SOC_DAPM_ENUM("AIF2DACR Mux", aif2dacr_src_enum);
1650
1651 static const struct snd_soc_dapm_widget wm8994_lateclk_revd_widgets[] = {
1652 SND_SOC_DAPM_SUPPLY("AIF1CLK", SND_SOC_NOPM, 0, 0, aif1clk_late_ev,
1653 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1654 SND_SOC_DAPM_SUPPLY("AIF2CLK", SND_SOC_NOPM, 0, 0, aif2clk_late_ev,
1655 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1656
1657 SND_SOC_DAPM_PGA_E("Late DAC1L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1658 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1659 SND_SOC_DAPM_PGA_E("Late DAC1R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1660 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1661 SND_SOC_DAPM_PGA_E("Late DAC2L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1662 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1663 SND_SOC_DAPM_PGA_E("Late DAC2R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1664 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1665 SND_SOC_DAPM_PGA_E("Direct Voice", SND_SOC_NOPM, 0, 0, NULL, 0,
1666 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1667
1668 SND_SOC_DAPM_MIXER_E("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0,
1669 left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer),
1670 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1671 SND_SOC_DAPM_MIXER_E("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0,
1672 right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer),
1673 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1674 SND_SOC_DAPM_MUX_E("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpl_mux,
1675 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1676 SND_SOC_DAPM_MUX_E("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpr_mux,
1677 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1678
1679 SND_SOC_DAPM_POST("Late Disable PGA", late_disable_ev)
1680 };
1681
1682 static const struct snd_soc_dapm_widget wm8994_lateclk_widgets[] = {
1683 SND_SOC_DAPM_SUPPLY("AIF1CLK", WM8994_AIF1_CLOCKING_1, 0, 0, aif1clk_ev,
1684 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1685 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
1686 SND_SOC_DAPM_SUPPLY("AIF2CLK", WM8994_AIF2_CLOCKING_1, 0, 0, aif2clk_ev,
1687 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1688 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
1689 SND_SOC_DAPM_PGA("Direct Voice", SND_SOC_NOPM, 0, 0, NULL, 0),
1690 SND_SOC_DAPM_MIXER("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0,
1691 left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)),
1692 SND_SOC_DAPM_MIXER("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0,
1693 right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer)),
1694 SND_SOC_DAPM_MUX("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpl_mux),
1695 SND_SOC_DAPM_MUX("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpr_mux),
1696 };
1697
1698 static const struct snd_soc_dapm_widget wm8994_dac_revd_widgets[] = {
1699 SND_SOC_DAPM_DAC_E("DAC2L", NULL, SND_SOC_NOPM, 3, 0,
1700 dac_ev, SND_SOC_DAPM_PRE_PMU),
1701 SND_SOC_DAPM_DAC_E("DAC2R", NULL, SND_SOC_NOPM, 2, 0,
1702 dac_ev, SND_SOC_DAPM_PRE_PMU),
1703 SND_SOC_DAPM_DAC_E("DAC1L", NULL, SND_SOC_NOPM, 1, 0,
1704 dac_ev, SND_SOC_DAPM_PRE_PMU),
1705 SND_SOC_DAPM_DAC_E("DAC1R", NULL, SND_SOC_NOPM, 0, 0,
1706 dac_ev, SND_SOC_DAPM_PRE_PMU),
1707 };
1708
1709 static const struct snd_soc_dapm_widget wm8994_dac_widgets[] = {
1710 SND_SOC_DAPM_DAC("DAC2L", NULL, WM8994_POWER_MANAGEMENT_5, 3, 0),
1711 SND_SOC_DAPM_DAC("DAC2R", NULL, WM8994_POWER_MANAGEMENT_5, 2, 0),
1712 SND_SOC_DAPM_DAC("DAC1L", NULL, WM8994_POWER_MANAGEMENT_5, 1, 0),
1713 SND_SOC_DAPM_DAC("DAC1R", NULL, WM8994_POWER_MANAGEMENT_5, 0, 0),
1714 };
1715
1716 static const struct snd_soc_dapm_widget wm8994_adc_revd_widgets[] = {
1717 SND_SOC_DAPM_MUX_E("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux,
1718 adc_mux_ev, SND_SOC_DAPM_PRE_PMU),
1719 SND_SOC_DAPM_MUX_E("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux,
1720 adc_mux_ev, SND_SOC_DAPM_PRE_PMU),
1721 };
1722
1723 static const struct snd_soc_dapm_widget wm8994_adc_widgets[] = {
1724 SND_SOC_DAPM_MUX("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux),
1725 SND_SOC_DAPM_MUX("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux),
1726 };
1727
1728 static const struct snd_soc_dapm_widget wm8994_dapm_widgets[] = {
1729 SND_SOC_DAPM_INPUT("DMIC1DAT"),
1730 SND_SOC_DAPM_INPUT("DMIC2DAT"),
1731 SND_SOC_DAPM_INPUT("Clock"),
1732
1733 SND_SOC_DAPM_SUPPLY_S("MICBIAS Supply", 1, SND_SOC_NOPM, 0, 0, micbias_ev,
1734 SND_SOC_DAPM_PRE_PMU),
1735 SND_SOC_DAPM_SUPPLY("VMID", SND_SOC_NOPM, 0, 0, vmid_event,
1736 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1737
1738 SND_SOC_DAPM_SUPPLY("CLK_SYS", SND_SOC_NOPM, 0, 0, clk_sys_event,
1739 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1740 SND_SOC_DAPM_PRE_PMD),
1741
1742 SND_SOC_DAPM_SUPPLY("DSP1CLK", SND_SOC_NOPM, 3, 0, NULL, 0),
1743 SND_SOC_DAPM_SUPPLY("DSP2CLK", SND_SOC_NOPM, 2, 0, NULL, 0),
1744 SND_SOC_DAPM_SUPPLY("DSPINTCLK", SND_SOC_NOPM, 1, 0, NULL, 0),
1745
1746 SND_SOC_DAPM_AIF_OUT("AIF1ADC1L", NULL,
1747 0, SND_SOC_NOPM, 9, 0),
1748 SND_SOC_DAPM_AIF_OUT("AIF1ADC1R", NULL,
1749 0, SND_SOC_NOPM, 8, 0),
1750 SND_SOC_DAPM_AIF_IN_E("AIF1DAC1L", NULL, 0,
1751 SND_SOC_NOPM, 9, 0, wm8958_aif_ev,
1752 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1753 SND_SOC_DAPM_AIF_IN_E("AIF1DAC1R", NULL, 0,
1754 SND_SOC_NOPM, 8, 0, wm8958_aif_ev,
1755 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1756
1757 SND_SOC_DAPM_AIF_OUT("AIF1ADC2L", NULL,
1758 0, SND_SOC_NOPM, 11, 0),
1759 SND_SOC_DAPM_AIF_OUT("AIF1ADC2R", NULL,
1760 0, SND_SOC_NOPM, 10, 0),
1761 SND_SOC_DAPM_AIF_IN_E("AIF1DAC2L", NULL, 0,
1762 SND_SOC_NOPM, 11, 0, wm8958_aif_ev,
1763 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1764 SND_SOC_DAPM_AIF_IN_E("AIF1DAC2R", NULL, 0,
1765 SND_SOC_NOPM, 10, 0, wm8958_aif_ev,
1766 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1767
1768 SND_SOC_DAPM_MIXER("AIF1ADC1L Mixer", SND_SOC_NOPM, 0, 0,
1769 aif1adc1l_mix, ARRAY_SIZE(aif1adc1l_mix)),
1770 SND_SOC_DAPM_MIXER("AIF1ADC1R Mixer", SND_SOC_NOPM, 0, 0,
1771 aif1adc1r_mix, ARRAY_SIZE(aif1adc1r_mix)),
1772
1773 SND_SOC_DAPM_MIXER("AIF1ADC2L Mixer", SND_SOC_NOPM, 0, 0,
1774 aif1adc2l_mix, ARRAY_SIZE(aif1adc2l_mix)),
1775 SND_SOC_DAPM_MIXER("AIF1ADC2R Mixer", SND_SOC_NOPM, 0, 0,
1776 aif1adc2r_mix, ARRAY_SIZE(aif1adc2r_mix)),
1777
1778 SND_SOC_DAPM_MIXER("AIF2DAC2L Mixer", SND_SOC_NOPM, 0, 0,
1779 aif2dac2l_mix, ARRAY_SIZE(aif2dac2l_mix)),
1780 SND_SOC_DAPM_MIXER("AIF2DAC2R Mixer", SND_SOC_NOPM, 0, 0,
1781 aif2dac2r_mix, ARRAY_SIZE(aif2dac2r_mix)),
1782
1783 SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM, 0, 0, &sidetone1_mux),
1784 SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM, 0, 0, &sidetone2_mux),
1785
1786 SND_SOC_DAPM_MIXER("DAC1L Mixer", SND_SOC_NOPM, 0, 0,
1787 dac1l_mix, ARRAY_SIZE(dac1l_mix)),
1788 SND_SOC_DAPM_MIXER("DAC1R Mixer", SND_SOC_NOPM, 0, 0,
1789 dac1r_mix, ARRAY_SIZE(dac1r_mix)),
1790
1791 SND_SOC_DAPM_AIF_OUT("AIF2ADCL", NULL, 0,
1792 SND_SOC_NOPM, 13, 0),
1793 SND_SOC_DAPM_AIF_OUT("AIF2ADCR", NULL, 0,
1794 SND_SOC_NOPM, 12, 0),
1795 SND_SOC_DAPM_AIF_IN_E("AIF2DACL", NULL, 0,
1796 SND_SOC_NOPM, 13, 0, wm8958_aif_ev,
1797 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1798 SND_SOC_DAPM_AIF_IN_E("AIF2DACR", NULL, 0,
1799 SND_SOC_NOPM, 12, 0, wm8958_aif_ev,
1800 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1801
1802 SND_SOC_DAPM_AIF_IN("AIF1DACDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1803 SND_SOC_DAPM_AIF_IN("AIF2DACDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1804 SND_SOC_DAPM_AIF_OUT("AIF1ADCDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1805 SND_SOC_DAPM_AIF_OUT("AIF2ADCDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1806
1807 SND_SOC_DAPM_MUX("AIF1DAC Mux", SND_SOC_NOPM, 0, 0, &aif1dac_mux),
1808 SND_SOC_DAPM_MUX("AIF2DAC Mux", SND_SOC_NOPM, 0, 0, &aif2dac_mux),
1809 SND_SOC_DAPM_MUX("AIF2ADC Mux", SND_SOC_NOPM, 0, 0, &aif2adc_mux),
1810
1811 SND_SOC_DAPM_AIF_IN("AIF3DACDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1812 SND_SOC_DAPM_AIF_OUT("AIF3ADCDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1813
1814 SND_SOC_DAPM_SUPPLY("TOCLK", WM8994_CLOCKING_1, 4, 0, NULL, 0),
1815
1816 SND_SOC_DAPM_ADC("DMIC2L", NULL, WM8994_POWER_MANAGEMENT_4, 5, 0),
1817 SND_SOC_DAPM_ADC("DMIC2R", NULL, WM8994_POWER_MANAGEMENT_4, 4, 0),
1818 SND_SOC_DAPM_ADC("DMIC1L", NULL, WM8994_POWER_MANAGEMENT_4, 3, 0),
1819 SND_SOC_DAPM_ADC("DMIC1R", NULL, WM8994_POWER_MANAGEMENT_4, 2, 0),
1820
1821 /* Power is done with the muxes since the ADC power also controls the
1822 * downsampling chain, the chip will automatically manage the analogue
1823 * specific portions.
1824 */
1825 SND_SOC_DAPM_ADC("ADCL", NULL, SND_SOC_NOPM, 1, 0),
1826 SND_SOC_DAPM_ADC("ADCR", NULL, SND_SOC_NOPM, 0, 0),
1827
1828 SND_SOC_DAPM_MUX("AIF1 Loopback", SND_SOC_NOPM, 0, 0, &aif1_loopback),
1829 SND_SOC_DAPM_MUX("AIF2 Loopback", SND_SOC_NOPM, 0, 0, &aif2_loopback),
1830
1831 SND_SOC_DAPM_POST("Debug log", post_ev),
1832 };
1833
1834 static const struct snd_soc_dapm_widget wm8994_specific_dapm_widgets[] = {
1835 SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8994_aif3adc_mux),
1836 };
1837
1838 static const struct snd_soc_dapm_widget wm8958_dapm_widgets[] = {
1839 SND_SOC_DAPM_SUPPLY("AIF3", WM8994_POWER_MANAGEMENT_6, 5, 1, NULL, 0),
1840 SND_SOC_DAPM_MUX("Mono PCM Out Mux", SND_SOC_NOPM, 0, 0, &mono_pcm_out_mux),
1841 SND_SOC_DAPM_MUX("AIF2DACL Mux", SND_SOC_NOPM, 0, 0, &aif2dacl_src_mux),
1842 SND_SOC_DAPM_MUX("AIF2DACR Mux", SND_SOC_NOPM, 0, 0, &aif2dacr_src_mux),
1843 SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8958_aif3adc_mux),
1844 };
1845
1846 static const struct snd_soc_dapm_route intercon[] = {
1847 { "CLK_SYS", NULL, "AIF1CLK", check_clk_sys },
1848 { "CLK_SYS", NULL, "AIF2CLK", check_clk_sys },
1849
1850 { "DSP1CLK", NULL, "CLK_SYS" },
1851 { "DSP2CLK", NULL, "CLK_SYS" },
1852 { "DSPINTCLK", NULL, "CLK_SYS" },
1853
1854 { "AIF1ADC1L", NULL, "AIF1CLK" },
1855 { "AIF1ADC1L", NULL, "DSP1CLK" },
1856 { "AIF1ADC1R", NULL, "AIF1CLK" },
1857 { "AIF1ADC1R", NULL, "DSP1CLK" },
1858 { "AIF1ADC1R", NULL, "DSPINTCLK" },
1859
1860 { "AIF1DAC1L", NULL, "AIF1CLK" },
1861 { "AIF1DAC1L", NULL, "DSP1CLK" },
1862 { "AIF1DAC1R", NULL, "AIF1CLK" },
1863 { "AIF1DAC1R", NULL, "DSP1CLK" },
1864 { "AIF1DAC1R", NULL, "DSPINTCLK" },
1865
1866 { "AIF1ADC2L", NULL, "AIF1CLK" },
1867 { "AIF1ADC2L", NULL, "DSP1CLK" },
1868 { "AIF1ADC2R", NULL, "AIF1CLK" },
1869 { "AIF1ADC2R", NULL, "DSP1CLK" },
1870 { "AIF1ADC2R", NULL, "DSPINTCLK" },
1871
1872 { "AIF1DAC2L", NULL, "AIF1CLK" },
1873 { "AIF1DAC2L", NULL, "DSP1CLK" },
1874 { "AIF1DAC2R", NULL, "AIF1CLK" },
1875 { "AIF1DAC2R", NULL, "DSP1CLK" },
1876 { "AIF1DAC2R", NULL, "DSPINTCLK" },
1877
1878 { "AIF2ADCL", NULL, "AIF2CLK" },
1879 { "AIF2ADCL", NULL, "DSP2CLK" },
1880 { "AIF2ADCR", NULL, "AIF2CLK" },
1881 { "AIF2ADCR", NULL, "DSP2CLK" },
1882 { "AIF2ADCR", NULL, "DSPINTCLK" },
1883
1884 { "AIF2DACL", NULL, "AIF2CLK" },
1885 { "AIF2DACL", NULL, "DSP2CLK" },
1886 { "AIF2DACR", NULL, "AIF2CLK" },
1887 { "AIF2DACR", NULL, "DSP2CLK" },
1888 { "AIF2DACR", NULL, "DSPINTCLK" },
1889
1890 { "DMIC1L", NULL, "DMIC1DAT" },
1891 { "DMIC1L", NULL, "CLK_SYS" },
1892 { "DMIC1R", NULL, "DMIC1DAT" },
1893 { "DMIC1R", NULL, "CLK_SYS" },
1894 { "DMIC2L", NULL, "DMIC2DAT" },
1895 { "DMIC2L", NULL, "CLK_SYS" },
1896 { "DMIC2R", NULL, "DMIC2DAT" },
1897 { "DMIC2R", NULL, "CLK_SYS" },
1898
1899 { "ADCL", NULL, "AIF1CLK" },
1900 { "ADCL", NULL, "DSP1CLK" },
1901 { "ADCL", NULL, "DSPINTCLK" },
1902
1903 { "ADCR", NULL, "AIF1CLK" },
1904 { "ADCR", NULL, "DSP1CLK" },
1905 { "ADCR", NULL, "DSPINTCLK" },
1906
1907 { "ADCL Mux", "ADC", "ADCL" },
1908 { "ADCL Mux", "DMIC", "DMIC1L" },
1909 { "ADCR Mux", "ADC", "ADCR" },
1910 { "ADCR Mux", "DMIC", "DMIC1R" },
1911
1912 { "DAC1L", NULL, "AIF1CLK" },
1913 { "DAC1L", NULL, "DSP1CLK" },
1914 { "DAC1L", NULL, "DSPINTCLK" },
1915
1916 { "DAC1R", NULL, "AIF1CLK" },
1917 { "DAC1R", NULL, "DSP1CLK" },
1918 { "DAC1R", NULL, "DSPINTCLK" },
1919
1920 { "DAC2L", NULL, "AIF2CLK" },
1921 { "DAC2L", NULL, "DSP2CLK" },
1922 { "DAC2L", NULL, "DSPINTCLK" },
1923
1924 { "DAC2R", NULL, "AIF2DACR" },
1925 { "DAC2R", NULL, "AIF2CLK" },
1926 { "DAC2R", NULL, "DSP2CLK" },
1927 { "DAC2R", NULL, "DSPINTCLK" },
1928
1929 { "TOCLK", NULL, "CLK_SYS" },
1930
1931 { "AIF1DACDAT", NULL, "AIF1 Playback" },
1932 { "AIF2DACDAT", NULL, "AIF2 Playback" },
1933 { "AIF3DACDAT", NULL, "AIF3 Playback" },
1934
1935 { "AIF1 Capture", NULL, "AIF1ADCDAT" },
1936 { "AIF2 Capture", NULL, "AIF2ADCDAT" },
1937 { "AIF3 Capture", NULL, "AIF3ADCDAT" },
1938
1939 /* AIF1 outputs */
1940 { "AIF1ADC1L", NULL, "AIF1ADC1L Mixer" },
1941 { "AIF1ADC1L Mixer", "ADC/DMIC Switch", "ADCL Mux" },
1942 { "AIF1ADC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1943
1944 { "AIF1ADC1R", NULL, "AIF1ADC1R Mixer" },
1945 { "AIF1ADC1R Mixer", "ADC/DMIC Switch", "ADCR Mux" },
1946 { "AIF1ADC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1947
1948 { "AIF1ADC2L", NULL, "AIF1ADC2L Mixer" },
1949 { "AIF1ADC2L Mixer", "DMIC Switch", "DMIC2L" },
1950 { "AIF1ADC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1951
1952 { "AIF1ADC2R", NULL, "AIF1ADC2R Mixer" },
1953 { "AIF1ADC2R Mixer", "DMIC Switch", "DMIC2R" },
1954 { "AIF1ADC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1955
1956 /* Pin level routing for AIF3 */
1957 { "AIF1DAC1L", NULL, "AIF1DAC Mux" },
1958 { "AIF1DAC1R", NULL, "AIF1DAC Mux" },
1959 { "AIF1DAC2L", NULL, "AIF1DAC Mux" },
1960 { "AIF1DAC2R", NULL, "AIF1DAC Mux" },
1961
1962 { "AIF1DAC Mux", "AIF1DACDAT", "AIF1 Loopback" },
1963 { "AIF1DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1964 { "AIF2DAC Mux", "AIF2DACDAT", "AIF2 Loopback" },
1965 { "AIF2DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1966 { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCL" },
1967 { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCR" },
1968 { "AIF2ADC Mux", "AIF3DACDAT", "AIF3ADCDAT" },
1969
1970 /* DAC1 inputs */
1971 { "DAC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1972 { "DAC1L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1973 { "DAC1L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1974 { "DAC1L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1975 { "DAC1L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1976
1977 { "DAC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1978 { "DAC1R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1979 { "DAC1R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1980 { "DAC1R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1981 { "DAC1R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1982
1983 /* DAC2/AIF2 outputs */
1984 { "AIF2ADCL", NULL, "AIF2DAC2L Mixer" },
1985 { "AIF2DAC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1986 { "AIF2DAC2L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1987 { "AIF2DAC2L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1988 { "AIF2DAC2L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1989 { "AIF2DAC2L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1990
1991 { "AIF2ADCR", NULL, "AIF2DAC2R Mixer" },
1992 { "AIF2DAC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1993 { "AIF2DAC2R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1994 { "AIF2DAC2R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1995 { "AIF2DAC2R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1996 { "AIF2DAC2R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1997
1998 { "AIF1ADCDAT", NULL, "AIF1ADC1L" },
1999 { "AIF1ADCDAT", NULL, "AIF1ADC1R" },
2000 { "AIF1ADCDAT", NULL, "AIF1ADC2L" },
2001 { "AIF1ADCDAT", NULL, "AIF1ADC2R" },
2002
2003 { "AIF2ADCDAT", NULL, "AIF2ADC Mux" },
2004
2005 /* AIF3 output */
2006 { "AIF3ADC Mux", "AIF1ADCDAT", "AIF1ADC1L" },
2007 { "AIF3ADC Mux", "AIF1ADCDAT", "AIF1ADC1R" },
2008 { "AIF3ADC Mux", "AIF1ADCDAT", "AIF1ADC2L" },
2009 { "AIF3ADC Mux", "AIF1ADCDAT", "AIF1ADC2R" },
2010 { "AIF3ADC Mux", "AIF2ADCDAT", "AIF2ADCL" },
2011 { "AIF3ADC Mux", "AIF2ADCDAT", "AIF2ADCR" },
2012 { "AIF3ADC Mux", "AIF2DACDAT", "AIF2DACL" },
2013 { "AIF3ADC Mux", "AIF2DACDAT", "AIF2DACR" },
2014
2015 { "AIF3ADCDAT", NULL, "AIF3ADC Mux" },
2016
2017 /* Loopback */
2018 { "AIF1 Loopback", "ADCDAT", "AIF1ADCDAT" },
2019 { "AIF1 Loopback", "None", "AIF1DACDAT" },
2020 { "AIF2 Loopback", "ADCDAT", "AIF2ADCDAT" },
2021 { "AIF2 Loopback", "None", "AIF2DACDAT" },
2022
2023 /* Sidetone */
2024 { "Left Sidetone", "ADC/DMIC1", "ADCL Mux" },
2025 { "Left Sidetone", "DMIC2", "DMIC2L" },
2026 { "Right Sidetone", "ADC/DMIC1", "ADCR Mux" },
2027 { "Right Sidetone", "DMIC2", "DMIC2R" },
2028
2029 /* Output stages */
2030 { "Left Output Mixer", "DAC Switch", "DAC1L" },
2031 { "Right Output Mixer", "DAC Switch", "DAC1R" },
2032
2033 { "SPKL", "DAC1 Switch", "DAC1L" },
2034 { "SPKL", "DAC2 Switch", "DAC2L" },
2035
2036 { "SPKR", "DAC1 Switch", "DAC1R" },
2037 { "SPKR", "DAC2 Switch", "DAC2R" },
2038
2039 { "Left Headphone Mux", "DAC", "DAC1L" },
2040 { "Right Headphone Mux", "DAC", "DAC1R" },
2041 };
2042
2043 static const struct snd_soc_dapm_route wm8994_lateclk_revd_intercon[] = {
2044 { "DAC1L", NULL, "Late DAC1L Enable PGA" },
2045 { "Late DAC1L Enable PGA", NULL, "DAC1L Mixer" },
2046 { "DAC1R", NULL, "Late DAC1R Enable PGA" },
2047 { "Late DAC1R Enable PGA", NULL, "DAC1R Mixer" },
2048 { "DAC2L", NULL, "Late DAC2L Enable PGA" },
2049 { "Late DAC2L Enable PGA", NULL, "AIF2DAC2L Mixer" },
2050 { "DAC2R", NULL, "Late DAC2R Enable PGA" },
2051 { "Late DAC2R Enable PGA", NULL, "AIF2DAC2R Mixer" }
2052 };
2053
2054 static const struct snd_soc_dapm_route wm8994_lateclk_intercon[] = {
2055 { "DAC1L", NULL, "DAC1L Mixer" },
2056 { "DAC1R", NULL, "DAC1R Mixer" },
2057 { "DAC2L", NULL, "AIF2DAC2L Mixer" },
2058 { "DAC2R", NULL, "AIF2DAC2R Mixer" },
2059 };
2060
2061 static const struct snd_soc_dapm_route wm8994_revd_intercon[] = {
2062 { "AIF1DACDAT", NULL, "AIF2DACDAT" },
2063 { "AIF2DACDAT", NULL, "AIF1DACDAT" },
2064 { "AIF1ADCDAT", NULL, "AIF2ADCDAT" },
2065 { "AIF2ADCDAT", NULL, "AIF1ADCDAT" },
2066 { "MICBIAS1", NULL, "CLK_SYS" },
2067 { "MICBIAS1", NULL, "MICBIAS Supply" },
2068 { "MICBIAS2", NULL, "CLK_SYS" },
2069 { "MICBIAS2", NULL, "MICBIAS Supply" },
2070 };
2071
2072 static const struct snd_soc_dapm_route wm8994_intercon[] = {
2073 { "AIF2DACL", NULL, "AIF2DAC Mux" },
2074 { "AIF2DACR", NULL, "AIF2DAC Mux" },
2075 { "MICBIAS1", NULL, "VMID" },
2076 { "MICBIAS2", NULL, "VMID" },
2077 };
2078
2079 static const struct snd_soc_dapm_route wm8958_intercon[] = {
2080 { "AIF2DACL", NULL, "AIF2DACL Mux" },
2081 { "AIF2DACR", NULL, "AIF2DACR Mux" },
2082
2083 { "AIF2DACL Mux", "AIF2", "AIF2DAC Mux" },
2084 { "AIF2DACL Mux", "AIF3", "AIF3DACDAT" },
2085 { "AIF2DACR Mux", "AIF2", "AIF2DAC Mux" },
2086 { "AIF2DACR Mux", "AIF3", "AIF3DACDAT" },
2087
2088 { "AIF3DACDAT", NULL, "AIF3" },
2089 { "AIF3ADCDAT", NULL, "AIF3" },
2090
2091 { "Mono PCM Out Mux", "AIF2ADCL", "AIF2ADCL" },
2092 { "Mono PCM Out Mux", "AIF2ADCR", "AIF2ADCR" },
2093
2094 { "AIF3ADC Mux", "Mono PCM", "Mono PCM Out Mux" },
2095 };
2096
2097 /* The size in bits of the FLL divide multiplied by 10
2098 * to allow rounding later */
2099 #define FIXED_FLL_SIZE ((1 << 16) * 10)
2100
2101 struct fll_div {
2102 u16 outdiv;
2103 u16 n;
2104 u16 k;
2105 u16 lambda;
2106 u16 clk_ref_div;
2107 u16 fll_fratio;
2108 };
2109
2110 static int wm8994_get_fll_config(struct wm8994 *control, struct fll_div *fll,
2111 int freq_in, int freq_out)
2112 {
2113 u64 Kpart;
2114 unsigned int K, Ndiv, Nmod, gcd_fll;
2115
2116 pr_debug("FLL input=%dHz, output=%dHz\n", freq_in, freq_out);
2117
2118 /* Scale the input frequency down to <= 13.5MHz */
2119 fll->clk_ref_div = 0;
2120 while (freq_in > 13500000) {
2121 fll->clk_ref_div++;
2122 freq_in /= 2;
2123
2124 if (fll->clk_ref_div > 3)
2125 return -EINVAL;
2126 }
2127 pr_debug("CLK_REF_DIV=%d, Fref=%dHz\n", fll->clk_ref_div, freq_in);
2128
2129 /* Scale the output to give 90MHz<=Fvco<=100MHz */
2130 fll->outdiv = 3;
2131 while (freq_out * (fll->outdiv + 1) < 90000000) {
2132 fll->outdiv++;
2133 if (fll->outdiv > 63)
2134 return -EINVAL;
2135 }
2136 freq_out *= fll->outdiv + 1;
2137 pr_debug("OUTDIV=%d, Fvco=%dHz\n", fll->outdiv, freq_out);
2138
2139 if (freq_in > 1000000) {
2140 fll->fll_fratio = 0;
2141 } else if (freq_in > 256000) {
2142 fll->fll_fratio = 1;
2143 freq_in *= 2;
2144 } else if (freq_in > 128000) {
2145 fll->fll_fratio = 2;
2146 freq_in *= 4;
2147 } else if (freq_in > 64000) {
2148 fll->fll_fratio = 3;
2149 freq_in *= 8;
2150 } else {
2151 fll->fll_fratio = 4;
2152 freq_in *= 16;
2153 }
2154 pr_debug("FLL_FRATIO=%d, Fref=%dHz\n", fll->fll_fratio, freq_in);
2155
2156 /* Now, calculate N.K */
2157 Ndiv = freq_out / freq_in;
2158
2159 fll->n = Ndiv;
2160 Nmod = freq_out % freq_in;
2161 pr_debug("Nmod=%d\n", Nmod);
2162
2163 switch (control->type) {
2164 case WM8994:
2165 /* Calculate fractional part - scale up so we can round. */
2166 Kpart = FIXED_FLL_SIZE * (long long)Nmod;
2167
2168 do_div(Kpart, freq_in);
2169
2170 K = Kpart & 0xFFFFFFFF;
2171
2172 if ((K % 10) >= 5)
2173 K += 5;
2174
2175 /* Move down to proper range now rounding is done */
2176 fll->k = K / 10;
2177 fll->lambda = 0;
2178
2179 pr_debug("N=%x K=%x\n", fll->n, fll->k);
2180 break;
2181
2182 default:
2183 gcd_fll = gcd(freq_out, freq_in);
2184
2185 fll->k = (freq_out - (freq_in * fll->n)) / gcd_fll;
2186 fll->lambda = freq_in / gcd_fll;
2187
2188 }
2189
2190 return 0;
2191 }
2192
2193 static int _wm8994_set_fll(struct snd_soc_component *component, int id, int src,
2194 unsigned int freq_in, unsigned int freq_out)
2195 {
2196 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
2197 struct wm8994 *control = wm8994->wm8994;
2198 int reg_offset, ret;
2199 struct fll_div fll;
2200 u16 reg, clk1, aif_reg, aif_src;
2201 unsigned long timeout;
2202 bool was_enabled;
2203 struct clk *mclk;
2204
2205 switch (id) {
2206 case WM8994_FLL1:
2207 reg_offset = 0;
2208 id = 0;
2209 aif_src = 0x10;
2210 break;
2211 case WM8994_FLL2:
2212 reg_offset = 0x20;
2213 id = 1;
2214 aif_src = 0x18;
2215 break;
2216 default:
2217 return -EINVAL;
2218 }
2219
2220 reg = snd_soc_component_read32(component, WM8994_FLL1_CONTROL_1 + reg_offset);
2221 was_enabled = reg & WM8994_FLL1_ENA;
2222
2223 switch (src) {
2224 case 0:
2225 /* Allow no source specification when stopping */
2226 if (freq_out)
2227 return -EINVAL;
2228 src = wm8994->fll[id].src;
2229 break;
2230 case WM8994_FLL_SRC_MCLK1:
2231 case WM8994_FLL_SRC_MCLK2:
2232 case WM8994_FLL_SRC_LRCLK:
2233 case WM8994_FLL_SRC_BCLK:
2234 break;
2235 case WM8994_FLL_SRC_INTERNAL:
2236 freq_in = 12000000;
2237 freq_out = 12000000;
2238 break;
2239 default:
2240 return -EINVAL;
2241 }
2242
2243 /* Are we changing anything? */
2244 if (wm8994->fll[id].src == src &&
2245 wm8994->fll[id].in == freq_in && wm8994->fll[id].out == freq_out)
2246 return 0;
2247
2248 /* If we're stopping the FLL redo the old config - no
2249 * registers will actually be written but we avoid GCC flow
2250 * analysis bugs spewing warnings.
2251 */
2252 if (freq_out)
2253 ret = wm8994_get_fll_config(control, &fll, freq_in, freq_out);
2254 else
2255 ret = wm8994_get_fll_config(control, &fll, wm8994->fll[id].in,
2256 wm8994->fll[id].out);
2257 if (ret < 0)
2258 return ret;
2259
2260 /* Make sure that we're not providing SYSCLK right now */
2261 clk1 = snd_soc_component_read32(component, WM8994_CLOCKING_1);
2262 if (clk1 & WM8994_SYSCLK_SRC)
2263 aif_reg = WM8994_AIF2_CLOCKING_1;
2264 else
2265 aif_reg = WM8994_AIF1_CLOCKING_1;
2266 reg = snd_soc_component_read32(component, aif_reg);
2267
2268 if ((reg & WM8994_AIF1CLK_ENA) &&
2269 (reg & WM8994_AIF1CLK_SRC_MASK) == aif_src) {
2270 dev_err(component->dev, "FLL%d is currently providing SYSCLK\n",
2271 id + 1);
2272 return -EBUSY;
2273 }
2274
2275 /* We always need to disable the FLL while reconfiguring */
2276 snd_soc_component_update_bits(component, WM8994_FLL1_CONTROL_1 + reg_offset,
2277 WM8994_FLL1_ENA, 0);
2278
2279 /* Disable MCLK if needed before we possibly change to new clock parent */
2280 if (was_enabled) {
2281 reg = snd_soc_component_read32(component, WM8994_FLL1_CONTROL_5
2282 + reg_offset);
2283 reg = ((reg & WM8994_FLL1_REFCLK_SRC_MASK)
2284 >> WM8994_FLL1_REFCLK_SRC_SHIFT) + 1;
2285
2286 switch (reg) {
2287 case WM8994_FLL_SRC_MCLK1:
2288 mclk = wm8994->mclk[WM8994_MCLK1].clk;
2289 break;
2290 case WM8994_FLL_SRC_MCLK2:
2291 mclk = wm8994->mclk[WM8994_MCLK2].clk;
2292 break;
2293 default:
2294 mclk = NULL;
2295 }
2296
2297 clk_disable_unprepare(mclk);
2298 }
2299
2300 if (wm8994->fll_byp && src == WM8994_FLL_SRC_BCLK &&
2301 freq_in == freq_out && freq_out) {
2302 dev_dbg(component->dev, "Bypassing FLL%d\n", id + 1);
2303 snd_soc_component_update_bits(component, WM8994_FLL1_CONTROL_5 + reg_offset,
2304 WM8958_FLL1_BYP, WM8958_FLL1_BYP);
2305 goto out;
2306 }
2307
2308 reg = (fll.outdiv << WM8994_FLL1_OUTDIV_SHIFT) |
2309 (fll.fll_fratio << WM8994_FLL1_FRATIO_SHIFT);
2310 snd_soc_component_update_bits(component, WM8994_FLL1_CONTROL_2 + reg_offset,
2311 WM8994_FLL1_OUTDIV_MASK |
2312 WM8994_FLL1_FRATIO_MASK, reg);
2313
2314 snd_soc_component_update_bits(component, WM8994_FLL1_CONTROL_3 + reg_offset,
2315 WM8994_FLL1_K_MASK, fll.k);
2316
2317 snd_soc_component_update_bits(component, WM8994_FLL1_CONTROL_4 + reg_offset,
2318 WM8994_FLL1_N_MASK,
2319 fll.n << WM8994_FLL1_N_SHIFT);
2320
2321 if (fll.lambda) {
2322 snd_soc_component_update_bits(component, WM8958_FLL1_EFS_1 + reg_offset,
2323 WM8958_FLL1_LAMBDA_MASK,
2324 fll.lambda);
2325 snd_soc_component_update_bits(component, WM8958_FLL1_EFS_2 + reg_offset,
2326 WM8958_FLL1_EFS_ENA, WM8958_FLL1_EFS_ENA);
2327 } else {
2328 snd_soc_component_update_bits(component, WM8958_FLL1_EFS_2 + reg_offset,
2329 WM8958_FLL1_EFS_ENA, 0);
2330 }
2331
2332 snd_soc_component_update_bits(component, WM8994_FLL1_CONTROL_5 + reg_offset,
2333 WM8994_FLL1_FRC_NCO | WM8958_FLL1_BYP |
2334 WM8994_FLL1_REFCLK_DIV_MASK |
2335 WM8994_FLL1_REFCLK_SRC_MASK,
2336 ((src == WM8994_FLL_SRC_INTERNAL)
2337 << WM8994_FLL1_FRC_NCO_SHIFT) |
2338 (fll.clk_ref_div << WM8994_FLL1_REFCLK_DIV_SHIFT) |
2339 (src - 1));
2340
2341 /* Clear any pending completion from a previous failure */
2342 try_wait_for_completion(&wm8994->fll_locked[id]);
2343
2344 switch (src) {
2345 case WM8994_FLL_SRC_MCLK1:
2346 mclk = wm8994->mclk[WM8994_MCLK1].clk;
2347 break;
2348 case WM8994_FLL_SRC_MCLK2:
2349 mclk = wm8994->mclk[WM8994_MCLK2].clk;
2350 break;
2351 default:
2352 mclk = NULL;
2353 }
2354
2355 /* Enable (with fractional mode if required) */
2356 if (freq_out) {
2357 ret = clk_prepare_enable(mclk);
2358 if (ret < 0) {
2359 dev_err(component->dev, "Failed to enable MCLK for FLL%d\n",
2360 id + 1);
2361 return ret;
2362 }
2363
2364 /* Enable VMID if we need it */
2365 if (!was_enabled) {
2366
2367 active_reference(component);
2368
2369 switch (control->type) {
2370 case WM8994:
2371 vmid_reference(component);
2372 break;
2373 case WM8958:
2374 if (control->revision < 1)
2375 vmid_reference(component);
2376 break;
2377 default:
2378 break;
2379 }
2380 }
2381
2382 reg = WM8994_FLL1_ENA;
2383
2384 if (fll.k)
2385 reg |= WM8994_FLL1_FRAC;
2386 if (src == WM8994_FLL_SRC_INTERNAL)
2387 reg |= WM8994_FLL1_OSC_ENA;
2388
2389 snd_soc_component_update_bits(component, WM8994_FLL1_CONTROL_1 + reg_offset,
2390 WM8994_FLL1_ENA | WM8994_FLL1_OSC_ENA |
2391 WM8994_FLL1_FRAC, reg);
2392
2393 if (wm8994->fll_locked_irq) {
2394 timeout = wait_for_completion_timeout(&wm8994->fll_locked[id],
2395 msecs_to_jiffies(10));
2396 if (timeout == 0)
2397 dev_warn(component->dev,
2398 "Timed out waiting for FLL lock\n");
2399 } else {
2400 msleep(5);
2401 }
2402 } else {
2403 if (was_enabled) {
2404 switch (control->type) {
2405 case WM8994:
2406 vmid_dereference(component);
2407 break;
2408 case WM8958:
2409 if (control->revision < 1)
2410 vmid_dereference(component);
2411 break;
2412 default:
2413 break;
2414 }
2415
2416 active_dereference(component);
2417 }
2418 }
2419
2420 out:
2421 wm8994->fll[id].in = freq_in;
2422 wm8994->fll[id].out = freq_out;
2423 wm8994->fll[id].src = src;
2424
2425 configure_clock(component);
2426
2427 /*
2428 * If SYSCLK will be less than 50kHz adjust AIFnCLK dividers
2429 * for detection.
2430 */
2431 if (max(wm8994->aifclk[0], wm8994->aifclk[1]) < 50000) {
2432 dev_dbg(component->dev, "Configuring AIFs for 128fs\n");
2433
2434 wm8994->aifdiv[0] = snd_soc_component_read32(component, WM8994_AIF1_RATE)
2435 & WM8994_AIF1CLK_RATE_MASK;
2436 wm8994->aifdiv[1] = snd_soc_component_read32(component, WM8994_AIF2_RATE)
2437 & WM8994_AIF1CLK_RATE_MASK;
2438
2439 snd_soc_component_update_bits(component, WM8994_AIF1_RATE,
2440 WM8994_AIF1CLK_RATE_MASK, 0x1);
2441 snd_soc_component_update_bits(component, WM8994_AIF2_RATE,
2442 WM8994_AIF2CLK_RATE_MASK, 0x1);
2443 } else if (wm8994->aifdiv[0]) {
2444 snd_soc_component_update_bits(component, WM8994_AIF1_RATE,
2445 WM8994_AIF1CLK_RATE_MASK,
2446 wm8994->aifdiv[0]);
2447 snd_soc_component_update_bits(component, WM8994_AIF2_RATE,
2448 WM8994_AIF2CLK_RATE_MASK,
2449 wm8994->aifdiv[1]);
2450
2451 wm8994->aifdiv[0] = 0;
2452 wm8994->aifdiv[1] = 0;
2453 }
2454
2455 return 0;
2456 }
2457
2458 static irqreturn_t wm8994_fll_locked_irq(int irq, void *data)
2459 {
2460 struct completion *completion = data;
2461
2462 complete(completion);
2463
2464 return IRQ_HANDLED;
2465 }
2466
2467 static int opclk_divs[] = { 10, 20, 30, 40, 55, 60, 80, 120, 160 };
2468
2469 static int wm8994_set_fll(struct snd_soc_dai *dai, int id, int src,
2470 unsigned int freq_in, unsigned int freq_out)
2471 {
2472 return _wm8994_set_fll(dai->component, id, src, freq_in, freq_out);
2473 }
2474
2475 static int wm8994_set_mclk_rate(struct wm8994_priv *wm8994, unsigned int id,
2476 unsigned int *freq)
2477 {
2478 int ret;
2479
2480 if (!wm8994->mclk[id].clk || *freq == wm8994->mclk_rate[id])
2481 return 0;
2482
2483 ret = clk_set_rate(wm8994->mclk[id].clk, *freq);
2484 if (ret < 0)
2485 return ret;
2486
2487 *freq = clk_get_rate(wm8994->mclk[id].clk);
2488
2489 return 0;
2490 }
2491
2492 static int wm8994_set_dai_sysclk(struct snd_soc_dai *dai,
2493 int clk_id, unsigned int freq, int dir)
2494 {
2495 struct snd_soc_component *component = dai->component;
2496 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
2497 int ret, i;
2498
2499 switch (dai->id) {
2500 case 1:
2501 case 2:
2502 break;
2503
2504 default:
2505 /* AIF3 shares clocking with AIF1/2 */
2506 return -EINVAL;
2507 }
2508
2509 switch (clk_id) {
2510 case WM8994_SYSCLK_MCLK1:
2511 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK1;
2512
2513 ret = wm8994_set_mclk_rate(wm8994, dai->id - 1, &freq);
2514 if (ret < 0)
2515 return ret;
2516
2517 wm8994->mclk_rate[0] = freq;
2518 dev_dbg(dai->dev, "AIF%d using MCLK1 at %uHz\n",
2519 dai->id, freq);
2520 break;
2521
2522 case WM8994_SYSCLK_MCLK2:
2523 /* TODO: Set GPIO AF */
2524 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK2;
2525
2526 ret = wm8994_set_mclk_rate(wm8994, dai->id - 1, &freq);
2527 if (ret < 0)
2528 return ret;
2529
2530 wm8994->mclk_rate[1] = freq;
2531 dev_dbg(dai->dev, "AIF%d using MCLK2 at %uHz\n",
2532 dai->id, freq);
2533 break;
2534
2535 case WM8994_SYSCLK_FLL1:
2536 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL1;
2537 dev_dbg(dai->dev, "AIF%d using FLL1\n", dai->id);
2538 break;
2539
2540 case WM8994_SYSCLK_FLL2:
2541 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL2;
2542 dev_dbg(dai->dev, "AIF%d using FLL2\n", dai->id);
2543 break;
2544
2545 case WM8994_SYSCLK_OPCLK:
2546 /* Special case - a division (times 10) is given and
2547 * no effect on main clocking.
2548 */
2549 if (freq) {
2550 for (i = 0; i < ARRAY_SIZE(opclk_divs); i++)
2551 if (opclk_divs[i] == freq)
2552 break;
2553 if (i == ARRAY_SIZE(opclk_divs))
2554 return -EINVAL;
2555 snd_soc_component_update_bits(component, WM8994_CLOCKING_2,
2556 WM8994_OPCLK_DIV_MASK, i);
2557 snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_2,
2558 WM8994_OPCLK_ENA, WM8994_OPCLK_ENA);
2559 } else {
2560 snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_2,
2561 WM8994_OPCLK_ENA, 0);
2562 }
2563 break;
2564
2565 default:
2566 return -EINVAL;
2567 }
2568
2569 configure_clock(component);
2570
2571 /*
2572 * If SYSCLK will be less than 50kHz adjust AIFnCLK dividers
2573 * for detection.
2574 */
2575 if (max(wm8994->aifclk[0], wm8994->aifclk[1]) < 50000) {
2576 dev_dbg(component->dev, "Configuring AIFs for 128fs\n");
2577
2578 wm8994->aifdiv[0] = snd_soc_component_read32(component, WM8994_AIF1_RATE)
2579 & WM8994_AIF1CLK_RATE_MASK;
2580 wm8994->aifdiv[1] = snd_soc_component_read32(component, WM8994_AIF2_RATE)
2581 & WM8994_AIF1CLK_RATE_MASK;
2582
2583 snd_soc_component_update_bits(component, WM8994_AIF1_RATE,
2584 WM8994_AIF1CLK_RATE_MASK, 0x1);
2585 snd_soc_component_update_bits(component, WM8994_AIF2_RATE,
2586 WM8994_AIF2CLK_RATE_MASK, 0x1);
2587 } else if (wm8994->aifdiv[0]) {
2588 snd_soc_component_update_bits(component, WM8994_AIF1_RATE,
2589 WM8994_AIF1CLK_RATE_MASK,
2590 wm8994->aifdiv[0]);
2591 snd_soc_component_update_bits(component, WM8994_AIF2_RATE,
2592 WM8994_AIF2CLK_RATE_MASK,
2593 wm8994->aifdiv[1]);
2594
2595 wm8994->aifdiv[0] = 0;
2596 wm8994->aifdiv[1] = 0;
2597 }
2598
2599 return 0;
2600 }
2601
2602 static int wm8994_set_bias_level(struct snd_soc_component *component,
2603 enum snd_soc_bias_level level)
2604 {
2605 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
2606 struct wm8994 *control = wm8994->wm8994;
2607
2608 wm_hubs_set_bias_level(component, level);
2609
2610 switch (level) {
2611 case SND_SOC_BIAS_ON:
2612 break;
2613
2614 case SND_SOC_BIAS_PREPARE:
2615 /* MICBIAS into regulating mode */
2616 switch (control->type) {
2617 case WM8958:
2618 case WM1811:
2619 snd_soc_component_update_bits(component, WM8958_MICBIAS1,
2620 WM8958_MICB1_MODE, 0);
2621 snd_soc_component_update_bits(component, WM8958_MICBIAS2,
2622 WM8958_MICB2_MODE, 0);
2623 break;
2624 default:
2625 break;
2626 }
2627
2628 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_STANDBY)
2629 active_reference(component);
2630 break;
2631
2632 case SND_SOC_BIAS_STANDBY:
2633 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
2634 switch (control->type) {
2635 case WM8958:
2636 if (control->revision == 0) {
2637 /* Optimise performance for rev A */
2638 snd_soc_component_update_bits(component,
2639 WM8958_CHARGE_PUMP_2,
2640 WM8958_CP_DISCH,
2641 WM8958_CP_DISCH);
2642 }
2643 break;
2644
2645 default:
2646 break;
2647 }
2648
2649 /* Discharge LINEOUT1 & 2 */
2650 snd_soc_component_update_bits(component, WM8994_ANTIPOP_1,
2651 WM8994_LINEOUT1_DISCH |
2652 WM8994_LINEOUT2_DISCH,
2653 WM8994_LINEOUT1_DISCH |
2654 WM8994_LINEOUT2_DISCH);
2655 }
2656
2657 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_PREPARE)
2658 active_dereference(component);
2659
2660 /* MICBIAS into bypass mode on newer devices */
2661 switch (control->type) {
2662 case WM8958:
2663 case WM1811:
2664 snd_soc_component_update_bits(component, WM8958_MICBIAS1,
2665 WM8958_MICB1_MODE,
2666 WM8958_MICB1_MODE);
2667 snd_soc_component_update_bits(component, WM8958_MICBIAS2,
2668 WM8958_MICB2_MODE,
2669 WM8958_MICB2_MODE);
2670 break;
2671 default:
2672 break;
2673 }
2674 break;
2675
2676 case SND_SOC_BIAS_OFF:
2677 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_STANDBY)
2678 wm8994->cur_fw = NULL;
2679 break;
2680 }
2681
2682 return 0;
2683 }
2684
2685 int wm8994_vmid_mode(struct snd_soc_component *component, enum wm8994_vmid_mode mode)
2686 {
2687 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
2688 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
2689
2690 switch (mode) {
2691 case WM8994_VMID_NORMAL:
2692 snd_soc_dapm_mutex_lock(dapm);
2693
2694 if (wm8994->hubs.lineout1_se) {
2695 snd_soc_dapm_disable_pin_unlocked(dapm,
2696 "LINEOUT1N Driver");
2697 snd_soc_dapm_disable_pin_unlocked(dapm,
2698 "LINEOUT1P Driver");
2699 }
2700 if (wm8994->hubs.lineout2_se) {
2701 snd_soc_dapm_disable_pin_unlocked(dapm,
2702 "LINEOUT2N Driver");
2703 snd_soc_dapm_disable_pin_unlocked(dapm,
2704 "LINEOUT2P Driver");
2705 }
2706
2707 /* Do the sync with the old mode to allow it to clean up */
2708 snd_soc_dapm_sync_unlocked(dapm);
2709 wm8994->vmid_mode = mode;
2710
2711 snd_soc_dapm_mutex_unlock(dapm);
2712 break;
2713
2714 case WM8994_VMID_FORCE:
2715 snd_soc_dapm_mutex_lock(dapm);
2716
2717 if (wm8994->hubs.lineout1_se) {
2718 snd_soc_dapm_force_enable_pin_unlocked(dapm,
2719 "LINEOUT1N Driver");
2720 snd_soc_dapm_force_enable_pin_unlocked(dapm,
2721 "LINEOUT1P Driver");
2722 }
2723 if (wm8994->hubs.lineout2_se) {
2724 snd_soc_dapm_force_enable_pin_unlocked(dapm,
2725 "LINEOUT2N Driver");
2726 snd_soc_dapm_force_enable_pin_unlocked(dapm,
2727 "LINEOUT2P Driver");
2728 }
2729
2730 wm8994->vmid_mode = mode;
2731 snd_soc_dapm_sync_unlocked(dapm);
2732
2733 snd_soc_dapm_mutex_unlock(dapm);
2734 break;
2735
2736 default:
2737 return -EINVAL;
2738 }
2739
2740 return 0;
2741 }
2742
2743 static int wm8994_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
2744 {
2745 struct snd_soc_component *component = dai->component;
2746 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
2747 struct wm8994 *control = wm8994->wm8994;
2748 int ms_reg;
2749 int aif1_reg;
2750 int dac_reg;
2751 int adc_reg;
2752 int ms = 0;
2753 int aif1 = 0;
2754 int lrclk = 0;
2755
2756 switch (dai->id) {
2757 case 1:
2758 ms_reg = WM8994_AIF1_MASTER_SLAVE;
2759 aif1_reg = WM8994_AIF1_CONTROL_1;
2760 dac_reg = WM8994_AIF1DAC_LRCLK;
2761 adc_reg = WM8994_AIF1ADC_LRCLK;
2762 break;
2763 case 2:
2764 ms_reg = WM8994_AIF2_MASTER_SLAVE;
2765 aif1_reg = WM8994_AIF2_CONTROL_1;
2766 dac_reg = WM8994_AIF1DAC_LRCLK;
2767 adc_reg = WM8994_AIF1ADC_LRCLK;
2768 break;
2769 default:
2770 return -EINVAL;
2771 }
2772
2773 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
2774 case SND_SOC_DAIFMT_CBS_CFS:
2775 break;
2776 case SND_SOC_DAIFMT_CBM_CFM:
2777 ms = WM8994_AIF1_MSTR;
2778 break;
2779 default:
2780 return -EINVAL;
2781 }
2782
2783 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2784 case SND_SOC_DAIFMT_DSP_B:
2785 aif1 |= WM8994_AIF1_LRCLK_INV;
2786 lrclk |= WM8958_AIF1_LRCLK_INV;
2787 /* fall through */
2788 case SND_SOC_DAIFMT_DSP_A:
2789 aif1 |= 0x18;
2790 break;
2791 case SND_SOC_DAIFMT_I2S:
2792 aif1 |= 0x10;
2793 break;
2794 case SND_SOC_DAIFMT_RIGHT_J:
2795 break;
2796 case SND_SOC_DAIFMT_LEFT_J:
2797 aif1 |= 0x8;
2798 break;
2799 default:
2800 return -EINVAL;
2801 }
2802
2803 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2804 case SND_SOC_DAIFMT_DSP_A:
2805 case SND_SOC_DAIFMT_DSP_B:
2806 /* frame inversion not valid for DSP modes */
2807 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2808 case SND_SOC_DAIFMT_NB_NF:
2809 break;
2810 case SND_SOC_DAIFMT_IB_NF:
2811 aif1 |= WM8994_AIF1_BCLK_INV;
2812 break;
2813 default:
2814 return -EINVAL;
2815 }
2816 break;
2817
2818 case SND_SOC_DAIFMT_I2S:
2819 case SND_SOC_DAIFMT_RIGHT_J:
2820 case SND_SOC_DAIFMT_LEFT_J:
2821 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2822 case SND_SOC_DAIFMT_NB_NF:
2823 break;
2824 case SND_SOC_DAIFMT_IB_IF:
2825 aif1 |= WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV;
2826 lrclk |= WM8958_AIF1_LRCLK_INV;
2827 break;
2828 case SND_SOC_DAIFMT_IB_NF:
2829 aif1 |= WM8994_AIF1_BCLK_INV;
2830 break;
2831 case SND_SOC_DAIFMT_NB_IF:
2832 aif1 |= WM8994_AIF1_LRCLK_INV;
2833 lrclk |= WM8958_AIF1_LRCLK_INV;
2834 break;
2835 default:
2836 return -EINVAL;
2837 }
2838 break;
2839 default:
2840 return -EINVAL;
2841 }
2842
2843 /* The AIF2 format configuration needs to be mirrored to AIF3
2844 * on WM8958 if it's in use so just do it all the time. */
2845 switch (control->type) {
2846 case WM1811:
2847 case WM8958:
2848 if (dai->id == 2)
2849 snd_soc_component_update_bits(component, WM8958_AIF3_CONTROL_1,
2850 WM8994_AIF1_LRCLK_INV |
2851 WM8958_AIF3_FMT_MASK, aif1);
2852 break;
2853
2854 default:
2855 break;
2856 }
2857
2858 snd_soc_component_update_bits(component, aif1_reg,
2859 WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV |
2860 WM8994_AIF1_FMT_MASK,
2861 aif1);
2862 snd_soc_component_update_bits(component, ms_reg, WM8994_AIF1_MSTR,
2863 ms);
2864 snd_soc_component_update_bits(component, dac_reg,
2865 WM8958_AIF1_LRCLK_INV, lrclk);
2866 snd_soc_component_update_bits(component, adc_reg,
2867 WM8958_AIF1_LRCLK_INV, lrclk);
2868
2869 return 0;
2870 }
2871
2872 static struct {
2873 int val, rate;
2874 } srs[] = {
2875 { 0, 8000 },
2876 { 1, 11025 },
2877 { 2, 12000 },
2878 { 3, 16000 },
2879 { 4, 22050 },
2880 { 5, 24000 },
2881 { 6, 32000 },
2882 { 7, 44100 },
2883 { 8, 48000 },
2884 { 9, 88200 },
2885 { 10, 96000 },
2886 };
2887
2888 static int fs_ratios[] = {
2889 64, 128, 192, 256, 384, 512, 768, 1024, 1408, 1536
2890 };
2891
2892 static int bclk_divs[] = {
2893 10, 15, 20, 30, 40, 50, 60, 80, 110, 120, 160, 220, 240, 320, 440, 480,
2894 640, 880, 960, 1280, 1760, 1920
2895 };
2896
2897 static int wm8994_hw_params(struct snd_pcm_substream *substream,
2898 struct snd_pcm_hw_params *params,
2899 struct snd_soc_dai *dai)
2900 {
2901 struct snd_soc_component *component = dai->component;
2902 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
2903 struct wm8994 *control = wm8994->wm8994;
2904 struct wm8994_pdata *pdata = &control->pdata;
2905 int aif1_reg;
2906 int aif2_reg;
2907 int bclk_reg;
2908 int lrclk_reg;
2909 int rate_reg;
2910 int aif1 = 0;
2911 int aif2 = 0;
2912 int bclk = 0;
2913 int lrclk = 0;
2914 int rate_val = 0;
2915 int id = dai->id - 1;
2916
2917 int i, cur_val, best_val, bclk_rate, best;
2918
2919 switch (dai->id) {
2920 case 1:
2921 aif1_reg = WM8994_AIF1_CONTROL_1;
2922 aif2_reg = WM8994_AIF1_CONTROL_2;
2923 bclk_reg = WM8994_AIF1_BCLK;
2924 rate_reg = WM8994_AIF1_RATE;
2925 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
2926 wm8994->lrclk_shared[0]) {
2927 lrclk_reg = WM8994_AIF1DAC_LRCLK;
2928 } else {
2929 lrclk_reg = WM8994_AIF1ADC_LRCLK;
2930 dev_dbg(component->dev, "AIF1 using split LRCLK\n");
2931 }
2932 break;
2933 case 2:
2934 aif1_reg = WM8994_AIF2_CONTROL_1;
2935 aif2_reg = WM8994_AIF2_CONTROL_2;
2936 bclk_reg = WM8994_AIF2_BCLK;
2937 rate_reg = WM8994_AIF2_RATE;
2938 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
2939 wm8994->lrclk_shared[1]) {
2940 lrclk_reg = WM8994_AIF2DAC_LRCLK;
2941 } else {
2942 lrclk_reg = WM8994_AIF2ADC_LRCLK;
2943 dev_dbg(component->dev, "AIF2 using split LRCLK\n");
2944 }
2945 break;
2946 default:
2947 return -EINVAL;
2948 }
2949
2950 bclk_rate = params_rate(params);
2951 switch (params_width(params)) {
2952 case 16:
2953 bclk_rate *= 16;
2954 break;
2955 case 20:
2956 bclk_rate *= 20;
2957 aif1 |= 0x20;
2958 break;
2959 case 24:
2960 bclk_rate *= 24;
2961 aif1 |= 0x40;
2962 break;
2963 case 32:
2964 bclk_rate *= 32;
2965 aif1 |= 0x60;
2966 break;
2967 default:
2968 return -EINVAL;
2969 }
2970
2971 wm8994->channels[id] = params_channels(params);
2972 if (pdata->max_channels_clocked[id] &&
2973 wm8994->channels[id] > pdata->max_channels_clocked[id]) {
2974 dev_dbg(dai->dev, "Constraining channels to %d from %d\n",
2975 pdata->max_channels_clocked[id], wm8994->channels[id]);
2976 wm8994->channels[id] = pdata->max_channels_clocked[id];
2977 }
2978
2979 switch (wm8994->channels[id]) {
2980 case 1:
2981 case 2:
2982 bclk_rate *= 2;
2983 break;
2984 default:
2985 bclk_rate *= 4;
2986 break;
2987 }
2988
2989 /* Try to find an appropriate sample rate; look for an exact match. */
2990 for (i = 0; i < ARRAY_SIZE(srs); i++)
2991 if (srs[i].rate == params_rate(params))
2992 break;
2993 if (i == ARRAY_SIZE(srs))
2994 return -EINVAL;
2995 rate_val |= srs[i].val << WM8994_AIF1_SR_SHIFT;
2996
2997 dev_dbg(dai->dev, "Sample rate is %dHz\n", srs[i].rate);
2998 dev_dbg(dai->dev, "AIF%dCLK is %dHz, target BCLK %dHz\n",
2999 dai->id, wm8994->aifclk[id], bclk_rate);
3000
3001 if (wm8994->channels[id] == 1 &&
3002 (snd_soc_component_read32(component, aif1_reg) & 0x18) == 0x18)
3003 aif2 |= WM8994_AIF1_MONO;
3004
3005 if (wm8994->aifclk[id] == 0) {
3006 dev_err(dai->dev, "AIF%dCLK not configured\n", dai->id);
3007 return -EINVAL;
3008 }
3009
3010 /* AIFCLK/fs ratio; look for a close match in either direction */
3011 best = 0;
3012 best_val = abs((fs_ratios[0] * params_rate(params))
3013 - wm8994->aifclk[id]);
3014 for (i = 1; i < ARRAY_SIZE(fs_ratios); i++) {
3015 cur_val = abs((fs_ratios[i] * params_rate(params))
3016 - wm8994->aifclk[id]);
3017 if (cur_val >= best_val)
3018 continue;
3019 best = i;
3020 best_val = cur_val;
3021 }
3022 dev_dbg(dai->dev, "Selected AIF%dCLK/fs = %d\n",
3023 dai->id, fs_ratios[best]);
3024 rate_val |= best;
3025
3026 /* We may not get quite the right frequency if using
3027 * approximate clocks so look for the closest match that is
3028 * higher than the target (we need to ensure that there enough
3029 * BCLKs to clock out the samples).
3030 */
3031 best = 0;
3032 for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
3033 cur_val = (wm8994->aifclk[id] * 10 / bclk_divs[i]) - bclk_rate;
3034 if (cur_val < 0) /* BCLK table is sorted */
3035 break;
3036 best = i;
3037 }
3038 bclk_rate = wm8994->aifclk[id] * 10 / bclk_divs[best];
3039 dev_dbg(dai->dev, "Using BCLK_DIV %d for actual BCLK %dHz\n",
3040 bclk_divs[best], bclk_rate);
3041 bclk |= best << WM8994_AIF1_BCLK_DIV_SHIFT;
3042
3043 lrclk = bclk_rate / params_rate(params);
3044 if (!lrclk) {
3045 dev_err(dai->dev, "Unable to generate LRCLK from %dHz BCLK\n",
3046 bclk_rate);
3047 return -EINVAL;
3048 }
3049 dev_dbg(dai->dev, "Using LRCLK rate %d for actual LRCLK %dHz\n",
3050 lrclk, bclk_rate / lrclk);
3051
3052 snd_soc_component_update_bits(component, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
3053 snd_soc_component_update_bits(component, aif2_reg, WM8994_AIF1_MONO, aif2);
3054 snd_soc_component_update_bits(component, bclk_reg, WM8994_AIF1_BCLK_DIV_MASK, bclk);
3055 snd_soc_component_update_bits(component, lrclk_reg, WM8994_AIF1DAC_RATE_MASK,
3056 lrclk);
3057 snd_soc_component_update_bits(component, rate_reg, WM8994_AIF1_SR_MASK |
3058 WM8994_AIF1CLK_RATE_MASK, rate_val);
3059
3060 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
3061 switch (dai->id) {
3062 case 1:
3063 wm8994->dac_rates[0] = params_rate(params);
3064 wm8994_set_retune_mobile(component, 0);
3065 wm8994_set_retune_mobile(component, 1);
3066 break;
3067 case 2:
3068 wm8994->dac_rates[1] = params_rate(params);
3069 wm8994_set_retune_mobile(component, 2);
3070 break;
3071 }
3072 }
3073
3074 return 0;
3075 }
3076
3077 static int wm8994_aif3_hw_params(struct snd_pcm_substream *substream,
3078 struct snd_pcm_hw_params *params,
3079 struct snd_soc_dai *dai)
3080 {
3081 struct snd_soc_component *component = dai->component;
3082 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
3083 struct wm8994 *control = wm8994->wm8994;
3084 int aif1_reg;
3085 int aif1 = 0;
3086
3087 switch (dai->id) {
3088 case 3:
3089 switch (control->type) {
3090 case WM1811:
3091 case WM8958:
3092 aif1_reg = WM8958_AIF3_CONTROL_1;
3093 break;
3094 default:
3095 return 0;
3096 }
3097 break;
3098 default:
3099 return 0;
3100 }
3101
3102 switch (params_width(params)) {
3103 case 16:
3104 break;
3105 case 20:
3106 aif1 |= 0x20;
3107 break;
3108 case 24:
3109 aif1 |= 0x40;
3110 break;
3111 case 32:
3112 aif1 |= 0x60;
3113 break;
3114 default:
3115 return -EINVAL;
3116 }
3117
3118 return snd_soc_component_update_bits(component, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
3119 }
3120
3121 static int wm8994_aif_mute(struct snd_soc_dai *codec_dai, int mute)
3122 {
3123 struct snd_soc_component *component = codec_dai->component;
3124 int mute_reg;
3125 int reg;
3126
3127 switch (codec_dai->id) {
3128 case 1:
3129 mute_reg = WM8994_AIF1_DAC1_FILTERS_1;
3130 break;
3131 case 2:
3132 mute_reg = WM8994_AIF2_DAC_FILTERS_1;
3133 break;
3134 default:
3135 return -EINVAL;
3136 }
3137
3138 if (mute)
3139 reg = WM8994_AIF1DAC1_MUTE;
3140 else
3141 reg = 0;
3142
3143 snd_soc_component_update_bits(component, mute_reg, WM8994_AIF1DAC1_MUTE, reg);
3144
3145 return 0;
3146 }
3147
3148 static int wm8994_set_tristate(struct snd_soc_dai *codec_dai, int tristate)
3149 {
3150 struct snd_soc_component *component = codec_dai->component;
3151 int reg, val, mask;
3152
3153 switch (codec_dai->id) {
3154 case 1:
3155 reg = WM8994_AIF1_MASTER_SLAVE;
3156 mask = WM8994_AIF1_TRI;
3157 break;
3158 case 2:
3159 reg = WM8994_AIF2_MASTER_SLAVE;
3160 mask = WM8994_AIF2_TRI;
3161 break;
3162 default:
3163 return -EINVAL;
3164 }
3165
3166 if (tristate)
3167 val = mask;
3168 else
3169 val = 0;
3170
3171 return snd_soc_component_update_bits(component, reg, mask, val);
3172 }
3173
3174 static int wm8994_aif2_probe(struct snd_soc_dai *dai)
3175 {
3176 struct snd_soc_component *component = dai->component;
3177
3178 /* Disable the pulls on the AIF if we're using it to save power. */
3179 snd_soc_component_update_bits(component, WM8994_GPIO_3,
3180 WM8994_GPN_PU | WM8994_GPN_PD, 0);
3181 snd_soc_component_update_bits(component, WM8994_GPIO_4,
3182 WM8994_GPN_PU | WM8994_GPN_PD, 0);
3183 snd_soc_component_update_bits(component, WM8994_GPIO_5,
3184 WM8994_GPN_PU | WM8994_GPN_PD, 0);
3185
3186 return 0;
3187 }
3188
3189 #define WM8994_RATES SNDRV_PCM_RATE_8000_96000
3190
3191 #define WM8994_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
3192 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
3193
3194 static const struct snd_soc_dai_ops wm8994_aif1_dai_ops = {
3195 .set_sysclk = wm8994_set_dai_sysclk,
3196 .set_fmt = wm8994_set_dai_fmt,
3197 .hw_params = wm8994_hw_params,
3198 .digital_mute = wm8994_aif_mute,
3199 .set_pll = wm8994_set_fll,
3200 .set_tristate = wm8994_set_tristate,
3201 };
3202
3203 static const struct snd_soc_dai_ops wm8994_aif2_dai_ops = {
3204 .set_sysclk = wm8994_set_dai_sysclk,
3205 .set_fmt = wm8994_set_dai_fmt,
3206 .hw_params = wm8994_hw_params,
3207 .digital_mute = wm8994_aif_mute,
3208 .set_pll = wm8994_set_fll,
3209 .set_tristate = wm8994_set_tristate,
3210 };
3211
3212 static const struct snd_soc_dai_ops wm8994_aif3_dai_ops = {
3213 .hw_params = wm8994_aif3_hw_params,
3214 };
3215
3216 static struct snd_soc_dai_driver wm8994_dai[] = {
3217 {
3218 .name = "wm8994-aif1",
3219 .id = 1,
3220 .playback = {
3221 .stream_name = "AIF1 Playback",
3222 .channels_min = 1,
3223 .channels_max = 2,
3224 .rates = WM8994_RATES,
3225 .formats = WM8994_FORMATS,
3226 .sig_bits = 24,
3227 },
3228 .capture = {
3229 .stream_name = "AIF1 Capture",
3230 .channels_min = 1,
3231 .channels_max = 2,
3232 .rates = WM8994_RATES,
3233 .formats = WM8994_FORMATS,
3234 .sig_bits = 24,
3235 },
3236 .ops = &wm8994_aif1_dai_ops,
3237 },
3238 {
3239 .name = "wm8994-aif2",
3240 .id = 2,
3241 .playback = {
3242 .stream_name = "AIF2 Playback",
3243 .channels_min = 1,
3244 .channels_max = 2,
3245 .rates = WM8994_RATES,
3246 .formats = WM8994_FORMATS,
3247 .sig_bits = 24,
3248 },
3249 .capture = {
3250 .stream_name = "AIF2 Capture",
3251 .channels_min = 1,
3252 .channels_max = 2,
3253 .rates = WM8994_RATES,
3254 .formats = WM8994_FORMATS,
3255 .sig_bits = 24,
3256 },
3257 .probe = wm8994_aif2_probe,
3258 .ops = &wm8994_aif2_dai_ops,
3259 },
3260 {
3261 .name = "wm8994-aif3",
3262 .id = 3,
3263 .playback = {
3264 .stream_name = "AIF3 Playback",
3265 .channels_min = 1,
3266 .channels_max = 2,
3267 .rates = WM8994_RATES,
3268 .formats = WM8994_FORMATS,
3269 .sig_bits = 24,
3270 },
3271 .capture = {
3272 .stream_name = "AIF3 Capture",
3273 .channels_min = 1,
3274 .channels_max = 2,
3275 .rates = WM8994_RATES,
3276 .formats = WM8994_FORMATS,
3277 .sig_bits = 24,
3278 },
3279 .ops = &wm8994_aif3_dai_ops,
3280 }
3281 };
3282
3283 #ifdef CONFIG_PM
3284 static int wm8994_component_suspend(struct snd_soc_component *component)
3285 {
3286 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
3287 int i, ret;
3288
3289 for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) {
3290 memcpy(&wm8994->fll_suspend[i], &wm8994->fll[i],
3291 sizeof(struct wm8994_fll_config));
3292 ret = _wm8994_set_fll(component, i + 1, 0, 0, 0);
3293 if (ret < 0)
3294 dev_warn(component->dev, "Failed to stop FLL%d: %d\n",
3295 i + 1, ret);
3296 }
3297
3298 snd_soc_component_force_bias_level(component, SND_SOC_BIAS_OFF);
3299
3300 return 0;
3301 }
3302
3303 static int wm8994_component_resume(struct snd_soc_component *component)
3304 {
3305 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
3306 int i, ret;
3307
3308 for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) {
3309 if (!wm8994->fll_suspend[i].out)
3310 continue;
3311
3312 ret = _wm8994_set_fll(component, i + 1,
3313 wm8994->fll_suspend[i].src,
3314 wm8994->fll_suspend[i].in,
3315 wm8994->fll_suspend[i].out);
3316 if (ret < 0)
3317 dev_warn(component->dev, "Failed to restore FLL%d: %d\n",
3318 i + 1, ret);
3319 }
3320
3321 return 0;
3322 }
3323 #else
3324 #define wm8994_component_suspend NULL
3325 #define wm8994_component_resume NULL
3326 #endif
3327
3328 static void wm8994_handle_retune_mobile_pdata(struct wm8994_priv *wm8994)
3329 {
3330 struct snd_soc_component *component = wm8994->hubs.component;
3331 struct wm8994 *control = wm8994->wm8994;
3332 struct wm8994_pdata *pdata = &control->pdata;
3333 struct snd_kcontrol_new controls[] = {
3334 SOC_ENUM_EXT("AIF1.1 EQ Mode",
3335 wm8994->retune_mobile_enum,
3336 wm8994_get_retune_mobile_enum,
3337 wm8994_put_retune_mobile_enum),
3338 SOC_ENUM_EXT("AIF1.2 EQ Mode",
3339 wm8994->retune_mobile_enum,
3340 wm8994_get_retune_mobile_enum,
3341 wm8994_put_retune_mobile_enum),
3342 SOC_ENUM_EXT("AIF2 EQ Mode",
3343 wm8994->retune_mobile_enum,
3344 wm8994_get_retune_mobile_enum,
3345 wm8994_put_retune_mobile_enum),
3346 };
3347 int ret, i, j;
3348 const char **t;
3349
3350 /* We need an array of texts for the enum API but the number
3351 * of texts is likely to be less than the number of
3352 * configurations due to the sample rate dependency of the
3353 * configurations. */
3354 wm8994->num_retune_mobile_texts = 0;
3355 wm8994->retune_mobile_texts = NULL;
3356 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
3357 for (j = 0; j < wm8994->num_retune_mobile_texts; j++) {
3358 if (strcmp(pdata->retune_mobile_cfgs[i].name,
3359 wm8994->retune_mobile_texts[j]) == 0)
3360 break;
3361 }
3362
3363 if (j != wm8994->num_retune_mobile_texts)
3364 continue;
3365
3366 /* Expand the array... */
3367 t = krealloc(wm8994->retune_mobile_texts,
3368 sizeof(char *) *
3369 (wm8994->num_retune_mobile_texts + 1),
3370 GFP_KERNEL);
3371 if (t == NULL)
3372 continue;
3373
3374 /* ...store the new entry... */
3375 t[wm8994->num_retune_mobile_texts] =
3376 pdata->retune_mobile_cfgs[i].name;
3377
3378 /* ...and remember the new version. */
3379 wm8994->num_retune_mobile_texts++;
3380 wm8994->retune_mobile_texts = t;
3381 }
3382
3383 dev_dbg(component->dev, "Allocated %d unique ReTune Mobile names\n",
3384 wm8994->num_retune_mobile_texts);
3385
3386 wm8994->retune_mobile_enum.items = wm8994->num_retune_mobile_texts;
3387 wm8994->retune_mobile_enum.texts = wm8994->retune_mobile_texts;
3388
3389 ret = snd_soc_add_component_controls(wm8994->hubs.component, controls,
3390 ARRAY_SIZE(controls));
3391 if (ret != 0)
3392 dev_err(wm8994->hubs.component->dev,
3393 "Failed to add ReTune Mobile controls: %d\n", ret);
3394 }
3395
3396 static void wm8994_handle_pdata(struct wm8994_priv *wm8994)
3397 {
3398 struct snd_soc_component *component = wm8994->hubs.component;
3399 struct wm8994 *control = wm8994->wm8994;
3400 struct wm8994_pdata *pdata = &control->pdata;
3401 int ret, i;
3402
3403 if (!pdata)
3404 return;
3405
3406 wm_hubs_handle_analogue_pdata(component, pdata->lineout1_diff,
3407 pdata->lineout2_diff,
3408 pdata->lineout1fb,
3409 pdata->lineout2fb,
3410 pdata->jd_scthr,
3411 pdata->jd_thr,
3412 pdata->micb1_delay,
3413 pdata->micb2_delay,
3414 pdata->micbias1_lvl,
3415 pdata->micbias2_lvl);
3416
3417 dev_dbg(component->dev, "%d DRC configurations\n", pdata->num_drc_cfgs);
3418
3419 if (pdata->num_drc_cfgs) {
3420 struct snd_kcontrol_new controls[] = {
3421 SOC_ENUM_EXT("AIF1DRC1 Mode", wm8994->drc_enum,
3422 wm8994_get_drc_enum, wm8994_put_drc_enum),
3423 SOC_ENUM_EXT("AIF1DRC2 Mode", wm8994->drc_enum,
3424 wm8994_get_drc_enum, wm8994_put_drc_enum),
3425 SOC_ENUM_EXT("AIF2DRC Mode", wm8994->drc_enum,
3426 wm8994_get_drc_enum, wm8994_put_drc_enum),
3427 };
3428
3429 /* We need an array of texts for the enum API */
3430 wm8994->drc_texts = devm_kcalloc(wm8994->hubs.component->dev,
3431 pdata->num_drc_cfgs, sizeof(char *), GFP_KERNEL);
3432 if (!wm8994->drc_texts)
3433 return;
3434
3435 for (i = 0; i < pdata->num_drc_cfgs; i++)
3436 wm8994->drc_texts[i] = pdata->drc_cfgs[i].name;
3437
3438 wm8994->drc_enum.items = pdata->num_drc_cfgs;
3439 wm8994->drc_enum.texts = wm8994->drc_texts;
3440
3441 ret = snd_soc_add_component_controls(wm8994->hubs.component, controls,
3442 ARRAY_SIZE(controls));
3443 for (i = 0; i < WM8994_NUM_DRC; i++)
3444 wm8994_set_drc(component, i);
3445 } else {
3446 ret = snd_soc_add_component_controls(wm8994->hubs.component,
3447 wm8994_drc_controls,
3448 ARRAY_SIZE(wm8994_drc_controls));
3449 }
3450
3451 if (ret != 0)
3452 dev_err(wm8994->hubs.component->dev,
3453 "Failed to add DRC mode controls: %d\n", ret);
3454
3455
3456 dev_dbg(component->dev, "%d ReTune Mobile configurations\n",
3457 pdata->num_retune_mobile_cfgs);
3458
3459 if (pdata->num_retune_mobile_cfgs)
3460 wm8994_handle_retune_mobile_pdata(wm8994);
3461 else
3462 snd_soc_add_component_controls(wm8994->hubs.component, wm8994_eq_controls,
3463 ARRAY_SIZE(wm8994_eq_controls));
3464
3465 for (i = 0; i < ARRAY_SIZE(pdata->micbias); i++) {
3466 if (pdata->micbias[i]) {
3467 snd_soc_component_write(component, WM8958_MICBIAS1 + i,
3468 pdata->micbias[i] & 0xffff);
3469 }
3470 }
3471 }
3472
3473 /**
3474 * wm8994_mic_detect - Enable microphone detection via the WM8994 IRQ
3475 *
3476 * @component: WM8994 component
3477 * @jack: jack to report detection events on
3478 * @micbias: microphone bias to detect on
3479 *
3480 * Enable microphone detection via IRQ on the WM8994. If GPIOs are
3481 * being used to bring out signals to the processor then only platform
3482 * data configuration is needed for WM8994 and processor GPIOs should
3483 * be configured using snd_soc_jack_add_gpios() instead.
3484 *
3485 * Configuration of detection levels is available via the micbias1_lvl
3486 * and micbias2_lvl platform data members.
3487 */
3488 int wm8994_mic_detect(struct snd_soc_component *component, struct snd_soc_jack *jack,
3489 int micbias)
3490 {
3491 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
3492 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
3493 struct wm8994_micdet *micdet;
3494 struct wm8994 *control = wm8994->wm8994;
3495 int reg, ret;
3496
3497 if (control->type != WM8994) {
3498 dev_warn(component->dev, "Not a WM8994\n");
3499 return -EINVAL;
3500 }
3501
3502 switch (micbias) {
3503 case 1:
3504 micdet = &wm8994->micdet[0];
3505 if (jack)
3506 ret = snd_soc_dapm_force_enable_pin(dapm, "MICBIAS1");
3507 else
3508 ret = snd_soc_dapm_disable_pin(dapm, "MICBIAS1");
3509 break;
3510 case 2:
3511 micdet = &wm8994->micdet[1];
3512 if (jack)
3513 ret = snd_soc_dapm_force_enable_pin(dapm, "MICBIAS1");
3514 else
3515 ret = snd_soc_dapm_disable_pin(dapm, "MICBIAS1");
3516 break;
3517 default:
3518 dev_warn(component->dev, "Invalid MICBIAS %d\n", micbias);
3519 return -EINVAL;
3520 }
3521
3522 if (ret != 0)
3523 dev_warn(component->dev, "Failed to configure MICBIAS%d: %d\n",
3524 micbias, ret);
3525
3526 dev_dbg(component->dev, "Configuring microphone detection on %d %p\n",
3527 micbias, jack);
3528
3529 /* Store the configuration */
3530 micdet->jack = jack;
3531 micdet->detecting = true;
3532
3533 /* If either of the jacks is set up then enable detection */
3534 if (wm8994->micdet[0].jack || wm8994->micdet[1].jack)
3535 reg = WM8994_MICD_ENA;
3536 else
3537 reg = 0;
3538
3539 snd_soc_component_update_bits(component, WM8994_MICBIAS, WM8994_MICD_ENA, reg);
3540
3541 /* enable MICDET and MICSHRT deboune */
3542 snd_soc_component_update_bits(component, WM8994_IRQ_DEBOUNCE,
3543 WM8994_MIC1_DET_DB_MASK | WM8994_MIC1_SHRT_DB_MASK |
3544 WM8994_MIC2_DET_DB_MASK | WM8994_MIC2_SHRT_DB_MASK,
3545 WM8994_MIC1_DET_DB | WM8994_MIC1_SHRT_DB);
3546
3547 snd_soc_dapm_sync(dapm);
3548
3549 return 0;
3550 }
3551 EXPORT_SYMBOL_GPL(wm8994_mic_detect);
3552
3553 static void wm8994_mic_work(struct work_struct *work)
3554 {
3555 struct wm8994_priv *priv = container_of(work,
3556 struct wm8994_priv,
3557 mic_work.work);
3558 struct regmap *regmap = priv->wm8994->regmap;
3559 struct device *dev = priv->wm8994->dev;
3560 unsigned int reg;
3561 int ret;
3562 int report;
3563
3564 pm_runtime_get_sync(dev);
3565
3566 ret = regmap_read(regmap, WM8994_INTERRUPT_RAW_STATUS_2, &reg);
3567 if (ret < 0) {
3568 dev_err(dev, "Failed to read microphone status: %d\n",
3569 ret);
3570 pm_runtime_put(dev);
3571 return;
3572 }
3573
3574 dev_dbg(dev, "Microphone status: %x\n", reg);
3575
3576 report = 0;
3577 if (reg & WM8994_MIC1_DET_STS) {
3578 if (priv->micdet[0].detecting)
3579 report = SND_JACK_HEADSET;
3580 }
3581 if (reg & WM8994_MIC1_SHRT_STS) {
3582 if (priv->micdet[0].detecting)
3583 report = SND_JACK_HEADPHONE;
3584 else
3585 report |= SND_JACK_BTN_0;
3586 }
3587 if (report)
3588 priv->micdet[0].detecting = false;
3589 else
3590 priv->micdet[0].detecting = true;
3591
3592 snd_soc_jack_report(priv->micdet[0].jack, report,
3593 SND_JACK_HEADSET | SND_JACK_BTN_0);
3594
3595 report = 0;
3596 if (reg & WM8994_MIC2_DET_STS) {
3597 if (priv->micdet[1].detecting)
3598 report = SND_JACK_HEADSET;
3599 }
3600 if (reg & WM8994_MIC2_SHRT_STS) {
3601 if (priv->micdet[1].detecting)
3602 report = SND_JACK_HEADPHONE;
3603 else
3604 report |= SND_JACK_BTN_0;
3605 }
3606 if (report)
3607 priv->micdet[1].detecting = false;
3608 else
3609 priv->micdet[1].detecting = true;
3610
3611 snd_soc_jack_report(priv->micdet[1].jack, report,
3612 SND_JACK_HEADSET | SND_JACK_BTN_0);
3613
3614 pm_runtime_put(dev);
3615 }
3616
3617 static irqreturn_t wm8994_mic_irq(int irq, void *data)
3618 {
3619 struct wm8994_priv *priv = data;
3620 struct snd_soc_component *component = priv->hubs.component;
3621
3622 #ifndef CONFIG_SND_SOC_WM8994_MODULE
3623 trace_snd_soc_jack_irq(dev_name(component->dev));
3624 #endif
3625
3626 pm_wakeup_event(component->dev, 300);
3627
3628 queue_delayed_work(system_power_efficient_wq,
3629 &priv->mic_work, msecs_to_jiffies(250));
3630
3631 return IRQ_HANDLED;
3632 }
3633
3634 /* Should be called with accdet_lock held */
3635 static void wm1811_micd_stop(struct snd_soc_component *component)
3636 {
3637 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
3638 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
3639
3640 if (!wm8994->jackdet)
3641 return;
3642
3643 snd_soc_component_update_bits(component, WM8958_MIC_DETECT_1, WM8958_MICD_ENA, 0);
3644
3645 wm1811_jackdet_set_mode(component, WM1811_JACKDET_MODE_JACK);
3646
3647 if (wm8994->wm8994->pdata.jd_ext_cap)
3648 snd_soc_dapm_disable_pin(dapm, "MICBIAS2");
3649 }
3650
3651 static void wm8958_button_det(struct snd_soc_component *component, u16 status)
3652 {
3653 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
3654 int report;
3655
3656 report = 0;
3657 if (status & 0x4)
3658 report |= SND_JACK_BTN_0;
3659
3660 if (status & 0x8)
3661 report |= SND_JACK_BTN_1;
3662
3663 if (status & 0x10)
3664 report |= SND_JACK_BTN_2;
3665
3666 if (status & 0x20)
3667 report |= SND_JACK_BTN_3;
3668
3669 if (status & 0x40)
3670 report |= SND_JACK_BTN_4;
3671
3672 if (status & 0x80)
3673 report |= SND_JACK_BTN_5;
3674
3675 snd_soc_jack_report(wm8994->micdet[0].jack, report,
3676 wm8994->btn_mask);
3677 }
3678
3679 static void wm8958_open_circuit_work(struct work_struct *work)
3680 {
3681 struct wm8994_priv *wm8994 = container_of(work,
3682 struct wm8994_priv,
3683 open_circuit_work.work);
3684 struct device *dev = wm8994->wm8994->dev;
3685
3686 mutex_lock(&wm8994->accdet_lock);
3687
3688 wm1811_micd_stop(wm8994->hubs.component);
3689
3690 dev_dbg(dev, "Reporting open circuit\n");
3691
3692 wm8994->jack_mic = false;
3693 wm8994->mic_detecting = true;
3694
3695 wm8958_micd_set_rate(wm8994->hubs.component);
3696
3697 snd_soc_jack_report(wm8994->micdet[0].jack, 0,
3698 wm8994->btn_mask |
3699 SND_JACK_HEADSET);
3700
3701 mutex_unlock(&wm8994->accdet_lock);
3702 }
3703
3704 static void wm8958_mic_id(void *data, u16 status)
3705 {
3706 struct snd_soc_component *component = data;
3707 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
3708
3709 /* Either nothing present or just starting detection */
3710 if (!(status & WM8958_MICD_STS)) {
3711 /* If nothing present then clear our statuses */
3712 dev_dbg(component->dev, "Detected open circuit\n");
3713
3714 queue_delayed_work(system_power_efficient_wq,
3715 &wm8994->open_circuit_work,
3716 msecs_to_jiffies(2500));
3717 return;
3718 }
3719
3720 /* If the measurement is showing a high impedence we've got a
3721 * microphone.
3722 */
3723 if (status & 0x600) {
3724 dev_dbg(component->dev, "Detected microphone\n");
3725
3726 wm8994->mic_detecting = false;
3727 wm8994->jack_mic = true;
3728
3729 wm8958_micd_set_rate(component);
3730
3731 snd_soc_jack_report(wm8994->micdet[0].jack, SND_JACK_HEADSET,
3732 SND_JACK_HEADSET);
3733 }
3734
3735
3736 if (status & 0xfc) {
3737 dev_dbg(component->dev, "Detected headphone\n");
3738 wm8994->mic_detecting = false;
3739
3740 wm8958_micd_set_rate(component);
3741
3742 /* If we have jackdet that will detect removal */
3743 wm1811_micd_stop(component);
3744
3745 snd_soc_jack_report(wm8994->micdet[0].jack, SND_JACK_HEADPHONE,
3746 SND_JACK_HEADSET);
3747 }
3748 }
3749
3750 /* Deferred mic detection to allow for extra settling time */
3751 static void wm1811_mic_work(struct work_struct *work)
3752 {
3753 struct wm8994_priv *wm8994 = container_of(work, struct wm8994_priv,
3754 mic_work.work);
3755 struct wm8994 *control = wm8994->wm8994;
3756 struct snd_soc_component *component = wm8994->hubs.component;
3757 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
3758
3759 pm_runtime_get_sync(component->dev);
3760
3761 /* If required for an external cap force MICBIAS on */
3762 if (control->pdata.jd_ext_cap) {
3763 snd_soc_dapm_force_enable_pin(dapm, "MICBIAS2");
3764 snd_soc_dapm_sync(dapm);
3765 }
3766
3767 mutex_lock(&wm8994->accdet_lock);
3768
3769 dev_dbg(component->dev, "Starting mic detection\n");
3770
3771 /* Use a user-supplied callback if we have one */
3772 if (wm8994->micd_cb) {
3773 wm8994->micd_cb(wm8994->micd_cb_data);
3774 } else {
3775 /*
3776 * Start off measument of microphone impedence to find out
3777 * what's actually there.
3778 */
3779 wm8994->mic_detecting = true;
3780 wm1811_jackdet_set_mode(component, WM1811_JACKDET_MODE_MIC);
3781
3782 snd_soc_component_update_bits(component, WM8958_MIC_DETECT_1,
3783 WM8958_MICD_ENA, WM8958_MICD_ENA);
3784 }
3785
3786 mutex_unlock(&wm8994->accdet_lock);
3787
3788 pm_runtime_put(component->dev);
3789 }
3790
3791 static irqreturn_t wm1811_jackdet_irq(int irq, void *data)
3792 {
3793 struct wm8994_priv *wm8994 = data;
3794 struct wm8994 *control = wm8994->wm8994;
3795 struct snd_soc_component *component = wm8994->hubs.component;
3796 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
3797 int reg, delay;
3798 bool present;
3799
3800 pm_runtime_get_sync(component->dev);
3801
3802 cancel_delayed_work_sync(&wm8994->mic_complete_work);
3803
3804 mutex_lock(&wm8994->accdet_lock);
3805
3806 reg = snd_soc_component_read32(component, WM1811_JACKDET_CTRL);
3807 if (reg < 0) {
3808 dev_err(component->dev, "Failed to read jack status: %d\n", reg);
3809 mutex_unlock(&wm8994->accdet_lock);
3810 pm_runtime_put(component->dev);
3811 return IRQ_NONE;
3812 }
3813
3814 dev_dbg(component->dev, "JACKDET %x\n", reg);
3815
3816 present = reg & WM1811_JACKDET_LVL;
3817
3818 if (present) {
3819 dev_dbg(component->dev, "Jack detected\n");
3820
3821 wm8958_micd_set_rate(component);
3822
3823 snd_soc_component_update_bits(component, WM8958_MICBIAS2,
3824 WM8958_MICB2_DISCH, 0);
3825
3826 /* Disable debounce while inserted */
3827 snd_soc_component_update_bits(component, WM1811_JACKDET_CTRL,
3828 WM1811_JACKDET_DB, 0);
3829
3830 delay = control->pdata.micdet_delay;
3831 queue_delayed_work(system_power_efficient_wq,
3832 &wm8994->mic_work,
3833 msecs_to_jiffies(delay));
3834 } else {
3835 dev_dbg(component->dev, "Jack not detected\n");
3836
3837 cancel_delayed_work_sync(&wm8994->mic_work);
3838
3839 snd_soc_component_update_bits(component, WM8958_MICBIAS2,
3840 WM8958_MICB2_DISCH, WM8958_MICB2_DISCH);
3841
3842 /* Enable debounce while removed */
3843 snd_soc_component_update_bits(component, WM1811_JACKDET_CTRL,
3844 WM1811_JACKDET_DB, WM1811_JACKDET_DB);
3845
3846 wm8994->mic_detecting = false;
3847 wm8994->jack_mic = false;
3848 snd_soc_component_update_bits(component, WM8958_MIC_DETECT_1,
3849 WM8958_MICD_ENA, 0);
3850 wm1811_jackdet_set_mode(component, WM1811_JACKDET_MODE_JACK);
3851 }
3852
3853 mutex_unlock(&wm8994->accdet_lock);
3854
3855 /* Turn off MICBIAS if it was on for an external cap */
3856 if (control->pdata.jd_ext_cap && !present)
3857 snd_soc_dapm_disable_pin(dapm, "MICBIAS2");
3858
3859 if (present)
3860 snd_soc_jack_report(wm8994->micdet[0].jack,
3861 SND_JACK_MECHANICAL, SND_JACK_MECHANICAL);
3862 else
3863 snd_soc_jack_report(wm8994->micdet[0].jack, 0,
3864 SND_JACK_MECHANICAL | SND_JACK_HEADSET |
3865 wm8994->btn_mask);
3866
3867 /* Since we only report deltas force an update, ensures we
3868 * avoid bootstrapping issues with the core. */
3869 snd_soc_jack_report(wm8994->micdet[0].jack, 0, 0);
3870
3871 pm_runtime_put(component->dev);
3872 return IRQ_HANDLED;
3873 }
3874
3875 static void wm1811_jackdet_bootstrap(struct work_struct *work)
3876 {
3877 struct wm8994_priv *wm8994 = container_of(work,
3878 struct wm8994_priv,
3879 jackdet_bootstrap.work);
3880 wm1811_jackdet_irq(0, wm8994);
3881 }
3882
3883 /**
3884 * wm8958_mic_detect - Enable microphone detection via the WM8958 IRQ
3885 *
3886 * @component: WM8958 component
3887 * @jack: jack to report detection events on
3888 *
3889 * Enable microphone detection functionality for the WM8958. By
3890 * default simple detection which supports the detection of up to 6
3891 * buttons plus video and microphone functionality is supported.
3892 *
3893 * The WM8958 has an advanced jack detection facility which is able to
3894 * support complex accessory detection, especially when used in
3895 * conjunction with external circuitry. In order to provide maximum
3896 * flexiblity a callback is provided which allows a completely custom
3897 * detection algorithm.
3898 */
3899 int wm8958_mic_detect(struct snd_soc_component *component, struct snd_soc_jack *jack,
3900 wm1811_micdet_cb det_cb, void *det_cb_data,
3901 wm1811_mic_id_cb id_cb, void *id_cb_data)
3902 {
3903 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
3904 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
3905 struct wm8994 *control = wm8994->wm8994;
3906 u16 micd_lvl_sel;
3907
3908 switch (control->type) {
3909 case WM1811:
3910 case WM8958:
3911 break;
3912 default:
3913 return -EINVAL;
3914 }
3915
3916 if (jack) {
3917 snd_soc_dapm_force_enable_pin(dapm, "CLK_SYS");
3918 snd_soc_dapm_sync(dapm);
3919
3920 wm8994->micdet[0].jack = jack;
3921
3922 if (det_cb) {
3923 wm8994->micd_cb = det_cb;
3924 wm8994->micd_cb_data = det_cb_data;
3925 } else {
3926 wm8994->mic_detecting = true;
3927 wm8994->jack_mic = false;
3928 }
3929
3930 if (id_cb) {
3931 wm8994->mic_id_cb = id_cb;
3932 wm8994->mic_id_cb_data = id_cb_data;
3933 } else {
3934 wm8994->mic_id_cb = wm8958_mic_id;
3935 wm8994->mic_id_cb_data = component;
3936 }
3937
3938 wm8958_micd_set_rate(component);
3939
3940 /* Detect microphones and short circuits by default */
3941 if (control->pdata.micd_lvl_sel)
3942 micd_lvl_sel = control->pdata.micd_lvl_sel;
3943 else
3944 micd_lvl_sel = 0x41;
3945
3946 wm8994->btn_mask = SND_JACK_BTN_0 | SND_JACK_BTN_1 |
3947 SND_JACK_BTN_2 | SND_JACK_BTN_3 |
3948 SND_JACK_BTN_4 | SND_JACK_BTN_5;
3949
3950 snd_soc_component_update_bits(component, WM8958_MIC_DETECT_2,
3951 WM8958_MICD_LVL_SEL_MASK, micd_lvl_sel);
3952
3953 WARN_ON(snd_soc_component_get_bias_level(component) > SND_SOC_BIAS_STANDBY);
3954
3955 /*
3956 * If we can use jack detection start off with that,
3957 * otherwise jump straight to microphone detection.
3958 */
3959 if (wm8994->jackdet) {
3960 /* Disable debounce for the initial detect */
3961 snd_soc_component_update_bits(component, WM1811_JACKDET_CTRL,
3962 WM1811_JACKDET_DB, 0);
3963
3964 snd_soc_component_update_bits(component, WM8958_MICBIAS2,
3965 WM8958_MICB2_DISCH,
3966 WM8958_MICB2_DISCH);
3967 snd_soc_component_update_bits(component, WM8994_LDO_1,
3968 WM8994_LDO1_DISCH, 0);
3969 wm1811_jackdet_set_mode(component,
3970 WM1811_JACKDET_MODE_JACK);
3971 } else {
3972 snd_soc_component_update_bits(component, WM8958_MIC_DETECT_1,
3973 WM8958_MICD_ENA, WM8958_MICD_ENA);
3974 }
3975
3976 } else {
3977 snd_soc_component_update_bits(component, WM8958_MIC_DETECT_1,
3978 WM8958_MICD_ENA, 0);
3979 wm1811_jackdet_set_mode(component, WM1811_JACKDET_MODE_NONE);
3980 snd_soc_dapm_disable_pin(dapm, "CLK_SYS");
3981 snd_soc_dapm_sync(dapm);
3982 }
3983
3984 return 0;
3985 }
3986 EXPORT_SYMBOL_GPL(wm8958_mic_detect);
3987
3988 static void wm8958_mic_work(struct work_struct *work)
3989 {
3990 struct wm8994_priv *wm8994 = container_of(work,
3991 struct wm8994_priv,
3992 mic_complete_work.work);
3993 struct snd_soc_component *component = wm8994->hubs.component;
3994
3995 pm_runtime_get_sync(component->dev);
3996
3997 mutex_lock(&wm8994->accdet_lock);
3998
3999 wm8994->mic_id_cb(wm8994->mic_id_cb_data, wm8994->mic_status);
4000
4001 mutex_unlock(&wm8994->accdet_lock);
4002
4003 pm_runtime_put(component->dev);
4004 }
4005
4006 static irqreturn_t wm8958_mic_irq(int irq, void *data)
4007 {
4008 struct wm8994_priv *wm8994 = data;
4009 struct snd_soc_component *component = wm8994->hubs.component;
4010 int reg, count, ret, id_delay;
4011
4012 /*
4013 * Jack detection may have detected a removal simulataneously
4014 * with an update of the MICDET status; if so it will have
4015 * stopped detection and we can ignore this interrupt.
4016 */
4017 if (!(snd_soc_component_read32(component, WM8958_MIC_DETECT_1) & WM8958_MICD_ENA))
4018 return IRQ_HANDLED;
4019
4020 cancel_delayed_work_sync(&wm8994->mic_complete_work);
4021 cancel_delayed_work_sync(&wm8994->open_circuit_work);
4022
4023 pm_runtime_get_sync(component->dev);
4024
4025 /* We may occasionally read a detection without an impedence
4026 * range being provided - if that happens loop again.
4027 */
4028 count = 10;
4029 do {
4030 reg = snd_soc_component_read32(component, WM8958_MIC_DETECT_3);
4031 if (reg < 0) {
4032 dev_err(component->dev,
4033 "Failed to read mic detect status: %d\n",
4034 reg);
4035 pm_runtime_put(component->dev);
4036 return IRQ_NONE;
4037 }
4038
4039 if (!(reg & WM8958_MICD_VALID)) {
4040 dev_dbg(component->dev, "Mic detect data not valid\n");
4041 goto out;
4042 }
4043
4044 if (!(reg & WM8958_MICD_STS) || (reg & WM8958_MICD_LVL_MASK))
4045 break;
4046
4047 msleep(1);
4048 } while (count--);
4049
4050 if (count == 0)
4051 dev_warn(component->dev, "No impedance range reported for jack\n");
4052
4053 #ifndef CONFIG_SND_SOC_WM8994_MODULE
4054 trace_snd_soc_jack_irq(dev_name(component->dev));
4055 #endif
4056
4057 /* Avoid a transient report when the accessory is being removed */
4058 if (wm8994->jackdet) {
4059 ret = snd_soc_component_read32(component, WM1811_JACKDET_CTRL);
4060 if (ret < 0) {
4061 dev_err(component->dev, "Failed to read jack status: %d\n",
4062 ret);
4063 } else if (!(ret & WM1811_JACKDET_LVL)) {
4064 dev_dbg(component->dev, "Ignoring removed jack\n");
4065 goto out;
4066 }
4067 } else if (!(reg & WM8958_MICD_STS)) {
4068 snd_soc_jack_report(wm8994->micdet[0].jack, 0,
4069 SND_JACK_MECHANICAL | SND_JACK_HEADSET |
4070 wm8994->btn_mask);
4071 wm8994->mic_detecting = true;
4072 goto out;
4073 }
4074
4075 wm8994->mic_status = reg;
4076 id_delay = wm8994->wm8994->pdata.mic_id_delay;
4077
4078 if (wm8994->mic_detecting)
4079 queue_delayed_work(system_power_efficient_wq,
4080 &wm8994->mic_complete_work,
4081 msecs_to_jiffies(id_delay));
4082 else
4083 wm8958_button_det(component, reg);
4084
4085 out:
4086 pm_runtime_put(component->dev);
4087 return IRQ_HANDLED;
4088 }
4089
4090 static irqreturn_t wm8994_fifo_error(int irq, void *data)
4091 {
4092 struct snd_soc_component *component = data;
4093
4094 dev_err(component->dev, "FIFO error\n");
4095
4096 return IRQ_HANDLED;
4097 }
4098
4099 static irqreturn_t wm8994_temp_warn(int irq, void *data)
4100 {
4101 struct snd_soc_component *component = data;
4102
4103 dev_err(component->dev, "Thermal warning\n");
4104
4105 return IRQ_HANDLED;
4106 }
4107
4108 static irqreturn_t wm8994_temp_shut(int irq, void *data)
4109 {
4110 struct snd_soc_component *component = data;
4111
4112 dev_crit(component->dev, "Thermal shutdown\n");
4113
4114 return IRQ_HANDLED;
4115 }
4116
4117 static int wm8994_component_probe(struct snd_soc_component *component)
4118 {
4119 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
4120 struct wm8994 *control = dev_get_drvdata(component->dev->parent);
4121 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
4122 unsigned int reg;
4123 int ret, i;
4124
4125 snd_soc_component_init_regmap(component, control->regmap);
4126
4127 wm8994->hubs.component = component;
4128
4129 mutex_init(&wm8994->accdet_lock);
4130 INIT_DELAYED_WORK(&wm8994->jackdet_bootstrap,
4131 wm1811_jackdet_bootstrap);
4132 INIT_DELAYED_WORK(&wm8994->open_circuit_work,
4133 wm8958_open_circuit_work);
4134
4135 switch (control->type) {
4136 case WM8994:
4137 INIT_DELAYED_WORK(&wm8994->mic_work, wm8994_mic_work);
4138 break;
4139 case WM1811:
4140 INIT_DELAYED_WORK(&wm8994->mic_work, wm1811_mic_work);
4141 break;
4142 default:
4143 break;
4144 }
4145
4146 INIT_DELAYED_WORK(&wm8994->mic_complete_work, wm8958_mic_work);
4147
4148 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
4149 init_completion(&wm8994->fll_locked[i]);
4150
4151 wm8994->micdet_irq = control->pdata.micdet_irq;
4152
4153 /* By default use idle_bias_off, will override for WM8994 */
4154 dapm->idle_bias_off = 1;
4155
4156 /* Set revision-specific configuration */
4157 switch (control->type) {
4158 case WM8994:
4159 /* Single ended line outputs should have VMID on. */
4160 if (!control->pdata.lineout1_diff ||
4161 !control->pdata.lineout2_diff)
4162 dapm->idle_bias_off = 0;
4163
4164 switch (control->revision) {
4165 case 2:
4166 case 3:
4167 wm8994->hubs.dcs_codes_l = -5;
4168 wm8994->hubs.dcs_codes_r = -5;
4169 wm8994->hubs.hp_startup_mode = 1;
4170 wm8994->hubs.dcs_readback_mode = 1;
4171 wm8994->hubs.series_startup = 1;
4172 break;
4173 default:
4174 wm8994->hubs.dcs_readback_mode = 2;
4175 break;
4176 }
4177 break;
4178
4179 case WM8958:
4180 wm8994->hubs.dcs_readback_mode = 1;
4181 wm8994->hubs.hp_startup_mode = 1;
4182
4183 switch (control->revision) {
4184 case 0:
4185 break;
4186 default:
4187 wm8994->fll_byp = true;
4188 break;
4189 }
4190 break;
4191
4192 case WM1811:
4193 wm8994->hubs.dcs_readback_mode = 2;
4194 wm8994->hubs.no_series_update = 1;
4195 wm8994->hubs.hp_startup_mode = 1;
4196 wm8994->hubs.no_cache_dac_hp_direct = true;
4197 wm8994->fll_byp = true;
4198
4199 wm8994->hubs.dcs_codes_l = -9;
4200 wm8994->hubs.dcs_codes_r = -7;
4201
4202 snd_soc_component_update_bits(component, WM8994_ANALOGUE_HP_1,
4203 WM1811_HPOUT1_ATTN, WM1811_HPOUT1_ATTN);
4204 break;
4205
4206 default:
4207 break;
4208 }
4209
4210 wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_FIFOS_ERR,
4211 wm8994_fifo_error, "FIFO error", component);
4212 wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_TEMP_WARN,
4213 wm8994_temp_warn, "Thermal warning", component);
4214 wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_TEMP_SHUT,
4215 wm8994_temp_shut, "Thermal shutdown", component);
4216
4217 switch (control->type) {
4218 case WM8994:
4219 if (wm8994->micdet_irq)
4220 ret = request_threaded_irq(wm8994->micdet_irq, NULL,
4221 wm8994_mic_irq,
4222 IRQF_TRIGGER_RISING |
4223 IRQF_ONESHOT,
4224 "Mic1 detect",
4225 wm8994);
4226 else
4227 ret = wm8994_request_irq(wm8994->wm8994,
4228 WM8994_IRQ_MIC1_DET,
4229 wm8994_mic_irq, "Mic 1 detect",
4230 wm8994);
4231
4232 if (ret != 0)
4233 dev_warn(component->dev,
4234 "Failed to request Mic1 detect IRQ: %d\n",
4235 ret);
4236
4237
4238 ret = wm8994_request_irq(wm8994->wm8994,
4239 WM8994_IRQ_MIC1_SHRT,
4240 wm8994_mic_irq, "Mic 1 short",
4241 wm8994);
4242 if (ret != 0)
4243 dev_warn(component->dev,
4244 "Failed to request Mic1 short IRQ: %d\n",
4245 ret);
4246
4247 ret = wm8994_request_irq(wm8994->wm8994,
4248 WM8994_IRQ_MIC2_DET,
4249 wm8994_mic_irq, "Mic 2 detect",
4250 wm8994);
4251 if (ret != 0)
4252 dev_warn(component->dev,
4253 "Failed to request Mic2 detect IRQ: %d\n",
4254 ret);
4255
4256 ret = wm8994_request_irq(wm8994->wm8994,
4257 WM8994_IRQ_MIC2_SHRT,
4258 wm8994_mic_irq, "Mic 2 short",
4259 wm8994);
4260 if (ret != 0)
4261 dev_warn(component->dev,
4262 "Failed to request Mic2 short IRQ: %d\n",
4263 ret);
4264 break;
4265
4266 case WM8958:
4267 case WM1811:
4268 if (wm8994->micdet_irq) {
4269 ret = request_threaded_irq(wm8994->micdet_irq, NULL,
4270 wm8958_mic_irq,
4271 IRQF_TRIGGER_RISING |
4272 IRQF_ONESHOT,
4273 "Mic detect",
4274 wm8994);
4275 if (ret != 0)
4276 dev_warn(component->dev,
4277 "Failed to request Mic detect IRQ: %d\n",
4278 ret);
4279 } else {
4280 wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_MIC1_DET,
4281 wm8958_mic_irq, "Mic detect",
4282 wm8994);
4283 }
4284 }
4285
4286 switch (control->type) {
4287 case WM1811:
4288 if (control->cust_id > 1 || control->revision > 1) {
4289 ret = wm8994_request_irq(wm8994->wm8994,
4290 WM8994_IRQ_GPIO(6),
4291 wm1811_jackdet_irq, "JACKDET",
4292 wm8994);
4293 if (ret == 0)
4294 wm8994->jackdet = true;
4295 }
4296 break;
4297 default:
4298 break;
4299 }
4300
4301 wm8994->fll_locked_irq = true;
4302 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++) {
4303 ret = wm8994_request_irq(wm8994->wm8994,
4304 WM8994_IRQ_FLL1_LOCK + i,
4305 wm8994_fll_locked_irq, "FLL lock",
4306 &wm8994->fll_locked[i]);
4307 if (ret != 0)
4308 wm8994->fll_locked_irq = false;
4309 }
4310
4311 /* Make sure we can read from the GPIOs if they're inputs */
4312 pm_runtime_get_sync(component->dev);
4313
4314 /* Remember if AIFnLRCLK is configured as a GPIO. This should be
4315 * configured on init - if a system wants to do this dynamically
4316 * at runtime we can deal with that then.
4317 */
4318 ret = regmap_read(control->regmap, WM8994_GPIO_1, &reg);
4319 if (ret < 0) {
4320 dev_err(component->dev, "Failed to read GPIO1 state: %d\n", ret);
4321 goto err_irq;
4322 }
4323 if ((reg & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) {
4324 wm8994->lrclk_shared[0] = 1;
4325 wm8994_dai[0].symmetric_rates = 1;
4326 } else {
4327 wm8994->lrclk_shared[0] = 0;
4328 }
4329
4330 ret = regmap_read(control->regmap, WM8994_GPIO_6, &reg);
4331 if (ret < 0) {
4332 dev_err(component->dev, "Failed to read GPIO6 state: %d\n", ret);
4333 goto err_irq;
4334 }
4335 if ((reg & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) {
4336 wm8994->lrclk_shared[1] = 1;
4337 wm8994_dai[1].symmetric_rates = 1;
4338 } else {
4339 wm8994->lrclk_shared[1] = 0;
4340 }
4341
4342 pm_runtime_put(component->dev);
4343
4344 /* Latch volume update bits */
4345 for (i = 0; i < ARRAY_SIZE(wm8994_vu_bits); i++)
4346 snd_soc_component_update_bits(component, wm8994_vu_bits[i].reg,
4347 wm8994_vu_bits[i].mask,
4348 wm8994_vu_bits[i].mask);
4349
4350 /* Set the low bit of the 3D stereo depth so TLV matches */
4351 snd_soc_component_update_bits(component, WM8994_AIF1_DAC1_FILTERS_2,
4352 1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT,
4353 1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT);
4354 snd_soc_component_update_bits(component, WM8994_AIF1_DAC2_FILTERS_2,
4355 1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT,
4356 1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT);
4357 snd_soc_component_update_bits(component, WM8994_AIF2_DAC_FILTERS_2,
4358 1 << WM8994_AIF2DAC_3D_GAIN_SHIFT,
4359 1 << WM8994_AIF2DAC_3D_GAIN_SHIFT);
4360
4361 /* Unconditionally enable AIF1 ADC TDM mode on chips which can
4362 * use this; it only affects behaviour on idle TDM clock
4363 * cycles. */
4364 switch (control->type) {
4365 case WM8994:
4366 case WM8958:
4367 snd_soc_component_update_bits(component, WM8994_AIF1_CONTROL_1,
4368 WM8994_AIF1ADC_TDM, WM8994_AIF1ADC_TDM);
4369 break;
4370 default:
4371 break;
4372 }
4373
4374 /* Put MICBIAS into bypass mode by default on newer devices */
4375 switch (control->type) {
4376 case WM8958:
4377 case WM1811:
4378 snd_soc_component_update_bits(component, WM8958_MICBIAS1,
4379 WM8958_MICB1_MODE, WM8958_MICB1_MODE);
4380 snd_soc_component_update_bits(component, WM8958_MICBIAS2,
4381 WM8958_MICB2_MODE, WM8958_MICB2_MODE);
4382 break;
4383 default:
4384 break;
4385 }
4386
4387 wm8994->hubs.check_class_w_digital = wm8994_check_class_w_digital;
4388 wm_hubs_update_class_w(component);
4389
4390 wm8994_handle_pdata(wm8994);
4391
4392 wm_hubs_add_analogue_controls(component);
4393 snd_soc_add_component_controls(component, wm8994_common_snd_controls,
4394 ARRAY_SIZE(wm8994_common_snd_controls));
4395 snd_soc_dapm_new_controls(dapm, wm8994_dapm_widgets,
4396 ARRAY_SIZE(wm8994_dapm_widgets));
4397
4398 switch (control->type) {
4399 case WM8994:
4400 snd_soc_add_component_controls(component, wm8994_snd_controls,
4401 ARRAY_SIZE(wm8994_snd_controls));
4402 snd_soc_dapm_new_controls(dapm, wm8994_specific_dapm_widgets,
4403 ARRAY_SIZE(wm8994_specific_dapm_widgets));
4404 if (control->revision < 4) {
4405 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_revd_widgets,
4406 ARRAY_SIZE(wm8994_lateclk_revd_widgets));
4407 snd_soc_dapm_new_controls(dapm, wm8994_adc_revd_widgets,
4408 ARRAY_SIZE(wm8994_adc_revd_widgets));
4409 snd_soc_dapm_new_controls(dapm, wm8994_dac_revd_widgets,
4410 ARRAY_SIZE(wm8994_dac_revd_widgets));
4411 } else {
4412 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
4413 ARRAY_SIZE(wm8994_lateclk_widgets));
4414 snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
4415 ARRAY_SIZE(wm8994_adc_widgets));
4416 snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
4417 ARRAY_SIZE(wm8994_dac_widgets));
4418 }
4419 break;
4420 case WM8958:
4421 snd_soc_add_component_controls(component, wm8994_snd_controls,
4422 ARRAY_SIZE(wm8994_snd_controls));
4423 snd_soc_add_component_controls(component, wm8958_snd_controls,
4424 ARRAY_SIZE(wm8958_snd_controls));
4425 snd_soc_dapm_new_controls(dapm, wm8958_dapm_widgets,
4426 ARRAY_SIZE(wm8958_dapm_widgets));
4427 if (control->revision < 1) {
4428 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_revd_widgets,
4429 ARRAY_SIZE(wm8994_lateclk_revd_widgets));
4430 snd_soc_dapm_new_controls(dapm, wm8994_adc_revd_widgets,
4431 ARRAY_SIZE(wm8994_adc_revd_widgets));
4432 snd_soc_dapm_new_controls(dapm, wm8994_dac_revd_widgets,
4433 ARRAY_SIZE(wm8994_dac_revd_widgets));
4434 } else {
4435 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
4436 ARRAY_SIZE(wm8994_lateclk_widgets));
4437 snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
4438 ARRAY_SIZE(wm8994_adc_widgets));
4439 snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
4440 ARRAY_SIZE(wm8994_dac_widgets));
4441 }
4442 break;
4443
4444 case WM1811:
4445 snd_soc_add_component_controls(component, wm8958_snd_controls,
4446 ARRAY_SIZE(wm8958_snd_controls));
4447 snd_soc_dapm_new_controls(dapm, wm8958_dapm_widgets,
4448 ARRAY_SIZE(wm8958_dapm_widgets));
4449 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
4450 ARRAY_SIZE(wm8994_lateclk_widgets));
4451 snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
4452 ARRAY_SIZE(wm8994_adc_widgets));
4453 snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
4454 ARRAY_SIZE(wm8994_dac_widgets));
4455 break;
4456 }
4457
4458 wm_hubs_add_analogue_routes(component, 0, 0);
4459 ret = wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_DCS_DONE,
4460 wm_hubs_dcs_done, "DC servo done",
4461 &wm8994->hubs);
4462 if (ret == 0)
4463 wm8994->hubs.dcs_done_irq = true;
4464 snd_soc_dapm_add_routes(dapm, intercon, ARRAY_SIZE(intercon));
4465
4466 switch (control->type) {
4467 case WM8994:
4468 snd_soc_dapm_add_routes(dapm, wm8994_intercon,
4469 ARRAY_SIZE(wm8994_intercon));
4470
4471 if (control->revision < 4) {
4472 snd_soc_dapm_add_routes(dapm, wm8994_revd_intercon,
4473 ARRAY_SIZE(wm8994_revd_intercon));
4474 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_revd_intercon,
4475 ARRAY_SIZE(wm8994_lateclk_revd_intercon));
4476 } else {
4477 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
4478 ARRAY_SIZE(wm8994_lateclk_intercon));
4479 }
4480 break;
4481 case WM8958:
4482 if (control->revision < 1) {
4483 snd_soc_dapm_add_routes(dapm, wm8994_intercon,
4484 ARRAY_SIZE(wm8994_intercon));
4485 snd_soc_dapm_add_routes(dapm, wm8994_revd_intercon,
4486 ARRAY_SIZE(wm8994_revd_intercon));
4487 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_revd_intercon,
4488 ARRAY_SIZE(wm8994_lateclk_revd_intercon));
4489 } else {
4490 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
4491 ARRAY_SIZE(wm8994_lateclk_intercon));
4492 snd_soc_dapm_add_routes(dapm, wm8958_intercon,
4493 ARRAY_SIZE(wm8958_intercon));
4494 }
4495
4496 wm8958_dsp2_init(component);
4497 break;
4498 case WM1811:
4499 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
4500 ARRAY_SIZE(wm8994_lateclk_intercon));
4501 snd_soc_dapm_add_routes(dapm, wm8958_intercon,
4502 ARRAY_SIZE(wm8958_intercon));
4503 break;
4504 }
4505
4506 return 0;
4507
4508 err_irq:
4509 if (wm8994->jackdet)
4510 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_GPIO(6), wm8994);
4511 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC2_SHRT, wm8994);
4512 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC2_DET, wm8994);
4513 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC1_SHRT, wm8994);
4514 if (wm8994->micdet_irq)
4515 free_irq(wm8994->micdet_irq, wm8994);
4516 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
4517 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FLL1_LOCK + i,
4518 &wm8994->fll_locked[i]);
4519 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_DCS_DONE,
4520 &wm8994->hubs);
4521 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FIFOS_ERR, component);
4522 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_SHUT, component);
4523 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_WARN, component);
4524
4525 return ret;
4526 }
4527
4528 static void wm8994_component_remove(struct snd_soc_component *component)
4529 {
4530 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
4531 struct wm8994 *control = wm8994->wm8994;
4532 int i;
4533
4534 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
4535 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FLL1_LOCK + i,
4536 &wm8994->fll_locked[i]);
4537
4538 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_DCS_DONE,
4539 &wm8994->hubs);
4540 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FIFOS_ERR, component);
4541 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_SHUT, component);
4542 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_WARN, component);
4543
4544 if (wm8994->jackdet)
4545 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_GPIO(6), wm8994);
4546
4547 switch (control->type) {
4548 case WM8994:
4549 if (wm8994->micdet_irq)
4550 free_irq(wm8994->micdet_irq, wm8994);
4551 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC2_DET,
4552 wm8994);
4553 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC1_SHRT,
4554 wm8994);
4555 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC1_DET,
4556 wm8994);
4557 break;
4558
4559 case WM1811:
4560 case WM8958:
4561 if (wm8994->micdet_irq)
4562 free_irq(wm8994->micdet_irq, wm8994);
4563 break;
4564 }
4565 release_firmware(wm8994->mbc);
4566 release_firmware(wm8994->mbc_vss);
4567 release_firmware(wm8994->enh_eq);
4568 kfree(wm8994->retune_mobile_texts);
4569 }
4570
4571 static const struct snd_soc_component_driver soc_component_dev_wm8994 = {
4572 .probe = wm8994_component_probe,
4573 .remove = wm8994_component_remove,
4574 .suspend = wm8994_component_suspend,
4575 .resume = wm8994_component_resume,
4576 .set_bias_level = wm8994_set_bias_level,
4577 .idle_bias_on = 1,
4578 .use_pmdown_time = 1,
4579 .endianness = 1,
4580 .non_legacy_dai_naming = 1,
4581 };
4582
4583 static int wm8994_probe(struct platform_device *pdev)
4584 {
4585 struct wm8994_priv *wm8994;
4586 int ret;
4587
4588 wm8994 = devm_kzalloc(&pdev->dev, sizeof(struct wm8994_priv),
4589 GFP_KERNEL);
4590 if (wm8994 == NULL)
4591 return -ENOMEM;
4592 platform_set_drvdata(pdev, wm8994);
4593
4594 mutex_init(&wm8994->fw_lock);
4595
4596 wm8994->wm8994 = dev_get_drvdata(pdev->dev.parent);
4597
4598 wm8994->mclk[WM8994_MCLK1].id = "MCLK1";
4599 wm8994->mclk[WM8994_MCLK2].id = "MCLK2";
4600
4601 ret = devm_clk_bulk_get_optional(pdev->dev.parent, ARRAY_SIZE(wm8994->mclk),
4602 wm8994->mclk);
4603 if (ret < 0) {
4604 dev_err(&pdev->dev, "Failed to get clocks: %d\n", ret);
4605 return ret;
4606 }
4607
4608 pm_runtime_enable(&pdev->dev);
4609 pm_runtime_idle(&pdev->dev);
4610
4611 return devm_snd_soc_register_component(&pdev->dev, &soc_component_dev_wm8994,
4612 wm8994_dai, ARRAY_SIZE(wm8994_dai));
4613 }
4614
4615 static int wm8994_remove(struct platform_device *pdev)
4616 {
4617 pm_runtime_disable(&pdev->dev);
4618
4619 return 0;
4620 }
4621
4622 #ifdef CONFIG_PM_SLEEP
4623 static int wm8994_suspend(struct device *dev)
4624 {
4625 struct wm8994_priv *wm8994 = dev_get_drvdata(dev);
4626
4627 /* Drop down to power saving mode when system is suspended */
4628 if (wm8994->jackdet && !wm8994->active_refcount)
4629 regmap_update_bits(wm8994->wm8994->regmap, WM8994_ANTIPOP_2,
4630 WM1811_JACKDET_MODE_MASK,
4631 wm8994->jackdet_mode);
4632
4633 return 0;
4634 }
4635
4636 static int wm8994_resume(struct device *dev)
4637 {
4638 struct wm8994_priv *wm8994 = dev_get_drvdata(dev);
4639
4640 if (wm8994->jackdet && wm8994->jackdet_mode)
4641 regmap_update_bits(wm8994->wm8994->regmap, WM8994_ANTIPOP_2,
4642 WM1811_JACKDET_MODE_MASK,
4643 WM1811_JACKDET_MODE_AUDIO);
4644
4645 return 0;
4646 }
4647 #endif
4648
4649 static const struct dev_pm_ops wm8994_pm_ops = {
4650 SET_SYSTEM_SLEEP_PM_OPS(wm8994_suspend, wm8994_resume)
4651 };
4652
4653 static struct platform_driver wm8994_codec_driver = {
4654 .driver = {
4655 .name = "wm8994-codec",
4656 .pm = &wm8994_pm_ops,
4657 },
4658 .probe = wm8994_probe,
4659 .remove = wm8994_remove,
4660 };
4661
4662 module_platform_driver(wm8994_codec_driver);
4663
4664 MODULE_DESCRIPTION("ASoC WM8994 driver");
4665 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
4666 MODULE_LICENSE("GPL");
4667 MODULE_ALIAS("platform:wm8994-codec");
Linux with added FPC-III support