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btrfs: account for non-CoW'd blocks in btrfs_abort_transaction
[linux/fpc-iii.git] / arch / arm / mach-omap2 / omap_hwmod_44xx_data.c
blobf5e68a7820251360dc1aad459e259ee1c6d217ae
1 /*
2 * Hardware modules present on the OMAP44xx chips
3 *
4 * Copyright (C) 2009-2012 Texas Instruments, Inc.
5 * Copyright (C) 2009-2010 Nokia Corporation
6 *
7 * Paul Walmsley
8 * Benoit Cousson
9 *
10 * This file is automatically generated from the OMAP hardware databases.
11 * We respectfully ask that any modifications to this file be coordinated
12 * with the public linux-omap@vger.kernel.org mailing list and the
13 * authors above to ensure that the autogeneration scripts are kept
14 * up-to-date with the file contents.
15 * Note that this file is currently not in sync with autogeneration scripts.
16 * The above note to be removed, once it is synced up.
17 *
18 * This program is free software; you can redistribute it and/or modify
19 * it under the terms of the GNU General Public License version 2 as
20 * published by the Free Software Foundation.
21 */
22
23 #include <linux/io.h>
24 #include <linux/platform_data/gpio-omap.h>
25 #include <linux/platform_data/hsmmc-omap.h>
26 #include <linux/power/smartreflex.h>
27 #include <linux/i2c-omap.h>
28
29 #include <linux/omap-dma.h>
30
31 #include <linux/platform_data/spi-omap2-mcspi.h>
32 #include <linux/platform_data/asoc-ti-mcbsp.h>
33 #include <linux/platform_data/iommu-omap.h>
34 #include <plat/dmtimer.h>
35
36 #include "omap_hwmod.h"
37 #include "omap_hwmod_common_data.h"
38 #include "cm1_44xx.h"
39 #include "cm2_44xx.h"
40 #include "prm44xx.h"
41 #include "prm-regbits-44xx.h"
42 #include "i2c.h"
43 #include "wd_timer.h"
44
45 /* Base offset for all OMAP4 interrupts external to MPUSS */
46 #define OMAP44XX_IRQ_GIC_START 32
47
48 /* Base offset for all OMAP4 dma requests */
49 #define OMAP44XX_DMA_REQ_START 1
50
51 /*
52 * IP blocks
53 */
54
55 /*
56 * 'dmm' class
57 * instance(s): dmm
58 */
59 static struct omap_hwmod_class omap44xx_dmm_hwmod_class = {
60 .name = "dmm",
61 };
62
63 /* dmm */
64 static struct omap_hwmod omap44xx_dmm_hwmod = {
65 .name = "dmm",
66 .class = &omap44xx_dmm_hwmod_class,
67 .clkdm_name = "l3_emif_clkdm",
68 .prcm = {
69 .omap4 = {
70 .clkctrl_offs = OMAP4_CM_MEMIF_DMM_CLKCTRL_OFFSET,
71 .context_offs = OMAP4_RM_MEMIF_DMM_CONTEXT_OFFSET,
72 },
73 },
74 };
75
76 /*
77 * 'l3' class
78 * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3
79 */
80 static struct omap_hwmod_class omap44xx_l3_hwmod_class = {
81 .name = "l3",
82 };
83
84 /* l3_instr */
85 static struct omap_hwmod omap44xx_l3_instr_hwmod = {
86 .name = "l3_instr",
87 .class = &omap44xx_l3_hwmod_class,
88 .clkdm_name = "l3_instr_clkdm",
89 .prcm = {
90 .omap4 = {
91 .clkctrl_offs = OMAP4_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
92 .context_offs = OMAP4_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
93 .modulemode = MODULEMODE_HWCTRL,
94 },
95 },
96 };
97
98 /* l3_main_1 */
99 static struct omap_hwmod omap44xx_l3_main_1_hwmod = {
100 .name = "l3_main_1",
101 .class = &omap44xx_l3_hwmod_class,
102 .clkdm_name = "l3_1_clkdm",
103 .prcm = {
104 .omap4 = {
105 .clkctrl_offs = OMAP4_CM_L3_1_L3_1_CLKCTRL_OFFSET,
106 .context_offs = OMAP4_RM_L3_1_L3_1_CONTEXT_OFFSET,
107 },
108 },
109 };
110
111 /* l3_main_2 */
112 static struct omap_hwmod omap44xx_l3_main_2_hwmod = {
113 .name = "l3_main_2",
114 .class = &omap44xx_l3_hwmod_class,
115 .clkdm_name = "l3_2_clkdm",
116 .prcm = {
117 .omap4 = {
118 .clkctrl_offs = OMAP4_CM_L3_2_L3_2_CLKCTRL_OFFSET,
119 .context_offs = OMAP4_RM_L3_2_L3_2_CONTEXT_OFFSET,
120 },
121 },
122 };
123
124 /* l3_main_3 */
125 static struct omap_hwmod omap44xx_l3_main_3_hwmod = {
126 .name = "l3_main_3",
127 .class = &omap44xx_l3_hwmod_class,
128 .clkdm_name = "l3_instr_clkdm",
129 .prcm = {
130 .omap4 = {
131 .clkctrl_offs = OMAP4_CM_L3INSTR_L3_3_CLKCTRL_OFFSET,
132 .context_offs = OMAP4_RM_L3INSTR_L3_3_CONTEXT_OFFSET,
133 .modulemode = MODULEMODE_HWCTRL,
134 },
135 },
136 };
137
138 /*
139 * 'l4' class
140 * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup
141 */
142 static struct omap_hwmod_class omap44xx_l4_hwmod_class = {
143 .name = "l4",
144 };
145
146 /* l4_abe */
147 static struct omap_hwmod omap44xx_l4_abe_hwmod = {
148 .name = "l4_abe",
149 .class = &omap44xx_l4_hwmod_class,
150 .clkdm_name = "abe_clkdm",
151 .prcm = {
152 .omap4 = {
153 .clkctrl_offs = OMAP4_CM1_ABE_L4ABE_CLKCTRL_OFFSET,
154 .context_offs = OMAP4_RM_ABE_AESS_CONTEXT_OFFSET,
155 .lostcontext_mask = OMAP4430_LOSTMEM_AESSMEM_MASK,
156 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
157 },
158 },
159 };
160
161 /* l4_cfg */
162 static struct omap_hwmod omap44xx_l4_cfg_hwmod = {
163 .name = "l4_cfg",
164 .class = &omap44xx_l4_hwmod_class,
165 .clkdm_name = "l4_cfg_clkdm",
166 .prcm = {
167 .omap4 = {
168 .clkctrl_offs = OMAP4_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
169 .context_offs = OMAP4_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
170 },
171 },
172 };
173
174 /* l4_per */
175 static struct omap_hwmod omap44xx_l4_per_hwmod = {
176 .name = "l4_per",
177 .class = &omap44xx_l4_hwmod_class,
178 .clkdm_name = "l4_per_clkdm",
179 .prcm = {
180 .omap4 = {
181 .clkctrl_offs = OMAP4_CM_L4PER_L4PER_CLKCTRL_OFFSET,
182 .context_offs = OMAP4_RM_L4PER_L4_PER_CONTEXT_OFFSET,
183 },
184 },
185 };
186
187 /* l4_wkup */
188 static struct omap_hwmod omap44xx_l4_wkup_hwmod = {
189 .name = "l4_wkup",
190 .class = &omap44xx_l4_hwmod_class,
191 .clkdm_name = "l4_wkup_clkdm",
192 .prcm = {
193 .omap4 = {
194 .clkctrl_offs = OMAP4_CM_WKUP_L4WKUP_CLKCTRL_OFFSET,
195 .context_offs = OMAP4_RM_WKUP_L4WKUP_CONTEXT_OFFSET,
196 },
197 },
198 };
199
200 /*
201 * 'mpu_bus' class
202 * instance(s): mpu_private
203 */
204 static struct omap_hwmod_class omap44xx_mpu_bus_hwmod_class = {
205 .name = "mpu_bus",
206 };
207
208 /* mpu_private */
209 static struct omap_hwmod omap44xx_mpu_private_hwmod = {
210 .name = "mpu_private",
211 .class = &omap44xx_mpu_bus_hwmod_class,
212 .clkdm_name = "mpuss_clkdm",
213 .prcm = {
214 .omap4 = {
215 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
216 },
217 },
218 };
219
220 /*
221 * 'ocp_wp_noc' class
222 * instance(s): ocp_wp_noc
223 */
224 static struct omap_hwmod_class omap44xx_ocp_wp_noc_hwmod_class = {
225 .name = "ocp_wp_noc",
226 };
227
228 /* ocp_wp_noc */
229 static struct omap_hwmod omap44xx_ocp_wp_noc_hwmod = {
230 .name = "ocp_wp_noc",
231 .class = &omap44xx_ocp_wp_noc_hwmod_class,
232 .clkdm_name = "l3_instr_clkdm",
233 .prcm = {
234 .omap4 = {
235 .clkctrl_offs = OMAP4_CM_L3INSTR_OCP_WP1_CLKCTRL_OFFSET,
236 .context_offs = OMAP4_RM_L3INSTR_OCP_WP1_CONTEXT_OFFSET,
237 .modulemode = MODULEMODE_HWCTRL,
238 },
239 },
240 };
241
242 /*
243 * Modules omap_hwmod structures
244 *
245 * The following IPs are excluded for the moment because:
246 * - They do not need an explicit SW control using omap_hwmod API.
247 * - They still need to be validated with the driver
248 * properly adapted to omap_hwmod / omap_device
249 *
250 * usim
251 */
252
253 /*
254 * 'aess' class
255 * audio engine sub system
256 */
257
258 static struct omap_hwmod_class_sysconfig omap44xx_aess_sysc = {
259 .rev_offs = 0x0000,
260 .sysc_offs = 0x0010,
261 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
262 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
263 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART |
264 MSTANDBY_SMART_WKUP),
265 .sysc_fields = &omap_hwmod_sysc_type2,
266 };
267
268 static struct omap_hwmod_class omap44xx_aess_hwmod_class = {
269 .name = "aess",
270 .sysc = &omap44xx_aess_sysc,
271 .enable_preprogram = omap_hwmod_aess_preprogram,
272 };
273
274 /* aess */
275 static struct omap_hwmod omap44xx_aess_hwmod = {
276 .name = "aess",
277 .class = &omap44xx_aess_hwmod_class,
278 .clkdm_name = "abe_clkdm",
279 .main_clk = "aess_fclk",
280 .prcm = {
281 .omap4 = {
282 .clkctrl_offs = OMAP4_CM1_ABE_AESS_CLKCTRL_OFFSET,
283 .context_offs = OMAP4_RM_ABE_AESS_CONTEXT_OFFSET,
284 .lostcontext_mask = OMAP4430_LOSTCONTEXT_DFF_MASK,
285 .modulemode = MODULEMODE_SWCTRL,
286 },
287 },
288 };
289
290 /*
291 * 'c2c' class
292 * chip 2 chip interface used to plug the ape soc (omap) with an external modem
293 * soc
294 */
295
296 static struct omap_hwmod_class omap44xx_c2c_hwmod_class = {
297 .name = "c2c",
298 };
299
300 /* c2c */
301 static struct omap_hwmod omap44xx_c2c_hwmod = {
302 .name = "c2c",
303 .class = &omap44xx_c2c_hwmod_class,
304 .clkdm_name = "d2d_clkdm",
305 .prcm = {
306 .omap4 = {
307 .clkctrl_offs = OMAP4_CM_D2D_SAD2D_CLKCTRL_OFFSET,
308 .context_offs = OMAP4_RM_D2D_SAD2D_CONTEXT_OFFSET,
309 },
310 },
311 };
312
313 /*
314 * 'counter' class
315 * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
316 */
317
318 static struct omap_hwmod_class_sysconfig omap44xx_counter_sysc = {
319 .rev_offs = 0x0000,
320 .sysc_offs = 0x0004,
321 .sysc_flags = SYSC_HAS_SIDLEMODE,
322 .idlemodes = (SIDLE_FORCE | SIDLE_NO),
323 .sysc_fields = &omap_hwmod_sysc_type1,
324 };
325
326 static struct omap_hwmod_class omap44xx_counter_hwmod_class = {
327 .name = "counter",
328 .sysc = &omap44xx_counter_sysc,
329 };
330
331 /* counter_32k */
332 static struct omap_hwmod omap44xx_counter_32k_hwmod = {
333 .name = "counter_32k",
334 .class = &omap44xx_counter_hwmod_class,
335 .clkdm_name = "l4_wkup_clkdm",
336 .flags = HWMOD_SWSUP_SIDLE,
337 .main_clk = "sys_32k_ck",
338 .prcm = {
339 .omap4 = {
340 .clkctrl_offs = OMAP4_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET,
341 .context_offs = OMAP4_RM_WKUP_SYNCTIMER_CONTEXT_OFFSET,
342 },
343 },
344 };
345
346 /*
347 * 'ctrl_module' class
348 * attila core control module + core pad control module + wkup pad control
349 * module + attila wkup control module
350 */
351
352 static struct omap_hwmod_class_sysconfig omap44xx_ctrl_module_sysc = {
353 .rev_offs = 0x0000,
354 .sysc_offs = 0x0010,
355 .sysc_flags = SYSC_HAS_SIDLEMODE,
356 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
357 SIDLE_SMART_WKUP),
358 .sysc_fields = &omap_hwmod_sysc_type2,
359 };
360
361 static struct omap_hwmod_class omap44xx_ctrl_module_hwmod_class = {
362 .name = "ctrl_module",
363 .sysc = &omap44xx_ctrl_module_sysc,
364 };
365
366 /* ctrl_module_core */
367 static struct omap_hwmod omap44xx_ctrl_module_core_hwmod = {
368 .name = "ctrl_module_core",
369 .class = &omap44xx_ctrl_module_hwmod_class,
370 .clkdm_name = "l4_cfg_clkdm",
371 .prcm = {
372 .omap4 = {
373 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
374 },
375 },
376 };
377
378 /* ctrl_module_pad_core */
379 static struct omap_hwmod omap44xx_ctrl_module_pad_core_hwmod = {
380 .name = "ctrl_module_pad_core",
381 .class = &omap44xx_ctrl_module_hwmod_class,
382 .clkdm_name = "l4_cfg_clkdm",
383 .prcm = {
384 .omap4 = {
385 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
386 },
387 },
388 };
389
390 /* ctrl_module_wkup */
391 static struct omap_hwmod omap44xx_ctrl_module_wkup_hwmod = {
392 .name = "ctrl_module_wkup",
393 .class = &omap44xx_ctrl_module_hwmod_class,
394 .clkdm_name = "l4_wkup_clkdm",
395 .prcm = {
396 .omap4 = {
397 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
398 },
399 },
400 };
401
402 /* ctrl_module_pad_wkup */
403 static struct omap_hwmod omap44xx_ctrl_module_pad_wkup_hwmod = {
404 .name = "ctrl_module_pad_wkup",
405 .class = &omap44xx_ctrl_module_hwmod_class,
406 .clkdm_name = "l4_wkup_clkdm",
407 .prcm = {
408 .omap4 = {
409 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
410 },
411 },
412 };
413
414 /*
415 * 'debugss' class
416 * debug and emulation sub system
417 */
418
419 static struct omap_hwmod_class omap44xx_debugss_hwmod_class = {
420 .name = "debugss",
421 };
422
423 /* debugss */
424 static struct omap_hwmod omap44xx_debugss_hwmod = {
425 .name = "debugss",
426 .class = &omap44xx_debugss_hwmod_class,
427 .clkdm_name = "emu_sys_clkdm",
428 .main_clk = "trace_clk_div_ck",
429 .prcm = {
430 .omap4 = {
431 .clkctrl_offs = OMAP4_CM_EMU_DEBUGSS_CLKCTRL_OFFSET,
432 .context_offs = OMAP4_RM_EMU_DEBUGSS_CONTEXT_OFFSET,
433 },
434 },
435 };
436
437 /*
438 * 'dma' class
439 * dma controller for data exchange between memory to memory (i.e. internal or
440 * external memory) and gp peripherals to memory or memory to gp peripherals
441 */
442
443 static struct omap_hwmod_class_sysconfig omap44xx_dma_sysc = {
444 .rev_offs = 0x0000,
445 .sysc_offs = 0x002c,
446 .syss_offs = 0x0028,
447 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
448 SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
449 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
450 SYSS_HAS_RESET_STATUS),
451 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
452 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
453 .sysc_fields = &omap_hwmod_sysc_type1,
454 };
455
456 static struct omap_hwmod_class omap44xx_dma_hwmod_class = {
457 .name = "dma",
458 .sysc = &omap44xx_dma_sysc,
459 };
460
461 /* dma dev_attr */
462 static struct omap_dma_dev_attr dma_dev_attr = {
463 .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
464 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
465 .lch_count = 32,
466 };
467
468 /* dma_system */
469 static struct omap_hwmod_irq_info omap44xx_dma_system_irqs[] = {
470 { .name = "0", .irq = 12 + OMAP44XX_IRQ_GIC_START },
471 { .name = "1", .irq = 13 + OMAP44XX_IRQ_GIC_START },
472 { .name = "2", .irq = 14 + OMAP44XX_IRQ_GIC_START },
473 { .name = "3", .irq = 15 + OMAP44XX_IRQ_GIC_START },
474 { .irq = -1 }
475 };
476
477 static struct omap_hwmod omap44xx_dma_system_hwmod = {
478 .name = "dma_system",
479 .class = &omap44xx_dma_hwmod_class,
480 .clkdm_name = "l3_dma_clkdm",
481 .mpu_irqs = omap44xx_dma_system_irqs,
482 .xlate_irq = omap4_xlate_irq,
483 .main_clk = "l3_div_ck",
484 .prcm = {
485 .omap4 = {
486 .clkctrl_offs = OMAP4_CM_SDMA_SDMA_CLKCTRL_OFFSET,
487 .context_offs = OMAP4_RM_SDMA_SDMA_CONTEXT_OFFSET,
488 },
489 },
490 .dev_attr = &dma_dev_attr,
491 };
492
493 /*
494 * 'dmic' class
495 * digital microphone controller
496 */
497
498 static struct omap_hwmod_class_sysconfig omap44xx_dmic_sysc = {
499 .rev_offs = 0x0000,
500 .sysc_offs = 0x0010,
501 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
502 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
503 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
504 SIDLE_SMART_WKUP),
505 .sysc_fields = &omap_hwmod_sysc_type2,
506 };
507
508 static struct omap_hwmod_class omap44xx_dmic_hwmod_class = {
509 .name = "dmic",
510 .sysc = &omap44xx_dmic_sysc,
511 };
512
513 /* dmic */
514 static struct omap_hwmod omap44xx_dmic_hwmod = {
515 .name = "dmic",
516 .class = &omap44xx_dmic_hwmod_class,
517 .clkdm_name = "abe_clkdm",
518 .main_clk = "func_dmic_abe_gfclk",
519 .prcm = {
520 .omap4 = {
521 .clkctrl_offs = OMAP4_CM1_ABE_DMIC_CLKCTRL_OFFSET,
522 .context_offs = OMAP4_RM_ABE_DMIC_CONTEXT_OFFSET,
523 .modulemode = MODULEMODE_SWCTRL,
524 },
525 },
526 };
527
528 /*
529 * 'dsp' class
530 * dsp sub-system
531 */
532
533 static struct omap_hwmod_class omap44xx_dsp_hwmod_class = {
534 .name = "dsp",
535 };
536
537 /* dsp */
538 static struct omap_hwmod_rst_info omap44xx_dsp_resets[] = {
539 { .name = "dsp", .rst_shift = 0 },
540 };
541
542 static struct omap_hwmod omap44xx_dsp_hwmod = {
543 .name = "dsp",
544 .class = &omap44xx_dsp_hwmod_class,
545 .clkdm_name = "tesla_clkdm",
546 .rst_lines = omap44xx_dsp_resets,
547 .rst_lines_cnt = ARRAY_SIZE(omap44xx_dsp_resets),
548 .main_clk = "dpll_iva_m4x2_ck",
549 .prcm = {
550 .omap4 = {
551 .clkctrl_offs = OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET,
552 .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET,
553 .context_offs = OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET,
554 .modulemode = MODULEMODE_HWCTRL,
555 },
556 },
557 };
558
559 /*
560 * 'dss' class
561 * display sub-system
562 */
563
564 static struct omap_hwmod_class_sysconfig omap44xx_dss_sysc = {
565 .rev_offs = 0x0000,
566 .syss_offs = 0x0014,
567 .sysc_flags = SYSS_HAS_RESET_STATUS,
568 };
569
570 static struct omap_hwmod_class omap44xx_dss_hwmod_class = {
571 .name = "dss",
572 .sysc = &omap44xx_dss_sysc,
573 .reset = omap_dss_reset,
574 };
575
576 /* dss */
577 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
578 { .role = "sys_clk", .clk = "dss_sys_clk" },
579 { .role = "tv_clk", .clk = "dss_tv_clk" },
580 { .role = "hdmi_clk", .clk = "dss_48mhz_clk" },
581 };
582
583 static struct omap_hwmod omap44xx_dss_hwmod = {
584 .name = "dss_core",
585 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
586 .class = &omap44xx_dss_hwmod_class,
587 .clkdm_name = "l3_dss_clkdm",
588 .main_clk = "dss_dss_clk",
589 .prcm = {
590 .omap4 = {
591 .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
592 .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
593 .modulemode = MODULEMODE_SWCTRL,
594 },
595 },
596 .opt_clks = dss_opt_clks,
597 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
598 };
599
600 /*
601 * 'dispc' class
602 * display controller
603 */
604
605 static struct omap_hwmod_class_sysconfig omap44xx_dispc_sysc = {
606 .rev_offs = 0x0000,
607 .sysc_offs = 0x0010,
608 .syss_offs = 0x0014,
609 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
610 SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE |
611 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
612 SYSS_HAS_RESET_STATUS),
613 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
614 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
615 .sysc_fields = &omap_hwmod_sysc_type1,
616 };
617
618 static struct omap_hwmod_class omap44xx_dispc_hwmod_class = {
619 .name = "dispc",
620 .sysc = &omap44xx_dispc_sysc,
621 };
622
623 /* dss_dispc */
624 static struct omap_hwmod_irq_info omap44xx_dss_dispc_irqs[] = {
625 { .irq = 25 + OMAP44XX_IRQ_GIC_START },
626 { .irq = -1 }
627 };
628
629 static struct omap_hwmod_dma_info omap44xx_dss_dispc_sdma_reqs[] = {
630 { .dma_req = 5 + OMAP44XX_DMA_REQ_START },
631 { .dma_req = -1 }
632 };
633
634 static struct omap_dss_dispc_dev_attr omap44xx_dss_dispc_dev_attr = {
635 .manager_count = 3,
636 .has_framedonetv_irq = 1
637 };
638
639 static struct omap_hwmod omap44xx_dss_dispc_hwmod = {
640 .name = "dss_dispc",
641 .class = &omap44xx_dispc_hwmod_class,
642 .clkdm_name = "l3_dss_clkdm",
643 .mpu_irqs = omap44xx_dss_dispc_irqs,
644 .xlate_irq = omap4_xlate_irq,
645 .sdma_reqs = omap44xx_dss_dispc_sdma_reqs,
646 .main_clk = "dss_dss_clk",
647 .prcm = {
648 .omap4 = {
649 .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
650 .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
651 },
652 },
653 .dev_attr = &omap44xx_dss_dispc_dev_attr,
654 .parent_hwmod = &omap44xx_dss_hwmod,
655 };
656
657 /*
658 * 'dsi' class
659 * display serial interface controller
660 */
661
662 static struct omap_hwmod_class_sysconfig omap44xx_dsi_sysc = {
663 .rev_offs = 0x0000,
664 .sysc_offs = 0x0010,
665 .syss_offs = 0x0014,
666 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
667 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
668 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
669 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
670 .sysc_fields = &omap_hwmod_sysc_type1,
671 };
672
673 static struct omap_hwmod_class omap44xx_dsi_hwmod_class = {
674 .name = "dsi",
675 .sysc = &omap44xx_dsi_sysc,
676 };
677
678 /* dss_dsi1 */
679 static struct omap_hwmod_irq_info omap44xx_dss_dsi1_irqs[] = {
680 { .irq = 53 + OMAP44XX_IRQ_GIC_START },
681 { .irq = -1 }
682 };
683
684 static struct omap_hwmod_dma_info omap44xx_dss_dsi1_sdma_reqs[] = {
685 { .dma_req = 74 + OMAP44XX_DMA_REQ_START },
686 { .dma_req = -1 }
687 };
688
689 static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = {
690 { .role = "sys_clk", .clk = "dss_sys_clk" },
691 };
692
693 static struct omap_hwmod omap44xx_dss_dsi1_hwmod = {
694 .name = "dss_dsi1",
695 .class = &omap44xx_dsi_hwmod_class,
696 .clkdm_name = "l3_dss_clkdm",
697 .mpu_irqs = omap44xx_dss_dsi1_irqs,
698 .xlate_irq = omap4_xlate_irq,
699 .sdma_reqs = omap44xx_dss_dsi1_sdma_reqs,
700 .main_clk = "dss_dss_clk",
701 .prcm = {
702 .omap4 = {
703 .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
704 .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
705 },
706 },
707 .opt_clks = dss_dsi1_opt_clks,
708 .opt_clks_cnt = ARRAY_SIZE(dss_dsi1_opt_clks),
709 .parent_hwmod = &omap44xx_dss_hwmod,
710 };
711
712 /* dss_dsi2 */
713 static struct omap_hwmod_irq_info omap44xx_dss_dsi2_irqs[] = {
714 { .irq = 84 + OMAP44XX_IRQ_GIC_START },
715 { .irq = -1 }
716 };
717
718 static struct omap_hwmod_dma_info omap44xx_dss_dsi2_sdma_reqs[] = {
719 { .dma_req = 83 + OMAP44XX_DMA_REQ_START },
720 { .dma_req = -1 }
721 };
722
723 static struct omap_hwmod_opt_clk dss_dsi2_opt_clks[] = {
724 { .role = "sys_clk", .clk = "dss_sys_clk" },
725 };
726
727 static struct omap_hwmod omap44xx_dss_dsi2_hwmod = {
728 .name = "dss_dsi2",
729 .class = &omap44xx_dsi_hwmod_class,
730 .clkdm_name = "l3_dss_clkdm",
731 .mpu_irqs = omap44xx_dss_dsi2_irqs,
732 .xlate_irq = omap4_xlate_irq,
733 .sdma_reqs = omap44xx_dss_dsi2_sdma_reqs,
734 .main_clk = "dss_dss_clk",
735 .prcm = {
736 .omap4 = {
737 .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
738 .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
739 },
740 },
741 .opt_clks = dss_dsi2_opt_clks,
742 .opt_clks_cnt = ARRAY_SIZE(dss_dsi2_opt_clks),
743 .parent_hwmod = &omap44xx_dss_hwmod,
744 };
745
746 /*
747 * 'hdmi' class
748 * hdmi controller
749 */
750
751 static struct omap_hwmod_class_sysconfig omap44xx_hdmi_sysc = {
752 .rev_offs = 0x0000,
753 .sysc_offs = 0x0010,
754 .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
755 SYSC_HAS_SOFTRESET),
756 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
757 SIDLE_SMART_WKUP),
758 .sysc_fields = &omap_hwmod_sysc_type2,
759 };
760
761 static struct omap_hwmod_class omap44xx_hdmi_hwmod_class = {
762 .name = "hdmi",
763 .sysc = &omap44xx_hdmi_sysc,
764 };
765
766 /* dss_hdmi */
767 static struct omap_hwmod_irq_info omap44xx_dss_hdmi_irqs[] = {
768 { .irq = 101 + OMAP44XX_IRQ_GIC_START },
769 { .irq = -1 }
770 };
771
772 static struct omap_hwmod_dma_info omap44xx_dss_hdmi_sdma_reqs[] = {
773 { .dma_req = 75 + OMAP44XX_DMA_REQ_START },
774 { .dma_req = -1 }
775 };
776
777 static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
778 { .role = "sys_clk", .clk = "dss_sys_clk" },
779 };
780
781 static struct omap_hwmod omap44xx_dss_hdmi_hwmod = {
782 .name = "dss_hdmi",
783 .class = &omap44xx_hdmi_hwmod_class,
784 .clkdm_name = "l3_dss_clkdm",
785 /*
786 * HDMI audio requires to use no-idle mode. Hence,
787 * set idle mode by software.
788 */
789 .flags = HWMOD_SWSUP_SIDLE,
790 .mpu_irqs = omap44xx_dss_hdmi_irqs,
791 .xlate_irq = omap4_xlate_irq,
792 .sdma_reqs = omap44xx_dss_hdmi_sdma_reqs,
793 .main_clk = "dss_48mhz_clk",
794 .prcm = {
795 .omap4 = {
796 .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
797 .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
798 },
799 },
800 .opt_clks = dss_hdmi_opt_clks,
801 .opt_clks_cnt = ARRAY_SIZE(dss_hdmi_opt_clks),
802 .parent_hwmod = &omap44xx_dss_hwmod,
803 };
804
805 /*
806 * 'rfbi' class
807 * remote frame buffer interface
808 */
809
810 static struct omap_hwmod_class_sysconfig omap44xx_rfbi_sysc = {
811 .rev_offs = 0x0000,
812 .sysc_offs = 0x0010,
813 .syss_offs = 0x0014,
814 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
815 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
816 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
817 .sysc_fields = &omap_hwmod_sysc_type1,
818 };
819
820 static struct omap_hwmod_class omap44xx_rfbi_hwmod_class = {
821 .name = "rfbi",
822 .sysc = &omap44xx_rfbi_sysc,
823 };
824
825 /* dss_rfbi */
826 static struct omap_hwmod_dma_info omap44xx_dss_rfbi_sdma_reqs[] = {
827 { .dma_req = 13 + OMAP44XX_DMA_REQ_START },
828 { .dma_req = -1 }
829 };
830
831 static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
832 { .role = "ick", .clk = "l3_div_ck" },
833 };
834
835 static struct omap_hwmod omap44xx_dss_rfbi_hwmod = {
836 .name = "dss_rfbi",
837 .class = &omap44xx_rfbi_hwmod_class,
838 .clkdm_name = "l3_dss_clkdm",
839 .sdma_reqs = omap44xx_dss_rfbi_sdma_reqs,
840 .main_clk = "dss_dss_clk",
841 .prcm = {
842 .omap4 = {
843 .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
844 .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
845 },
846 },
847 .opt_clks = dss_rfbi_opt_clks,
848 .opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks),
849 .parent_hwmod = &omap44xx_dss_hwmod,
850 };
851
852 /*
853 * 'venc' class
854 * video encoder
855 */
856
857 static struct omap_hwmod_class omap44xx_venc_hwmod_class = {
858 .name = "venc",
859 };
860
861 /* dss_venc */
862 static struct omap_hwmod omap44xx_dss_venc_hwmod = {
863 .name = "dss_venc",
864 .class = &omap44xx_venc_hwmod_class,
865 .clkdm_name = "l3_dss_clkdm",
866 .main_clk = "dss_tv_clk",
867 .prcm = {
868 .omap4 = {
869 .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
870 .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
871 },
872 },
873 .parent_hwmod = &omap44xx_dss_hwmod,
874 };
875
876 /*
877 * 'elm' class
878 * bch error location module
879 */
880
881 static struct omap_hwmod_class_sysconfig omap44xx_elm_sysc = {
882 .rev_offs = 0x0000,
883 .sysc_offs = 0x0010,
884 .syss_offs = 0x0014,
885 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
886 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
887 SYSS_HAS_RESET_STATUS),
888 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
889 .sysc_fields = &omap_hwmod_sysc_type1,
890 };
891
892 static struct omap_hwmod_class omap44xx_elm_hwmod_class = {
893 .name = "elm",
894 .sysc = &omap44xx_elm_sysc,
895 };
896
897 /* elm */
898 static struct omap_hwmod omap44xx_elm_hwmod = {
899 .name = "elm",
900 .class = &omap44xx_elm_hwmod_class,
901 .clkdm_name = "l4_per_clkdm",
902 .prcm = {
903 .omap4 = {
904 .clkctrl_offs = OMAP4_CM_L4PER_ELM_CLKCTRL_OFFSET,
905 .context_offs = OMAP4_RM_L4PER_ELM_CONTEXT_OFFSET,
906 },
907 },
908 };
909
910 /*
911 * 'emif' class
912 * external memory interface no1
913 */
914
915 static struct omap_hwmod_class_sysconfig omap44xx_emif_sysc = {
916 .rev_offs = 0x0000,
917 };
918
919 static struct omap_hwmod_class omap44xx_emif_hwmod_class = {
920 .name = "emif",
921 .sysc = &omap44xx_emif_sysc,
922 };
923
924 /* emif1 */
925 static struct omap_hwmod omap44xx_emif1_hwmod = {
926 .name = "emif1",
927 .class = &omap44xx_emif_hwmod_class,
928 .clkdm_name = "l3_emif_clkdm",
929 .flags = HWMOD_INIT_NO_IDLE,
930 .main_clk = "ddrphy_ck",
931 .prcm = {
932 .omap4 = {
933 .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_1_CLKCTRL_OFFSET,
934 .context_offs = OMAP4_RM_MEMIF_EMIF_1_CONTEXT_OFFSET,
935 .modulemode = MODULEMODE_HWCTRL,
936 },
937 },
938 };
939
940 /* emif2 */
941 static struct omap_hwmod omap44xx_emif2_hwmod = {
942 .name = "emif2",
943 .class = &omap44xx_emif_hwmod_class,
944 .clkdm_name = "l3_emif_clkdm",
945 .flags = HWMOD_INIT_NO_IDLE,
946 .main_clk = "ddrphy_ck",
947 .prcm = {
948 .omap4 = {
949 .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_2_CLKCTRL_OFFSET,
950 .context_offs = OMAP4_RM_MEMIF_EMIF_2_CONTEXT_OFFSET,
951 .modulemode = MODULEMODE_HWCTRL,
952 },
953 },
954 };
955
956 /*
957 * 'fdif' class
958 * face detection hw accelerator module
959 */
960
961 static struct omap_hwmod_class_sysconfig omap44xx_fdif_sysc = {
962 .rev_offs = 0x0000,
963 .sysc_offs = 0x0010,
964 /*
965 * FDIF needs 100 OCP clk cycles delay after a softreset before
966 * accessing sysconfig again.
967 * The lowest frequency at the moment for L3 bus is 100 MHz, so
968 * 1usec delay is needed. Add an x2 margin to be safe (2 usecs).
969 *
970 * TODO: Indicate errata when available.
971 */
972 .srst_udelay = 2,
973 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
974 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
975 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
976 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
977 .sysc_fields = &omap_hwmod_sysc_type2,
978 };
979
980 static struct omap_hwmod_class omap44xx_fdif_hwmod_class = {
981 .name = "fdif",
982 .sysc = &omap44xx_fdif_sysc,
983 };
984
985 /* fdif */
986 static struct omap_hwmod omap44xx_fdif_hwmod = {
987 .name = "fdif",
988 .class = &omap44xx_fdif_hwmod_class,
989 .clkdm_name = "iss_clkdm",
990 .main_clk = "fdif_fck",
991 .prcm = {
992 .omap4 = {
993 .clkctrl_offs = OMAP4_CM_CAM_FDIF_CLKCTRL_OFFSET,
994 .context_offs = OMAP4_RM_CAM_FDIF_CONTEXT_OFFSET,
995 .modulemode = MODULEMODE_SWCTRL,
996 },
997 },
998 };
999
1000 /*
1001 * 'gpio' class
1002 * general purpose io module
1003 */
1004
1005 static struct omap_hwmod_class_sysconfig omap44xx_gpio_sysc = {
1006 .rev_offs = 0x0000,
1007 .sysc_offs = 0x0010,
1008 .syss_offs = 0x0114,
1009 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
1010 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1011 SYSS_HAS_RESET_STATUS),
1012 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1013 SIDLE_SMART_WKUP),
1014 .sysc_fields = &omap_hwmod_sysc_type1,
1015 };
1016
1017 static struct omap_hwmod_class omap44xx_gpio_hwmod_class = {
1018 .name = "gpio",
1019 .sysc = &omap44xx_gpio_sysc,
1020 .rev = 2,
1021 };
1022
1023 /* gpio dev_attr */
1024 static struct omap_gpio_dev_attr gpio_dev_attr = {
1025 .bank_width = 32,
1026 .dbck_flag = true,
1027 };
1028
1029 /* gpio1 */
1030 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
1031 { .role = "dbclk", .clk = "gpio1_dbclk" },
1032 };
1033
1034 static struct omap_hwmod omap44xx_gpio1_hwmod = {
1035 .name = "gpio1",
1036 .class = &omap44xx_gpio_hwmod_class,
1037 .clkdm_name = "l4_wkup_clkdm",
1038 .main_clk = "l4_wkup_clk_mux_ck",
1039 .prcm = {
1040 .omap4 = {
1041 .clkctrl_offs = OMAP4_CM_WKUP_GPIO1_CLKCTRL_OFFSET,
1042 .context_offs = OMAP4_RM_WKUP_GPIO1_CONTEXT_OFFSET,
1043 .modulemode = MODULEMODE_HWCTRL,
1044 },
1045 },
1046 .opt_clks = gpio1_opt_clks,
1047 .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
1048 .dev_attr = &gpio_dev_attr,
1049 };
1050
1051 /* gpio2 */
1052 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
1053 { .role = "dbclk", .clk = "gpio2_dbclk" },
1054 };
1055
1056 static struct omap_hwmod omap44xx_gpio2_hwmod = {
1057 .name = "gpio2",
1058 .class = &omap44xx_gpio_hwmod_class,
1059 .clkdm_name = "l4_per_clkdm",
1060 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1061 .main_clk = "l4_div_ck",
1062 .prcm = {
1063 .omap4 = {
1064 .clkctrl_offs = OMAP4_CM_L4PER_GPIO2_CLKCTRL_OFFSET,
1065 .context_offs = OMAP4_RM_L4PER_GPIO2_CONTEXT_OFFSET,
1066 .modulemode = MODULEMODE_HWCTRL,
1067 },
1068 },
1069 .opt_clks = gpio2_opt_clks,
1070 .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
1071 .dev_attr = &gpio_dev_attr,
1072 };
1073
1074 /* gpio3 */
1075 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
1076 { .role = "dbclk", .clk = "gpio3_dbclk" },
1077 };
1078
1079 static struct omap_hwmod omap44xx_gpio3_hwmod = {
1080 .name = "gpio3",
1081 .class = &omap44xx_gpio_hwmod_class,
1082 .clkdm_name = "l4_per_clkdm",
1083 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1084 .main_clk = "l4_div_ck",
1085 .prcm = {
1086 .omap4 = {
1087 .clkctrl_offs = OMAP4_CM_L4PER_GPIO3_CLKCTRL_OFFSET,
1088 .context_offs = OMAP4_RM_L4PER_GPIO3_CONTEXT_OFFSET,
1089 .modulemode = MODULEMODE_HWCTRL,
1090 },
1091 },
1092 .opt_clks = gpio3_opt_clks,
1093 .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
1094 .dev_attr = &gpio_dev_attr,
1095 };
1096
1097 /* gpio4 */
1098 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
1099 { .role = "dbclk", .clk = "gpio4_dbclk" },
1100 };
1101
1102 static struct omap_hwmod omap44xx_gpio4_hwmod = {
1103 .name = "gpio4",
1104 .class = &omap44xx_gpio_hwmod_class,
1105 .clkdm_name = "l4_per_clkdm",
1106 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1107 .main_clk = "l4_div_ck",
1108 .prcm = {
1109 .omap4 = {
1110 .clkctrl_offs = OMAP4_CM_L4PER_GPIO4_CLKCTRL_OFFSET,
1111 .context_offs = OMAP4_RM_L4PER_GPIO4_CONTEXT_OFFSET,
1112 .modulemode = MODULEMODE_HWCTRL,
1113 },
1114 },
1115 .opt_clks = gpio4_opt_clks,
1116 .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks),
1117 .dev_attr = &gpio_dev_attr,
1118 };
1119
1120 /* gpio5 */
1121 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
1122 { .role = "dbclk", .clk = "gpio5_dbclk" },
1123 };
1124
1125 static struct omap_hwmod omap44xx_gpio5_hwmod = {
1126 .name = "gpio5",
1127 .class = &omap44xx_gpio_hwmod_class,
1128 .clkdm_name = "l4_per_clkdm",
1129 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1130 .main_clk = "l4_div_ck",
1131 .prcm = {
1132 .omap4 = {
1133 .clkctrl_offs = OMAP4_CM_L4PER_GPIO5_CLKCTRL_OFFSET,
1134 .context_offs = OMAP4_RM_L4PER_GPIO5_CONTEXT_OFFSET,
1135 .modulemode = MODULEMODE_HWCTRL,
1136 },
1137 },
1138 .opt_clks = gpio5_opt_clks,
1139 .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks),
1140 .dev_attr = &gpio_dev_attr,
1141 };
1142
1143 /* gpio6 */
1144 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
1145 { .role = "dbclk", .clk = "gpio6_dbclk" },
1146 };
1147
1148 static struct omap_hwmod omap44xx_gpio6_hwmod = {
1149 .name = "gpio6",
1150 .class = &omap44xx_gpio_hwmod_class,
1151 .clkdm_name = "l4_per_clkdm",
1152 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1153 .main_clk = "l4_div_ck",
1154 .prcm = {
1155 .omap4 = {
1156 .clkctrl_offs = OMAP4_CM_L4PER_GPIO6_CLKCTRL_OFFSET,
1157 .context_offs = OMAP4_RM_L4PER_GPIO6_CONTEXT_OFFSET,
1158 .modulemode = MODULEMODE_HWCTRL,
1159 },
1160 },
1161 .opt_clks = gpio6_opt_clks,
1162 .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks),
1163 .dev_attr = &gpio_dev_attr,
1164 };
1165
1166 /*
1167 * 'gpmc' class
1168 * general purpose memory controller
1169 */
1170
1171 static struct omap_hwmod_class_sysconfig omap44xx_gpmc_sysc = {
1172 .rev_offs = 0x0000,
1173 .sysc_offs = 0x0010,
1174 .syss_offs = 0x0014,
1175 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1176 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1177 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1178 .sysc_fields = &omap_hwmod_sysc_type1,
1179 };
1180
1181 static struct omap_hwmod_class omap44xx_gpmc_hwmod_class = {
1182 .name = "gpmc",
1183 .sysc = &omap44xx_gpmc_sysc,
1184 };
1185
1186 /* gpmc */
1187 static struct omap_hwmod omap44xx_gpmc_hwmod = {
1188 .name = "gpmc",
1189 .class = &omap44xx_gpmc_hwmod_class,
1190 .clkdm_name = "l3_2_clkdm",
1191 /*
1192 * XXX HWMOD_INIT_NO_RESET should not be needed for this IP
1193 * block. It is not being added due to any known bugs with
1194 * resetting the GPMC IP block, but rather because any timings
1195 * set by the bootloader are not being correctly programmed by
1196 * the kernel from the board file or DT data.
1197 * HWMOD_INIT_NO_RESET should be removed ASAP.
1198 */
1199 .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
1200 .prcm = {
1201 .omap4 = {
1202 .clkctrl_offs = OMAP4_CM_L3_2_GPMC_CLKCTRL_OFFSET,
1203 .context_offs = OMAP4_RM_L3_2_GPMC_CONTEXT_OFFSET,
1204 .modulemode = MODULEMODE_HWCTRL,
1205 },
1206 },
1207 };
1208
1209 /*
1210 * 'gpu' class
1211 * 2d/3d graphics accelerator
1212 */
1213
1214 static struct omap_hwmod_class_sysconfig omap44xx_gpu_sysc = {
1215 .rev_offs = 0x1fc00,
1216 .sysc_offs = 0x1fc10,
1217 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
1218 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1219 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1220 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1221 .sysc_fields = &omap_hwmod_sysc_type2,
1222 };
1223
1224 static struct omap_hwmod_class omap44xx_gpu_hwmod_class = {
1225 .name = "gpu",
1226 .sysc = &omap44xx_gpu_sysc,
1227 };
1228
1229 /* gpu */
1230 static struct omap_hwmod omap44xx_gpu_hwmod = {
1231 .name = "gpu",
1232 .class = &omap44xx_gpu_hwmod_class,
1233 .clkdm_name = "l3_gfx_clkdm",
1234 .main_clk = "sgx_clk_mux",
1235 .prcm = {
1236 .omap4 = {
1237 .clkctrl_offs = OMAP4_CM_GFX_GFX_CLKCTRL_OFFSET,
1238 .context_offs = OMAP4_RM_GFX_GFX_CONTEXT_OFFSET,
1239 .modulemode = MODULEMODE_SWCTRL,
1240 },
1241 },
1242 };
1243
1244 /*
1245 * 'hdq1w' class
1246 * hdq / 1-wire serial interface controller
1247 */
1248
1249 static struct omap_hwmod_class_sysconfig omap44xx_hdq1w_sysc = {
1250 .rev_offs = 0x0000,
1251 .sysc_offs = 0x0014,
1252 .syss_offs = 0x0018,
1253 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SOFTRESET |
1254 SYSS_HAS_RESET_STATUS),
1255 .sysc_fields = &omap_hwmod_sysc_type1,
1256 };
1257
1258 static struct omap_hwmod_class omap44xx_hdq1w_hwmod_class = {
1259 .name = "hdq1w",
1260 .sysc = &omap44xx_hdq1w_sysc,
1261 };
1262
1263 /* hdq1w */
1264 static struct omap_hwmod omap44xx_hdq1w_hwmod = {
1265 .name = "hdq1w",
1266 .class = &omap44xx_hdq1w_hwmod_class,
1267 .clkdm_name = "l4_per_clkdm",
1268 .flags = HWMOD_INIT_NO_RESET, /* XXX temporary */
1269 .main_clk = "func_12m_fclk",
1270 .prcm = {
1271 .omap4 = {
1272 .clkctrl_offs = OMAP4_CM_L4PER_HDQ1W_CLKCTRL_OFFSET,
1273 .context_offs = OMAP4_RM_L4PER_HDQ1W_CONTEXT_OFFSET,
1274 .modulemode = MODULEMODE_SWCTRL,
1275 },
1276 },
1277 };
1278
1279 /*
1280 * 'hsi' class
1281 * mipi high-speed synchronous serial interface (multichannel and full-duplex
1282 * serial if)
1283 */
1284
1285 static struct omap_hwmod_class_sysconfig omap44xx_hsi_sysc = {
1286 .rev_offs = 0x0000,
1287 .sysc_offs = 0x0010,
1288 .syss_offs = 0x0014,
1289 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_EMUFREE |
1290 SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
1291 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1292 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1293 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1294 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1295 .sysc_fields = &omap_hwmod_sysc_type1,
1296 };
1297
1298 static struct omap_hwmod_class omap44xx_hsi_hwmod_class = {
1299 .name = "hsi",
1300 .sysc = &omap44xx_hsi_sysc,
1301 };
1302
1303 /* hsi */
1304 static struct omap_hwmod omap44xx_hsi_hwmod = {
1305 .name = "hsi",
1306 .class = &omap44xx_hsi_hwmod_class,
1307 .clkdm_name = "l3_init_clkdm",
1308 .main_clk = "hsi_fck",
1309 .prcm = {
1310 .omap4 = {
1311 .clkctrl_offs = OMAP4_CM_L3INIT_HSI_CLKCTRL_OFFSET,
1312 .context_offs = OMAP4_RM_L3INIT_HSI_CONTEXT_OFFSET,
1313 .modulemode = MODULEMODE_HWCTRL,
1314 },
1315 },
1316 };
1317
1318 /*
1319 * 'i2c' class
1320 * multimaster high-speed i2c controller
1321 */
1322
1323 static struct omap_hwmod_class_sysconfig omap44xx_i2c_sysc = {
1324 .sysc_offs = 0x0010,
1325 .syss_offs = 0x0090,
1326 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1327 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1328 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1329 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1330 SIDLE_SMART_WKUP),
1331 .clockact = CLOCKACT_TEST_ICLK,
1332 .sysc_fields = &omap_hwmod_sysc_type1,
1333 };
1334
1335 static struct omap_hwmod_class omap44xx_i2c_hwmod_class = {
1336 .name = "i2c",
1337 .sysc = &omap44xx_i2c_sysc,
1338 .rev = OMAP_I2C_IP_VERSION_2,
1339 .reset = &omap_i2c_reset,
1340 };
1341
1342 static struct omap_i2c_dev_attr i2c_dev_attr = {
1343 .flags = OMAP_I2C_FLAG_BUS_SHIFT_NONE,
1344 };
1345
1346 /* i2c1 */
1347 static struct omap_hwmod omap44xx_i2c1_hwmod = {
1348 .name = "i2c1",
1349 .class = &omap44xx_i2c_hwmod_class,
1350 .clkdm_name = "l4_per_clkdm",
1351 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1352 .main_clk = "func_96m_fclk",
1353 .prcm = {
1354 .omap4 = {
1355 .clkctrl_offs = OMAP4_CM_L4PER_I2C1_CLKCTRL_OFFSET,
1356 .context_offs = OMAP4_RM_L4PER_I2C1_CONTEXT_OFFSET,
1357 .modulemode = MODULEMODE_SWCTRL,
1358 },
1359 },
1360 .dev_attr = &i2c_dev_attr,
1361 };
1362
1363 /* i2c2 */
1364 static struct omap_hwmod omap44xx_i2c2_hwmod = {
1365 .name = "i2c2",
1366 .class = &omap44xx_i2c_hwmod_class,
1367 .clkdm_name = "l4_per_clkdm",
1368 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1369 .main_clk = "func_96m_fclk",
1370 .prcm = {
1371 .omap4 = {
1372 .clkctrl_offs = OMAP4_CM_L4PER_I2C2_CLKCTRL_OFFSET,
1373 .context_offs = OMAP4_RM_L4PER_I2C2_CONTEXT_OFFSET,
1374 .modulemode = MODULEMODE_SWCTRL,
1375 },
1376 },
1377 .dev_attr = &i2c_dev_attr,
1378 };
1379
1380 /* i2c3 */
1381 static struct omap_hwmod omap44xx_i2c3_hwmod = {
1382 .name = "i2c3",
1383 .class = &omap44xx_i2c_hwmod_class,
1384 .clkdm_name = "l4_per_clkdm",
1385 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1386 .main_clk = "func_96m_fclk",
1387 .prcm = {
1388 .omap4 = {
1389 .clkctrl_offs = OMAP4_CM_L4PER_I2C3_CLKCTRL_OFFSET,
1390 .context_offs = OMAP4_RM_L4PER_I2C3_CONTEXT_OFFSET,
1391 .modulemode = MODULEMODE_SWCTRL,
1392 },
1393 },
1394 .dev_attr = &i2c_dev_attr,
1395 };
1396
1397 /* i2c4 */
1398 static struct omap_hwmod omap44xx_i2c4_hwmod = {
1399 .name = "i2c4",
1400 .class = &omap44xx_i2c_hwmod_class,
1401 .clkdm_name = "l4_per_clkdm",
1402 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1403 .main_clk = "func_96m_fclk",
1404 .prcm = {
1405 .omap4 = {
1406 .clkctrl_offs = OMAP4_CM_L4PER_I2C4_CLKCTRL_OFFSET,
1407 .context_offs = OMAP4_RM_L4PER_I2C4_CONTEXT_OFFSET,
1408 .modulemode = MODULEMODE_SWCTRL,
1409 },
1410 },
1411 .dev_attr = &i2c_dev_attr,
1412 };
1413
1414 /*
1415 * 'ipu' class
1416 * imaging processor unit
1417 */
1418
1419 static struct omap_hwmod_class omap44xx_ipu_hwmod_class = {
1420 .name = "ipu",
1421 };
1422
1423 /* ipu */
1424 static struct omap_hwmod_rst_info omap44xx_ipu_resets[] = {
1425 { .name = "cpu0", .rst_shift = 0 },
1426 { .name = "cpu1", .rst_shift = 1 },
1427 };
1428
1429 static struct omap_hwmod omap44xx_ipu_hwmod = {
1430 .name = "ipu",
1431 .class = &omap44xx_ipu_hwmod_class,
1432 .clkdm_name = "ducati_clkdm",
1433 .rst_lines = omap44xx_ipu_resets,
1434 .rst_lines_cnt = ARRAY_SIZE(omap44xx_ipu_resets),
1435 .main_clk = "ducati_clk_mux_ck",
1436 .prcm = {
1437 .omap4 = {
1438 .clkctrl_offs = OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET,
1439 .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
1440 .context_offs = OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET,
1441 .modulemode = MODULEMODE_HWCTRL,
1442 },
1443 },
1444 };
1445
1446 /*
1447 * 'iss' class
1448 * external images sensor pixel data processor
1449 */
1450
1451 static struct omap_hwmod_class_sysconfig omap44xx_iss_sysc = {
1452 .rev_offs = 0x0000,
1453 .sysc_offs = 0x0010,
1454 /*
1455 * ISS needs 100 OCP clk cycles delay after a softreset before
1456 * accessing sysconfig again.
1457 * The lowest frequency at the moment for L3 bus is 100 MHz, so
1458 * 1usec delay is needed. Add an x2 margin to be safe (2 usecs).
1459 *
1460 * TODO: Indicate errata when available.
1461 */
1462 .srst_udelay = 2,
1463 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
1464 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1465 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1466 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1467 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1468 .sysc_fields = &omap_hwmod_sysc_type2,
1469 };
1470
1471 static struct omap_hwmod_class omap44xx_iss_hwmod_class = {
1472 .name = "iss",
1473 .sysc = &omap44xx_iss_sysc,
1474 };
1475
1476 /* iss */
1477 static struct omap_hwmod_opt_clk iss_opt_clks[] = {
1478 { .role = "ctrlclk", .clk = "iss_ctrlclk" },
1479 };
1480
1481 static struct omap_hwmod omap44xx_iss_hwmod = {
1482 .name = "iss",
1483 .class = &omap44xx_iss_hwmod_class,
1484 .clkdm_name = "iss_clkdm",
1485 .main_clk = "ducati_clk_mux_ck",
1486 .prcm = {
1487 .omap4 = {
1488 .clkctrl_offs = OMAP4_CM_CAM_ISS_CLKCTRL_OFFSET,
1489 .context_offs = OMAP4_RM_CAM_ISS_CONTEXT_OFFSET,
1490 .modulemode = MODULEMODE_SWCTRL,
1491 },
1492 },
1493 .opt_clks = iss_opt_clks,
1494 .opt_clks_cnt = ARRAY_SIZE(iss_opt_clks),
1495 };
1496
1497 /*
1498 * 'iva' class
1499 * multi-standard video encoder/decoder hardware accelerator
1500 */
1501
1502 static struct omap_hwmod_class omap44xx_iva_hwmod_class = {
1503 .name = "iva",
1504 };
1505
1506 /* iva */
1507 static struct omap_hwmod_rst_info omap44xx_iva_resets[] = {
1508 { .name = "seq0", .rst_shift = 0 },
1509 { .name = "seq1", .rst_shift = 1 },
1510 { .name = "logic", .rst_shift = 2 },
1511 };
1512
1513 static struct omap_hwmod omap44xx_iva_hwmod = {
1514 .name = "iva",
1515 .class = &omap44xx_iva_hwmod_class,
1516 .clkdm_name = "ivahd_clkdm",
1517 .rst_lines = omap44xx_iva_resets,
1518 .rst_lines_cnt = ARRAY_SIZE(omap44xx_iva_resets),
1519 .main_clk = "dpll_iva_m5x2_ck",
1520 .prcm = {
1521 .omap4 = {
1522 .clkctrl_offs = OMAP4_CM_IVAHD_IVAHD_CLKCTRL_OFFSET,
1523 .rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET,
1524 .context_offs = OMAP4_RM_IVAHD_IVAHD_CONTEXT_OFFSET,
1525 .modulemode = MODULEMODE_HWCTRL,
1526 },
1527 },
1528 };
1529
1530 /*
1531 * 'kbd' class
1532 * keyboard controller
1533 */
1534
1535 static struct omap_hwmod_class_sysconfig omap44xx_kbd_sysc = {
1536 .rev_offs = 0x0000,
1537 .sysc_offs = 0x0010,
1538 .syss_offs = 0x0014,
1539 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1540 SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
1541 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1542 SYSS_HAS_RESET_STATUS),
1543 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1544 .sysc_fields = &omap_hwmod_sysc_type1,
1545 };
1546
1547 static struct omap_hwmod_class omap44xx_kbd_hwmod_class = {
1548 .name = "kbd",
1549 .sysc = &omap44xx_kbd_sysc,
1550 };
1551
1552 /* kbd */
1553 static struct omap_hwmod omap44xx_kbd_hwmod = {
1554 .name = "kbd",
1555 .class = &omap44xx_kbd_hwmod_class,
1556 .clkdm_name = "l4_wkup_clkdm",
1557 .main_clk = "sys_32k_ck",
1558 .prcm = {
1559 .omap4 = {
1560 .clkctrl_offs = OMAP4_CM_WKUP_KEYBOARD_CLKCTRL_OFFSET,
1561 .context_offs = OMAP4_RM_WKUP_KEYBOARD_CONTEXT_OFFSET,
1562 .modulemode = MODULEMODE_SWCTRL,
1563 },
1564 },
1565 };
1566
1567 /*
1568 * 'mailbox' class
1569 * mailbox module allowing communication between the on-chip processors using a
1570 * queued mailbox-interrupt mechanism.
1571 */
1572
1573 static struct omap_hwmod_class_sysconfig omap44xx_mailbox_sysc = {
1574 .rev_offs = 0x0000,
1575 .sysc_offs = 0x0010,
1576 .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1577 SYSC_HAS_SOFTRESET),
1578 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1579 .sysc_fields = &omap_hwmod_sysc_type2,
1580 };
1581
1582 static struct omap_hwmod_class omap44xx_mailbox_hwmod_class = {
1583 .name = "mailbox",
1584 .sysc = &omap44xx_mailbox_sysc,
1585 };
1586
1587 /* mailbox */
1588 static struct omap_hwmod omap44xx_mailbox_hwmod = {
1589 .name = "mailbox",
1590 .class = &omap44xx_mailbox_hwmod_class,
1591 .clkdm_name = "l4_cfg_clkdm",
1592 .prcm = {
1593 .omap4 = {
1594 .clkctrl_offs = OMAP4_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET,
1595 .context_offs = OMAP4_RM_L4CFG_MAILBOX_CONTEXT_OFFSET,
1596 },
1597 },
1598 };
1599
1600 /*
1601 * 'mcasp' class
1602 * multi-channel audio serial port controller
1603 */
1604
1605 /* The IP is not compliant to type1 / type2 scheme */
1606 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_mcasp = {
1607 .sidle_shift = 0,
1608 };
1609
1610 static struct omap_hwmod_class_sysconfig omap44xx_mcasp_sysc = {
1611 .sysc_offs = 0x0004,
1612 .sysc_flags = SYSC_HAS_SIDLEMODE,
1613 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1614 SIDLE_SMART_WKUP),
1615 .sysc_fields = &omap_hwmod_sysc_type_mcasp,
1616 };
1617
1618 static struct omap_hwmod_class omap44xx_mcasp_hwmod_class = {
1619 .name = "mcasp",
1620 .sysc = &omap44xx_mcasp_sysc,
1621 };
1622
1623 /* mcasp */
1624 static struct omap_hwmod omap44xx_mcasp_hwmod = {
1625 .name = "mcasp",
1626 .class = &omap44xx_mcasp_hwmod_class,
1627 .clkdm_name = "abe_clkdm",
1628 .main_clk = "func_mcasp_abe_gfclk",
1629 .prcm = {
1630 .omap4 = {
1631 .clkctrl_offs = OMAP4_CM1_ABE_MCASP_CLKCTRL_OFFSET,
1632 .context_offs = OMAP4_RM_ABE_MCASP_CONTEXT_OFFSET,
1633 .modulemode = MODULEMODE_SWCTRL,
1634 },
1635 },
1636 };
1637
1638 /*
1639 * 'mcbsp' class
1640 * multi channel buffered serial port controller
1641 */
1642
1643 static struct omap_hwmod_class_sysconfig omap44xx_mcbsp_sysc = {
1644 .sysc_offs = 0x008c,
1645 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
1646 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1647 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1648 .sysc_fields = &omap_hwmod_sysc_type1,
1649 };
1650
1651 static struct omap_hwmod_class omap44xx_mcbsp_hwmod_class = {
1652 .name = "mcbsp",
1653 .sysc = &omap44xx_mcbsp_sysc,
1654 .rev = MCBSP_CONFIG_TYPE4,
1655 };
1656
1657 /* mcbsp1 */
1658 static struct omap_hwmod_opt_clk mcbsp1_opt_clks[] = {
1659 { .role = "pad_fck", .clk = "pad_clks_ck" },
1660 { .role = "prcm_fck", .clk = "mcbsp1_sync_mux_ck" },
1661 };
1662
1663 static struct omap_hwmod omap44xx_mcbsp1_hwmod = {
1664 .name = "mcbsp1",
1665 .class = &omap44xx_mcbsp_hwmod_class,
1666 .clkdm_name = "abe_clkdm",
1667 .main_clk = "func_mcbsp1_gfclk",
1668 .prcm = {
1669 .omap4 = {
1670 .clkctrl_offs = OMAP4_CM1_ABE_MCBSP1_CLKCTRL_OFFSET,
1671 .context_offs = OMAP4_RM_ABE_MCBSP1_CONTEXT_OFFSET,
1672 .modulemode = MODULEMODE_SWCTRL,
1673 },
1674 },
1675 .opt_clks = mcbsp1_opt_clks,
1676 .opt_clks_cnt = ARRAY_SIZE(mcbsp1_opt_clks),
1677 };
1678
1679 /* mcbsp2 */
1680 static struct omap_hwmod_opt_clk mcbsp2_opt_clks[] = {
1681 { .role = "pad_fck", .clk = "pad_clks_ck" },
1682 { .role = "prcm_fck", .clk = "mcbsp2_sync_mux_ck" },
1683 };
1684
1685 static struct omap_hwmod omap44xx_mcbsp2_hwmod = {
1686 .name = "mcbsp2",
1687 .class = &omap44xx_mcbsp_hwmod_class,
1688 .clkdm_name = "abe_clkdm",
1689 .main_clk = "func_mcbsp2_gfclk",
1690 .prcm = {
1691 .omap4 = {
1692 .clkctrl_offs = OMAP4_CM1_ABE_MCBSP2_CLKCTRL_OFFSET,
1693 .context_offs = OMAP4_RM_ABE_MCBSP2_CONTEXT_OFFSET,
1694 .modulemode = MODULEMODE_SWCTRL,
1695 },
1696 },
1697 .opt_clks = mcbsp2_opt_clks,
1698 .opt_clks_cnt = ARRAY_SIZE(mcbsp2_opt_clks),
1699 };
1700
1701 /* mcbsp3 */
1702 static struct omap_hwmod_opt_clk mcbsp3_opt_clks[] = {
1703 { .role = "pad_fck", .clk = "pad_clks_ck" },
1704 { .role = "prcm_fck", .clk = "mcbsp3_sync_mux_ck" },
1705 };
1706
1707 static struct omap_hwmod omap44xx_mcbsp3_hwmod = {
1708 .name = "mcbsp3",
1709 .class = &omap44xx_mcbsp_hwmod_class,
1710 .clkdm_name = "abe_clkdm",
1711 .main_clk = "func_mcbsp3_gfclk",
1712 .prcm = {
1713 .omap4 = {
1714 .clkctrl_offs = OMAP4_CM1_ABE_MCBSP3_CLKCTRL_OFFSET,
1715 .context_offs = OMAP4_RM_ABE_MCBSP3_CONTEXT_OFFSET,
1716 .modulemode = MODULEMODE_SWCTRL,
1717 },
1718 },
1719 .opt_clks = mcbsp3_opt_clks,
1720 .opt_clks_cnt = ARRAY_SIZE(mcbsp3_opt_clks),
1721 };
1722
1723 /* mcbsp4 */
1724 static struct omap_hwmod_opt_clk mcbsp4_opt_clks[] = {
1725 { .role = "pad_fck", .clk = "pad_clks_ck" },
1726 { .role = "prcm_fck", .clk = "mcbsp4_sync_mux_ck" },
1727 };
1728
1729 static struct omap_hwmod omap44xx_mcbsp4_hwmod = {
1730 .name = "mcbsp4",
1731 .class = &omap44xx_mcbsp_hwmod_class,
1732 .clkdm_name = "l4_per_clkdm",
1733 .main_clk = "per_mcbsp4_gfclk",
1734 .prcm = {
1735 .omap4 = {
1736 .clkctrl_offs = OMAP4_CM_L4PER_MCBSP4_CLKCTRL_OFFSET,
1737 .context_offs = OMAP4_RM_L4PER_MCBSP4_CONTEXT_OFFSET,
1738 .modulemode = MODULEMODE_SWCTRL,
1739 },
1740 },
1741 .opt_clks = mcbsp4_opt_clks,
1742 .opt_clks_cnt = ARRAY_SIZE(mcbsp4_opt_clks),
1743 };
1744
1745 /*
1746 * 'mcpdm' class
1747 * multi channel pdm controller (proprietary interface with phoenix power
1748 * ic)
1749 */
1750
1751 static struct omap_hwmod_class_sysconfig omap44xx_mcpdm_sysc = {
1752 .rev_offs = 0x0000,
1753 .sysc_offs = 0x0010,
1754 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1755 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1756 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1757 SIDLE_SMART_WKUP),
1758 .sysc_fields = &omap_hwmod_sysc_type2,
1759 };
1760
1761 static struct omap_hwmod_class omap44xx_mcpdm_hwmod_class = {
1762 .name = "mcpdm",
1763 .sysc = &omap44xx_mcpdm_sysc,
1764 };
1765
1766 /* mcpdm */
1767 static struct omap_hwmod omap44xx_mcpdm_hwmod = {
1768 .name = "mcpdm",
1769 .class = &omap44xx_mcpdm_hwmod_class,
1770 .clkdm_name = "abe_clkdm",
1771 /*
1772 * It's suspected that the McPDM requires an off-chip main
1773 * functional clock, controlled via I2C. This IP block is
1774 * currently reset very early during boot, before I2C is
1775 * available, so it doesn't seem that we have any choice in
1776 * the kernel other than to avoid resetting it.
1777 *
1778 * Also, McPDM needs to be configured to NO_IDLE mode when it
1779 * is in used otherwise vital clocks will be gated which
1780 * results 'slow motion' audio playback.
1781 */
1782 .flags = HWMOD_EXT_OPT_MAIN_CLK | HWMOD_SWSUP_SIDLE,
1783 .main_clk = "pad_clks_ck",
1784 .prcm = {
1785 .omap4 = {
1786 .clkctrl_offs = OMAP4_CM1_ABE_PDM_CLKCTRL_OFFSET,
1787 .context_offs = OMAP4_RM_ABE_PDM_CONTEXT_OFFSET,
1788 .modulemode = MODULEMODE_SWCTRL,
1789 },
1790 },
1791 };
1792
1793 /*
1794 * 'mcspi' class
1795 * multichannel serial port interface (mcspi) / master/slave synchronous serial
1796 * bus
1797 */
1798
1799 static struct omap_hwmod_class_sysconfig omap44xx_mcspi_sysc = {
1800 .rev_offs = 0x0000,
1801 .sysc_offs = 0x0010,
1802 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1803 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1804 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1805 SIDLE_SMART_WKUP),
1806 .sysc_fields = &omap_hwmod_sysc_type2,
1807 };
1808
1809 static struct omap_hwmod_class omap44xx_mcspi_hwmod_class = {
1810 .name = "mcspi",
1811 .sysc = &omap44xx_mcspi_sysc,
1812 .rev = OMAP4_MCSPI_REV,
1813 };
1814
1815 /* mcspi1 */
1816 static struct omap_hwmod_dma_info omap44xx_mcspi1_sdma_reqs[] = {
1817 { .name = "tx0", .dma_req = 34 + OMAP44XX_DMA_REQ_START },
1818 { .name = "rx0", .dma_req = 35 + OMAP44XX_DMA_REQ_START },
1819 { .name = "tx1", .dma_req = 36 + OMAP44XX_DMA_REQ_START },
1820 { .name = "rx1", .dma_req = 37 + OMAP44XX_DMA_REQ_START },
1821 { .name = "tx2", .dma_req = 38 + OMAP44XX_DMA_REQ_START },
1822 { .name = "rx2", .dma_req = 39 + OMAP44XX_DMA_REQ_START },
1823 { .name = "tx3", .dma_req = 40 + OMAP44XX_DMA_REQ_START },
1824 { .name = "rx3", .dma_req = 41 + OMAP44XX_DMA_REQ_START },
1825 { .dma_req = -1 }
1826 };
1827
1828 /* mcspi1 dev_attr */
1829 static struct omap2_mcspi_dev_attr mcspi1_dev_attr = {
1830 .num_chipselect = 4,
1831 };
1832
1833 static struct omap_hwmod omap44xx_mcspi1_hwmod = {
1834 .name = "mcspi1",
1835 .class = &omap44xx_mcspi_hwmod_class,
1836 .clkdm_name = "l4_per_clkdm",
1837 .sdma_reqs = omap44xx_mcspi1_sdma_reqs,
1838 .main_clk = "func_48m_fclk",
1839 .prcm = {
1840 .omap4 = {
1841 .clkctrl_offs = OMAP4_CM_L4PER_MCSPI1_CLKCTRL_OFFSET,
1842 .context_offs = OMAP4_RM_L4PER_MCSPI1_CONTEXT_OFFSET,
1843 .modulemode = MODULEMODE_SWCTRL,
1844 },
1845 },
1846 .dev_attr = &mcspi1_dev_attr,
1847 };
1848
1849 /* mcspi2 */
1850 static struct omap_hwmod_dma_info omap44xx_mcspi2_sdma_reqs[] = {
1851 { .name = "tx0", .dma_req = 42 + OMAP44XX_DMA_REQ_START },
1852 { .name = "rx0", .dma_req = 43 + OMAP44XX_DMA_REQ_START },
1853 { .name = "tx1", .dma_req = 44 + OMAP44XX_DMA_REQ_START },
1854 { .name = "rx1", .dma_req = 45 + OMAP44XX_DMA_REQ_START },
1855 { .dma_req = -1 }
1856 };
1857
1858 /* mcspi2 dev_attr */
1859 static struct omap2_mcspi_dev_attr mcspi2_dev_attr = {
1860 .num_chipselect = 2,
1861 };
1862
1863 static struct omap_hwmod omap44xx_mcspi2_hwmod = {
1864 .name = "mcspi2",
1865 .class = &omap44xx_mcspi_hwmod_class,
1866 .clkdm_name = "l4_per_clkdm",
1867 .sdma_reqs = omap44xx_mcspi2_sdma_reqs,
1868 .main_clk = "func_48m_fclk",
1869 .prcm = {
1870 .omap4 = {
1871 .clkctrl_offs = OMAP4_CM_L4PER_MCSPI2_CLKCTRL_OFFSET,
1872 .context_offs = OMAP4_RM_L4PER_MCSPI2_CONTEXT_OFFSET,
1873 .modulemode = MODULEMODE_SWCTRL,
1874 },
1875 },
1876 .dev_attr = &mcspi2_dev_attr,
1877 };
1878
1879 /* mcspi3 */
1880 static struct omap_hwmod_dma_info omap44xx_mcspi3_sdma_reqs[] = {
1881 { .name = "tx0", .dma_req = 14 + OMAP44XX_DMA_REQ_START },
1882 { .name = "rx0", .dma_req = 15 + OMAP44XX_DMA_REQ_START },
1883 { .name = "tx1", .dma_req = 22 + OMAP44XX_DMA_REQ_START },
1884 { .name = "rx1", .dma_req = 23 + OMAP44XX_DMA_REQ_START },
1885 { .dma_req = -1 }
1886 };
1887
1888 /* mcspi3 dev_attr */
1889 static struct omap2_mcspi_dev_attr mcspi3_dev_attr = {
1890 .num_chipselect = 2,
1891 };
1892
1893 static struct omap_hwmod omap44xx_mcspi3_hwmod = {
1894 .name = "mcspi3",
1895 .class = &omap44xx_mcspi_hwmod_class,
1896 .clkdm_name = "l4_per_clkdm",
1897 .sdma_reqs = omap44xx_mcspi3_sdma_reqs,
1898 .main_clk = "func_48m_fclk",
1899 .prcm = {
1900 .omap4 = {
1901 .clkctrl_offs = OMAP4_CM_L4PER_MCSPI3_CLKCTRL_OFFSET,
1902 .context_offs = OMAP4_RM_L4PER_MCSPI3_CONTEXT_OFFSET,
1903 .modulemode = MODULEMODE_SWCTRL,
1904 },
1905 },
1906 .dev_attr = &mcspi3_dev_attr,
1907 };
1908
1909 /* mcspi4 */
1910 static struct omap_hwmod_dma_info omap44xx_mcspi4_sdma_reqs[] = {
1911 { .name = "tx0", .dma_req = 69 + OMAP44XX_DMA_REQ_START },
1912 { .name = "rx0", .dma_req = 70 + OMAP44XX_DMA_REQ_START },
1913 { .dma_req = -1 }
1914 };
1915
1916 /* mcspi4 dev_attr */
1917 static struct omap2_mcspi_dev_attr mcspi4_dev_attr = {
1918 .num_chipselect = 1,
1919 };
1920
1921 static struct omap_hwmod omap44xx_mcspi4_hwmod = {
1922 .name = "mcspi4",
1923 .class = &omap44xx_mcspi_hwmod_class,
1924 .clkdm_name = "l4_per_clkdm",
1925 .sdma_reqs = omap44xx_mcspi4_sdma_reqs,
1926 .main_clk = "func_48m_fclk",
1927 .prcm = {
1928 .omap4 = {
1929 .clkctrl_offs = OMAP4_CM_L4PER_MCSPI4_CLKCTRL_OFFSET,
1930 .context_offs = OMAP4_RM_L4PER_MCSPI4_CONTEXT_OFFSET,
1931 .modulemode = MODULEMODE_SWCTRL,
1932 },
1933 },
1934 .dev_attr = &mcspi4_dev_attr,
1935 };
1936
1937 /*
1938 * 'mmc' class
1939 * multimedia card high-speed/sd/sdio (mmc/sd/sdio) host controller
1940 */
1941
1942 static struct omap_hwmod_class_sysconfig omap44xx_mmc_sysc = {
1943 .rev_offs = 0x0000,
1944 .sysc_offs = 0x0010,
1945 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
1946 SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1947 SYSC_HAS_SOFTRESET),
1948 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1949 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1950 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1951 .sysc_fields = &omap_hwmod_sysc_type2,
1952 };
1953
1954 static struct omap_hwmod_class omap44xx_mmc_hwmod_class = {
1955 .name = "mmc",
1956 .sysc = &omap44xx_mmc_sysc,
1957 };
1958
1959 /* mmc1 */
1960 static struct omap_hwmod_dma_info omap44xx_mmc1_sdma_reqs[] = {
1961 { .name = "tx", .dma_req = 60 + OMAP44XX_DMA_REQ_START },
1962 { .name = "rx", .dma_req = 61 + OMAP44XX_DMA_REQ_START },
1963 { .dma_req = -1 }
1964 };
1965
1966 /* mmc1 dev_attr */
1967 static struct omap_hsmmc_dev_attr mmc1_dev_attr = {
1968 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1969 };
1970
1971 static struct omap_hwmod omap44xx_mmc1_hwmod = {
1972 .name = "mmc1",
1973 .class = &omap44xx_mmc_hwmod_class,
1974 .clkdm_name = "l3_init_clkdm",
1975 .sdma_reqs = omap44xx_mmc1_sdma_reqs,
1976 .main_clk = "hsmmc1_fclk",
1977 .prcm = {
1978 .omap4 = {
1979 .clkctrl_offs = OMAP4_CM_L3INIT_MMC1_CLKCTRL_OFFSET,
1980 .context_offs = OMAP4_RM_L3INIT_MMC1_CONTEXT_OFFSET,
1981 .modulemode = MODULEMODE_SWCTRL,
1982 },
1983 },
1984 .dev_attr = &mmc1_dev_attr,
1985 };
1986
1987 /* mmc2 */
1988 static struct omap_hwmod_dma_info omap44xx_mmc2_sdma_reqs[] = {
1989 { .name = "tx", .dma_req = 46 + OMAP44XX_DMA_REQ_START },
1990 { .name = "rx", .dma_req = 47 + OMAP44XX_DMA_REQ_START },
1991 { .dma_req = -1 }
1992 };
1993
1994 static struct omap_hwmod omap44xx_mmc2_hwmod = {
1995 .name = "mmc2",
1996 .class = &omap44xx_mmc_hwmod_class,
1997 .clkdm_name = "l3_init_clkdm",
1998 .sdma_reqs = omap44xx_mmc2_sdma_reqs,
1999 .main_clk = "hsmmc2_fclk",
2000 .prcm = {
2001 .omap4 = {
2002 .clkctrl_offs = OMAP4_CM_L3INIT_MMC2_CLKCTRL_OFFSET,
2003 .context_offs = OMAP4_RM_L3INIT_MMC2_CONTEXT_OFFSET,
2004 .modulemode = MODULEMODE_SWCTRL,
2005 },
2006 },
2007 };
2008
2009 /* mmc3 */
2010 static struct omap_hwmod_dma_info omap44xx_mmc3_sdma_reqs[] = {
2011 { .name = "tx", .dma_req = 76 + OMAP44XX_DMA_REQ_START },
2012 { .name = "rx", .dma_req = 77 + OMAP44XX_DMA_REQ_START },
2013 { .dma_req = -1 }
2014 };
2015
2016 static struct omap_hwmod omap44xx_mmc3_hwmod = {
2017 .name = "mmc3",
2018 .class = &omap44xx_mmc_hwmod_class,
2019 .clkdm_name = "l4_per_clkdm",
2020 .sdma_reqs = omap44xx_mmc3_sdma_reqs,
2021 .main_clk = "func_48m_fclk",
2022 .prcm = {
2023 .omap4 = {
2024 .clkctrl_offs = OMAP4_CM_L4PER_MMCSD3_CLKCTRL_OFFSET,
2025 .context_offs = OMAP4_RM_L4PER_MMCSD3_CONTEXT_OFFSET,
2026 .modulemode = MODULEMODE_SWCTRL,
2027 },
2028 },
2029 };
2030
2031 /* mmc4 */
2032 static struct omap_hwmod_dma_info omap44xx_mmc4_sdma_reqs[] = {
2033 { .name = "tx", .dma_req = 56 + OMAP44XX_DMA_REQ_START },
2034 { .name = "rx", .dma_req = 57 + OMAP44XX_DMA_REQ_START },
2035 { .dma_req = -1 }
2036 };
2037
2038 static struct omap_hwmod omap44xx_mmc4_hwmod = {
2039 .name = "mmc4",
2040 .class = &omap44xx_mmc_hwmod_class,
2041 .clkdm_name = "l4_per_clkdm",
2042 .sdma_reqs = omap44xx_mmc4_sdma_reqs,
2043 .main_clk = "func_48m_fclk",
2044 .prcm = {
2045 .omap4 = {
2046 .clkctrl_offs = OMAP4_CM_L4PER_MMCSD4_CLKCTRL_OFFSET,
2047 .context_offs = OMAP4_RM_L4PER_MMCSD4_CONTEXT_OFFSET,
2048 .modulemode = MODULEMODE_SWCTRL,
2049 },
2050 },
2051 };
2052
2053 /* mmc5 */
2054 static struct omap_hwmod_dma_info omap44xx_mmc5_sdma_reqs[] = {
2055 { .name = "tx", .dma_req = 58 + OMAP44XX_DMA_REQ_START },
2056 { .name = "rx", .dma_req = 59 + OMAP44XX_DMA_REQ_START },
2057 { .dma_req = -1 }
2058 };
2059
2060 static struct omap_hwmod omap44xx_mmc5_hwmod = {
2061 .name = "mmc5",
2062 .class = &omap44xx_mmc_hwmod_class,
2063 .clkdm_name = "l4_per_clkdm",
2064 .sdma_reqs = omap44xx_mmc5_sdma_reqs,
2065 .main_clk = "func_48m_fclk",
2066 .prcm = {
2067 .omap4 = {
2068 .clkctrl_offs = OMAP4_CM_L4PER_MMCSD5_CLKCTRL_OFFSET,
2069 .context_offs = OMAP4_RM_L4PER_MMCSD5_CONTEXT_OFFSET,
2070 .modulemode = MODULEMODE_SWCTRL,
2071 },
2072 },
2073 };
2074
2075 /*
2076 * 'mmu' class
2077 * The memory management unit performs virtual to physical address translation
2078 * for its requestors.
2079 */
2080
2081 static struct omap_hwmod_class_sysconfig mmu_sysc = {
2082 .rev_offs = 0x000,
2083 .sysc_offs = 0x010,
2084 .syss_offs = 0x014,
2085 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
2086 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
2087 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2088 .sysc_fields = &omap_hwmod_sysc_type1,
2089 };
2090
2091 static struct omap_hwmod_class omap44xx_mmu_hwmod_class = {
2092 .name = "mmu",
2093 .sysc = &mmu_sysc,
2094 };
2095
2096 /* mmu ipu */
2097
2098 static struct omap_mmu_dev_attr mmu_ipu_dev_attr = {
2099 .nr_tlb_entries = 32,
2100 };
2101
2102 static struct omap_hwmod omap44xx_mmu_ipu_hwmod;
2103 static struct omap_hwmod_rst_info omap44xx_mmu_ipu_resets[] = {
2104 { .name = "mmu_cache", .rst_shift = 2 },
2105 };
2106
2107 static struct omap_hwmod_addr_space omap44xx_mmu_ipu_addrs[] = {
2108 {
2109 .pa_start = 0x55082000,
2110 .pa_end = 0x550820ff,
2111 .flags = ADDR_TYPE_RT,
2112 },
2113 { }
2114 };
2115
2116 /* l3_main_2 -> mmu_ipu */
2117 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__mmu_ipu = {
2118 .master = &omap44xx_l3_main_2_hwmod,
2119 .slave = &omap44xx_mmu_ipu_hwmod,
2120 .clk = "l3_div_ck",
2121 .addr = omap44xx_mmu_ipu_addrs,
2122 .user = OCP_USER_MPU | OCP_USER_SDMA,
2123 };
2124
2125 static struct omap_hwmod omap44xx_mmu_ipu_hwmod = {
2126 .name = "mmu_ipu",
2127 .class = &omap44xx_mmu_hwmod_class,
2128 .clkdm_name = "ducati_clkdm",
2129 .rst_lines = omap44xx_mmu_ipu_resets,
2130 .rst_lines_cnt = ARRAY_SIZE(omap44xx_mmu_ipu_resets),
2131 .main_clk = "ducati_clk_mux_ck",
2132 .prcm = {
2133 .omap4 = {
2134 .clkctrl_offs = OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET,
2135 .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
2136 .context_offs = OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET,
2137 .modulemode = MODULEMODE_HWCTRL,
2138 },
2139 },
2140 .dev_attr = &mmu_ipu_dev_attr,
2141 };
2142
2143 /* mmu dsp */
2144
2145 static struct omap_mmu_dev_attr mmu_dsp_dev_attr = {
2146 .nr_tlb_entries = 32,
2147 };
2148
2149 static struct omap_hwmod omap44xx_mmu_dsp_hwmod;
2150 static struct omap_hwmod_rst_info omap44xx_mmu_dsp_resets[] = {
2151 { .name = "mmu_cache", .rst_shift = 1 },
2152 };
2153
2154 static struct omap_hwmod_addr_space omap44xx_mmu_dsp_addrs[] = {
2155 {
2156 .pa_start = 0x4a066000,
2157 .pa_end = 0x4a0660ff,
2158 .flags = ADDR_TYPE_RT,
2159 },
2160 { }
2161 };
2162
2163 /* l4_cfg -> dsp */
2164 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mmu_dsp = {
2165 .master = &omap44xx_l4_cfg_hwmod,
2166 .slave = &omap44xx_mmu_dsp_hwmod,
2167 .clk = "l4_div_ck",
2168 .addr = omap44xx_mmu_dsp_addrs,
2169 .user = OCP_USER_MPU | OCP_USER_SDMA,
2170 };
2171
2172 static struct omap_hwmod omap44xx_mmu_dsp_hwmod = {
2173 .name = "mmu_dsp",
2174 .class = &omap44xx_mmu_hwmod_class,
2175 .clkdm_name = "tesla_clkdm",
2176 .rst_lines = omap44xx_mmu_dsp_resets,
2177 .rst_lines_cnt = ARRAY_SIZE(omap44xx_mmu_dsp_resets),
2178 .main_clk = "dpll_iva_m4x2_ck",
2179 .prcm = {
2180 .omap4 = {
2181 .clkctrl_offs = OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET,
2182 .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET,
2183 .context_offs = OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET,
2184 .modulemode = MODULEMODE_HWCTRL,
2185 },
2186 },
2187 .dev_attr = &mmu_dsp_dev_attr,
2188 };
2189
2190 /*
2191 * 'mpu' class
2192 * mpu sub-system
2193 */
2194
2195 static struct omap_hwmod_class omap44xx_mpu_hwmod_class = {
2196 .name = "mpu",
2197 };
2198
2199 /* mpu */
2200 static struct omap_hwmod omap44xx_mpu_hwmod = {
2201 .name = "mpu",
2202 .class = &omap44xx_mpu_hwmod_class,
2203 .clkdm_name = "mpuss_clkdm",
2204 .flags = HWMOD_INIT_NO_IDLE,
2205 .main_clk = "dpll_mpu_m2_ck",
2206 .prcm = {
2207 .omap4 = {
2208 .clkctrl_offs = OMAP4_CM_MPU_MPU_CLKCTRL_OFFSET,
2209 .context_offs = OMAP4_RM_MPU_MPU_CONTEXT_OFFSET,
2210 },
2211 },
2212 };
2213
2214 /*
2215 * 'ocmc_ram' class
2216 * top-level core on-chip ram
2217 */
2218
2219 static struct omap_hwmod_class omap44xx_ocmc_ram_hwmod_class = {
2220 .name = "ocmc_ram",
2221 };
2222
2223 /* ocmc_ram */
2224 static struct omap_hwmod omap44xx_ocmc_ram_hwmod = {
2225 .name = "ocmc_ram",
2226 .class = &omap44xx_ocmc_ram_hwmod_class,
2227 .clkdm_name = "l3_2_clkdm",
2228 .prcm = {
2229 .omap4 = {
2230 .clkctrl_offs = OMAP4_CM_L3_2_OCMC_RAM_CLKCTRL_OFFSET,
2231 .context_offs = OMAP4_RM_L3_2_OCMC_RAM_CONTEXT_OFFSET,
2232 },
2233 },
2234 };
2235
2236 /*
2237 * 'ocp2scp' class
2238 * bridge to transform ocp interface protocol to scp (serial control port)
2239 * protocol
2240 */
2241
2242 static struct omap_hwmod_class_sysconfig omap44xx_ocp2scp_sysc = {
2243 .rev_offs = 0x0000,
2244 .sysc_offs = 0x0010,
2245 .syss_offs = 0x0014,
2246 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
2247 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2248 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2249 .sysc_fields = &omap_hwmod_sysc_type1,
2250 };
2251
2252 static struct omap_hwmod_class omap44xx_ocp2scp_hwmod_class = {
2253 .name = "ocp2scp",
2254 .sysc = &omap44xx_ocp2scp_sysc,
2255 };
2256
2257 /* ocp2scp_usb_phy */
2258 static struct omap_hwmod omap44xx_ocp2scp_usb_phy_hwmod = {
2259 .name = "ocp2scp_usb_phy",
2260 .class = &omap44xx_ocp2scp_hwmod_class,
2261 .clkdm_name = "l3_init_clkdm",
2262 /*
2263 * ocp2scp_usb_phy_phy_48m is provided by the OMAP4 PRCM IP
2264 * block as an "optional clock," and normally should never be
2265 * specified as the main_clk for an OMAP IP block. However it
2266 * turns out that this clock is actually the main clock for
2267 * the ocp2scp_usb_phy IP block:
2268 * http://lists.infradead.org/pipermail/linux-arm-kernel/2012-September/119943.html
2269 * So listing ocp2scp_usb_phy_phy_48m as a main_clk here seems
2270 * to be the best workaround.
2271 */
2272 .main_clk = "ocp2scp_usb_phy_phy_48m",
2273 .prcm = {
2274 .omap4 = {
2275 .clkctrl_offs = OMAP4_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL_OFFSET,
2276 .context_offs = OMAP4_RM_L3INIT_USBPHYOCP2SCP_CONTEXT_OFFSET,
2277 .modulemode = MODULEMODE_HWCTRL,
2278 },
2279 },
2280 };
2281
2282 /*
2283 * 'prcm' class
2284 * power and reset manager (part of the prcm infrastructure) + clock manager 2
2285 * + clock manager 1 (in always on power domain) + local prm in mpu
2286 */
2287
2288 static struct omap_hwmod_class omap44xx_prcm_hwmod_class = {
2289 .name = "prcm",
2290 };
2291
2292 /* prcm_mpu */
2293 static struct omap_hwmod omap44xx_prcm_mpu_hwmod = {
2294 .name = "prcm_mpu",
2295 .class = &omap44xx_prcm_hwmod_class,
2296 .clkdm_name = "l4_wkup_clkdm",
2297 .flags = HWMOD_NO_IDLEST,
2298 .prcm = {
2299 .omap4 = {
2300 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
2301 },
2302 },
2303 };
2304
2305 /* cm_core_aon */
2306 static struct omap_hwmod omap44xx_cm_core_aon_hwmod = {
2307 .name = "cm_core_aon",
2308 .class = &omap44xx_prcm_hwmod_class,
2309 .flags = HWMOD_NO_IDLEST,
2310 .prcm = {
2311 .omap4 = {
2312 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
2313 },
2314 },
2315 };
2316
2317 /* cm_core */
2318 static struct omap_hwmod omap44xx_cm_core_hwmod = {
2319 .name = "cm_core",
2320 .class = &omap44xx_prcm_hwmod_class,
2321 .flags = HWMOD_NO_IDLEST,
2322 .prcm = {
2323 .omap4 = {
2324 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
2325 },
2326 },
2327 };
2328
2329 /* prm */
2330 static struct omap_hwmod_rst_info omap44xx_prm_resets[] = {
2331 { .name = "rst_global_warm_sw", .rst_shift = 0 },
2332 { .name = "rst_global_cold_sw", .rst_shift = 1 },
2333 };
2334
2335 static struct omap_hwmod omap44xx_prm_hwmod = {
2336 .name = "prm",
2337 .class = &omap44xx_prcm_hwmod_class,
2338 .rst_lines = omap44xx_prm_resets,
2339 .rst_lines_cnt = ARRAY_SIZE(omap44xx_prm_resets),
2340 };
2341
2342 /*
2343 * 'scrm' class
2344 * system clock and reset manager
2345 */
2346
2347 static struct omap_hwmod_class omap44xx_scrm_hwmod_class = {
2348 .name = "scrm",
2349 };
2350
2351 /* scrm */
2352 static struct omap_hwmod omap44xx_scrm_hwmod = {
2353 .name = "scrm",
2354 .class = &omap44xx_scrm_hwmod_class,
2355 .clkdm_name = "l4_wkup_clkdm",
2356 .prcm = {
2357 .omap4 = {
2358 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
2359 },
2360 },
2361 };
2362
2363 /*
2364 * 'sl2if' class
2365 * shared level 2 memory interface
2366 */
2367
2368 static struct omap_hwmod_class omap44xx_sl2if_hwmod_class = {
2369 .name = "sl2if",
2370 };
2371
2372 /* sl2if */
2373 static struct omap_hwmod omap44xx_sl2if_hwmod = {
2374 .name = "sl2if",
2375 .class = &omap44xx_sl2if_hwmod_class,
2376 .clkdm_name = "ivahd_clkdm",
2377 .prcm = {
2378 .omap4 = {
2379 .clkctrl_offs = OMAP4_CM_IVAHD_SL2_CLKCTRL_OFFSET,
2380 .context_offs = OMAP4_RM_IVAHD_SL2_CONTEXT_OFFSET,
2381 .modulemode = MODULEMODE_HWCTRL,
2382 },
2383 },
2384 };
2385
2386 /*
2387 * 'slimbus' class
2388 * bidirectional, multi-drop, multi-channel two-line serial interface between
2389 * the device and external components
2390 */
2391
2392 static struct omap_hwmod_class_sysconfig omap44xx_slimbus_sysc = {
2393 .rev_offs = 0x0000,
2394 .sysc_offs = 0x0010,
2395 .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
2396 SYSC_HAS_SOFTRESET),
2397 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2398 SIDLE_SMART_WKUP),
2399 .sysc_fields = &omap_hwmod_sysc_type2,
2400 };
2401
2402 static struct omap_hwmod_class omap44xx_slimbus_hwmod_class = {
2403 .name = "slimbus",
2404 .sysc = &omap44xx_slimbus_sysc,
2405 };
2406
2407 /* slimbus1 */
2408 static struct omap_hwmod_opt_clk slimbus1_opt_clks[] = {
2409 { .role = "fclk_1", .clk = "slimbus1_fclk_1" },
2410 { .role = "fclk_0", .clk = "slimbus1_fclk_0" },
2411 { .role = "fclk_2", .clk = "slimbus1_fclk_2" },
2412 { .role = "slimbus_clk", .clk = "slimbus1_slimbus_clk" },
2413 };
2414
2415 static struct omap_hwmod omap44xx_slimbus1_hwmod = {
2416 .name = "slimbus1",
2417 .class = &omap44xx_slimbus_hwmod_class,
2418 .clkdm_name = "abe_clkdm",
2419 .prcm = {
2420 .omap4 = {
2421 .clkctrl_offs = OMAP4_CM1_ABE_SLIMBUS_CLKCTRL_OFFSET,
2422 .context_offs = OMAP4_RM_ABE_SLIMBUS_CONTEXT_OFFSET,
2423 .modulemode = MODULEMODE_SWCTRL,
2424 },
2425 },
2426 .opt_clks = slimbus1_opt_clks,
2427 .opt_clks_cnt = ARRAY_SIZE(slimbus1_opt_clks),
2428 };
2429
2430 /* slimbus2 */
2431 static struct omap_hwmod_opt_clk slimbus2_opt_clks[] = {
2432 { .role = "fclk_1", .clk = "slimbus2_fclk_1" },
2433 { .role = "fclk_0", .clk = "slimbus2_fclk_0" },
2434 { .role = "slimbus_clk", .clk = "slimbus2_slimbus_clk" },
2435 };
2436
2437 static struct omap_hwmod omap44xx_slimbus2_hwmod = {
2438 .name = "slimbus2",
2439 .class = &omap44xx_slimbus_hwmod_class,
2440 .clkdm_name = "l4_per_clkdm",
2441 .prcm = {
2442 .omap4 = {
2443 .clkctrl_offs = OMAP4_CM_L4PER_SLIMBUS2_CLKCTRL_OFFSET,
2444 .context_offs = OMAP4_RM_L4PER_SLIMBUS2_CONTEXT_OFFSET,
2445 .modulemode = MODULEMODE_SWCTRL,
2446 },
2447 },
2448 .opt_clks = slimbus2_opt_clks,
2449 .opt_clks_cnt = ARRAY_SIZE(slimbus2_opt_clks),
2450 };
2451
2452 /*
2453 * 'smartreflex' class
2454 * smartreflex module (monitor silicon performance and outputs a measure of
2455 * performance error)
2456 */
2457
2458 /* The IP is not compliant to type1 / type2 scheme */
2459 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex = {
2460 .sidle_shift = 24,
2461 .enwkup_shift = 26,
2462 };
2463
2464 static struct omap_hwmod_class_sysconfig omap44xx_smartreflex_sysc = {
2465 .sysc_offs = 0x0038,
2466 .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE),
2467 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2468 SIDLE_SMART_WKUP),
2469 .sysc_fields = &omap_hwmod_sysc_type_smartreflex,
2470 };
2471
2472 static struct omap_hwmod_class omap44xx_smartreflex_hwmod_class = {
2473 .name = "smartreflex",
2474 .sysc = &omap44xx_smartreflex_sysc,
2475 .rev = 2,
2476 };
2477
2478 /* smartreflex_core */
2479 static struct omap_smartreflex_dev_attr smartreflex_core_dev_attr = {
2480 .sensor_voltdm_name = "core",
2481 };
2482
2483 static struct omap_hwmod omap44xx_smartreflex_core_hwmod = {
2484 .name = "smartreflex_core",
2485 .class = &omap44xx_smartreflex_hwmod_class,
2486 .clkdm_name = "l4_ao_clkdm",
2487
2488 .main_clk = "smartreflex_core_fck",
2489 .prcm = {
2490 .omap4 = {
2491 .clkctrl_offs = OMAP4_CM_ALWON_SR_CORE_CLKCTRL_OFFSET,
2492 .context_offs = OMAP4_RM_ALWON_SR_CORE_CONTEXT_OFFSET,
2493 .modulemode = MODULEMODE_SWCTRL,
2494 },
2495 },
2496 .dev_attr = &smartreflex_core_dev_attr,
2497 };
2498
2499 /* smartreflex_iva */
2500 static struct omap_smartreflex_dev_attr smartreflex_iva_dev_attr = {
2501 .sensor_voltdm_name = "iva",
2502 };
2503
2504 static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = {
2505 .name = "smartreflex_iva",
2506 .class = &omap44xx_smartreflex_hwmod_class,
2507 .clkdm_name = "l4_ao_clkdm",
2508 .main_clk = "smartreflex_iva_fck",
2509 .prcm = {
2510 .omap4 = {
2511 .clkctrl_offs = OMAP4_CM_ALWON_SR_IVA_CLKCTRL_OFFSET,
2512 .context_offs = OMAP4_RM_ALWON_SR_IVA_CONTEXT_OFFSET,
2513 .modulemode = MODULEMODE_SWCTRL,
2514 },
2515 },
2516 .dev_attr = &smartreflex_iva_dev_attr,
2517 };
2518
2519 /* smartreflex_mpu */
2520 static struct omap_smartreflex_dev_attr smartreflex_mpu_dev_attr = {
2521 .sensor_voltdm_name = "mpu",
2522 };
2523
2524 static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = {
2525 .name = "smartreflex_mpu",
2526 .class = &omap44xx_smartreflex_hwmod_class,
2527 .clkdm_name = "l4_ao_clkdm",
2528 .main_clk = "smartreflex_mpu_fck",
2529 .prcm = {
2530 .omap4 = {
2531 .clkctrl_offs = OMAP4_CM_ALWON_SR_MPU_CLKCTRL_OFFSET,
2532 .context_offs = OMAP4_RM_ALWON_SR_MPU_CONTEXT_OFFSET,
2533 .modulemode = MODULEMODE_SWCTRL,
2534 },
2535 },
2536 .dev_attr = &smartreflex_mpu_dev_attr,
2537 };
2538
2539 /*
2540 * 'spinlock' class
2541 * spinlock provides hardware assistance for synchronizing the processes
2542 * running on multiple processors
2543 */
2544
2545 static struct omap_hwmod_class_sysconfig omap44xx_spinlock_sysc = {
2546 .rev_offs = 0x0000,
2547 .sysc_offs = 0x0010,
2548 .syss_offs = 0x0014,
2549 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
2550 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
2551 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2552 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2553 .sysc_fields = &omap_hwmod_sysc_type1,
2554 };
2555
2556 static struct omap_hwmod_class omap44xx_spinlock_hwmod_class = {
2557 .name = "spinlock",
2558 .sysc = &omap44xx_spinlock_sysc,
2559 };
2560
2561 /* spinlock */
2562 static struct omap_hwmod omap44xx_spinlock_hwmod = {
2563 .name = "spinlock",
2564 .class = &omap44xx_spinlock_hwmod_class,
2565 .clkdm_name = "l4_cfg_clkdm",
2566 .prcm = {
2567 .omap4 = {
2568 .clkctrl_offs = OMAP4_CM_L4CFG_HW_SEM_CLKCTRL_OFFSET,
2569 .context_offs = OMAP4_RM_L4CFG_HW_SEM_CONTEXT_OFFSET,
2570 },
2571 },
2572 };
2573
2574 /*
2575 * 'timer' class
2576 * general purpose timer module with accurate 1ms tick
2577 * This class contains several variants: ['timer_1ms', 'timer']
2578 */
2579
2580 static struct omap_hwmod_class_sysconfig omap44xx_timer_1ms_sysc = {
2581 .rev_offs = 0x0000,
2582 .sysc_offs = 0x0010,
2583 .syss_offs = 0x0014,
2584 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
2585 SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
2586 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2587 SYSS_HAS_RESET_STATUS),
2588 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2589 .clockact = CLOCKACT_TEST_ICLK,
2590 .sysc_fields = &omap_hwmod_sysc_type1,
2591 };
2592
2593 static struct omap_hwmod_class omap44xx_timer_1ms_hwmod_class = {
2594 .name = "timer",
2595 .sysc = &omap44xx_timer_1ms_sysc,
2596 };
2597
2598 static struct omap_hwmod_class_sysconfig omap44xx_timer_sysc = {
2599 .rev_offs = 0x0000,
2600 .sysc_offs = 0x0010,
2601 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
2602 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2603 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2604 SIDLE_SMART_WKUP),
2605 .sysc_fields = &omap_hwmod_sysc_type2,
2606 };
2607
2608 static struct omap_hwmod_class omap44xx_timer_hwmod_class = {
2609 .name = "timer",
2610 .sysc = &omap44xx_timer_sysc,
2611 };
2612
2613 /* always-on timers dev attribute */
2614 static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
2615 .timer_capability = OMAP_TIMER_ALWON,
2616 };
2617
2618 /* pwm timers dev attribute */
2619 static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
2620 .timer_capability = OMAP_TIMER_HAS_PWM,
2621 };
2622
2623 /* timers with DSP interrupt dev attribute */
2624 static struct omap_timer_capability_dev_attr capability_dsp_dev_attr = {
2625 .timer_capability = OMAP_TIMER_HAS_DSP_IRQ,
2626 };
2627
2628 /* pwm timers with DSP interrupt dev attribute */
2629 static struct omap_timer_capability_dev_attr capability_dsp_pwm_dev_attr = {
2630 .timer_capability = OMAP_TIMER_HAS_DSP_IRQ | OMAP_TIMER_HAS_PWM,
2631 };
2632
2633 /* timer1 */
2634 static struct omap_hwmod omap44xx_timer1_hwmod = {
2635 .name = "timer1",
2636 .class = &omap44xx_timer_1ms_hwmod_class,
2637 .clkdm_name = "l4_wkup_clkdm",
2638 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
2639 .main_clk = "dmt1_clk_mux",
2640 .prcm = {
2641 .omap4 = {
2642 .clkctrl_offs = OMAP4_CM_WKUP_TIMER1_CLKCTRL_OFFSET,
2643 .context_offs = OMAP4_RM_WKUP_TIMER1_CONTEXT_OFFSET,
2644 .modulemode = MODULEMODE_SWCTRL,
2645 },
2646 },
2647 .dev_attr = &capability_alwon_dev_attr,
2648 };
2649
2650 /* timer2 */
2651 static struct omap_hwmod omap44xx_timer2_hwmod = {
2652 .name = "timer2",
2653 .class = &omap44xx_timer_1ms_hwmod_class,
2654 .clkdm_name = "l4_per_clkdm",
2655 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
2656 .main_clk = "cm2_dm2_mux",
2657 .prcm = {
2658 .omap4 = {
2659 .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER2_CLKCTRL_OFFSET,
2660 .context_offs = OMAP4_RM_L4PER_DMTIMER2_CONTEXT_OFFSET,
2661 .modulemode = MODULEMODE_SWCTRL,
2662 },
2663 },
2664 };
2665
2666 /* timer3 */
2667 static struct omap_hwmod omap44xx_timer3_hwmod = {
2668 .name = "timer3",
2669 .class = &omap44xx_timer_hwmod_class,
2670 .clkdm_name = "l4_per_clkdm",
2671 .main_clk = "cm2_dm3_mux",
2672 .prcm = {
2673 .omap4 = {
2674 .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER3_CLKCTRL_OFFSET,
2675 .context_offs = OMAP4_RM_L4PER_DMTIMER3_CONTEXT_OFFSET,
2676 .modulemode = MODULEMODE_SWCTRL,
2677 },
2678 },
2679 };
2680
2681 /* timer4 */
2682 static struct omap_hwmod omap44xx_timer4_hwmod = {
2683 .name = "timer4",
2684 .class = &omap44xx_timer_hwmod_class,
2685 .clkdm_name = "l4_per_clkdm",
2686 .main_clk = "cm2_dm4_mux",
2687 .prcm = {
2688 .omap4 = {
2689 .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER4_CLKCTRL_OFFSET,
2690 .context_offs = OMAP4_RM_L4PER_DMTIMER4_CONTEXT_OFFSET,
2691 .modulemode = MODULEMODE_SWCTRL,
2692 },
2693 },
2694 };
2695
2696 /* timer5 */
2697 static struct omap_hwmod omap44xx_timer5_hwmod = {
2698 .name = "timer5",
2699 .class = &omap44xx_timer_hwmod_class,
2700 .clkdm_name = "abe_clkdm",
2701 .main_clk = "timer5_sync_mux",
2702 .prcm = {
2703 .omap4 = {
2704 .clkctrl_offs = OMAP4_CM1_ABE_TIMER5_CLKCTRL_OFFSET,
2705 .context_offs = OMAP4_RM_ABE_TIMER5_CONTEXT_OFFSET,
2706 .modulemode = MODULEMODE_SWCTRL,
2707 },
2708 },
2709 .dev_attr = &capability_dsp_dev_attr,
2710 };
2711
2712 /* timer6 */
2713 static struct omap_hwmod omap44xx_timer6_hwmod = {
2714 .name = "timer6",
2715 .class = &omap44xx_timer_hwmod_class,
2716 .clkdm_name = "abe_clkdm",
2717 .main_clk = "timer6_sync_mux",
2718 .prcm = {
2719 .omap4 = {
2720 .clkctrl_offs = OMAP4_CM1_ABE_TIMER6_CLKCTRL_OFFSET,
2721 .context_offs = OMAP4_RM_ABE_TIMER6_CONTEXT_OFFSET,
2722 .modulemode = MODULEMODE_SWCTRL,
2723 },
2724 },
2725 .dev_attr = &capability_dsp_dev_attr,
2726 };
2727
2728 /* timer7 */
2729 static struct omap_hwmod omap44xx_timer7_hwmod = {
2730 .name = "timer7",
2731 .class = &omap44xx_timer_hwmod_class,
2732 .clkdm_name = "abe_clkdm",
2733 .main_clk = "timer7_sync_mux",
2734 .prcm = {
2735 .omap4 = {
2736 .clkctrl_offs = OMAP4_CM1_ABE_TIMER7_CLKCTRL_OFFSET,
2737 .context_offs = OMAP4_RM_ABE_TIMER7_CONTEXT_OFFSET,
2738 .modulemode = MODULEMODE_SWCTRL,
2739 },
2740 },
2741 .dev_attr = &capability_dsp_dev_attr,
2742 };
2743
2744 /* timer8 */
2745 static struct omap_hwmod omap44xx_timer8_hwmod = {
2746 .name = "timer8",
2747 .class = &omap44xx_timer_hwmod_class,
2748 .clkdm_name = "abe_clkdm",
2749 .main_clk = "timer8_sync_mux",
2750 .prcm = {
2751 .omap4 = {
2752 .clkctrl_offs = OMAP4_CM1_ABE_TIMER8_CLKCTRL_OFFSET,
2753 .context_offs = OMAP4_RM_ABE_TIMER8_CONTEXT_OFFSET,
2754 .modulemode = MODULEMODE_SWCTRL,
2755 },
2756 },
2757 .dev_attr = &capability_dsp_pwm_dev_attr,
2758 };
2759
2760 /* timer9 */
2761 static struct omap_hwmod omap44xx_timer9_hwmod = {
2762 .name = "timer9",
2763 .class = &omap44xx_timer_hwmod_class,
2764 .clkdm_name = "l4_per_clkdm",
2765 .main_clk = "cm2_dm9_mux",
2766 .prcm = {
2767 .omap4 = {
2768 .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER9_CLKCTRL_OFFSET,
2769 .context_offs = OMAP4_RM_L4PER_DMTIMER9_CONTEXT_OFFSET,
2770 .modulemode = MODULEMODE_SWCTRL,
2771 },
2772 },
2773 .dev_attr = &capability_pwm_dev_attr,
2774 };
2775
2776 /* timer10 */
2777 static struct omap_hwmod omap44xx_timer10_hwmod = {
2778 .name = "timer10",
2779 .class = &omap44xx_timer_1ms_hwmod_class,
2780 .clkdm_name = "l4_per_clkdm",
2781 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
2782 .main_clk = "cm2_dm10_mux",
2783 .prcm = {
2784 .omap4 = {
2785 .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER10_CLKCTRL_OFFSET,
2786 .context_offs = OMAP4_RM_L4PER_DMTIMER10_CONTEXT_OFFSET,
2787 .modulemode = MODULEMODE_SWCTRL,
2788 },
2789 },
2790 .dev_attr = &capability_pwm_dev_attr,
2791 };
2792
2793 /* timer11 */
2794 static struct omap_hwmod omap44xx_timer11_hwmod = {
2795 .name = "timer11",
2796 .class = &omap44xx_timer_hwmod_class,
2797 .clkdm_name = "l4_per_clkdm",
2798 .main_clk = "cm2_dm11_mux",
2799 .prcm = {
2800 .omap4 = {
2801 .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER11_CLKCTRL_OFFSET,
2802 .context_offs = OMAP4_RM_L4PER_DMTIMER11_CONTEXT_OFFSET,
2803 .modulemode = MODULEMODE_SWCTRL,
2804 },
2805 },
2806 .dev_attr = &capability_pwm_dev_attr,
2807 };
2808
2809 /*
2810 * 'uart' class
2811 * universal asynchronous receiver/transmitter (uart)
2812 */
2813
2814 static struct omap_hwmod_class_sysconfig omap44xx_uart_sysc = {
2815 .rev_offs = 0x0050,
2816 .sysc_offs = 0x0054,
2817 .syss_offs = 0x0058,
2818 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
2819 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2820 SYSS_HAS_RESET_STATUS),
2821 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2822 SIDLE_SMART_WKUP),
2823 .sysc_fields = &omap_hwmod_sysc_type1,
2824 };
2825
2826 static struct omap_hwmod_class omap44xx_uart_hwmod_class = {
2827 .name = "uart",
2828 .sysc = &omap44xx_uart_sysc,
2829 };
2830
2831 /* uart1 */
2832 static struct omap_hwmod omap44xx_uart1_hwmod = {
2833 .name = "uart1",
2834 .class = &omap44xx_uart_hwmod_class,
2835 .clkdm_name = "l4_per_clkdm",
2836 .flags = HWMOD_SWSUP_SIDLE_ACT,
2837 .main_clk = "func_48m_fclk",
2838 .prcm = {
2839 .omap4 = {
2840 .clkctrl_offs = OMAP4_CM_L4PER_UART1_CLKCTRL_OFFSET,
2841 .context_offs = OMAP4_RM_L4PER_UART1_CONTEXT_OFFSET,
2842 .modulemode = MODULEMODE_SWCTRL,
2843 },
2844 },
2845 };
2846
2847 /* uart2 */
2848 static struct omap_hwmod omap44xx_uart2_hwmod = {
2849 .name = "uart2",
2850 .class = &omap44xx_uart_hwmod_class,
2851 .clkdm_name = "l4_per_clkdm",
2852 .flags = HWMOD_SWSUP_SIDLE_ACT,
2853 .main_clk = "func_48m_fclk",
2854 .prcm = {
2855 .omap4 = {
2856 .clkctrl_offs = OMAP4_CM_L4PER_UART2_CLKCTRL_OFFSET,
2857 .context_offs = OMAP4_RM_L4PER_UART2_CONTEXT_OFFSET,
2858 .modulemode = MODULEMODE_SWCTRL,
2859 },
2860 },
2861 };
2862
2863 /* uart3 */
2864 static struct omap_hwmod omap44xx_uart3_hwmod = {
2865 .name = "uart3",
2866 .class = &omap44xx_uart_hwmod_class,
2867 .clkdm_name = "l4_per_clkdm",
2868 .flags = DEBUG_OMAP4UART3_FLAGS | HWMOD_SWSUP_SIDLE_ACT,
2869 .main_clk = "func_48m_fclk",
2870 .prcm = {
2871 .omap4 = {
2872 .clkctrl_offs = OMAP4_CM_L4PER_UART3_CLKCTRL_OFFSET,
2873 .context_offs = OMAP4_RM_L4PER_UART3_CONTEXT_OFFSET,
2874 .modulemode = MODULEMODE_SWCTRL,
2875 },
2876 },
2877 };
2878
2879 /* uart4 */
2880 static struct omap_hwmod omap44xx_uart4_hwmod = {
2881 .name = "uart4",
2882 .class = &omap44xx_uart_hwmod_class,
2883 .clkdm_name = "l4_per_clkdm",
2884 .flags = DEBUG_OMAP4UART4_FLAGS | HWMOD_SWSUP_SIDLE_ACT,
2885 .main_clk = "func_48m_fclk",
2886 .prcm = {
2887 .omap4 = {
2888 .clkctrl_offs = OMAP4_CM_L4PER_UART4_CLKCTRL_OFFSET,
2889 .context_offs = OMAP4_RM_L4PER_UART4_CONTEXT_OFFSET,
2890 .modulemode = MODULEMODE_SWCTRL,
2891 },
2892 },
2893 };
2894
2895 /*
2896 * 'usb_host_fs' class
2897 * full-speed usb host controller
2898 */
2899
2900 /* The IP is not compliant to type1 / type2 scheme */
2901 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_usb_host_fs = {
2902 .midle_shift = 4,
2903 .sidle_shift = 2,
2904 .srst_shift = 1,
2905 };
2906
2907 static struct omap_hwmod_class_sysconfig omap44xx_usb_host_fs_sysc = {
2908 .rev_offs = 0x0000,
2909 .sysc_offs = 0x0210,
2910 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
2911 SYSC_HAS_SOFTRESET),
2912 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2913 SIDLE_SMART_WKUP),
2914 .sysc_fields = &omap_hwmod_sysc_type_usb_host_fs,
2915 };
2916
2917 static struct omap_hwmod_class omap44xx_usb_host_fs_hwmod_class = {
2918 .name = "usb_host_fs",
2919 .sysc = &omap44xx_usb_host_fs_sysc,
2920 };
2921
2922 /* usb_host_fs */
2923 static struct omap_hwmod omap44xx_usb_host_fs_hwmod = {
2924 .name = "usb_host_fs",
2925 .class = &omap44xx_usb_host_fs_hwmod_class,
2926 .clkdm_name = "l3_init_clkdm",
2927 .main_clk = "usb_host_fs_fck",
2928 .prcm = {
2929 .omap4 = {
2930 .clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_FS_CLKCTRL_OFFSET,
2931 .context_offs = OMAP4_RM_L3INIT_USB_HOST_FS_CONTEXT_OFFSET,
2932 .modulemode = MODULEMODE_SWCTRL,
2933 },
2934 },
2935 };
2936
2937 /*
2938 * 'usb_host_hs' class
2939 * high-speed multi-port usb host controller
2940 */
2941
2942 static struct omap_hwmod_class_sysconfig omap44xx_usb_host_hs_sysc = {
2943 .rev_offs = 0x0000,
2944 .sysc_offs = 0x0010,
2945 .syss_offs = 0x0014,
2946 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
2947 SYSC_HAS_SOFTRESET | SYSC_HAS_RESET_STATUS),
2948 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2949 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2950 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
2951 .sysc_fields = &omap_hwmod_sysc_type2,
2952 };
2953
2954 static struct omap_hwmod_class omap44xx_usb_host_hs_hwmod_class = {
2955 .name = "usb_host_hs",
2956 .sysc = &omap44xx_usb_host_hs_sysc,
2957 };
2958
2959 /* usb_host_hs */
2960 static struct omap_hwmod omap44xx_usb_host_hs_hwmod = {
2961 .name = "usb_host_hs",
2962 .class = &omap44xx_usb_host_hs_hwmod_class,
2963 .clkdm_name = "l3_init_clkdm",
2964 .main_clk = "usb_host_hs_fck",
2965 .prcm = {
2966 .omap4 = {
2967 .clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_CLKCTRL_OFFSET,
2968 .context_offs = OMAP4_RM_L3INIT_USB_HOST_CONTEXT_OFFSET,
2969 .modulemode = MODULEMODE_SWCTRL,
2970 },
2971 },
2972
2973 /*
2974 * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock
2975 * id: i660
2976 *
2977 * Description:
2978 * In the following configuration :
2979 * - USBHOST module is set to smart-idle mode
2980 * - PRCM asserts idle_req to the USBHOST module ( This typically
2981 * happens when the system is going to a low power mode : all ports
2982 * have been suspended, the master part of the USBHOST module has
2983 * entered the standby state, and SW has cut the functional clocks)
2984 * - an USBHOST interrupt occurs before the module is able to answer
2985 * idle_ack, typically a remote wakeup IRQ.
2986 * Then the USB HOST module will enter a deadlock situation where it
2987 * is no more accessible nor functional.
2988 *
2989 * Workaround:
2990 * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE
2991 */
2992
2993 /*
2994 * Errata: USB host EHCI may stall when entering smart-standby mode
2995 * Id: i571
2996 *
2997 * Description:
2998 * When the USBHOST module is set to smart-standby mode, and when it is
2999 * ready to enter the standby state (i.e. all ports are suspended and
3000 * all attached devices are in suspend mode), then it can wrongly assert
3001 * the Mstandby signal too early while there are still some residual OCP
3002 * transactions ongoing. If this condition occurs, the internal state
3003 * machine may go to an undefined state and the USB link may be stuck
3004 * upon the next resume.
3005 *
3006 * Workaround:
3007 * Don't use smart standby; use only force standby,
3008 * hence HWMOD_SWSUP_MSTANDBY
3009 */
3010
3011 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
3012 };
3013
3014 /*
3015 * 'usb_otg_hs' class
3016 * high-speed on-the-go universal serial bus (usb_otg_hs) controller
3017 */
3018
3019 static struct omap_hwmod_class_sysconfig omap44xx_usb_otg_hs_sysc = {
3020 .rev_offs = 0x0400,
3021 .sysc_offs = 0x0404,
3022 .syss_offs = 0x0408,
3023 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
3024 SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
3025 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
3026 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3027 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
3028 MSTANDBY_SMART),
3029 .sysc_fields = &omap_hwmod_sysc_type1,
3030 };
3031
3032 static struct omap_hwmod_class omap44xx_usb_otg_hs_hwmod_class = {
3033 .name = "usb_otg_hs",
3034 .sysc = &omap44xx_usb_otg_hs_sysc,
3035 };
3036
3037 /* usb_otg_hs */
3038 static struct omap_hwmod_opt_clk usb_otg_hs_opt_clks[] = {
3039 { .role = "xclk", .clk = "usb_otg_hs_xclk" },
3040 };
3041
3042 static struct omap_hwmod omap44xx_usb_otg_hs_hwmod = {
3043 .name = "usb_otg_hs",
3044 .class = &omap44xx_usb_otg_hs_hwmod_class,
3045 .clkdm_name = "l3_init_clkdm",
3046 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
3047 .main_clk = "usb_otg_hs_ick",
3048 .prcm = {
3049 .omap4 = {
3050 .clkctrl_offs = OMAP4_CM_L3INIT_USB_OTG_CLKCTRL_OFFSET,
3051 .context_offs = OMAP4_RM_L3INIT_USB_OTG_CONTEXT_OFFSET,
3052 .modulemode = MODULEMODE_HWCTRL,
3053 },
3054 },
3055 .opt_clks = usb_otg_hs_opt_clks,
3056 .opt_clks_cnt = ARRAY_SIZE(usb_otg_hs_opt_clks),
3057 };
3058
3059 /*
3060 * 'usb_tll_hs' class
3061 * usb_tll_hs module is the adapter on the usb_host_hs ports
3062 */
3063
3064 static struct omap_hwmod_class_sysconfig omap44xx_usb_tll_hs_sysc = {
3065 .rev_offs = 0x0000,
3066 .sysc_offs = 0x0010,
3067 .syss_offs = 0x0014,
3068 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
3069 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
3070 SYSC_HAS_AUTOIDLE),
3071 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
3072 .sysc_fields = &omap_hwmod_sysc_type1,
3073 };
3074
3075 static struct omap_hwmod_class omap44xx_usb_tll_hs_hwmod_class = {
3076 .name = "usb_tll_hs",
3077 .sysc = &omap44xx_usb_tll_hs_sysc,
3078 };
3079
3080 static struct omap_hwmod omap44xx_usb_tll_hs_hwmod = {
3081 .name = "usb_tll_hs",
3082 .class = &omap44xx_usb_tll_hs_hwmod_class,
3083 .clkdm_name = "l3_init_clkdm",
3084 .main_clk = "usb_tll_hs_ick",
3085 .prcm = {
3086 .omap4 = {
3087 .clkctrl_offs = OMAP4_CM_L3INIT_USB_TLL_CLKCTRL_OFFSET,
3088 .context_offs = OMAP4_RM_L3INIT_USB_TLL_CONTEXT_OFFSET,
3089 .modulemode = MODULEMODE_HWCTRL,
3090 },
3091 },
3092 };
3093
3094 /*
3095 * 'wd_timer' class
3096 * 32-bit watchdog upward counter that generates a pulse on the reset pin on
3097 * overflow condition
3098 */
3099
3100 static struct omap_hwmod_class_sysconfig omap44xx_wd_timer_sysc = {
3101 .rev_offs = 0x0000,
3102 .sysc_offs = 0x0010,
3103 .syss_offs = 0x0014,
3104 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
3105 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
3106 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3107 SIDLE_SMART_WKUP),
3108 .sysc_fields = &omap_hwmod_sysc_type1,
3109 };
3110
3111 static struct omap_hwmod_class omap44xx_wd_timer_hwmod_class = {
3112 .name = "wd_timer",
3113 .sysc = &omap44xx_wd_timer_sysc,
3114 .pre_shutdown = &omap2_wd_timer_disable,
3115 .reset = &omap2_wd_timer_reset,
3116 };
3117
3118 /* wd_timer2 */
3119 static struct omap_hwmod omap44xx_wd_timer2_hwmod = {
3120 .name = "wd_timer2",
3121 .class = &omap44xx_wd_timer_hwmod_class,
3122 .clkdm_name = "l4_wkup_clkdm",
3123 .main_clk = "sys_32k_ck",
3124 .prcm = {
3125 .omap4 = {
3126 .clkctrl_offs = OMAP4_CM_WKUP_WDT2_CLKCTRL_OFFSET,
3127 .context_offs = OMAP4_RM_WKUP_WDT2_CONTEXT_OFFSET,
3128 .modulemode = MODULEMODE_SWCTRL,
3129 },
3130 },
3131 };
3132
3133 /* wd_timer3 */
3134 static struct omap_hwmod omap44xx_wd_timer3_hwmod = {
3135 .name = "wd_timer3",
3136 .class = &omap44xx_wd_timer_hwmod_class,
3137 .clkdm_name = "abe_clkdm",
3138 .main_clk = "sys_32k_ck",
3139 .prcm = {
3140 .omap4 = {
3141 .clkctrl_offs = OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET,
3142 .context_offs = OMAP4_RM_ABE_WDT3_CONTEXT_OFFSET,
3143 .modulemode = MODULEMODE_SWCTRL,
3144 },
3145 },
3146 };
3147
3148
3149 /*
3150 * interfaces
3151 */
3152
3153 /* l3_main_1 -> dmm */
3154 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = {
3155 .master = &omap44xx_l3_main_1_hwmod,
3156 .slave = &omap44xx_dmm_hwmod,
3157 .clk = "l3_div_ck",
3158 .user = OCP_USER_SDMA,
3159 };
3160
3161 /* mpu -> dmm */
3162 static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = {
3163 .master = &omap44xx_mpu_hwmod,
3164 .slave = &omap44xx_dmm_hwmod,
3165 .clk = "l3_div_ck",
3166 .user = OCP_USER_MPU,
3167 };
3168
3169 /* iva -> l3_instr */
3170 static struct omap_hwmod_ocp_if omap44xx_iva__l3_instr = {
3171 .master = &omap44xx_iva_hwmod,
3172 .slave = &omap44xx_l3_instr_hwmod,
3173 .clk = "l3_div_ck",
3174 .user = OCP_USER_MPU | OCP_USER_SDMA,
3175 };
3176
3177 /* l3_main_3 -> l3_instr */
3178 static struct omap_hwmod_ocp_if omap44xx_l3_main_3__l3_instr = {
3179 .master = &omap44xx_l3_main_3_hwmod,
3180 .slave = &omap44xx_l3_instr_hwmod,
3181 .clk = "l3_div_ck",
3182 .user = OCP_USER_MPU | OCP_USER_SDMA,
3183 };
3184
3185 /* ocp_wp_noc -> l3_instr */
3186 static struct omap_hwmod_ocp_if omap44xx_ocp_wp_noc__l3_instr = {
3187 .master = &omap44xx_ocp_wp_noc_hwmod,
3188 .slave = &omap44xx_l3_instr_hwmod,
3189 .clk = "l3_div_ck",
3190 .user = OCP_USER_MPU | OCP_USER_SDMA,
3191 };
3192
3193 /* dsp -> l3_main_1 */
3194 static struct omap_hwmod_ocp_if omap44xx_dsp__l3_main_1 = {
3195 .master = &omap44xx_dsp_hwmod,
3196 .slave = &omap44xx_l3_main_1_hwmod,
3197 .clk = "l3_div_ck",
3198 .user = OCP_USER_MPU | OCP_USER_SDMA,
3199 };
3200
3201 /* dss -> l3_main_1 */
3202 static struct omap_hwmod_ocp_if omap44xx_dss__l3_main_1 = {
3203 .master = &omap44xx_dss_hwmod,
3204 .slave = &omap44xx_l3_main_1_hwmod,
3205 .clk = "l3_div_ck",
3206 .user = OCP_USER_MPU | OCP_USER_SDMA,
3207 };
3208
3209 /* l3_main_2 -> l3_main_1 */
3210 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1 = {
3211 .master = &omap44xx_l3_main_2_hwmod,
3212 .slave = &omap44xx_l3_main_1_hwmod,
3213 .clk = "l3_div_ck",
3214 .user = OCP_USER_MPU | OCP_USER_SDMA,
3215 };
3216
3217 /* l4_cfg -> l3_main_1 */
3218 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_1 = {
3219 .master = &omap44xx_l4_cfg_hwmod,
3220 .slave = &omap44xx_l3_main_1_hwmod,
3221 .clk = "l4_div_ck",
3222 .user = OCP_USER_MPU | OCP_USER_SDMA,
3223 };
3224
3225 /* mmc1 -> l3_main_1 */
3226 static struct omap_hwmod_ocp_if omap44xx_mmc1__l3_main_1 = {
3227 .master = &omap44xx_mmc1_hwmod,
3228 .slave = &omap44xx_l3_main_1_hwmod,
3229 .clk = "l3_div_ck",
3230 .user = OCP_USER_MPU | OCP_USER_SDMA,
3231 };
3232
3233 /* mmc2 -> l3_main_1 */
3234 static struct omap_hwmod_ocp_if omap44xx_mmc2__l3_main_1 = {
3235 .master = &omap44xx_mmc2_hwmod,
3236 .slave = &omap44xx_l3_main_1_hwmod,
3237 .clk = "l3_div_ck",
3238 .user = OCP_USER_MPU | OCP_USER_SDMA,
3239 };
3240
3241 /* mpu -> l3_main_1 */
3242 static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = {
3243 .master = &omap44xx_mpu_hwmod,
3244 .slave = &omap44xx_l3_main_1_hwmod,
3245 .clk = "l3_div_ck",
3246 .user = OCP_USER_MPU,
3247 };
3248
3249 /* debugss -> l3_main_2 */
3250 static struct omap_hwmod_ocp_if omap44xx_debugss__l3_main_2 = {
3251 .master = &omap44xx_debugss_hwmod,
3252 .slave = &omap44xx_l3_main_2_hwmod,
3253 .clk = "dbgclk_mux_ck",
3254 .user = OCP_USER_MPU | OCP_USER_SDMA,
3255 };
3256
3257 /* dma_system -> l3_main_2 */
3258 static struct omap_hwmod_ocp_if omap44xx_dma_system__l3_main_2 = {
3259 .master = &omap44xx_dma_system_hwmod,
3260 .slave = &omap44xx_l3_main_2_hwmod,
3261 .clk = "l3_div_ck",
3262 .user = OCP_USER_MPU | OCP_USER_SDMA,
3263 };
3264
3265 /* fdif -> l3_main_2 */
3266 static struct omap_hwmod_ocp_if omap44xx_fdif__l3_main_2 = {
3267 .master = &omap44xx_fdif_hwmod,
3268 .slave = &omap44xx_l3_main_2_hwmod,
3269 .clk = "l3_div_ck",
3270 .user = OCP_USER_MPU | OCP_USER_SDMA,
3271 };
3272
3273 /* gpu -> l3_main_2 */
3274 static struct omap_hwmod_ocp_if omap44xx_gpu__l3_main_2 = {
3275 .master = &omap44xx_gpu_hwmod,
3276 .slave = &omap44xx_l3_main_2_hwmod,
3277 .clk = "l3_div_ck",
3278 .user = OCP_USER_MPU | OCP_USER_SDMA,
3279 };
3280
3281 /* hsi -> l3_main_2 */
3282 static struct omap_hwmod_ocp_if omap44xx_hsi__l3_main_2 = {
3283 .master = &omap44xx_hsi_hwmod,
3284 .slave = &omap44xx_l3_main_2_hwmod,
3285 .clk = "l3_div_ck",
3286 .user = OCP_USER_MPU | OCP_USER_SDMA,
3287 };
3288
3289 /* ipu -> l3_main_2 */
3290 static struct omap_hwmod_ocp_if omap44xx_ipu__l3_main_2 = {
3291 .master = &omap44xx_ipu_hwmod,
3292 .slave = &omap44xx_l3_main_2_hwmod,
3293 .clk = "l3_div_ck",
3294 .user = OCP_USER_MPU | OCP_USER_SDMA,
3295 };
3296
3297 /* iss -> l3_main_2 */
3298 static struct omap_hwmod_ocp_if omap44xx_iss__l3_main_2 = {
3299 .master = &omap44xx_iss_hwmod,
3300 .slave = &omap44xx_l3_main_2_hwmod,
3301 .clk = "l3_div_ck",
3302 .user = OCP_USER_MPU | OCP_USER_SDMA,
3303 };
3304
3305 /* iva -> l3_main_2 */
3306 static struct omap_hwmod_ocp_if omap44xx_iva__l3_main_2 = {
3307 .master = &omap44xx_iva_hwmod,
3308 .slave = &omap44xx_l3_main_2_hwmod,
3309 .clk = "l3_div_ck",
3310 .user = OCP_USER_MPU | OCP_USER_SDMA,
3311 };
3312
3313 /* l3_main_1 -> l3_main_2 */
3314 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = {
3315 .master = &omap44xx_l3_main_1_hwmod,
3316 .slave = &omap44xx_l3_main_2_hwmod,
3317 .clk = "l3_div_ck",
3318 .user = OCP_USER_MPU,
3319 };
3320
3321 /* l4_cfg -> l3_main_2 */
3322 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = {
3323 .master = &omap44xx_l4_cfg_hwmod,
3324 .slave = &omap44xx_l3_main_2_hwmod,
3325 .clk = "l4_div_ck",
3326 .user = OCP_USER_MPU | OCP_USER_SDMA,
3327 };
3328
3329 /* usb_host_fs -> l3_main_2 */
3330 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_usb_host_fs__l3_main_2 = {
3331 .master = &omap44xx_usb_host_fs_hwmod,
3332 .slave = &omap44xx_l3_main_2_hwmod,
3333 .clk = "l3_div_ck",
3334 .user = OCP_USER_MPU | OCP_USER_SDMA,
3335 };
3336
3337 /* usb_host_hs -> l3_main_2 */
3338 static struct omap_hwmod_ocp_if omap44xx_usb_host_hs__l3_main_2 = {
3339 .master = &omap44xx_usb_host_hs_hwmod,
3340 .slave = &omap44xx_l3_main_2_hwmod,
3341 .clk = "l3_div_ck",
3342 .user = OCP_USER_MPU | OCP_USER_SDMA,
3343 };
3344
3345 /* usb_otg_hs -> l3_main_2 */
3346 static struct omap_hwmod_ocp_if omap44xx_usb_otg_hs__l3_main_2 = {
3347 .master = &omap44xx_usb_otg_hs_hwmod,
3348 .slave = &omap44xx_l3_main_2_hwmod,
3349 .clk = "l3_div_ck",
3350 .user = OCP_USER_MPU | OCP_USER_SDMA,
3351 };
3352
3353 /* l3_main_1 -> l3_main_3 */
3354 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = {
3355 .master = &omap44xx_l3_main_1_hwmod,
3356 .slave = &omap44xx_l3_main_3_hwmod,
3357 .clk = "l3_div_ck",
3358 .user = OCP_USER_MPU,
3359 };
3360
3361 /* l3_main_2 -> l3_main_3 */
3362 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_3 = {
3363 .master = &omap44xx_l3_main_2_hwmod,
3364 .slave = &omap44xx_l3_main_3_hwmod,
3365 .clk = "l3_div_ck",
3366 .user = OCP_USER_MPU | OCP_USER_SDMA,
3367 };
3368
3369 /* l4_cfg -> l3_main_3 */
3370 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_3 = {
3371 .master = &omap44xx_l4_cfg_hwmod,
3372 .slave = &omap44xx_l3_main_3_hwmod,
3373 .clk = "l4_div_ck",
3374 .user = OCP_USER_MPU | OCP_USER_SDMA,
3375 };
3376
3377 /* aess -> l4_abe */
3378 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_aess__l4_abe = {
3379 .master = &omap44xx_aess_hwmod,
3380 .slave = &omap44xx_l4_abe_hwmod,
3381 .clk = "ocp_abe_iclk",
3382 .user = OCP_USER_MPU | OCP_USER_SDMA,
3383 };
3384
3385 /* dsp -> l4_abe */
3386 static struct omap_hwmod_ocp_if omap44xx_dsp__l4_abe = {
3387 .master = &omap44xx_dsp_hwmod,
3388 .slave = &omap44xx_l4_abe_hwmod,
3389 .clk = "ocp_abe_iclk",
3390 .user = OCP_USER_MPU | OCP_USER_SDMA,
3391 };
3392
3393 /* l3_main_1 -> l4_abe */
3394 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_abe = {
3395 .master = &omap44xx_l3_main_1_hwmod,
3396 .slave = &omap44xx_l4_abe_hwmod,
3397 .clk = "l3_div_ck",
3398 .user = OCP_USER_MPU | OCP_USER_SDMA,
3399 };
3400
3401 /* mpu -> l4_abe */
3402 static struct omap_hwmod_ocp_if omap44xx_mpu__l4_abe = {
3403 .master = &omap44xx_mpu_hwmod,
3404 .slave = &omap44xx_l4_abe_hwmod,
3405 .clk = "ocp_abe_iclk",
3406 .user = OCP_USER_MPU | OCP_USER_SDMA,
3407 };
3408
3409 /* l3_main_1 -> l4_cfg */
3410 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_cfg = {
3411 .master = &omap44xx_l3_main_1_hwmod,
3412 .slave = &omap44xx_l4_cfg_hwmod,
3413 .clk = "l3_div_ck",
3414 .user = OCP_USER_MPU | OCP_USER_SDMA,
3415 };
3416
3417 /* l3_main_2 -> l4_per */
3418 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l4_per = {
3419 .master = &omap44xx_l3_main_2_hwmod,
3420 .slave = &omap44xx_l4_per_hwmod,
3421 .clk = "l3_div_ck",
3422 .user = OCP_USER_MPU | OCP_USER_SDMA,
3423 };
3424
3425 /* l4_cfg -> l4_wkup */
3426 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l4_wkup = {
3427 .master = &omap44xx_l4_cfg_hwmod,
3428 .slave = &omap44xx_l4_wkup_hwmod,
3429 .clk = "l4_div_ck",
3430 .user = OCP_USER_MPU | OCP_USER_SDMA,
3431 };
3432
3433 /* mpu -> mpu_private */
3434 static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private = {
3435 .master = &omap44xx_mpu_hwmod,
3436 .slave = &omap44xx_mpu_private_hwmod,
3437 .clk = "l3_div_ck",
3438 .user = OCP_USER_MPU | OCP_USER_SDMA,
3439 };
3440
3441 /* l4_cfg -> ocp_wp_noc */
3442 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp_wp_noc = {
3443 .master = &omap44xx_l4_cfg_hwmod,
3444 .slave = &omap44xx_ocp_wp_noc_hwmod,
3445 .clk = "l4_div_ck",
3446 .user = OCP_USER_MPU | OCP_USER_SDMA,
3447 };
3448
3449 static struct omap_hwmod_addr_space omap44xx_aess_addrs[] = {
3450 {
3451 .name = "dmem",
3452 .pa_start = 0x40180000,
3453 .pa_end = 0x4018ffff
3454 },
3455 {
3456 .name = "cmem",
3457 .pa_start = 0x401a0000,
3458 .pa_end = 0x401a1fff
3459 },
3460 {
3461 .name = "smem",
3462 .pa_start = 0x401c0000,
3463 .pa_end = 0x401c5fff
3464 },
3465 {
3466 .name = "pmem",
3467 .pa_start = 0x401e0000,
3468 .pa_end = 0x401e1fff
3469 },
3470 {
3471 .name = "mpu",
3472 .pa_start = 0x401f1000,
3473 .pa_end = 0x401f13ff,
3474 .flags = ADDR_TYPE_RT
3475 },
3476 { }
3477 };
3478
3479 /* l4_abe -> aess */
3480 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_abe__aess = {
3481 .master = &omap44xx_l4_abe_hwmod,
3482 .slave = &omap44xx_aess_hwmod,
3483 .clk = "ocp_abe_iclk",
3484 .addr = omap44xx_aess_addrs,
3485 .user = OCP_USER_MPU,
3486 };
3487
3488 static struct omap_hwmod_addr_space omap44xx_aess_dma_addrs[] = {
3489 {
3490 .name = "dmem_dma",
3491 .pa_start = 0x49080000,
3492 .pa_end = 0x4908ffff
3493 },
3494 {
3495 .name = "cmem_dma",
3496 .pa_start = 0x490a0000,
3497 .pa_end = 0x490a1fff
3498 },
3499 {
3500 .name = "smem_dma",
3501 .pa_start = 0x490c0000,
3502 .pa_end = 0x490c5fff
3503 },
3504 {
3505 .name = "pmem_dma",
3506 .pa_start = 0x490e0000,
3507 .pa_end = 0x490e1fff
3508 },
3509 {
3510 .name = "dma",
3511 .pa_start = 0x490f1000,
3512 .pa_end = 0x490f13ff,
3513 .flags = ADDR_TYPE_RT
3514 },
3515 { }
3516 };
3517
3518 /* l4_abe -> aess (dma) */
3519 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_abe__aess_dma = {
3520 .master = &omap44xx_l4_abe_hwmod,
3521 .slave = &omap44xx_aess_hwmod,
3522 .clk = "ocp_abe_iclk",
3523 .addr = omap44xx_aess_dma_addrs,
3524 .user = OCP_USER_SDMA,
3525 };
3526
3527 /* l3_main_2 -> c2c */
3528 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__c2c = {
3529 .master = &omap44xx_l3_main_2_hwmod,
3530 .slave = &omap44xx_c2c_hwmod,
3531 .clk = "l3_div_ck",
3532 .user = OCP_USER_MPU | OCP_USER_SDMA,
3533 };
3534
3535 /* l4_wkup -> counter_32k */
3536 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__counter_32k = {
3537 .master = &omap44xx_l4_wkup_hwmod,
3538 .slave = &omap44xx_counter_32k_hwmod,
3539 .clk = "l4_wkup_clk_mux_ck",
3540 .user = OCP_USER_MPU | OCP_USER_SDMA,
3541 };
3542
3543 static struct omap_hwmod_addr_space omap44xx_ctrl_module_core_addrs[] = {
3544 {
3545 .pa_start = 0x4a002000,
3546 .pa_end = 0x4a0027ff,
3547 .flags = ADDR_TYPE_RT
3548 },
3549 { }
3550 };
3551
3552 /* l4_cfg -> ctrl_module_core */
3553 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ctrl_module_core = {
3554 .master = &omap44xx_l4_cfg_hwmod,
3555 .slave = &omap44xx_ctrl_module_core_hwmod,
3556 .clk = "l4_div_ck",
3557 .addr = omap44xx_ctrl_module_core_addrs,
3558 .user = OCP_USER_MPU | OCP_USER_SDMA,
3559 };
3560
3561 static struct omap_hwmod_addr_space omap44xx_ctrl_module_pad_core_addrs[] = {
3562 {
3563 .pa_start = 0x4a100000,
3564 .pa_end = 0x4a1007ff,
3565 .flags = ADDR_TYPE_RT
3566 },
3567 { }
3568 };
3569
3570 /* l4_cfg -> ctrl_module_pad_core */
3571 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ctrl_module_pad_core = {
3572 .master = &omap44xx_l4_cfg_hwmod,
3573 .slave = &omap44xx_ctrl_module_pad_core_hwmod,
3574 .clk = "l4_div_ck",
3575 .addr = omap44xx_ctrl_module_pad_core_addrs,
3576 .user = OCP_USER_MPU | OCP_USER_SDMA,
3577 };
3578
3579 static struct omap_hwmod_addr_space omap44xx_ctrl_module_wkup_addrs[] = {
3580 {
3581 .pa_start = 0x4a30c000,
3582 .pa_end = 0x4a30c7ff,
3583 .flags = ADDR_TYPE_RT
3584 },
3585 { }
3586 };
3587
3588 /* l4_wkup -> ctrl_module_wkup */
3589 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__ctrl_module_wkup = {
3590 .master = &omap44xx_l4_wkup_hwmod,
3591 .slave = &omap44xx_ctrl_module_wkup_hwmod,
3592 .clk = "l4_wkup_clk_mux_ck",
3593 .addr = omap44xx_ctrl_module_wkup_addrs,
3594 .user = OCP_USER_MPU | OCP_USER_SDMA,
3595 };
3596
3597 static struct omap_hwmod_addr_space omap44xx_ctrl_module_pad_wkup_addrs[] = {
3598 {
3599 .pa_start = 0x4a31e000,
3600 .pa_end = 0x4a31e7ff,
3601 .flags = ADDR_TYPE_RT
3602 },
3603 { }
3604 };
3605
3606 /* l4_wkup -> ctrl_module_pad_wkup */
3607 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__ctrl_module_pad_wkup = {
3608 .master = &omap44xx_l4_wkup_hwmod,
3609 .slave = &omap44xx_ctrl_module_pad_wkup_hwmod,
3610 .clk = "l4_wkup_clk_mux_ck",
3611 .addr = omap44xx_ctrl_module_pad_wkup_addrs,
3612 .user = OCP_USER_MPU | OCP_USER_SDMA,
3613 };
3614
3615 /* l3_instr -> debugss */
3616 static struct omap_hwmod_ocp_if omap44xx_l3_instr__debugss = {
3617 .master = &omap44xx_l3_instr_hwmod,
3618 .slave = &omap44xx_debugss_hwmod,
3619 .clk = "l3_div_ck",
3620 .user = OCP_USER_MPU | OCP_USER_SDMA,
3621 };
3622
3623 static struct omap_hwmod_addr_space omap44xx_dma_system_addrs[] = {
3624 {
3625 .pa_start = 0x4a056000,
3626 .pa_end = 0x4a056fff,
3627 .flags = ADDR_TYPE_RT
3628 },
3629 { }
3630 };
3631
3632 /* l4_cfg -> dma_system */
3633 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dma_system = {
3634 .master = &omap44xx_l4_cfg_hwmod,
3635 .slave = &omap44xx_dma_system_hwmod,
3636 .clk = "l4_div_ck",
3637 .addr = omap44xx_dma_system_addrs,
3638 .user = OCP_USER_MPU | OCP_USER_SDMA,
3639 };
3640
3641 /* l4_abe -> dmic */
3642 static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic = {
3643 .master = &omap44xx_l4_abe_hwmod,
3644 .slave = &omap44xx_dmic_hwmod,
3645 .clk = "ocp_abe_iclk",
3646 .user = OCP_USER_MPU | OCP_USER_SDMA,
3647 };
3648
3649 /* dsp -> iva */
3650 static struct omap_hwmod_ocp_if omap44xx_dsp__iva = {
3651 .master = &omap44xx_dsp_hwmod,
3652 .slave = &omap44xx_iva_hwmod,
3653 .clk = "dpll_iva_m5x2_ck",
3654 .user = OCP_USER_DSP,
3655 };
3656
3657 /* dsp -> sl2if */
3658 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_dsp__sl2if = {
3659 .master = &omap44xx_dsp_hwmod,
3660 .slave = &omap44xx_sl2if_hwmod,
3661 .clk = "dpll_iva_m5x2_ck",
3662 .user = OCP_USER_DSP,
3663 };
3664
3665 /* l4_cfg -> dsp */
3666 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dsp = {
3667 .master = &omap44xx_l4_cfg_hwmod,
3668 .slave = &omap44xx_dsp_hwmod,
3669 .clk = "l4_div_ck",
3670 .user = OCP_USER_MPU | OCP_USER_SDMA,
3671 };
3672
3673 static struct omap_hwmod_addr_space omap44xx_dss_dma_addrs[] = {
3674 {
3675 .pa_start = 0x58000000,
3676 .pa_end = 0x5800007f,
3677 .flags = ADDR_TYPE_RT
3678 },
3679 { }
3680 };
3681
3682 /* l3_main_2 -> dss */
3683 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss = {
3684 .master = &omap44xx_l3_main_2_hwmod,
3685 .slave = &omap44xx_dss_hwmod,
3686 .clk = "l3_div_ck",
3687 .addr = omap44xx_dss_dma_addrs,
3688 .user = OCP_USER_SDMA,
3689 };
3690
3691 static struct omap_hwmod_addr_space omap44xx_dss_addrs[] = {
3692 {
3693 .pa_start = 0x48040000,
3694 .pa_end = 0x4804007f,
3695 .flags = ADDR_TYPE_RT
3696 },
3697 { }
3698 };
3699
3700 /* l4_per -> dss */
3701 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss = {
3702 .master = &omap44xx_l4_per_hwmod,
3703 .slave = &omap44xx_dss_hwmod,
3704 .clk = "l4_div_ck",
3705 .addr = omap44xx_dss_addrs,
3706 .user = OCP_USER_MPU,
3707 };
3708
3709 static struct omap_hwmod_addr_space omap44xx_dss_dispc_dma_addrs[] = {
3710 {
3711 .pa_start = 0x58001000,
3712 .pa_end = 0x58001fff,
3713 .flags = ADDR_TYPE_RT
3714 },
3715 { }
3716 };
3717
3718 /* l3_main_2 -> dss_dispc */
3719 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dispc = {
3720 .master = &omap44xx_l3_main_2_hwmod,
3721 .slave = &omap44xx_dss_dispc_hwmod,
3722 .clk = "l3_div_ck",
3723 .addr = omap44xx_dss_dispc_dma_addrs,
3724 .user = OCP_USER_SDMA,
3725 };
3726
3727 static struct omap_hwmod_addr_space omap44xx_dss_dispc_addrs[] = {
3728 {
3729 .pa_start = 0x48041000,
3730 .pa_end = 0x48041fff,
3731 .flags = ADDR_TYPE_RT
3732 },
3733 { }
3734 };
3735
3736 /* l4_per -> dss_dispc */
3737 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dispc = {
3738 .master = &omap44xx_l4_per_hwmod,
3739 .slave = &omap44xx_dss_dispc_hwmod,
3740 .clk = "l4_div_ck",
3741 .addr = omap44xx_dss_dispc_addrs,
3742 .user = OCP_USER_MPU,
3743 };
3744
3745 static struct omap_hwmod_addr_space omap44xx_dss_dsi1_dma_addrs[] = {
3746 {
3747 .pa_start = 0x58004000,
3748 .pa_end = 0x580041ff,
3749 .flags = ADDR_TYPE_RT
3750 },
3751 { }
3752 };
3753
3754 /* l3_main_2 -> dss_dsi1 */
3755 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi1 = {
3756 .master = &omap44xx_l3_main_2_hwmod,
3757 .slave = &omap44xx_dss_dsi1_hwmod,
3758 .clk = "l3_div_ck",
3759 .addr = omap44xx_dss_dsi1_dma_addrs,
3760 .user = OCP_USER_SDMA,
3761 };
3762
3763 static struct omap_hwmod_addr_space omap44xx_dss_dsi1_addrs[] = {
3764 {
3765 .pa_start = 0x48044000,
3766 .pa_end = 0x480441ff,
3767 .flags = ADDR_TYPE_RT
3768 },
3769 { }
3770 };
3771
3772 /* l4_per -> dss_dsi1 */
3773 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi1 = {
3774 .master = &omap44xx_l4_per_hwmod,
3775 .slave = &omap44xx_dss_dsi1_hwmod,
3776 .clk = "l4_div_ck",
3777 .addr = omap44xx_dss_dsi1_addrs,
3778 .user = OCP_USER_MPU,
3779 };
3780
3781 static struct omap_hwmod_addr_space omap44xx_dss_dsi2_dma_addrs[] = {
3782 {
3783 .pa_start = 0x58005000,
3784 .pa_end = 0x580051ff,
3785 .flags = ADDR_TYPE_RT
3786 },
3787 { }
3788 };
3789
3790 /* l3_main_2 -> dss_dsi2 */
3791 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi2 = {
3792 .master = &omap44xx_l3_main_2_hwmod,
3793 .slave = &omap44xx_dss_dsi2_hwmod,
3794 .clk = "l3_div_ck",
3795 .addr = omap44xx_dss_dsi2_dma_addrs,
3796 .user = OCP_USER_SDMA,
3797 };
3798
3799 static struct omap_hwmod_addr_space omap44xx_dss_dsi2_addrs[] = {
3800 {
3801 .pa_start = 0x48045000,
3802 .pa_end = 0x480451ff,
3803 .flags = ADDR_TYPE_RT
3804 },
3805 { }
3806 };
3807
3808 /* l4_per -> dss_dsi2 */
3809 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi2 = {
3810 .master = &omap44xx_l4_per_hwmod,
3811 .slave = &omap44xx_dss_dsi2_hwmod,
3812 .clk = "l4_div_ck",
3813 .addr = omap44xx_dss_dsi2_addrs,
3814 .user = OCP_USER_MPU,
3815 };
3816
3817 static struct omap_hwmod_addr_space omap44xx_dss_hdmi_dma_addrs[] = {
3818 {
3819 .pa_start = 0x58006000,
3820 .pa_end = 0x58006fff,
3821 .flags = ADDR_TYPE_RT
3822 },
3823 { }
3824 };
3825
3826 /* l3_main_2 -> dss_hdmi */
3827 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_hdmi = {
3828 .master = &omap44xx_l3_main_2_hwmod,
3829 .slave = &omap44xx_dss_hdmi_hwmod,
3830 .clk = "l3_div_ck",
3831 .addr = omap44xx_dss_hdmi_dma_addrs,
3832 .user = OCP_USER_SDMA,
3833 };
3834
3835 static struct omap_hwmod_addr_space omap44xx_dss_hdmi_addrs[] = {
3836 {
3837 .pa_start = 0x48046000,
3838 .pa_end = 0x48046fff,
3839 .flags = ADDR_TYPE_RT
3840 },
3841 { }
3842 };
3843
3844 /* l4_per -> dss_hdmi */
3845 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_hdmi = {
3846 .master = &omap44xx_l4_per_hwmod,
3847 .slave = &omap44xx_dss_hdmi_hwmod,
3848 .clk = "l4_div_ck",
3849 .addr = omap44xx_dss_hdmi_addrs,
3850 .user = OCP_USER_MPU,
3851 };
3852
3853 static struct omap_hwmod_addr_space omap44xx_dss_rfbi_dma_addrs[] = {
3854 {
3855 .pa_start = 0x58002000,
3856 .pa_end = 0x580020ff,
3857 .flags = ADDR_TYPE_RT
3858 },
3859 { }
3860 };
3861
3862 /* l3_main_2 -> dss_rfbi */
3863 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_rfbi = {
3864 .master = &omap44xx_l3_main_2_hwmod,
3865 .slave = &omap44xx_dss_rfbi_hwmod,
3866 .clk = "l3_div_ck",
3867 .addr = omap44xx_dss_rfbi_dma_addrs,
3868 .user = OCP_USER_SDMA,
3869 };
3870
3871 static struct omap_hwmod_addr_space omap44xx_dss_rfbi_addrs[] = {
3872 {
3873 .pa_start = 0x48042000,
3874 .pa_end = 0x480420ff,
3875 .flags = ADDR_TYPE_RT
3876 },
3877 { }
3878 };
3879
3880 /* l4_per -> dss_rfbi */
3881 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_rfbi = {
3882 .master = &omap44xx_l4_per_hwmod,
3883 .slave = &omap44xx_dss_rfbi_hwmod,
3884 .clk = "l4_div_ck",
3885 .addr = omap44xx_dss_rfbi_addrs,
3886 .user = OCP_USER_MPU,
3887 };
3888
3889 static struct omap_hwmod_addr_space omap44xx_dss_venc_dma_addrs[] = {
3890 {
3891 .pa_start = 0x58003000,
3892 .pa_end = 0x580030ff,
3893 .flags = ADDR_TYPE_RT
3894 },
3895 { }
3896 };
3897
3898 /* l3_main_2 -> dss_venc */
3899 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_venc = {
3900 .master = &omap44xx_l3_main_2_hwmod,
3901 .slave = &omap44xx_dss_venc_hwmod,
3902 .clk = "l3_div_ck",
3903 .addr = omap44xx_dss_venc_dma_addrs,
3904 .user = OCP_USER_SDMA,
3905 };
3906
3907 static struct omap_hwmod_addr_space omap44xx_dss_venc_addrs[] = {
3908 {
3909 .pa_start = 0x48043000,
3910 .pa_end = 0x480430ff,
3911 .flags = ADDR_TYPE_RT
3912 },
3913 { }
3914 };
3915
3916 /* l4_per -> dss_venc */
3917 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_venc = {
3918 .master = &omap44xx_l4_per_hwmod,
3919 .slave = &omap44xx_dss_venc_hwmod,
3920 .clk = "l4_div_ck",
3921 .addr = omap44xx_dss_venc_addrs,
3922 .user = OCP_USER_MPU,
3923 };
3924
3925 static struct omap_hwmod_addr_space omap44xx_elm_addrs[] = {
3926 {
3927 .pa_start = 0x48078000,
3928 .pa_end = 0x48078fff,
3929 .flags = ADDR_TYPE_RT
3930 },
3931 { }
3932 };
3933
3934 /* l4_per -> elm */
3935 static struct omap_hwmod_ocp_if omap44xx_l4_per__elm = {
3936 .master = &omap44xx_l4_per_hwmod,
3937 .slave = &omap44xx_elm_hwmod,
3938 .clk = "l4_div_ck",
3939 .addr = omap44xx_elm_addrs,
3940 .user = OCP_USER_MPU | OCP_USER_SDMA,
3941 };
3942
3943 static struct omap_hwmod_addr_space omap44xx_fdif_addrs[] = {
3944 {
3945 .pa_start = 0x4a10a000,
3946 .pa_end = 0x4a10a1ff,
3947 .flags = ADDR_TYPE_RT
3948 },
3949 { }
3950 };
3951
3952 /* l4_cfg -> fdif */
3953 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__fdif = {
3954 .master = &omap44xx_l4_cfg_hwmod,
3955 .slave = &omap44xx_fdif_hwmod,
3956 .clk = "l4_div_ck",
3957 .addr = omap44xx_fdif_addrs,
3958 .user = OCP_USER_MPU | OCP_USER_SDMA,
3959 };
3960
3961 /* l4_wkup -> gpio1 */
3962 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__gpio1 = {
3963 .master = &omap44xx_l4_wkup_hwmod,
3964 .slave = &omap44xx_gpio1_hwmod,
3965 .clk = "l4_wkup_clk_mux_ck",
3966 .user = OCP_USER_MPU | OCP_USER_SDMA,
3967 };
3968
3969 /* l4_per -> gpio2 */
3970 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio2 = {
3971 .master = &omap44xx_l4_per_hwmod,
3972 .slave = &omap44xx_gpio2_hwmod,
3973 .clk = "l4_div_ck",
3974 .user = OCP_USER_MPU | OCP_USER_SDMA,
3975 };
3976
3977 /* l4_per -> gpio3 */
3978 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio3 = {
3979 .master = &omap44xx_l4_per_hwmod,
3980 .slave = &omap44xx_gpio3_hwmod,
3981 .clk = "l4_div_ck",
3982 .user = OCP_USER_MPU | OCP_USER_SDMA,
3983 };
3984
3985 /* l4_per -> gpio4 */
3986 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio4 = {
3987 .master = &omap44xx_l4_per_hwmod,
3988 .slave = &omap44xx_gpio4_hwmod,
3989 .clk = "l4_div_ck",
3990 .user = OCP_USER_MPU | OCP_USER_SDMA,
3991 };
3992
3993 /* l4_per -> gpio5 */
3994 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio5 = {
3995 .master = &omap44xx_l4_per_hwmod,
3996 .slave = &omap44xx_gpio5_hwmod,
3997 .clk = "l4_div_ck",
3998 .user = OCP_USER_MPU | OCP_USER_SDMA,
3999 };
4000
4001 /* l4_per -> gpio6 */
4002 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio6 = {
4003 .master = &omap44xx_l4_per_hwmod,
4004 .slave = &omap44xx_gpio6_hwmod,
4005 .clk = "l4_div_ck",
4006 .user = OCP_USER_MPU | OCP_USER_SDMA,
4007 };
4008
4009 /* l3_main_2 -> gpmc */
4010 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpmc = {
4011 .master = &omap44xx_l3_main_2_hwmod,
4012 .slave = &omap44xx_gpmc_hwmod,
4013 .clk = "l3_div_ck",
4014 .user = OCP_USER_MPU | OCP_USER_SDMA,
4015 };
4016
4017 static struct omap_hwmod_addr_space omap44xx_gpu_addrs[] = {
4018 {
4019 .pa_start = 0x56000000,
4020 .pa_end = 0x5600ffff,
4021 .flags = ADDR_TYPE_RT
4022 },
4023 { }
4024 };
4025
4026 /* l3_main_2 -> gpu */
4027 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpu = {
4028 .master = &omap44xx_l3_main_2_hwmod,
4029 .slave = &omap44xx_gpu_hwmod,
4030 .clk = "l3_div_ck",
4031 .addr = omap44xx_gpu_addrs,
4032 .user = OCP_USER_MPU | OCP_USER_SDMA,
4033 };
4034
4035 static struct omap_hwmod_addr_space omap44xx_hdq1w_addrs[] = {
4036 {
4037 .pa_start = 0x480b2000,
4038 .pa_end = 0x480b201f,
4039 .flags = ADDR_TYPE_RT
4040 },
4041 { }
4042 };
4043
4044 /* l4_per -> hdq1w */
4045 static struct omap_hwmod_ocp_if omap44xx_l4_per__hdq1w = {
4046 .master = &omap44xx_l4_per_hwmod,
4047 .slave = &omap44xx_hdq1w_hwmod,
4048 .clk = "l4_div_ck",
4049 .addr = omap44xx_hdq1w_addrs,
4050 .user = OCP_USER_MPU | OCP_USER_SDMA,
4051 };
4052
4053 static struct omap_hwmod_addr_space omap44xx_hsi_addrs[] = {
4054 {
4055 .pa_start = 0x4a058000,
4056 .pa_end = 0x4a05bfff,
4057 .flags = ADDR_TYPE_RT
4058 },
4059 { }
4060 };
4061
4062 /* l4_cfg -> hsi */
4063 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__hsi = {
4064 .master = &omap44xx_l4_cfg_hwmod,
4065 .slave = &omap44xx_hsi_hwmod,
4066 .clk = "l4_div_ck",
4067 .addr = omap44xx_hsi_addrs,
4068 .user = OCP_USER_MPU | OCP_USER_SDMA,
4069 };
4070
4071 /* l4_per -> i2c1 */
4072 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c1 = {
4073 .master = &omap44xx_l4_per_hwmod,
4074 .slave = &omap44xx_i2c1_hwmod,
4075 .clk = "l4_div_ck",
4076 .user = OCP_USER_MPU | OCP_USER_SDMA,
4077 };
4078
4079 /* l4_per -> i2c2 */
4080 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c2 = {
4081 .master = &omap44xx_l4_per_hwmod,
4082 .slave = &omap44xx_i2c2_hwmod,
4083 .clk = "l4_div_ck",
4084 .user = OCP_USER_MPU | OCP_USER_SDMA,
4085 };
4086
4087 /* l4_per -> i2c3 */
4088 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c3 = {
4089 .master = &omap44xx_l4_per_hwmod,
4090 .slave = &omap44xx_i2c3_hwmod,
4091 .clk = "l4_div_ck",
4092 .user = OCP_USER_MPU | OCP_USER_SDMA,
4093 };
4094
4095 /* l4_per -> i2c4 */
4096 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c4 = {
4097 .master = &omap44xx_l4_per_hwmod,
4098 .slave = &omap44xx_i2c4_hwmod,
4099 .clk = "l4_div_ck",
4100 .user = OCP_USER_MPU | OCP_USER_SDMA,
4101 };
4102
4103 /* l3_main_2 -> ipu */
4104 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ipu = {
4105 .master = &omap44xx_l3_main_2_hwmod,
4106 .slave = &omap44xx_ipu_hwmod,
4107 .clk = "l3_div_ck",
4108 .user = OCP_USER_MPU | OCP_USER_SDMA,
4109 };
4110
4111 static struct omap_hwmod_addr_space omap44xx_iss_addrs[] = {
4112 {
4113 .pa_start = 0x52000000,
4114 .pa_end = 0x520000ff,
4115 .flags = ADDR_TYPE_RT
4116 },
4117 { }
4118 };
4119
4120 /* l3_main_2 -> iss */
4121 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iss = {
4122 .master = &omap44xx_l3_main_2_hwmod,
4123 .slave = &omap44xx_iss_hwmod,
4124 .clk = "l3_div_ck",
4125 .addr = omap44xx_iss_addrs,
4126 .user = OCP_USER_MPU | OCP_USER_SDMA,
4127 };
4128
4129 /* iva -> sl2if */
4130 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_iva__sl2if = {
4131 .master = &omap44xx_iva_hwmod,
4132 .slave = &omap44xx_sl2if_hwmod,
4133 .clk = "dpll_iva_m5x2_ck",
4134 .user = OCP_USER_IVA,
4135 };
4136
4137 /* l3_main_2 -> iva */
4138 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iva = {
4139 .master = &omap44xx_l3_main_2_hwmod,
4140 .slave = &omap44xx_iva_hwmod,
4141 .clk = "l3_div_ck",
4142 .user = OCP_USER_MPU,
4143 };
4144
4145 /* l4_wkup -> kbd */
4146 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__kbd = {
4147 .master = &omap44xx_l4_wkup_hwmod,
4148 .slave = &omap44xx_kbd_hwmod,
4149 .clk = "l4_wkup_clk_mux_ck",
4150 .user = OCP_USER_MPU | OCP_USER_SDMA,
4151 };
4152
4153 /* l4_cfg -> mailbox */
4154 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mailbox = {
4155 .master = &omap44xx_l4_cfg_hwmod,
4156 .slave = &omap44xx_mailbox_hwmod,
4157 .clk = "l4_div_ck",
4158 .user = OCP_USER_MPU | OCP_USER_SDMA,
4159 };
4160
4161 static struct omap_hwmod_addr_space omap44xx_mcasp_addrs[] = {
4162 {
4163 .pa_start = 0x40128000,
4164 .pa_end = 0x401283ff,
4165 .flags = ADDR_TYPE_RT
4166 },
4167 { }
4168 };
4169
4170 /* l4_abe -> mcasp */
4171 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcasp = {
4172 .master = &omap44xx_l4_abe_hwmod,
4173 .slave = &omap44xx_mcasp_hwmod,
4174 .clk = "ocp_abe_iclk",
4175 .addr = omap44xx_mcasp_addrs,
4176 .user = OCP_USER_MPU,
4177 };
4178
4179 static struct omap_hwmod_addr_space omap44xx_mcasp_dma_addrs[] = {
4180 {
4181 .pa_start = 0x49028000,
4182 .pa_end = 0x490283ff,
4183 .flags = ADDR_TYPE_RT
4184 },
4185 { }
4186 };
4187
4188 /* l4_abe -> mcasp (dma) */
4189 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcasp_dma = {
4190 .master = &omap44xx_l4_abe_hwmod,
4191 .slave = &omap44xx_mcasp_hwmod,
4192 .clk = "ocp_abe_iclk",
4193 .addr = omap44xx_mcasp_dma_addrs,
4194 .user = OCP_USER_SDMA,
4195 };
4196
4197 /* l4_abe -> mcbsp1 */
4198 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1 = {
4199 .master = &omap44xx_l4_abe_hwmod,
4200 .slave = &omap44xx_mcbsp1_hwmod,
4201 .clk = "ocp_abe_iclk",
4202 .user = OCP_USER_MPU | OCP_USER_SDMA,
4203 };
4204
4205 /* l4_abe -> mcbsp2 */
4206 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2 = {
4207 .master = &omap44xx_l4_abe_hwmod,
4208 .slave = &omap44xx_mcbsp2_hwmod,
4209 .clk = "ocp_abe_iclk",
4210 .user = OCP_USER_MPU | OCP_USER_SDMA,
4211 };
4212
4213 /* l4_abe -> mcbsp3 */
4214 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3 = {
4215 .master = &omap44xx_l4_abe_hwmod,
4216 .slave = &omap44xx_mcbsp3_hwmod,
4217 .clk = "ocp_abe_iclk",
4218 .user = OCP_USER_MPU | OCP_USER_SDMA,
4219 };
4220
4221 /* l4_per -> mcbsp4 */
4222 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcbsp4 = {
4223 .master = &omap44xx_l4_per_hwmod,
4224 .slave = &omap44xx_mcbsp4_hwmod,
4225 .clk = "l4_div_ck",
4226 .user = OCP_USER_MPU | OCP_USER_SDMA,
4227 };
4228
4229 /* l4_abe -> mcpdm */
4230 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm = {
4231 .master = &omap44xx_l4_abe_hwmod,
4232 .slave = &omap44xx_mcpdm_hwmod,
4233 .clk = "ocp_abe_iclk",
4234 .user = OCP_USER_MPU | OCP_USER_SDMA,
4235 };
4236
4237 /* l4_per -> mcspi1 */
4238 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi1 = {
4239 .master = &omap44xx_l4_per_hwmod,
4240 .slave = &omap44xx_mcspi1_hwmod,
4241 .clk = "l4_div_ck",
4242 .user = OCP_USER_MPU | OCP_USER_SDMA,
4243 };
4244
4245 /* l4_per -> mcspi2 */
4246 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi2 = {
4247 .master = &omap44xx_l4_per_hwmod,
4248 .slave = &omap44xx_mcspi2_hwmod,
4249 .clk = "l4_div_ck",
4250 .user = OCP_USER_MPU | OCP_USER_SDMA,
4251 };
4252
4253 /* l4_per -> mcspi3 */
4254 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi3 = {
4255 .master = &omap44xx_l4_per_hwmod,
4256 .slave = &omap44xx_mcspi3_hwmod,
4257 .clk = "l4_div_ck",
4258 .user = OCP_USER_MPU | OCP_USER_SDMA,
4259 };
4260
4261 /* l4_per -> mcspi4 */
4262 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi4 = {
4263 .master = &omap44xx_l4_per_hwmod,
4264 .slave = &omap44xx_mcspi4_hwmod,
4265 .clk = "l4_div_ck",
4266 .user = OCP_USER_MPU | OCP_USER_SDMA,
4267 };
4268
4269 /* l4_per -> mmc1 */
4270 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc1 = {
4271 .master = &omap44xx_l4_per_hwmod,
4272 .slave = &omap44xx_mmc1_hwmod,
4273 .clk = "l4_div_ck",
4274 .user = OCP_USER_MPU | OCP_USER_SDMA,
4275 };
4276
4277 /* l4_per -> mmc2 */
4278 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc2 = {
4279 .master = &omap44xx_l4_per_hwmod,
4280 .slave = &omap44xx_mmc2_hwmod,
4281 .clk = "l4_div_ck",
4282 .user = OCP_USER_MPU | OCP_USER_SDMA,
4283 };
4284
4285 /* l4_per -> mmc3 */
4286 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc3 = {
4287 .master = &omap44xx_l4_per_hwmod,
4288 .slave = &omap44xx_mmc3_hwmod,
4289 .clk = "l4_div_ck",
4290 .user = OCP_USER_MPU | OCP_USER_SDMA,
4291 };
4292
4293 /* l4_per -> mmc4 */
4294 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc4 = {
4295 .master = &omap44xx_l4_per_hwmod,
4296 .slave = &omap44xx_mmc4_hwmod,
4297 .clk = "l4_div_ck",
4298 .user = OCP_USER_MPU | OCP_USER_SDMA,
4299 };
4300
4301 /* l4_per -> mmc5 */
4302 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc5 = {
4303 .master = &omap44xx_l4_per_hwmod,
4304 .slave = &omap44xx_mmc5_hwmod,
4305 .clk = "l4_div_ck",
4306 .user = OCP_USER_MPU | OCP_USER_SDMA,
4307 };
4308
4309 /* l3_main_2 -> ocmc_ram */
4310 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ocmc_ram = {
4311 .master = &omap44xx_l3_main_2_hwmod,
4312 .slave = &omap44xx_ocmc_ram_hwmod,
4313 .clk = "l3_div_ck",
4314 .user = OCP_USER_MPU | OCP_USER_SDMA,
4315 };
4316
4317 /* l4_cfg -> ocp2scp_usb_phy */
4318 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp2scp_usb_phy = {
4319 .master = &omap44xx_l4_cfg_hwmod,
4320 .slave = &omap44xx_ocp2scp_usb_phy_hwmod,
4321 .clk = "l4_div_ck",
4322 .user = OCP_USER_MPU | OCP_USER_SDMA,
4323 };
4324
4325 /* mpu_private -> prcm_mpu */
4326 static struct omap_hwmod_ocp_if omap44xx_mpu_private__prcm_mpu = {
4327 .master = &omap44xx_mpu_private_hwmod,
4328 .slave = &omap44xx_prcm_mpu_hwmod,
4329 .clk = "l3_div_ck",
4330 .user = OCP_USER_MPU | OCP_USER_SDMA,
4331 };
4332
4333 /* l4_wkup -> cm_core_aon */
4334 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__cm_core_aon = {
4335 .master = &omap44xx_l4_wkup_hwmod,
4336 .slave = &omap44xx_cm_core_aon_hwmod,
4337 .clk = "l4_wkup_clk_mux_ck",
4338 .user = OCP_USER_MPU | OCP_USER_SDMA,
4339 };
4340
4341 /* l4_cfg -> cm_core */
4342 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__cm_core = {
4343 .master = &omap44xx_l4_cfg_hwmod,
4344 .slave = &omap44xx_cm_core_hwmod,
4345 .clk = "l4_div_ck",
4346 .user = OCP_USER_MPU | OCP_USER_SDMA,
4347 };
4348
4349 /* l4_wkup -> prm */
4350 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__prm = {
4351 .master = &omap44xx_l4_wkup_hwmod,
4352 .slave = &omap44xx_prm_hwmod,
4353 .clk = "l4_wkup_clk_mux_ck",
4354 .user = OCP_USER_MPU | OCP_USER_SDMA,
4355 };
4356
4357 /* l4_wkup -> scrm */
4358 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__scrm = {
4359 .master = &omap44xx_l4_wkup_hwmod,
4360 .slave = &omap44xx_scrm_hwmod,
4361 .clk = "l4_wkup_clk_mux_ck",
4362 .user = OCP_USER_MPU | OCP_USER_SDMA,
4363 };
4364
4365 /* l3_main_2 -> sl2if */
4366 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l3_main_2__sl2if = {
4367 .master = &omap44xx_l3_main_2_hwmod,
4368 .slave = &omap44xx_sl2if_hwmod,
4369 .clk = "l3_div_ck",
4370 .user = OCP_USER_MPU | OCP_USER_SDMA,
4371 };
4372
4373 static struct omap_hwmod_addr_space omap44xx_slimbus1_addrs[] = {
4374 {
4375 .pa_start = 0x4012c000,
4376 .pa_end = 0x4012c3ff,
4377 .flags = ADDR_TYPE_RT
4378 },
4379 { }
4380 };
4381
4382 /* l4_abe -> slimbus1 */
4383 static struct omap_hwmod_ocp_if omap44xx_l4_abe__slimbus1 = {
4384 .master = &omap44xx_l4_abe_hwmod,
4385 .slave = &omap44xx_slimbus1_hwmod,
4386 .clk = "ocp_abe_iclk",
4387 .addr = omap44xx_slimbus1_addrs,
4388 .user = OCP_USER_MPU,
4389 };
4390
4391 static struct omap_hwmod_addr_space omap44xx_slimbus1_dma_addrs[] = {
4392 {
4393 .pa_start = 0x4902c000,
4394 .pa_end = 0x4902c3ff,
4395 .flags = ADDR_TYPE_RT
4396 },
4397 { }
4398 };
4399
4400 /* l4_abe -> slimbus1 (dma) */
4401 static struct omap_hwmod_ocp_if omap44xx_l4_abe__slimbus1_dma = {
4402 .master = &omap44xx_l4_abe_hwmod,
4403 .slave = &omap44xx_slimbus1_hwmod,
4404 .clk = "ocp_abe_iclk",
4405 .addr = omap44xx_slimbus1_dma_addrs,
4406 .user = OCP_USER_SDMA,
4407 };
4408
4409 static struct omap_hwmod_addr_space omap44xx_slimbus2_addrs[] = {
4410 {
4411 .pa_start = 0x48076000,
4412 .pa_end = 0x480763ff,
4413 .flags = ADDR_TYPE_RT
4414 },
4415 { }
4416 };
4417
4418 /* l4_per -> slimbus2 */
4419 static struct omap_hwmod_ocp_if omap44xx_l4_per__slimbus2 = {
4420 .master = &omap44xx_l4_per_hwmod,
4421 .slave = &omap44xx_slimbus2_hwmod,
4422 .clk = "l4_div_ck",
4423 .addr = omap44xx_slimbus2_addrs,
4424 .user = OCP_USER_MPU | OCP_USER_SDMA,
4425 };
4426
4427 static struct omap_hwmod_addr_space omap44xx_smartreflex_core_addrs[] = {
4428 {
4429 .pa_start = 0x4a0dd000,
4430 .pa_end = 0x4a0dd03f,
4431 .flags = ADDR_TYPE_RT
4432 },
4433 { }
4434 };
4435
4436 /* l4_cfg -> smartreflex_core */
4437 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_core = {
4438 .master = &omap44xx_l4_cfg_hwmod,
4439 .slave = &omap44xx_smartreflex_core_hwmod,
4440 .clk = "l4_div_ck",
4441 .addr = omap44xx_smartreflex_core_addrs,
4442 .user = OCP_USER_MPU | OCP_USER_SDMA,
4443 };
4444
4445 static struct omap_hwmod_addr_space omap44xx_smartreflex_iva_addrs[] = {
4446 {
4447 .pa_start = 0x4a0db000,
4448 .pa_end = 0x4a0db03f,
4449 .flags = ADDR_TYPE_RT
4450 },
4451 { }
4452 };
4453
4454 /* l4_cfg -> smartreflex_iva */
4455 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_iva = {
4456 .master = &omap44xx_l4_cfg_hwmod,
4457 .slave = &omap44xx_smartreflex_iva_hwmod,
4458 .clk = "l4_div_ck",
4459 .addr = omap44xx_smartreflex_iva_addrs,
4460 .user = OCP_USER_MPU | OCP_USER_SDMA,
4461 };
4462
4463 static struct omap_hwmod_addr_space omap44xx_smartreflex_mpu_addrs[] = {
4464 {
4465 .pa_start = 0x4a0d9000,
4466 .pa_end = 0x4a0d903f,
4467 .flags = ADDR_TYPE_RT
4468 },
4469 { }
4470 };
4471
4472 /* l4_cfg -> smartreflex_mpu */
4473 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_mpu = {
4474 .master = &omap44xx_l4_cfg_hwmod,
4475 .slave = &omap44xx_smartreflex_mpu_hwmod,
4476 .clk = "l4_div_ck",
4477 .addr = omap44xx_smartreflex_mpu_addrs,
4478 .user = OCP_USER_MPU | OCP_USER_SDMA,
4479 };
4480
4481 static struct omap_hwmod_addr_space omap44xx_spinlock_addrs[] = {
4482 {
4483 .pa_start = 0x4a0f6000,
4484 .pa_end = 0x4a0f6fff,
4485 .flags = ADDR_TYPE_RT
4486 },
4487 { }
4488 };
4489
4490 /* l4_cfg -> spinlock */
4491 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__spinlock = {
4492 .master = &omap44xx_l4_cfg_hwmod,
4493 .slave = &omap44xx_spinlock_hwmod,
4494 .clk = "l4_div_ck",
4495 .addr = omap44xx_spinlock_addrs,
4496 .user = OCP_USER_MPU | OCP_USER_SDMA,
4497 };
4498
4499 /* l4_wkup -> timer1 */
4500 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__timer1 = {
4501 .master = &omap44xx_l4_wkup_hwmod,
4502 .slave = &omap44xx_timer1_hwmod,
4503 .clk = "l4_wkup_clk_mux_ck",
4504 .user = OCP_USER_MPU | OCP_USER_SDMA,
4505 };
4506
4507 /* l4_per -> timer2 */
4508 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer2 = {
4509 .master = &omap44xx_l4_per_hwmod,
4510 .slave = &omap44xx_timer2_hwmod,
4511 .clk = "l4_div_ck",
4512 .user = OCP_USER_MPU | OCP_USER_SDMA,
4513 };
4514
4515 /* l4_per -> timer3 */
4516 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer3 = {
4517 .master = &omap44xx_l4_per_hwmod,
4518 .slave = &omap44xx_timer3_hwmod,
4519 .clk = "l4_div_ck",
4520 .user = OCP_USER_MPU | OCP_USER_SDMA,
4521 };
4522
4523 /* l4_per -> timer4 */
4524 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer4 = {
4525 .master = &omap44xx_l4_per_hwmod,
4526 .slave = &omap44xx_timer4_hwmod,
4527 .clk = "l4_div_ck",
4528 .user = OCP_USER_MPU | OCP_USER_SDMA,
4529 };
4530
4531 /* l4_abe -> timer5 */
4532 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5 = {
4533 .master = &omap44xx_l4_abe_hwmod,
4534 .slave = &omap44xx_timer5_hwmod,
4535 .clk = "ocp_abe_iclk",
4536 .user = OCP_USER_MPU | OCP_USER_SDMA,
4537 };
4538
4539 /* l4_abe -> timer6 */
4540 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6 = {
4541 .master = &omap44xx_l4_abe_hwmod,
4542 .slave = &omap44xx_timer6_hwmod,
4543 .clk = "ocp_abe_iclk",
4544 .user = OCP_USER_MPU | OCP_USER_SDMA,
4545 };
4546
4547 /* l4_abe -> timer7 */
4548 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7 = {
4549 .master = &omap44xx_l4_abe_hwmod,
4550 .slave = &omap44xx_timer7_hwmod,
4551 .clk = "ocp_abe_iclk",
4552 .user = OCP_USER_MPU | OCP_USER_SDMA,
4553 };
4554
4555 /* l4_abe -> timer8 */
4556 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8 = {
4557 .master = &omap44xx_l4_abe_hwmod,
4558 .slave = &omap44xx_timer8_hwmod,
4559 .clk = "ocp_abe_iclk",
4560 .user = OCP_USER_MPU | OCP_USER_SDMA,
4561 };
4562
4563 /* l4_per -> timer9 */
4564 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer9 = {
4565 .master = &omap44xx_l4_per_hwmod,
4566 .slave = &omap44xx_timer9_hwmod,
4567 .clk = "l4_div_ck",
4568 .user = OCP_USER_MPU | OCP_USER_SDMA,
4569 };
4570
4571 /* l4_per -> timer10 */
4572 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer10 = {
4573 .master = &omap44xx_l4_per_hwmod,
4574 .slave = &omap44xx_timer10_hwmod,
4575 .clk = "l4_div_ck",
4576 .user = OCP_USER_MPU | OCP_USER_SDMA,
4577 };
4578
4579 /* l4_per -> timer11 */
4580 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer11 = {
4581 .master = &omap44xx_l4_per_hwmod,
4582 .slave = &omap44xx_timer11_hwmod,
4583 .clk = "l4_div_ck",
4584 .user = OCP_USER_MPU | OCP_USER_SDMA,
4585 };
4586
4587 /* l4_per -> uart1 */
4588 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart1 = {
4589 .master = &omap44xx_l4_per_hwmod,
4590 .slave = &omap44xx_uart1_hwmod,
4591 .clk = "l4_div_ck",
4592 .user = OCP_USER_MPU | OCP_USER_SDMA,
4593 };
4594
4595 /* l4_per -> uart2 */
4596 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart2 = {
4597 .master = &omap44xx_l4_per_hwmod,
4598 .slave = &omap44xx_uart2_hwmod,
4599 .clk = "l4_div_ck",
4600 .user = OCP_USER_MPU | OCP_USER_SDMA,
4601 };
4602
4603 /* l4_per -> uart3 */
4604 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart3 = {
4605 .master = &omap44xx_l4_per_hwmod,
4606 .slave = &omap44xx_uart3_hwmod,
4607 .clk = "l4_div_ck",
4608 .user = OCP_USER_MPU | OCP_USER_SDMA,
4609 };
4610
4611 /* l4_per -> uart4 */
4612 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart4 = {
4613 .master = &omap44xx_l4_per_hwmod,
4614 .slave = &omap44xx_uart4_hwmod,
4615 .clk = "l4_div_ck",
4616 .user = OCP_USER_MPU | OCP_USER_SDMA,
4617 };
4618
4619 /* l4_cfg -> usb_host_fs */
4620 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_cfg__usb_host_fs = {
4621 .master = &omap44xx_l4_cfg_hwmod,
4622 .slave = &omap44xx_usb_host_fs_hwmod,
4623 .clk = "l4_div_ck",
4624 .user = OCP_USER_MPU | OCP_USER_SDMA,
4625 };
4626
4627 /* l4_cfg -> usb_host_hs */
4628 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_host_hs = {
4629 .master = &omap44xx_l4_cfg_hwmod,
4630 .slave = &omap44xx_usb_host_hs_hwmod,
4631 .clk = "l4_div_ck",
4632 .user = OCP_USER_MPU | OCP_USER_SDMA,
4633 };
4634
4635 /* l4_cfg -> usb_otg_hs */
4636 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_otg_hs = {
4637 .master = &omap44xx_l4_cfg_hwmod,
4638 .slave = &omap44xx_usb_otg_hs_hwmod,
4639 .clk = "l4_div_ck",
4640 .user = OCP_USER_MPU | OCP_USER_SDMA,
4641 };
4642
4643 /* l4_cfg -> usb_tll_hs */
4644 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_tll_hs = {
4645 .master = &omap44xx_l4_cfg_hwmod,
4646 .slave = &omap44xx_usb_tll_hs_hwmod,
4647 .clk = "l4_div_ck",
4648 .user = OCP_USER_MPU | OCP_USER_SDMA,
4649 };
4650
4651 /* l4_wkup -> wd_timer2 */
4652 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__wd_timer2 = {
4653 .master = &omap44xx_l4_wkup_hwmod,
4654 .slave = &omap44xx_wd_timer2_hwmod,
4655 .clk = "l4_wkup_clk_mux_ck",
4656 .user = OCP_USER_MPU | OCP_USER_SDMA,
4657 };
4658
4659 static struct omap_hwmod_addr_space omap44xx_wd_timer3_addrs[] = {
4660 {
4661 .pa_start = 0x40130000,
4662 .pa_end = 0x4013007f,
4663 .flags = ADDR_TYPE_RT
4664 },
4665 { }
4666 };
4667
4668 /* l4_abe -> wd_timer3 */
4669 static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3 = {
4670 .master = &omap44xx_l4_abe_hwmod,
4671 .slave = &omap44xx_wd_timer3_hwmod,
4672 .clk = "ocp_abe_iclk",
4673 .addr = omap44xx_wd_timer3_addrs,
4674 .user = OCP_USER_MPU,
4675 };
4676
4677 static struct omap_hwmod_addr_space omap44xx_wd_timer3_dma_addrs[] = {
4678 {
4679 .pa_start = 0x49030000,
4680 .pa_end = 0x4903007f,
4681 .flags = ADDR_TYPE_RT
4682 },
4683 { }
4684 };
4685
4686 /* l4_abe -> wd_timer3 (dma) */
4687 static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3_dma = {
4688 .master = &omap44xx_l4_abe_hwmod,
4689 .slave = &omap44xx_wd_timer3_hwmod,
4690 .clk = "ocp_abe_iclk",
4691 .addr = omap44xx_wd_timer3_dma_addrs,
4692 .user = OCP_USER_SDMA,
4693 };
4694
4695 /* mpu -> emif1 */
4696 static struct omap_hwmod_ocp_if omap44xx_mpu__emif1 = {
4697 .master = &omap44xx_mpu_hwmod,
4698 .slave = &omap44xx_emif1_hwmod,
4699 .clk = "l3_div_ck",
4700 .user = OCP_USER_MPU | OCP_USER_SDMA,
4701 };
4702
4703 /* mpu -> emif2 */
4704 static struct omap_hwmod_ocp_if omap44xx_mpu__emif2 = {
4705 .master = &omap44xx_mpu_hwmod,
4706 .slave = &omap44xx_emif2_hwmod,
4707 .clk = "l3_div_ck",
4708 .user = OCP_USER_MPU | OCP_USER_SDMA,
4709 };
4710
4711 static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
4712 &omap44xx_l3_main_1__dmm,
4713 &omap44xx_mpu__dmm,
4714 &omap44xx_iva__l3_instr,
4715 &omap44xx_l3_main_3__l3_instr,
4716 &omap44xx_ocp_wp_noc__l3_instr,
4717 &omap44xx_dsp__l3_main_1,
4718 &omap44xx_dss__l3_main_1,
4719 &omap44xx_l3_main_2__l3_main_1,
4720 &omap44xx_l4_cfg__l3_main_1,
4721 &omap44xx_mmc1__l3_main_1,
4722 &omap44xx_mmc2__l3_main_1,
4723 &omap44xx_mpu__l3_main_1,
4724 &omap44xx_debugss__l3_main_2,
4725 &omap44xx_dma_system__l3_main_2,
4726 &omap44xx_fdif__l3_main_2,
4727 &omap44xx_gpu__l3_main_2,
4728 &omap44xx_hsi__l3_main_2,
4729 &omap44xx_ipu__l3_main_2,
4730 &omap44xx_iss__l3_main_2,
4731 &omap44xx_iva__l3_main_2,
4732 &omap44xx_l3_main_1__l3_main_2,
4733 &omap44xx_l4_cfg__l3_main_2,
4734 /* &omap44xx_usb_host_fs__l3_main_2, */
4735 &omap44xx_usb_host_hs__l3_main_2,
4736 &omap44xx_usb_otg_hs__l3_main_2,
4737 &omap44xx_l3_main_1__l3_main_3,
4738 &omap44xx_l3_main_2__l3_main_3,
4739 &omap44xx_l4_cfg__l3_main_3,
4740 &omap44xx_aess__l4_abe,
4741 &omap44xx_dsp__l4_abe,
4742 &omap44xx_l3_main_1__l4_abe,
4743 &omap44xx_mpu__l4_abe,
4744 &omap44xx_l3_main_1__l4_cfg,
4745 &omap44xx_l3_main_2__l4_per,
4746 &omap44xx_l4_cfg__l4_wkup,
4747 &omap44xx_mpu__mpu_private,
4748 &omap44xx_l4_cfg__ocp_wp_noc,
4749 &omap44xx_l4_abe__aess,
4750 &omap44xx_l4_abe__aess_dma,
4751 &omap44xx_l3_main_2__c2c,
4752 &omap44xx_l4_wkup__counter_32k,
4753 &omap44xx_l4_cfg__ctrl_module_core,
4754 &omap44xx_l4_cfg__ctrl_module_pad_core,
4755 &omap44xx_l4_wkup__ctrl_module_wkup,
4756 &omap44xx_l4_wkup__ctrl_module_pad_wkup,
4757 &omap44xx_l3_instr__debugss,
4758 &omap44xx_l4_cfg__dma_system,
4759 &omap44xx_l4_abe__dmic,
4760 &omap44xx_dsp__iva,
4761 /* &omap44xx_dsp__sl2if, */
4762 &omap44xx_l4_cfg__dsp,
4763 &omap44xx_l3_main_2__dss,
4764 &omap44xx_l4_per__dss,
4765 &omap44xx_l3_main_2__dss_dispc,
4766 &omap44xx_l4_per__dss_dispc,
4767 &omap44xx_l3_main_2__dss_dsi1,
4768 &omap44xx_l4_per__dss_dsi1,
4769 &omap44xx_l3_main_2__dss_dsi2,
4770 &omap44xx_l4_per__dss_dsi2,
4771 &omap44xx_l3_main_2__dss_hdmi,
4772 &omap44xx_l4_per__dss_hdmi,
4773 &omap44xx_l3_main_2__dss_rfbi,
4774 &omap44xx_l4_per__dss_rfbi,
4775 &omap44xx_l3_main_2__dss_venc,
4776 &omap44xx_l4_per__dss_venc,
4777 &omap44xx_l4_per__elm,
4778 &omap44xx_l4_cfg__fdif,
4779 &omap44xx_l4_wkup__gpio1,
4780 &omap44xx_l4_per__gpio2,
4781 &omap44xx_l4_per__gpio3,
4782 &omap44xx_l4_per__gpio4,
4783 &omap44xx_l4_per__gpio5,
4784 &omap44xx_l4_per__gpio6,
4785 &omap44xx_l3_main_2__gpmc,
4786 &omap44xx_l3_main_2__gpu,
4787 &omap44xx_l4_per__hdq1w,
4788 &omap44xx_l4_cfg__hsi,
4789 &omap44xx_l4_per__i2c1,
4790 &omap44xx_l4_per__i2c2,
4791 &omap44xx_l4_per__i2c3,
4792 &omap44xx_l4_per__i2c4,
4793 &omap44xx_l3_main_2__ipu,
4794 &omap44xx_l3_main_2__iss,
4795 /* &omap44xx_iva__sl2if, */
4796 &omap44xx_l3_main_2__iva,
4797 &omap44xx_l4_wkup__kbd,
4798 &omap44xx_l4_cfg__mailbox,
4799 &omap44xx_l4_abe__mcasp,
4800 &omap44xx_l4_abe__mcasp_dma,
4801 &omap44xx_l4_abe__mcbsp1,
4802 &omap44xx_l4_abe__mcbsp2,
4803 &omap44xx_l4_abe__mcbsp3,
4804 &omap44xx_l4_per__mcbsp4,
4805 &omap44xx_l4_abe__mcpdm,
4806 &omap44xx_l4_per__mcspi1,
4807 &omap44xx_l4_per__mcspi2,
4808 &omap44xx_l4_per__mcspi3,
4809 &omap44xx_l4_per__mcspi4,
4810 &omap44xx_l4_per__mmc1,
4811 &omap44xx_l4_per__mmc2,
4812 &omap44xx_l4_per__mmc3,
4813 &omap44xx_l4_per__mmc4,
4814 &omap44xx_l4_per__mmc5,
4815 &omap44xx_l3_main_2__mmu_ipu,
4816 &omap44xx_l4_cfg__mmu_dsp,
4817 &omap44xx_l3_main_2__ocmc_ram,
4818 &omap44xx_l4_cfg__ocp2scp_usb_phy,
4819 &omap44xx_mpu_private__prcm_mpu,
4820 &omap44xx_l4_wkup__cm_core_aon,
4821 &omap44xx_l4_cfg__cm_core,
4822 &omap44xx_l4_wkup__prm,
4823 &omap44xx_l4_wkup__scrm,
4824 /* &omap44xx_l3_main_2__sl2if, */
4825 &omap44xx_l4_abe__slimbus1,
4826 &omap44xx_l4_abe__slimbus1_dma,
4827 &omap44xx_l4_per__slimbus2,
4828 &omap44xx_l4_cfg__smartreflex_core,
4829 &omap44xx_l4_cfg__smartreflex_iva,
4830 &omap44xx_l4_cfg__smartreflex_mpu,
4831 &omap44xx_l4_cfg__spinlock,
4832 &omap44xx_l4_wkup__timer1,
4833 &omap44xx_l4_per__timer2,
4834 &omap44xx_l4_per__timer3,
4835 &omap44xx_l4_per__timer4,
4836 &omap44xx_l4_abe__timer5,
4837 &omap44xx_l4_abe__timer6,
4838 &omap44xx_l4_abe__timer7,
4839 &omap44xx_l4_abe__timer8,
4840 &omap44xx_l4_per__timer9,
4841 &omap44xx_l4_per__timer10,
4842 &omap44xx_l4_per__timer11,
4843 &omap44xx_l4_per__uart1,
4844 &omap44xx_l4_per__uart2,
4845 &omap44xx_l4_per__uart3,
4846 &omap44xx_l4_per__uart4,
4847 /* &omap44xx_l4_cfg__usb_host_fs, */
4848 &omap44xx_l4_cfg__usb_host_hs,
4849 &omap44xx_l4_cfg__usb_otg_hs,
4850 &omap44xx_l4_cfg__usb_tll_hs,
4851 &omap44xx_l4_wkup__wd_timer2,
4852 &omap44xx_l4_abe__wd_timer3,
4853 &omap44xx_l4_abe__wd_timer3_dma,
4854 &omap44xx_mpu__emif1,
4855 &omap44xx_mpu__emif2,
4856 NULL,
4857 };
4858
4859 int __init omap44xx_hwmod_init(void)
4860 {
4861 omap_hwmod_init();
4862 return omap_hwmod_register_links(omap44xx_hwmod_ocp_ifs);
4863 }
4864
Linux with added FPC-III support