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btrfs: account for non-CoW'd blocks in btrfs_abort_transaction
[linux/fpc-iii.git] / arch / x86 / kvm / x86.c
blobbd84d2226ca15c84bb1b02bb65e100f55b22a16d
1 /*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
22 #include <linux/kvm_host.h>
23 #include "irq.h"
24 #include "mmu.h"
25 #include "i8254.h"
26 #include "tss.h"
27 #include "kvm_cache_regs.h"
28 #include "x86.h"
29 #include "cpuid.h"
30 #include "assigned-dev.h"
31
32 #include <linux/clocksource.h>
33 #include <linux/interrupt.h>
34 #include <linux/kvm.h>
35 #include <linux/fs.h>
36 #include <linux/vmalloc.h>
37 #include <linux/module.h>
38 #include <linux/mman.h>
39 #include <linux/highmem.h>
40 #include <linux/iommu.h>
41 #include <linux/intel-iommu.h>
42 #include <linux/cpufreq.h>
43 #include <linux/user-return-notifier.h>
44 #include <linux/srcu.h>
45 #include <linux/slab.h>
46 #include <linux/perf_event.h>
47 #include <linux/uaccess.h>
48 #include <linux/hash.h>
49 #include <linux/pci.h>
50 #include <linux/timekeeper_internal.h>
51 #include <linux/pvclock_gtod.h>
52 #include <trace/events/kvm.h>
53
54 #define CREATE_TRACE_POINTS
55 #include "trace.h"
56
57 #include <asm/debugreg.h>
58 #include <asm/msr.h>
59 #include <asm/desc.h>
60 #include <asm/mtrr.h>
61 #include <asm/mce.h>
62 #include <asm/i387.h>
63 #include <asm/fpu-internal.h> /* Ugh! */
64 #include <asm/xcr.h>
65 #include <asm/pvclock.h>
66 #include <asm/div64.h>
67
68 #define MAX_IO_MSRS 256
69 #define KVM_MAX_MCE_BANKS 32
70 #define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P)
71
72 #define emul_to_vcpu(ctxt) \
73 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
74
75 /* EFER defaults:
76 * - enable syscall per default because its emulated by KVM
77 * - enable LME and LMA per default on 64 bit KVM
78 */
79 #ifdef CONFIG_X86_64
80 static
81 u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
82 #else
83 static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
84 #endif
85
86 #define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
87 #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
88
89 static void update_cr8_intercept(struct kvm_vcpu *vcpu);
90 static void process_nmi(struct kvm_vcpu *vcpu);
91 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
92
93 struct kvm_x86_ops *kvm_x86_ops;
94 EXPORT_SYMBOL_GPL(kvm_x86_ops);
95
96 static bool ignore_msrs = 0;
97 module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
98
99 unsigned int min_timer_period_us = 500;
100 module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
101
102 bool kvm_has_tsc_control;
103 EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
104 u32 kvm_max_guest_tsc_khz;
105 EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
106
107 /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
108 static u32 tsc_tolerance_ppm = 250;
109 module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
110
111 /* lapic timer advance (tscdeadline mode only) in nanoseconds */
112 unsigned int lapic_timer_advance_ns = 0;
113 module_param(lapic_timer_advance_ns, uint, S_IRUGO | S_IWUSR);
114
115 static bool backwards_tsc_observed = false;
116
117 #define KVM_NR_SHARED_MSRS 16
118
119 struct kvm_shared_msrs_global {
120 int nr;
121 u32 msrs[KVM_NR_SHARED_MSRS];
122 };
123
124 struct kvm_shared_msrs {
125 struct user_return_notifier urn;
126 bool registered;
127 struct kvm_shared_msr_values {
128 u64 host;
129 u64 curr;
130 } values[KVM_NR_SHARED_MSRS];
131 };
132
133 static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
134 static struct kvm_shared_msrs __percpu *shared_msrs;
135
136 struct kvm_stats_debugfs_item debugfs_entries[] = {
137 { "pf_fixed", VCPU_STAT(pf_fixed) },
138 { "pf_guest", VCPU_STAT(pf_guest) },
139 { "tlb_flush", VCPU_STAT(tlb_flush) },
140 { "invlpg", VCPU_STAT(invlpg) },
141 { "exits", VCPU_STAT(exits) },
142 { "io_exits", VCPU_STAT(io_exits) },
143 { "mmio_exits", VCPU_STAT(mmio_exits) },
144 { "signal_exits", VCPU_STAT(signal_exits) },
145 { "irq_window", VCPU_STAT(irq_window_exits) },
146 { "nmi_window", VCPU_STAT(nmi_window_exits) },
147 { "halt_exits", VCPU_STAT(halt_exits) },
148 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) },
149 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
150 { "hypercalls", VCPU_STAT(hypercalls) },
151 { "request_irq", VCPU_STAT(request_irq_exits) },
152 { "irq_exits", VCPU_STAT(irq_exits) },
153 { "host_state_reload", VCPU_STAT(host_state_reload) },
154 { "efer_reload", VCPU_STAT(efer_reload) },
155 { "fpu_reload", VCPU_STAT(fpu_reload) },
156 { "insn_emulation", VCPU_STAT(insn_emulation) },
157 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
158 { "irq_injections", VCPU_STAT(irq_injections) },
159 { "nmi_injections", VCPU_STAT(nmi_injections) },
160 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
161 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
162 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
163 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
164 { "mmu_flooded", VM_STAT(mmu_flooded) },
165 { "mmu_recycled", VM_STAT(mmu_recycled) },
166 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
167 { "mmu_unsync", VM_STAT(mmu_unsync) },
168 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
169 { "largepages", VM_STAT(lpages) },
170 { NULL }
171 };
172
173 u64 __read_mostly host_xcr0;
174
175 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
176
177 static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
178 {
179 int i;
180 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
181 vcpu->arch.apf.gfns[i] = ~0;
182 }
183
184 static void kvm_on_user_return(struct user_return_notifier *urn)
185 {
186 unsigned slot;
187 struct kvm_shared_msrs *locals
188 = container_of(urn, struct kvm_shared_msrs, urn);
189 struct kvm_shared_msr_values *values;
190
191 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
192 values = &locals->values[slot];
193 if (values->host != values->curr) {
194 wrmsrl(shared_msrs_global.msrs[slot], values->host);
195 values->curr = values->host;
196 }
197 }
198 locals->registered = false;
199 user_return_notifier_unregister(urn);
200 }
201
202 static void shared_msr_update(unsigned slot, u32 msr)
203 {
204 u64 value;
205 unsigned int cpu = smp_processor_id();
206 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
207
208 /* only read, and nobody should modify it at this time,
209 * so don't need lock */
210 if (slot >= shared_msrs_global.nr) {
211 printk(KERN_ERR "kvm: invalid MSR slot!");
212 return;
213 }
214 rdmsrl_safe(msr, &value);
215 smsr->values[slot].host = value;
216 smsr->values[slot].curr = value;
217 }
218
219 void kvm_define_shared_msr(unsigned slot, u32 msr)
220 {
221 BUG_ON(slot >= KVM_NR_SHARED_MSRS);
222 if (slot >= shared_msrs_global.nr)
223 shared_msrs_global.nr = slot + 1;
224 shared_msrs_global.msrs[slot] = msr;
225 /* we need ensured the shared_msr_global have been updated */
226 smp_wmb();
227 }
228 EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
229
230 static void kvm_shared_msr_cpu_online(void)
231 {
232 unsigned i;
233
234 for (i = 0; i < shared_msrs_global.nr; ++i)
235 shared_msr_update(i, shared_msrs_global.msrs[i]);
236 }
237
238 int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
239 {
240 unsigned int cpu = smp_processor_id();
241 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
242 int err;
243
244 if (((value ^ smsr->values[slot].curr) & mask) == 0)
245 return 0;
246 smsr->values[slot].curr = value;
247 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
248 if (err)
249 return 1;
250
251 if (!smsr->registered) {
252 smsr->urn.on_user_return = kvm_on_user_return;
253 user_return_notifier_register(&smsr->urn);
254 smsr->registered = true;
255 }
256 return 0;
257 }
258 EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
259
260 static void drop_user_return_notifiers(void)
261 {
262 unsigned int cpu = smp_processor_id();
263 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
264
265 if (smsr->registered)
266 kvm_on_user_return(&smsr->urn);
267 }
268
269 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
270 {
271 return vcpu->arch.apic_base;
272 }
273 EXPORT_SYMBOL_GPL(kvm_get_apic_base);
274
275 int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
276 {
277 u64 old_state = vcpu->arch.apic_base &
278 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
279 u64 new_state = msr_info->data &
280 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
281 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) |
282 0x2ff | (guest_cpuid_has_x2apic(vcpu) ? 0 : X2APIC_ENABLE);
283
284 if (!msr_info->host_initiated &&
285 ((msr_info->data & reserved_bits) != 0 ||
286 new_state == X2APIC_ENABLE ||
287 (new_state == MSR_IA32_APICBASE_ENABLE &&
288 old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) ||
289 (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) &&
290 old_state == 0)))
291 return 1;
292
293 kvm_lapic_set_base(vcpu, msr_info->data);
294 return 0;
295 }
296 EXPORT_SYMBOL_GPL(kvm_set_apic_base);
297
298 asmlinkage __visible void kvm_spurious_fault(void)
299 {
300 /* Fault while not rebooting. We want the trace. */
301 BUG();
302 }
303 EXPORT_SYMBOL_GPL(kvm_spurious_fault);
304
305 #define EXCPT_BENIGN 0
306 #define EXCPT_CONTRIBUTORY 1
307 #define EXCPT_PF 2
308
309 static int exception_class(int vector)
310 {
311 switch (vector) {
312 case PF_VECTOR:
313 return EXCPT_PF;
314 case DE_VECTOR:
315 case TS_VECTOR:
316 case NP_VECTOR:
317 case SS_VECTOR:
318 case GP_VECTOR:
319 return EXCPT_CONTRIBUTORY;
320 default:
321 break;
322 }
323 return EXCPT_BENIGN;
324 }
325
326 #define EXCPT_FAULT 0
327 #define EXCPT_TRAP 1
328 #define EXCPT_ABORT 2
329 #define EXCPT_INTERRUPT 3
330
331 static int exception_type(int vector)
332 {
333 unsigned int mask;
334
335 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
336 return EXCPT_INTERRUPT;
337
338 mask = 1 << vector;
339
340 /* #DB is trap, as instruction watchpoints are handled elsewhere */
341 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
342 return EXCPT_TRAP;
343
344 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
345 return EXCPT_ABORT;
346
347 /* Reserved exceptions will result in fault */
348 return EXCPT_FAULT;
349 }
350
351 static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
352 unsigned nr, bool has_error, u32 error_code,
353 bool reinject)
354 {
355 u32 prev_nr;
356 int class1, class2;
357
358 kvm_make_request(KVM_REQ_EVENT, vcpu);
359
360 if (!vcpu->arch.exception.pending) {
361 queue:
362 if (has_error && !is_protmode(vcpu))
363 has_error = false;
364 vcpu->arch.exception.pending = true;
365 vcpu->arch.exception.has_error_code = has_error;
366 vcpu->arch.exception.nr = nr;
367 vcpu->arch.exception.error_code = error_code;
368 vcpu->arch.exception.reinject = reinject;
369 return;
370 }
371
372 /* to check exception */
373 prev_nr = vcpu->arch.exception.nr;
374 if (prev_nr == DF_VECTOR) {
375 /* triple fault -> shutdown */
376 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
377 return;
378 }
379 class1 = exception_class(prev_nr);
380 class2 = exception_class(nr);
381 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
382 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
383 /* generate double fault per SDM Table 5-5 */
384 vcpu->arch.exception.pending = true;
385 vcpu->arch.exception.has_error_code = true;
386 vcpu->arch.exception.nr = DF_VECTOR;
387 vcpu->arch.exception.error_code = 0;
388 } else
389 /* replace previous exception with a new one in a hope
390 that instruction re-execution will regenerate lost
391 exception */
392 goto queue;
393 }
394
395 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
396 {
397 kvm_multiple_exception(vcpu, nr, false, 0, false);
398 }
399 EXPORT_SYMBOL_GPL(kvm_queue_exception);
400
401 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
402 {
403 kvm_multiple_exception(vcpu, nr, false, 0, true);
404 }
405 EXPORT_SYMBOL_GPL(kvm_requeue_exception);
406
407 void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
408 {
409 if (err)
410 kvm_inject_gp(vcpu, 0);
411 else
412 kvm_x86_ops->skip_emulated_instruction(vcpu);
413 }
414 EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
415
416 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
417 {
418 ++vcpu->stat.pf_guest;
419 vcpu->arch.cr2 = fault->address;
420 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
421 }
422 EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
423
424 static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
425 {
426 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
427 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
428 else
429 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
430
431 return fault->nested_page_fault;
432 }
433
434 void kvm_inject_nmi(struct kvm_vcpu *vcpu)
435 {
436 atomic_inc(&vcpu->arch.nmi_queued);
437 kvm_make_request(KVM_REQ_NMI, vcpu);
438 }
439 EXPORT_SYMBOL_GPL(kvm_inject_nmi);
440
441 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
442 {
443 kvm_multiple_exception(vcpu, nr, true, error_code, false);
444 }
445 EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
446
447 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
448 {
449 kvm_multiple_exception(vcpu, nr, true, error_code, true);
450 }
451 EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
452
453 /*
454 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
455 * a #GP and return false.
456 */
457 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
458 {
459 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
460 return true;
461 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
462 return false;
463 }
464 EXPORT_SYMBOL_GPL(kvm_require_cpl);
465
466 bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
467 {
468 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
469 return true;
470
471 kvm_queue_exception(vcpu, UD_VECTOR);
472 return false;
473 }
474 EXPORT_SYMBOL_GPL(kvm_require_dr);
475
476 /*
477 * This function will be used to read from the physical memory of the currently
478 * running guest. The difference to kvm_read_guest_page is that this function
479 * can read from guest physical or from the guest's guest physical memory.
480 */
481 int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
482 gfn_t ngfn, void *data, int offset, int len,
483 u32 access)
484 {
485 struct x86_exception exception;
486 gfn_t real_gfn;
487 gpa_t ngpa;
488
489 ngpa = gfn_to_gpa(ngfn);
490 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
491 if (real_gfn == UNMAPPED_GVA)
492 return -EFAULT;
493
494 real_gfn = gpa_to_gfn(real_gfn);
495
496 return kvm_read_guest_page(vcpu->kvm, real_gfn, data, offset, len);
497 }
498 EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
499
500 static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
501 void *data, int offset, int len, u32 access)
502 {
503 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
504 data, offset, len, access);
505 }
506
507 /*
508 * Load the pae pdptrs. Return true is they are all valid.
509 */
510 int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
511 {
512 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
513 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
514 int i;
515 int ret;
516 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
517
518 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
519 offset * sizeof(u64), sizeof(pdpte),
520 PFERR_USER_MASK|PFERR_WRITE_MASK);
521 if (ret < 0) {
522 ret = 0;
523 goto out;
524 }
525 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
526 if (is_present_gpte(pdpte[i]) &&
527 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
528 ret = 0;
529 goto out;
530 }
531 }
532 ret = 1;
533
534 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
535 __set_bit(VCPU_EXREG_PDPTR,
536 (unsigned long *)&vcpu->arch.regs_avail);
537 __set_bit(VCPU_EXREG_PDPTR,
538 (unsigned long *)&vcpu->arch.regs_dirty);
539 out:
540
541 return ret;
542 }
543 EXPORT_SYMBOL_GPL(load_pdptrs);
544
545 static bool pdptrs_changed(struct kvm_vcpu *vcpu)
546 {
547 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
548 bool changed = true;
549 int offset;
550 gfn_t gfn;
551 int r;
552
553 if (is_long_mode(vcpu) || !is_pae(vcpu))
554 return false;
555
556 if (!test_bit(VCPU_EXREG_PDPTR,
557 (unsigned long *)&vcpu->arch.regs_avail))
558 return true;
559
560 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
561 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
562 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
563 PFERR_USER_MASK | PFERR_WRITE_MASK);
564 if (r < 0)
565 goto out;
566 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
567 out:
568
569 return changed;
570 }
571
572 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
573 {
574 unsigned long old_cr0 = kvm_read_cr0(vcpu);
575 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP |
576 X86_CR0_CD | X86_CR0_NW;
577
578 cr0 |= X86_CR0_ET;
579
580 #ifdef CONFIG_X86_64
581 if (cr0 & 0xffffffff00000000UL)
582 return 1;
583 #endif
584
585 cr0 &= ~CR0_RESERVED_BITS;
586
587 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
588 return 1;
589
590 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
591 return 1;
592
593 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
594 #ifdef CONFIG_X86_64
595 if ((vcpu->arch.efer & EFER_LME)) {
596 int cs_db, cs_l;
597
598 if (!is_pae(vcpu))
599 return 1;
600 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
601 if (cs_l)
602 return 1;
603 } else
604 #endif
605 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
606 kvm_read_cr3(vcpu)))
607 return 1;
608 }
609
610 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
611 return 1;
612
613 kvm_x86_ops->set_cr0(vcpu, cr0);
614
615 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
616 kvm_clear_async_pf_completion_queue(vcpu);
617 kvm_async_pf_hash_reset(vcpu);
618 }
619
620 if ((cr0 ^ old_cr0) & update_bits)
621 kvm_mmu_reset_context(vcpu);
622 return 0;
623 }
624 EXPORT_SYMBOL_GPL(kvm_set_cr0);
625
626 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
627 {
628 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
629 }
630 EXPORT_SYMBOL_GPL(kvm_lmsw);
631
632 static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
633 {
634 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
635 !vcpu->guest_xcr0_loaded) {
636 /* kvm_set_xcr() also depends on this */
637 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
638 vcpu->guest_xcr0_loaded = 1;
639 }
640 }
641
642 static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
643 {
644 if (vcpu->guest_xcr0_loaded) {
645 if (vcpu->arch.xcr0 != host_xcr0)
646 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
647 vcpu->guest_xcr0_loaded = 0;
648 }
649 }
650
651 static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
652 {
653 u64 xcr0 = xcr;
654 u64 old_xcr0 = vcpu->arch.xcr0;
655 u64 valid_bits;
656
657 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
658 if (index != XCR_XFEATURE_ENABLED_MASK)
659 return 1;
660 if (!(xcr0 & XSTATE_FP))
661 return 1;
662 if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE))
663 return 1;
664
665 /*
666 * Do not allow the guest to set bits that we do not support
667 * saving. However, xcr0 bit 0 is always set, even if the
668 * emulated CPU does not support XSAVE (see fx_init).
669 */
670 valid_bits = vcpu->arch.guest_supported_xcr0 | XSTATE_FP;
671 if (xcr0 & ~valid_bits)
672 return 1;
673
674 if ((!(xcr0 & XSTATE_BNDREGS)) != (!(xcr0 & XSTATE_BNDCSR)))
675 return 1;
676
677 if (xcr0 & XSTATE_AVX512) {
678 if (!(xcr0 & XSTATE_YMM))
679 return 1;
680 if ((xcr0 & XSTATE_AVX512) != XSTATE_AVX512)
681 return 1;
682 }
683 vcpu->arch.xcr0 = xcr0;
684
685 if ((xcr0 ^ old_xcr0) & XSTATE_EXTEND_MASK)
686 kvm_update_cpuid(vcpu);
687 return 0;
688 }
689
690 int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
691 {
692 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
693 __kvm_set_xcr(vcpu, index, xcr)) {
694 kvm_inject_gp(vcpu, 0);
695 return 1;
696 }
697 return 0;
698 }
699 EXPORT_SYMBOL_GPL(kvm_set_xcr);
700
701 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
702 {
703 unsigned long old_cr4 = kvm_read_cr4(vcpu);
704 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
705 X86_CR4_SMEP | X86_CR4_SMAP;
706
707 if (cr4 & CR4_RESERVED_BITS)
708 return 1;
709
710 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
711 return 1;
712
713 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
714 return 1;
715
716 if (!guest_cpuid_has_smap(vcpu) && (cr4 & X86_CR4_SMAP))
717 return 1;
718
719 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_FSGSBASE))
720 return 1;
721
722 if (is_long_mode(vcpu)) {
723 if (!(cr4 & X86_CR4_PAE))
724 return 1;
725 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
726 && ((cr4 ^ old_cr4) & pdptr_bits)
727 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
728 kvm_read_cr3(vcpu)))
729 return 1;
730
731 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
732 if (!guest_cpuid_has_pcid(vcpu))
733 return 1;
734
735 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
736 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
737 return 1;
738 }
739
740 if (kvm_x86_ops->set_cr4(vcpu, cr4))
741 return 1;
742
743 if (((cr4 ^ old_cr4) & pdptr_bits) ||
744 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
745 kvm_mmu_reset_context(vcpu);
746
747 if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
748 kvm_update_cpuid(vcpu);
749
750 return 0;
751 }
752 EXPORT_SYMBOL_GPL(kvm_set_cr4);
753
754 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
755 {
756 #ifdef CONFIG_X86_64
757 cr3 &= ~CR3_PCID_INVD;
758 #endif
759
760 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
761 kvm_mmu_sync_roots(vcpu);
762 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
763 return 0;
764 }
765
766 if (is_long_mode(vcpu)) {
767 if (cr3 & CR3_L_MODE_RESERVED_BITS)
768 return 1;
769 } else if (is_pae(vcpu) && is_paging(vcpu) &&
770 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
771 return 1;
772
773 vcpu->arch.cr3 = cr3;
774 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
775 kvm_mmu_new_cr3(vcpu);
776 return 0;
777 }
778 EXPORT_SYMBOL_GPL(kvm_set_cr3);
779
780 int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
781 {
782 if (cr8 & CR8_RESERVED_BITS)
783 return 1;
784 if (irqchip_in_kernel(vcpu->kvm))
785 kvm_lapic_set_tpr(vcpu, cr8);
786 else
787 vcpu->arch.cr8 = cr8;
788 return 0;
789 }
790 EXPORT_SYMBOL_GPL(kvm_set_cr8);
791
792 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
793 {
794 if (irqchip_in_kernel(vcpu->kvm))
795 return kvm_lapic_get_cr8(vcpu);
796 else
797 return vcpu->arch.cr8;
798 }
799 EXPORT_SYMBOL_GPL(kvm_get_cr8);
800
801 static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
802 {
803 int i;
804
805 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
806 for (i = 0; i < KVM_NR_DB_REGS; i++)
807 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
808 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
809 }
810 }
811
812 static void kvm_update_dr6(struct kvm_vcpu *vcpu)
813 {
814 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
815 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
816 }
817
818 static void kvm_update_dr7(struct kvm_vcpu *vcpu)
819 {
820 unsigned long dr7;
821
822 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
823 dr7 = vcpu->arch.guest_debug_dr7;
824 else
825 dr7 = vcpu->arch.dr7;
826 kvm_x86_ops->set_dr7(vcpu, dr7);
827 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
828 if (dr7 & DR7_BP_EN_MASK)
829 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
830 }
831
832 static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
833 {
834 u64 fixed = DR6_FIXED_1;
835
836 if (!guest_cpuid_has_rtm(vcpu))
837 fixed |= DR6_RTM;
838 return fixed;
839 }
840
841 static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
842 {
843 switch (dr) {
844 case 0 ... 3:
845 vcpu->arch.db[dr] = val;
846 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
847 vcpu->arch.eff_db[dr] = val;
848 break;
849 case 4:
850 /* fall through */
851 case 6:
852 if (val & 0xffffffff00000000ULL)
853 return -1; /* #GP */
854 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
855 kvm_update_dr6(vcpu);
856 break;
857 case 5:
858 /* fall through */
859 default: /* 7 */
860 if (val & 0xffffffff00000000ULL)
861 return -1; /* #GP */
862 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
863 kvm_update_dr7(vcpu);
864 break;
865 }
866
867 return 0;
868 }
869
870 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
871 {
872 if (__kvm_set_dr(vcpu, dr, val)) {
873 kvm_inject_gp(vcpu, 0);
874 return 1;
875 }
876 return 0;
877 }
878 EXPORT_SYMBOL_GPL(kvm_set_dr);
879
880 int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
881 {
882 switch (dr) {
883 case 0 ... 3:
884 *val = vcpu->arch.db[dr];
885 break;
886 case 4:
887 /* fall through */
888 case 6:
889 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
890 *val = vcpu->arch.dr6;
891 else
892 *val = kvm_x86_ops->get_dr6(vcpu);
893 break;
894 case 5:
895 /* fall through */
896 default: /* 7 */
897 *val = vcpu->arch.dr7;
898 break;
899 }
900 return 0;
901 }
902 EXPORT_SYMBOL_GPL(kvm_get_dr);
903
904 bool kvm_rdpmc(struct kvm_vcpu *vcpu)
905 {
906 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
907 u64 data;
908 int err;
909
910 err = kvm_pmu_read_pmc(vcpu, ecx, &data);
911 if (err)
912 return err;
913 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
914 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
915 return err;
916 }
917 EXPORT_SYMBOL_GPL(kvm_rdpmc);
918
919 /*
920 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
921 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
922 *
923 * This list is modified at module load time to reflect the
924 * capabilities of the host cpu. This capabilities test skips MSRs that are
925 * kvm-specific. Those are put in the beginning of the list.
926 */
927
928 #define KVM_SAVE_MSRS_BEGIN 12
929 static u32 msrs_to_save[] = {
930 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
931 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
932 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
933 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
934 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
935 MSR_KVM_PV_EOI_EN,
936 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
937 MSR_STAR,
938 #ifdef CONFIG_X86_64
939 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
940 #endif
941 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
942 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS, MSR_TSC_AUX,
943 };
944
945 static unsigned num_msrs_to_save;
946
947 static const u32 emulated_msrs[] = {
948 MSR_IA32_TSC_ADJUST,
949 MSR_IA32_TSCDEADLINE,
950 MSR_IA32_MISC_ENABLE,
951 MSR_IA32_MCG_STATUS,
952 MSR_IA32_MCG_CTL,
953 };
954
955 bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
956 {
957 if (efer & efer_reserved_bits)
958 return false;
959
960 if (efer & EFER_FFXSR) {
961 struct kvm_cpuid_entry2 *feat;
962
963 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
964 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
965 return false;
966 }
967
968 if (efer & EFER_SVME) {
969 struct kvm_cpuid_entry2 *feat;
970
971 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
972 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
973 return false;
974 }
975
976 return true;
977 }
978 EXPORT_SYMBOL_GPL(kvm_valid_efer);
979
980 static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
981 {
982 u64 old_efer = vcpu->arch.efer;
983
984 if (!kvm_valid_efer(vcpu, efer))
985 return 1;
986
987 if (is_paging(vcpu)
988 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
989 return 1;
990
991 efer &= ~EFER_LMA;
992 efer |= vcpu->arch.efer & EFER_LMA;
993
994 kvm_x86_ops->set_efer(vcpu, efer);
995
996 /* Update reserved bits */
997 if ((efer ^ old_efer) & EFER_NX)
998 kvm_mmu_reset_context(vcpu);
999
1000 return 0;
1001 }
1002
1003 void kvm_enable_efer_bits(u64 mask)
1004 {
1005 efer_reserved_bits &= ~mask;
1006 }
1007 EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1008
1009 /*
1010 * Writes msr value into into the appropriate "register".
1011 * Returns 0 on success, non-0 otherwise.
1012 * Assumes vcpu_load() was already called.
1013 */
1014 int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
1015 {
1016 switch (msr->index) {
1017 case MSR_FS_BASE:
1018 case MSR_GS_BASE:
1019 case MSR_KERNEL_GS_BASE:
1020 case MSR_CSTAR:
1021 case MSR_LSTAR:
1022 if (is_noncanonical_address(msr->data))
1023 return 1;
1024 break;
1025 case MSR_IA32_SYSENTER_EIP:
1026 case MSR_IA32_SYSENTER_ESP:
1027 /*
1028 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1029 * non-canonical address is written on Intel but not on
1030 * AMD (which ignores the top 32-bits, because it does
1031 * not implement 64-bit SYSENTER).
1032 *
1033 * 64-bit code should hence be able to write a non-canonical
1034 * value on AMD. Making the address canonical ensures that
1035 * vmentry does not fail on Intel after writing a non-canonical
1036 * value, and that something deterministic happens if the guest
1037 * invokes 64-bit SYSENTER.
1038 */
1039 msr->data = get_canonical(msr->data);
1040 }
1041 return kvm_x86_ops->set_msr(vcpu, msr);
1042 }
1043 EXPORT_SYMBOL_GPL(kvm_set_msr);
1044
1045 /*
1046 * Adapt set_msr() to msr_io()'s calling convention
1047 */
1048 static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1049 {
1050 struct msr_data msr;
1051
1052 msr.data = *data;
1053 msr.index = index;
1054 msr.host_initiated = true;
1055 return kvm_set_msr(vcpu, &msr);
1056 }
1057
1058 #ifdef CONFIG_X86_64
1059 struct pvclock_gtod_data {
1060 seqcount_t seq;
1061
1062 struct { /* extract of a clocksource struct */
1063 int vclock_mode;
1064 cycle_t cycle_last;
1065 cycle_t mask;
1066 u32 mult;
1067 u32 shift;
1068 } clock;
1069
1070 u64 boot_ns;
1071 u64 nsec_base;
1072 };
1073
1074 static struct pvclock_gtod_data pvclock_gtod_data;
1075
1076 static void update_pvclock_gtod(struct timekeeper *tk)
1077 {
1078 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
1079 u64 boot_ns;
1080
1081 boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot));
1082
1083 write_seqcount_begin(&vdata->seq);
1084
1085 /* copy pvclock gtod data */
1086 vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode;
1087 vdata->clock.cycle_last = tk->tkr_mono.cycle_last;
1088 vdata->clock.mask = tk->tkr_mono.mask;
1089 vdata->clock.mult = tk->tkr_mono.mult;
1090 vdata->clock.shift = tk->tkr_mono.shift;
1091
1092 vdata->boot_ns = boot_ns;
1093 vdata->nsec_base = tk->tkr_mono.xtime_nsec;
1094
1095 write_seqcount_end(&vdata->seq);
1096 }
1097 #endif
1098
1099 void kvm_set_pending_timer(struct kvm_vcpu *vcpu)
1100 {
1101 /*
1102 * Note: KVM_REQ_PENDING_TIMER is implicitly checked in
1103 * vcpu_enter_guest. This function is only called from
1104 * the physical CPU that is running vcpu.
1105 */
1106 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1107 }
1108
1109 static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1110 {
1111 int version;
1112 int r;
1113 struct pvclock_wall_clock wc;
1114 struct timespec boot;
1115
1116 if (!wall_clock)
1117 return;
1118
1119 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1120 if (r)
1121 return;
1122
1123 if (version & 1)
1124 ++version; /* first time write, random junk */
1125
1126 ++version;
1127
1128 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1129
1130 /*
1131 * The guest calculates current wall clock time by adding
1132 * system time (updated by kvm_guest_time_update below) to the
1133 * wall clock specified here. guest system time equals host
1134 * system time for us, thus we must fill in host boot time here.
1135 */
1136 getboottime(&boot);
1137
1138 if (kvm->arch.kvmclock_offset) {
1139 struct timespec ts = ns_to_timespec(kvm->arch.kvmclock_offset);
1140 boot = timespec_sub(boot, ts);
1141 }
1142 wc.sec = boot.tv_sec;
1143 wc.nsec = boot.tv_nsec;
1144 wc.version = version;
1145
1146 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1147
1148 version++;
1149 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1150 }
1151
1152 static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1153 {
1154 uint32_t quotient, remainder;
1155
1156 /* Don't try to replace with do_div(), this one calculates
1157 * "(dividend << 32) / divisor" */
1158 __asm__ ( "divl %4"
1159 : "=a" (quotient), "=d" (remainder)
1160 : "0" (0), "1" (dividend), "r" (divisor) );
1161 return quotient;
1162 }
1163
1164 static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz,
1165 s8 *pshift, u32 *pmultiplier)
1166 {
1167 uint64_t scaled64;
1168 int32_t shift = 0;
1169 uint64_t tps64;
1170 uint32_t tps32;
1171
1172 tps64 = base_khz * 1000LL;
1173 scaled64 = scaled_khz * 1000LL;
1174 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
1175 tps64 >>= 1;
1176 shift--;
1177 }
1178
1179 tps32 = (uint32_t)tps64;
1180 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1181 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
1182 scaled64 >>= 1;
1183 else
1184 tps32 <<= 1;
1185 shift++;
1186 }
1187
1188 *pshift = shift;
1189 *pmultiplier = div_frac(scaled64, tps32);
1190
1191 pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n",
1192 __func__, base_khz, scaled_khz, shift, *pmultiplier);
1193 }
1194
1195 static inline u64 get_kernel_ns(void)
1196 {
1197 return ktime_get_boot_ns();
1198 }
1199
1200 #ifdef CONFIG_X86_64
1201 static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
1202 #endif
1203
1204 static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
1205 static unsigned long max_tsc_khz;
1206
1207 static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
1208 {
1209 return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult,
1210 vcpu->arch.virtual_tsc_shift);
1211 }
1212
1213 static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1214 {
1215 u64 v = (u64)khz * (1000000 + ppm);
1216 do_div(v, 1000000);
1217 return v;
1218 }
1219
1220 static void kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 this_tsc_khz)
1221 {
1222 u32 thresh_lo, thresh_hi;
1223 int use_scaling = 0;
1224
1225 /* tsc_khz can be zero if TSC calibration fails */
1226 if (this_tsc_khz == 0)
1227 return;
1228
1229 /* Compute a scale to convert nanoseconds in TSC cycles */
1230 kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000,
1231 &vcpu->arch.virtual_tsc_shift,
1232 &vcpu->arch.virtual_tsc_mult);
1233 vcpu->arch.virtual_tsc_khz = this_tsc_khz;
1234
1235 /*
1236 * Compute the variation in TSC rate which is acceptable
1237 * within the range of tolerance and decide if the
1238 * rate being applied is within that bounds of the hardware
1239 * rate. If so, no scaling or compensation need be done.
1240 */
1241 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1242 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1243 if (this_tsc_khz < thresh_lo || this_tsc_khz > thresh_hi) {
1244 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", this_tsc_khz, thresh_lo, thresh_hi);
1245 use_scaling = 1;
1246 }
1247 kvm_x86_ops->set_tsc_khz(vcpu, this_tsc_khz, use_scaling);
1248 }
1249
1250 static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1251 {
1252 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
1253 vcpu->arch.virtual_tsc_mult,
1254 vcpu->arch.virtual_tsc_shift);
1255 tsc += vcpu->arch.this_tsc_write;
1256 return tsc;
1257 }
1258
1259 static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
1260 {
1261 #ifdef CONFIG_X86_64
1262 bool vcpus_matched;
1263 struct kvm_arch *ka = &vcpu->kvm->arch;
1264 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1265
1266 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1267 atomic_read(&vcpu->kvm->online_vcpus));
1268
1269 /*
1270 * Once the masterclock is enabled, always perform request in
1271 * order to update it.
1272 *
1273 * In order to enable masterclock, the host clocksource must be TSC
1274 * and the vcpus need to have matched TSCs. When that happens,
1275 * perform request to enable masterclock.
1276 */
1277 if (ka->use_master_clock ||
1278 (gtod->clock.vclock_mode == VCLOCK_TSC && vcpus_matched))
1279 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1280
1281 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1282 atomic_read(&vcpu->kvm->online_vcpus),
1283 ka->use_master_clock, gtod->clock.vclock_mode);
1284 #endif
1285 }
1286
1287 static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1288 {
1289 u64 curr_offset = kvm_x86_ops->read_tsc_offset(vcpu);
1290 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1291 }
1292
1293 void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
1294 {
1295 struct kvm *kvm = vcpu->kvm;
1296 u64 offset, ns, elapsed;
1297 unsigned long flags;
1298 s64 usdiff;
1299 bool matched;
1300 bool already_matched;
1301 u64 data = msr->data;
1302
1303 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
1304 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
1305 ns = get_kernel_ns();
1306 elapsed = ns - kvm->arch.last_tsc_nsec;
1307
1308 if (vcpu->arch.virtual_tsc_khz) {
1309 int faulted = 0;
1310
1311 /* n.b - signed multiplication and division required */
1312 usdiff = data - kvm->arch.last_tsc_write;
1313 #ifdef CONFIG_X86_64
1314 usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz;
1315 #else
1316 /* do_div() only does unsigned */
1317 asm("1: idivl %[divisor]\n"
1318 "2: xor %%edx, %%edx\n"
1319 " movl $0, %[faulted]\n"
1320 "3:\n"
1321 ".section .fixup,\"ax\"\n"
1322 "4: movl $1, %[faulted]\n"
1323 " jmp 3b\n"
1324 ".previous\n"
1325
1326 _ASM_EXTABLE(1b, 4b)
1327
1328 : "=A"(usdiff), [faulted] "=r" (faulted)
1329 : "A"(usdiff * 1000), [divisor] "rm"(vcpu->arch.virtual_tsc_khz));
1330
1331 #endif
1332 do_div(elapsed, 1000);
1333 usdiff -= elapsed;
1334 if (usdiff < 0)
1335 usdiff = -usdiff;
1336
1337 /* idivl overflow => difference is larger than USEC_PER_SEC */
1338 if (faulted)
1339 usdiff = USEC_PER_SEC;
1340 } else
1341 usdiff = USEC_PER_SEC; /* disable TSC match window below */
1342
1343 /*
1344 * Special case: TSC write with a small delta (1 second) of virtual
1345 * cycle time against real time is interpreted as an attempt to
1346 * synchronize the CPU.
1347 *
1348 * For a reliable TSC, we can match TSC offsets, and for an unstable
1349 * TSC, we add elapsed time in this computation. We could let the
1350 * compensation code attempt to catch up if we fall behind, but
1351 * it's better to try to match offsets from the beginning.
1352 */
1353 if (usdiff < USEC_PER_SEC &&
1354 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
1355 if (!check_tsc_unstable()) {
1356 offset = kvm->arch.cur_tsc_offset;
1357 pr_debug("kvm: matched tsc offset for %llu\n", data);
1358 } else {
1359 u64 delta = nsec_to_cycles(vcpu, elapsed);
1360 data += delta;
1361 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
1362 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
1363 }
1364 matched = true;
1365 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
1366 } else {
1367 /*
1368 * We split periods of matched TSC writes into generations.
1369 * For each generation, we track the original measured
1370 * nanosecond time, offset, and write, so if TSCs are in
1371 * sync, we can match exact offset, and if not, we can match
1372 * exact software computation in compute_guest_tsc()
1373 *
1374 * These values are tracked in kvm->arch.cur_xxx variables.
1375 */
1376 kvm->arch.cur_tsc_generation++;
1377 kvm->arch.cur_tsc_nsec = ns;
1378 kvm->arch.cur_tsc_write = data;
1379 kvm->arch.cur_tsc_offset = offset;
1380 matched = false;
1381 pr_debug("kvm: new tsc generation %llu, clock %llu\n",
1382 kvm->arch.cur_tsc_generation, data);
1383 }
1384
1385 /*
1386 * We also track th most recent recorded KHZ, write and time to
1387 * allow the matching interval to be extended at each write.
1388 */
1389 kvm->arch.last_tsc_nsec = ns;
1390 kvm->arch.last_tsc_write = data;
1391 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
1392
1393 vcpu->arch.last_guest_tsc = data;
1394
1395 /* Keep track of which generation this VCPU has synchronized to */
1396 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1397 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1398 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1399
1400 if (guest_cpuid_has_tsc_adjust(vcpu) && !msr->host_initiated)
1401 update_ia32_tsc_adjust_msr(vcpu, offset);
1402 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1403 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
1404
1405 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
1406 if (!matched) {
1407 kvm->arch.nr_vcpus_matched_tsc = 0;
1408 } else if (!already_matched) {
1409 kvm->arch.nr_vcpus_matched_tsc++;
1410 }
1411
1412 kvm_track_tsc_matching(vcpu);
1413 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
1414 }
1415
1416 EXPORT_SYMBOL_GPL(kvm_write_tsc);
1417
1418 #ifdef CONFIG_X86_64
1419
1420 static cycle_t read_tsc(void)
1421 {
1422 cycle_t ret;
1423 u64 last;
1424
1425 /*
1426 * Empirically, a fence (of type that depends on the CPU)
1427 * before rdtsc is enough to ensure that rdtsc is ordered
1428 * with respect to loads. The various CPU manuals are unclear
1429 * as to whether rdtsc can be reordered with later loads,
1430 * but no one has ever seen it happen.
1431 */
1432 rdtsc_barrier();
1433 ret = (cycle_t)vget_cycles();
1434
1435 last = pvclock_gtod_data.clock.cycle_last;
1436
1437 if (likely(ret >= last))
1438 return ret;
1439
1440 /*
1441 * GCC likes to generate cmov here, but this branch is extremely
1442 * predictable (it's just a funciton of time and the likely is
1443 * very likely) and there's a data dependence, so force GCC
1444 * to generate a branch instead. I don't barrier() because
1445 * we don't actually need a barrier, and if this function
1446 * ever gets inlined it will generate worse code.
1447 */
1448 asm volatile ("");
1449 return last;
1450 }
1451
1452 static inline u64 vgettsc(cycle_t *cycle_now)
1453 {
1454 long v;
1455 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1456
1457 *cycle_now = read_tsc();
1458
1459 v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask;
1460 return v * gtod->clock.mult;
1461 }
1462
1463 static int do_monotonic_boot(s64 *t, cycle_t *cycle_now)
1464 {
1465 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1466 unsigned long seq;
1467 int mode;
1468 u64 ns;
1469
1470 do {
1471 seq = read_seqcount_begin(&gtod->seq);
1472 mode = gtod->clock.vclock_mode;
1473 ns = gtod->nsec_base;
1474 ns += vgettsc(cycle_now);
1475 ns >>= gtod->clock.shift;
1476 ns += gtod->boot_ns;
1477 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
1478 *t = ns;
1479
1480 return mode;
1481 }
1482
1483 /* returns true if host is using tsc clocksource */
1484 static bool kvm_get_time_and_clockread(s64 *kernel_ns, cycle_t *cycle_now)
1485 {
1486 /* checked again under seqlock below */
1487 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1488 return false;
1489
1490 return do_monotonic_boot(kernel_ns, cycle_now) == VCLOCK_TSC;
1491 }
1492 #endif
1493
1494 /*
1495 *
1496 * Assuming a stable TSC across physical CPUS, and a stable TSC
1497 * across virtual CPUs, the following condition is possible.
1498 * Each numbered line represents an event visible to both
1499 * CPUs at the next numbered event.
1500 *
1501 * "timespecX" represents host monotonic time. "tscX" represents
1502 * RDTSC value.
1503 *
1504 * VCPU0 on CPU0 | VCPU1 on CPU1
1505 *
1506 * 1. read timespec0,tsc0
1507 * 2. | timespec1 = timespec0 + N
1508 * | tsc1 = tsc0 + M
1509 * 3. transition to guest | transition to guest
1510 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1511 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1512 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1513 *
1514 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1515 *
1516 * - ret0 < ret1
1517 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1518 * ...
1519 * - 0 < N - M => M < N
1520 *
1521 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1522 * always the case (the difference between two distinct xtime instances
1523 * might be smaller then the difference between corresponding TSC reads,
1524 * when updating guest vcpus pvclock areas).
1525 *
1526 * To avoid that problem, do not allow visibility of distinct
1527 * system_timestamp/tsc_timestamp values simultaneously: use a master
1528 * copy of host monotonic time values. Update that master copy
1529 * in lockstep.
1530 *
1531 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
1532 *
1533 */
1534
1535 static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1536 {
1537 #ifdef CONFIG_X86_64
1538 struct kvm_arch *ka = &kvm->arch;
1539 int vclock_mode;
1540 bool host_tsc_clocksource, vcpus_matched;
1541
1542 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1543 atomic_read(&kvm->online_vcpus));
1544
1545 /*
1546 * If the host uses TSC clock, then passthrough TSC as stable
1547 * to the guest.
1548 */
1549 host_tsc_clocksource = kvm_get_time_and_clockread(
1550 &ka->master_kernel_ns,
1551 &ka->master_cycle_now);
1552
1553 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
1554 && !backwards_tsc_observed
1555 && !ka->boot_vcpu_runs_old_kvmclock;
1556
1557 if (ka->use_master_clock)
1558 atomic_set(&kvm_guest_has_master_clock, 1);
1559
1560 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
1561 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1562 vcpus_matched);
1563 #endif
1564 }
1565
1566 static void kvm_gen_update_masterclock(struct kvm *kvm)
1567 {
1568 #ifdef CONFIG_X86_64
1569 int i;
1570 struct kvm_vcpu *vcpu;
1571 struct kvm_arch *ka = &kvm->arch;
1572
1573 spin_lock(&ka->pvclock_gtod_sync_lock);
1574 kvm_make_mclock_inprogress_request(kvm);
1575 /* no guest entries from this point */
1576 pvclock_update_vm_gtod_copy(kvm);
1577
1578 kvm_for_each_vcpu(i, vcpu, kvm)
1579 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
1580
1581 /* guest entries allowed */
1582 kvm_for_each_vcpu(i, vcpu, kvm)
1583 clear_bit(KVM_REQ_MCLOCK_INPROGRESS, &vcpu->requests);
1584
1585 spin_unlock(&ka->pvclock_gtod_sync_lock);
1586 #endif
1587 }
1588
1589 static int kvm_guest_time_update(struct kvm_vcpu *v)
1590 {
1591 unsigned long flags, this_tsc_khz;
1592 struct kvm_vcpu_arch *vcpu = &v->arch;
1593 struct kvm_arch *ka = &v->kvm->arch;
1594 s64 kernel_ns;
1595 u64 tsc_timestamp, host_tsc;
1596 struct pvclock_vcpu_time_info guest_hv_clock;
1597 u8 pvclock_flags;
1598 bool use_master_clock;
1599
1600 kernel_ns = 0;
1601 host_tsc = 0;
1602
1603 /*
1604 * If the host uses TSC clock, then passthrough TSC as stable
1605 * to the guest.
1606 */
1607 spin_lock(&ka->pvclock_gtod_sync_lock);
1608 use_master_clock = ka->use_master_clock;
1609 if (use_master_clock) {
1610 host_tsc = ka->master_cycle_now;
1611 kernel_ns = ka->master_kernel_ns;
1612 }
1613 spin_unlock(&ka->pvclock_gtod_sync_lock);
1614
1615 /* Keep irq disabled to prevent changes to the clock */
1616 local_irq_save(flags);
1617 this_tsc_khz = __this_cpu_read(cpu_tsc_khz);
1618 if (unlikely(this_tsc_khz == 0)) {
1619 local_irq_restore(flags);
1620 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1621 return 1;
1622 }
1623 if (!use_master_clock) {
1624 host_tsc = native_read_tsc();
1625 kernel_ns = get_kernel_ns();
1626 }
1627
1628 tsc_timestamp = kvm_x86_ops->read_l1_tsc(v, host_tsc);
1629
1630 /*
1631 * We may have to catch up the TSC to match elapsed wall clock
1632 * time for two reasons, even if kvmclock is used.
1633 * 1) CPU could have been running below the maximum TSC rate
1634 * 2) Broken TSC compensation resets the base at each VCPU
1635 * entry to avoid unknown leaps of TSC even when running
1636 * again on the same CPU. This may cause apparent elapsed
1637 * time to disappear, and the guest to stand still or run
1638 * very slowly.
1639 */
1640 if (vcpu->tsc_catchup) {
1641 u64 tsc = compute_guest_tsc(v, kernel_ns);
1642 if (tsc > tsc_timestamp) {
1643 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
1644 tsc_timestamp = tsc;
1645 }
1646 }
1647
1648 local_irq_restore(flags);
1649
1650 if (!vcpu->pv_time_enabled)
1651 return 0;
1652
1653 if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) {
1654 kvm_get_time_scale(NSEC_PER_SEC / 1000, this_tsc_khz,
1655 &vcpu->hv_clock.tsc_shift,
1656 &vcpu->hv_clock.tsc_to_system_mul);
1657 vcpu->hw_tsc_khz = this_tsc_khz;
1658 }
1659
1660 /* With all the info we got, fill in the values */
1661 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
1662 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
1663 vcpu->last_guest_tsc = tsc_timestamp;
1664
1665 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
1666 &guest_hv_clock, sizeof(guest_hv_clock))))
1667 return 0;
1668
1669 /* This VCPU is paused, but it's legal for a guest to read another
1670 * VCPU's kvmclock, so we really have to follow the specification where
1671 * it says that version is odd if data is being modified, and even after
1672 * it is consistent.
1673 *
1674 * Version field updates must be kept separate. This is because
1675 * kvm_write_guest_cached might use a "rep movs" instruction, and
1676 * writes within a string instruction are weakly ordered. So there
1677 * are three writes overall.
1678 *
1679 * As a small optimization, only write the version field in the first
1680 * and third write. The vcpu->pv_time cache is still valid, because the
1681 * version field is the first in the struct.
1682 */
1683 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
1684
1685 vcpu->hv_clock.version = guest_hv_clock.version + 1;
1686 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1687 &vcpu->hv_clock,
1688 sizeof(vcpu->hv_clock.version));
1689
1690 smp_wmb();
1691
1692 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
1693 pvclock_flags = (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
1694
1695 if (vcpu->pvclock_set_guest_stopped_request) {
1696 pvclock_flags |= PVCLOCK_GUEST_STOPPED;
1697 vcpu->pvclock_set_guest_stopped_request = false;
1698 }
1699
1700 /* If the host uses TSC clocksource, then it is stable */
1701 if (use_master_clock)
1702 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
1703
1704 vcpu->hv_clock.flags = pvclock_flags;
1705
1706 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
1707
1708 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1709 &vcpu->hv_clock,
1710 sizeof(vcpu->hv_clock));
1711
1712 smp_wmb();
1713
1714 vcpu->hv_clock.version++;
1715 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1716 &vcpu->hv_clock,
1717 sizeof(vcpu->hv_clock.version));
1718 return 0;
1719 }
1720
1721 /*
1722 * kvmclock updates which are isolated to a given vcpu, such as
1723 * vcpu->cpu migration, should not allow system_timestamp from
1724 * the rest of the vcpus to remain static. Otherwise ntp frequency
1725 * correction applies to one vcpu's system_timestamp but not
1726 * the others.
1727 *
1728 * So in those cases, request a kvmclock update for all vcpus.
1729 * We need to rate-limit these requests though, as they can
1730 * considerably slow guests that have a large number of vcpus.
1731 * The time for a remote vcpu to update its kvmclock is bound
1732 * by the delay we use to rate-limit the updates.
1733 */
1734
1735 #define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
1736
1737 static void kvmclock_update_fn(struct work_struct *work)
1738 {
1739 int i;
1740 struct delayed_work *dwork = to_delayed_work(work);
1741 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1742 kvmclock_update_work);
1743 struct kvm *kvm = container_of(ka, struct kvm, arch);
1744 struct kvm_vcpu *vcpu;
1745
1746 kvm_for_each_vcpu(i, vcpu, kvm) {
1747 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
1748 kvm_vcpu_kick(vcpu);
1749 }
1750 }
1751
1752 static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
1753 {
1754 struct kvm *kvm = v->kvm;
1755
1756 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1757 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
1758 KVMCLOCK_UPDATE_DELAY);
1759 }
1760
1761 #define KVMCLOCK_SYNC_PERIOD (300 * HZ)
1762
1763 static void kvmclock_sync_fn(struct work_struct *work)
1764 {
1765 struct delayed_work *dwork = to_delayed_work(work);
1766 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1767 kvmclock_sync_work);
1768 struct kvm *kvm = container_of(ka, struct kvm, arch);
1769
1770 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
1771 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
1772 KVMCLOCK_SYNC_PERIOD);
1773 }
1774
1775 static bool msr_mtrr_valid(unsigned msr)
1776 {
1777 switch (msr) {
1778 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
1779 case MSR_MTRRfix64K_00000:
1780 case MSR_MTRRfix16K_80000:
1781 case MSR_MTRRfix16K_A0000:
1782 case MSR_MTRRfix4K_C0000:
1783 case MSR_MTRRfix4K_C8000:
1784 case MSR_MTRRfix4K_D0000:
1785 case MSR_MTRRfix4K_D8000:
1786 case MSR_MTRRfix4K_E0000:
1787 case MSR_MTRRfix4K_E8000:
1788 case MSR_MTRRfix4K_F0000:
1789 case MSR_MTRRfix4K_F8000:
1790 case MSR_MTRRdefType:
1791 case MSR_IA32_CR_PAT:
1792 return true;
1793 case 0x2f8:
1794 return true;
1795 }
1796 return false;
1797 }
1798
1799 static bool valid_pat_type(unsigned t)
1800 {
1801 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
1802 }
1803
1804 static bool valid_mtrr_type(unsigned t)
1805 {
1806 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
1807 }
1808
1809 bool kvm_mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1810 {
1811 int i;
1812 u64 mask;
1813
1814 if (!msr_mtrr_valid(msr))
1815 return false;
1816
1817 if (msr == MSR_IA32_CR_PAT) {
1818 for (i = 0; i < 8; i++)
1819 if (!valid_pat_type((data >> (i * 8)) & 0xff))
1820 return false;
1821 return true;
1822 } else if (msr == MSR_MTRRdefType) {
1823 if (data & ~0xcff)
1824 return false;
1825 return valid_mtrr_type(data & 0xff);
1826 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
1827 for (i = 0; i < 8 ; i++)
1828 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
1829 return false;
1830 return true;
1831 }
1832
1833 /* variable MTRRs */
1834 WARN_ON(!(msr >= 0x200 && msr < 0x200 + 2 * KVM_NR_VAR_MTRR));
1835
1836 mask = (~0ULL) << cpuid_maxphyaddr(vcpu);
1837 if ((msr & 1) == 0) {
1838 /* MTRR base */
1839 if (!valid_mtrr_type(data & 0xff))
1840 return false;
1841 mask |= 0xf00;
1842 } else
1843 /* MTRR mask */
1844 mask |= 0x7ff;
1845 if (data & mask) {
1846 kvm_inject_gp(vcpu, 0);
1847 return false;
1848 }
1849
1850 return true;
1851 }
1852 EXPORT_SYMBOL_GPL(kvm_mtrr_valid);
1853
1854 static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1855 {
1856 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1857
1858 if (!kvm_mtrr_valid(vcpu, msr, data))
1859 return 1;
1860
1861 if (msr == MSR_MTRRdefType) {
1862 vcpu->arch.mtrr_state.def_type = data;
1863 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
1864 } else if (msr == MSR_MTRRfix64K_00000)
1865 p[0] = data;
1866 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1867 p[1 + msr - MSR_MTRRfix16K_80000] = data;
1868 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1869 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
1870 else if (msr == MSR_IA32_CR_PAT)
1871 vcpu->arch.pat = data;
1872 else { /* Variable MTRRs */
1873 int idx, is_mtrr_mask;
1874 u64 *pt;
1875
1876 idx = (msr - 0x200) / 2;
1877 is_mtrr_mask = msr - 0x200 - 2 * idx;
1878 if (!is_mtrr_mask)
1879 pt =
1880 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1881 else
1882 pt =
1883 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1884 *pt = data;
1885 }
1886
1887 kvm_mmu_reset_context(vcpu);
1888 return 0;
1889 }
1890
1891 static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1892 {
1893 u64 mcg_cap = vcpu->arch.mcg_cap;
1894 unsigned bank_num = mcg_cap & 0xff;
1895
1896 switch (msr) {
1897 case MSR_IA32_MCG_STATUS:
1898 vcpu->arch.mcg_status = data;
1899 break;
1900 case MSR_IA32_MCG_CTL:
1901 if (!(mcg_cap & MCG_CTL_P))
1902 return 1;
1903 if (data != 0 && data != ~(u64)0)
1904 return -1;
1905 vcpu->arch.mcg_ctl = data;
1906 break;
1907 default:
1908 if (msr >= MSR_IA32_MC0_CTL &&
1909 msr < MSR_IA32_MCx_CTL(bank_num)) {
1910 u32 offset = msr - MSR_IA32_MC0_CTL;
1911 /* only 0 or all 1s can be written to IA32_MCi_CTL
1912 * some Linux kernels though clear bit 10 in bank 4 to
1913 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1914 * this to avoid an uncatched #GP in the guest
1915 */
1916 if ((offset & 0x3) == 0 &&
1917 data != 0 && (data | (1 << 10)) != ~(u64)0)
1918 return -1;
1919 vcpu->arch.mce_banks[offset] = data;
1920 break;
1921 }
1922 return 1;
1923 }
1924 return 0;
1925 }
1926
1927 static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1928 {
1929 struct kvm *kvm = vcpu->kvm;
1930 int lm = is_long_mode(vcpu);
1931 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1932 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1933 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1934 : kvm->arch.xen_hvm_config.blob_size_32;
1935 u32 page_num = data & ~PAGE_MASK;
1936 u64 page_addr = data & PAGE_MASK;
1937 u8 *page;
1938 int r;
1939
1940 r = -E2BIG;
1941 if (page_num >= blob_size)
1942 goto out;
1943 r = -ENOMEM;
1944 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
1945 if (IS_ERR(page)) {
1946 r = PTR_ERR(page);
1947 goto out;
1948 }
1949 if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
1950 goto out_free;
1951 r = 0;
1952 out_free:
1953 kfree(page);
1954 out:
1955 return r;
1956 }
1957
1958 static bool kvm_hv_hypercall_enabled(struct kvm *kvm)
1959 {
1960 return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE;
1961 }
1962
1963 static bool kvm_hv_msr_partition_wide(u32 msr)
1964 {
1965 bool r = false;
1966 switch (msr) {
1967 case HV_X64_MSR_GUEST_OS_ID:
1968 case HV_X64_MSR_HYPERCALL:
1969 case HV_X64_MSR_REFERENCE_TSC:
1970 case HV_X64_MSR_TIME_REF_COUNT:
1971 r = true;
1972 break;
1973 }
1974
1975 return r;
1976 }
1977
1978 static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1979 {
1980 struct kvm *kvm = vcpu->kvm;
1981
1982 switch (msr) {
1983 case HV_X64_MSR_GUEST_OS_ID:
1984 kvm->arch.hv_guest_os_id = data;
1985 /* setting guest os id to zero disables hypercall page */
1986 if (!kvm->arch.hv_guest_os_id)
1987 kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE;
1988 break;
1989 case HV_X64_MSR_HYPERCALL: {
1990 u64 gfn;
1991 unsigned long addr;
1992 u8 instructions[4];
1993
1994 /* if guest os id is not set hypercall should remain disabled */
1995 if (!kvm->arch.hv_guest_os_id)
1996 break;
1997 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) {
1998 kvm->arch.hv_hypercall = data;
1999 break;
2000 }
2001 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT;
2002 addr = gfn_to_hva(kvm, gfn);
2003 if (kvm_is_error_hva(addr))
2004 return 1;
2005 kvm_x86_ops->patch_hypercall(vcpu, instructions);
2006 ((unsigned char *)instructions)[3] = 0xc3; /* ret */
2007 if (__copy_to_user((void __user *)addr, instructions, 4))
2008 return 1;
2009 kvm->arch.hv_hypercall = data;
2010 mark_page_dirty(kvm, gfn);
2011 break;
2012 }
2013 case HV_X64_MSR_REFERENCE_TSC: {
2014 u64 gfn;
2015 HV_REFERENCE_TSC_PAGE tsc_ref;
2016 memset(&tsc_ref, 0, sizeof(tsc_ref));
2017 kvm->arch.hv_tsc_page = data;
2018 if (!(data & HV_X64_MSR_TSC_REFERENCE_ENABLE))
2019 break;
2020 gfn = data >> HV_X64_MSR_TSC_REFERENCE_ADDRESS_SHIFT;
2021 if (kvm_write_guest(kvm, gfn << HV_X64_MSR_TSC_REFERENCE_ADDRESS_SHIFT,
2022 &tsc_ref, sizeof(tsc_ref)))
2023 return 1;
2024 mark_page_dirty(kvm, gfn);
2025 break;
2026 }
2027 default:
2028 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
2029 "data 0x%llx\n", msr, data);
2030 return 1;
2031 }
2032 return 0;
2033 }
2034
2035 static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data)
2036 {
2037 switch (msr) {
2038 case HV_X64_MSR_APIC_ASSIST_PAGE: {
2039 u64 gfn;
2040 unsigned long addr;
2041
2042 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) {
2043 vcpu->arch.hv_vapic = data;
2044 if (kvm_lapic_enable_pv_eoi(vcpu, 0))
2045 return 1;
2046 break;
2047 }
2048 gfn = data >> HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT;
2049 addr = gfn_to_hva(vcpu->kvm, gfn);
2050 if (kvm_is_error_hva(addr))
2051 return 1;
2052 if (__clear_user((void __user *)addr, PAGE_SIZE))
2053 return 1;
2054 vcpu->arch.hv_vapic = data;
2055 mark_page_dirty(vcpu->kvm, gfn);
2056 if (kvm_lapic_enable_pv_eoi(vcpu, gfn_to_gpa(gfn) | KVM_MSR_ENABLED))
2057 return 1;
2058 break;
2059 }
2060 case HV_X64_MSR_EOI:
2061 return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data);
2062 case HV_X64_MSR_ICR:
2063 return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data);
2064 case HV_X64_MSR_TPR:
2065 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data);
2066 default:
2067 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
2068 "data 0x%llx\n", msr, data);
2069 return 1;
2070 }
2071
2072 return 0;
2073 }
2074
2075 static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
2076 {
2077 gpa_t gpa = data & ~0x3f;
2078
2079 /* Bits 2:5 are reserved, Should be zero */
2080 if (data & 0x3c)
2081 return 1;
2082
2083 vcpu->arch.apf.msr_val = data;
2084
2085 if (!(data & KVM_ASYNC_PF_ENABLED)) {
2086 kvm_clear_async_pf_completion_queue(vcpu);
2087 kvm_async_pf_hash_reset(vcpu);
2088 return 0;
2089 }
2090
2091 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
2092 sizeof(u32)))
2093 return 1;
2094
2095 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
2096 kvm_async_pf_wakeup_all(vcpu);
2097 return 0;
2098 }
2099
2100 static void kvmclock_reset(struct kvm_vcpu *vcpu)
2101 {
2102 vcpu->arch.pv_time_enabled = false;
2103 }
2104
2105 static void accumulate_steal_time(struct kvm_vcpu *vcpu)
2106 {
2107 u64 delta;
2108
2109 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2110 return;
2111
2112 delta = current->sched_info.run_delay - vcpu->arch.st.last_steal;
2113 vcpu->arch.st.last_steal = current->sched_info.run_delay;
2114 vcpu->arch.st.accum_steal = delta;
2115 }
2116
2117 static void record_steal_time(struct kvm_vcpu *vcpu)
2118 {
2119 accumulate_steal_time(vcpu);
2120
2121 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2122 return;
2123
2124 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2125 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
2126 return;
2127
2128 vcpu->arch.st.steal.steal += vcpu->arch.st.accum_steal;
2129 vcpu->arch.st.steal.version += 2;
2130 vcpu->arch.st.accum_steal = 0;
2131
2132 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2133 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2134 }
2135
2136 int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2137 {
2138 bool pr = false;
2139 u32 msr = msr_info->index;
2140 u64 data = msr_info->data;
2141
2142 switch (msr) {
2143 case MSR_AMD64_NB_CFG:
2144 case MSR_IA32_UCODE_REV:
2145 case MSR_IA32_UCODE_WRITE:
2146 case MSR_VM_HSAVE_PA:
2147 case MSR_AMD64_PATCH_LOADER:
2148 case MSR_AMD64_BU_CFG2:
2149 break;
2150
2151 case MSR_EFER:
2152 return set_efer(vcpu, data);
2153 case MSR_K7_HWCR:
2154 data &= ~(u64)0x40; /* ignore flush filter disable */
2155 data &= ~(u64)0x100; /* ignore ignne emulation enable */
2156 data &= ~(u64)0x8; /* ignore TLB cache disable */
2157 data &= ~(u64)0x40000; /* ignore Mc status write enable */
2158 if (data != 0) {
2159 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2160 data);
2161 return 1;
2162 }
2163 break;
2164 case MSR_FAM10H_MMIO_CONF_BASE:
2165 if (data != 0) {
2166 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2167 "0x%llx\n", data);
2168 return 1;
2169 }
2170 break;
2171 case MSR_IA32_DEBUGCTLMSR:
2172 if (!data) {
2173 /* We support the non-activated case already */
2174 break;
2175 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2176 /* Values other than LBR and BTF are vendor-specific,
2177 thus reserved and should throw a #GP */
2178 return 1;
2179 }
2180 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2181 __func__, data);
2182 break;
2183 case 0x200 ... 0x2ff:
2184 return set_msr_mtrr(vcpu, msr, data);
2185 case MSR_IA32_APICBASE:
2186 return kvm_set_apic_base(vcpu, msr_info);
2187 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2188 return kvm_x2apic_msr_write(vcpu, msr, data);
2189 case MSR_IA32_TSCDEADLINE:
2190 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2191 break;
2192 case MSR_IA32_TSC_ADJUST:
2193 if (guest_cpuid_has_tsc_adjust(vcpu)) {
2194 if (!msr_info->host_initiated) {
2195 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
2196 adjust_tsc_offset_guest(vcpu, adj);
2197 }
2198 vcpu->arch.ia32_tsc_adjust_msr = data;
2199 }
2200 break;
2201 case MSR_IA32_MISC_ENABLE:
2202 vcpu->arch.ia32_misc_enable_msr = data;
2203 break;
2204 case MSR_KVM_WALL_CLOCK_NEW:
2205 case MSR_KVM_WALL_CLOCK:
2206 vcpu->kvm->arch.wall_clock = data;
2207 kvm_write_wall_clock(vcpu->kvm, data);
2208 break;
2209 case MSR_KVM_SYSTEM_TIME_NEW:
2210 case MSR_KVM_SYSTEM_TIME: {
2211 u64 gpa_offset;
2212 struct kvm_arch *ka = &vcpu->kvm->arch;
2213
2214 kvmclock_reset(vcpu);
2215
2216 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) {
2217 bool tmp = (msr == MSR_KVM_SYSTEM_TIME);
2218
2219 if (ka->boot_vcpu_runs_old_kvmclock != tmp)
2220 set_bit(KVM_REQ_MASTERCLOCK_UPDATE,
2221 &vcpu->requests);
2222
2223 ka->boot_vcpu_runs_old_kvmclock = tmp;
2224 }
2225
2226 vcpu->arch.time = data;
2227 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
2228
2229 /* we verify if the enable bit is set... */
2230 if (!(data & 1))
2231 break;
2232
2233 gpa_offset = data & ~(PAGE_MASK | 1);
2234
2235 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
2236 &vcpu->arch.pv_time, data & ~1ULL,
2237 sizeof(struct pvclock_vcpu_time_info)))
2238 vcpu->arch.pv_time_enabled = false;
2239 else
2240 vcpu->arch.pv_time_enabled = true;
2241
2242 break;
2243 }
2244 case MSR_KVM_ASYNC_PF_EN:
2245 if (kvm_pv_enable_async_pf(vcpu, data))
2246 return 1;
2247 break;
2248 case MSR_KVM_STEAL_TIME:
2249
2250 if (unlikely(!sched_info_on()))
2251 return 1;
2252
2253 if (data & KVM_STEAL_RESERVED_MASK)
2254 return 1;
2255
2256 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
2257 data & KVM_STEAL_VALID_BITS,
2258 sizeof(struct kvm_steal_time)))
2259 return 1;
2260
2261 vcpu->arch.st.msr_val = data;
2262
2263 if (!(data & KVM_MSR_ENABLED))
2264 break;
2265
2266 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2267
2268 break;
2269 case MSR_KVM_PV_EOI_EN:
2270 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2271 return 1;
2272 break;
2273
2274 case MSR_IA32_MCG_CTL:
2275 case MSR_IA32_MCG_STATUS:
2276 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
2277 return set_msr_mce(vcpu, msr, data);
2278
2279 /* Performance counters are not protected by a CPUID bit,
2280 * so we should check all of them in the generic path for the sake of
2281 * cross vendor migration.
2282 * Writing a zero into the event select MSRs disables them,
2283 * which we perfectly emulate ;-). Any other value should be at least
2284 * reported, some guests depend on them.
2285 */
2286 case MSR_K7_EVNTSEL0:
2287 case MSR_K7_EVNTSEL1:
2288 case MSR_K7_EVNTSEL2:
2289 case MSR_K7_EVNTSEL3:
2290 if (data != 0)
2291 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
2292 "0x%x data 0x%llx\n", msr, data);
2293 break;
2294 /* at least RHEL 4 unconditionally writes to the perfctr registers,
2295 * so we ignore writes to make it happy.
2296 */
2297 case MSR_K7_PERFCTR0:
2298 case MSR_K7_PERFCTR1:
2299 case MSR_K7_PERFCTR2:
2300 case MSR_K7_PERFCTR3:
2301 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
2302 "0x%x data 0x%llx\n", msr, data);
2303 break;
2304 case MSR_P6_PERFCTR0:
2305 case MSR_P6_PERFCTR1:
2306 pr = true;
2307 case MSR_P6_EVNTSEL0:
2308 case MSR_P6_EVNTSEL1:
2309 if (kvm_pmu_msr(vcpu, msr))
2310 return kvm_pmu_set_msr(vcpu, msr_info);
2311
2312 if (pr || data != 0)
2313 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2314 "0x%x data 0x%llx\n", msr, data);
2315 break;
2316 case MSR_K7_CLK_CTL:
2317 /*
2318 * Ignore all writes to this no longer documented MSR.
2319 * Writes are only relevant for old K7 processors,
2320 * all pre-dating SVM, but a recommended workaround from
2321 * AMD for these chips. It is possible to specify the
2322 * affected processor models on the command line, hence
2323 * the need to ignore the workaround.
2324 */
2325 break;
2326 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2327 if (kvm_hv_msr_partition_wide(msr)) {
2328 int r;
2329 mutex_lock(&vcpu->kvm->lock);
2330 r = set_msr_hyperv_pw(vcpu, msr, data);
2331 mutex_unlock(&vcpu->kvm->lock);
2332 return r;
2333 } else
2334 return set_msr_hyperv(vcpu, msr, data);
2335 break;
2336 case MSR_IA32_BBL_CR_CTL3:
2337 /* Drop writes to this legacy MSR -- see rdmsr
2338 * counterpart for further detail.
2339 */
2340 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data);
2341 break;
2342 case MSR_AMD64_OSVW_ID_LENGTH:
2343 if (!guest_cpuid_has_osvw(vcpu))
2344 return 1;
2345 vcpu->arch.osvw.length = data;
2346 break;
2347 case MSR_AMD64_OSVW_STATUS:
2348 if (!guest_cpuid_has_osvw(vcpu))
2349 return 1;
2350 vcpu->arch.osvw.status = data;
2351 break;
2352 default:
2353 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2354 return xen_hvm_config(vcpu, data);
2355 if (kvm_pmu_msr(vcpu, msr))
2356 return kvm_pmu_set_msr(vcpu, msr_info);
2357 if (!ignore_msrs) {
2358 vcpu_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
2359 msr, data);
2360 return 1;
2361 } else {
2362 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
2363 msr, data);
2364 break;
2365 }
2366 }
2367 return 0;
2368 }
2369 EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2370
2371
2372 /*
2373 * Reads an msr value (of 'msr_index') into 'pdata'.
2374 * Returns 0 on success, non-0 otherwise.
2375 * Assumes vcpu_load() was already called.
2376 */
2377 int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2378 {
2379 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
2380 }
2381 EXPORT_SYMBOL_GPL(kvm_get_msr);
2382
2383 static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2384 {
2385 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
2386
2387 if (!msr_mtrr_valid(msr))
2388 return 1;
2389
2390 if (msr == MSR_MTRRdefType)
2391 *pdata = vcpu->arch.mtrr_state.def_type +
2392 (vcpu->arch.mtrr_state.enabled << 10);
2393 else if (msr == MSR_MTRRfix64K_00000)
2394 *pdata = p[0];
2395 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
2396 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
2397 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
2398 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
2399 else if (msr == MSR_IA32_CR_PAT)
2400 *pdata = vcpu->arch.pat;
2401 else { /* Variable MTRRs */
2402 int idx, is_mtrr_mask;
2403 u64 *pt;
2404
2405 idx = (msr - 0x200) / 2;
2406 is_mtrr_mask = msr - 0x200 - 2 * idx;
2407 if (!is_mtrr_mask)
2408 pt =
2409 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
2410 else
2411 pt =
2412 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
2413 *pdata = *pt;
2414 }
2415
2416 return 0;
2417 }
2418
2419 static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2420 {
2421 u64 data;
2422 u64 mcg_cap = vcpu->arch.mcg_cap;
2423 unsigned bank_num = mcg_cap & 0xff;
2424
2425 switch (msr) {
2426 case MSR_IA32_P5_MC_ADDR:
2427 case MSR_IA32_P5_MC_TYPE:
2428 data = 0;
2429 break;
2430 case MSR_IA32_MCG_CAP:
2431 data = vcpu->arch.mcg_cap;
2432 break;
2433 case MSR_IA32_MCG_CTL:
2434 if (!(mcg_cap & MCG_CTL_P))
2435 return 1;
2436 data = vcpu->arch.mcg_ctl;
2437 break;
2438 case MSR_IA32_MCG_STATUS:
2439 data = vcpu->arch.mcg_status;
2440 break;
2441 default:
2442 if (msr >= MSR_IA32_MC0_CTL &&
2443 msr < MSR_IA32_MCx_CTL(bank_num)) {
2444 u32 offset = msr - MSR_IA32_MC0_CTL;
2445 data = vcpu->arch.mce_banks[offset];
2446 break;
2447 }
2448 return 1;
2449 }
2450 *pdata = data;
2451 return 0;
2452 }
2453
2454 static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2455 {
2456 u64 data = 0;
2457 struct kvm *kvm = vcpu->kvm;
2458
2459 switch (msr) {
2460 case HV_X64_MSR_GUEST_OS_ID:
2461 data = kvm->arch.hv_guest_os_id;
2462 break;
2463 case HV_X64_MSR_HYPERCALL:
2464 data = kvm->arch.hv_hypercall;
2465 break;
2466 case HV_X64_MSR_TIME_REF_COUNT: {
2467 data =
2468 div_u64(get_kernel_ns() + kvm->arch.kvmclock_offset, 100);
2469 break;
2470 }
2471 case HV_X64_MSR_REFERENCE_TSC:
2472 data = kvm->arch.hv_tsc_page;
2473 break;
2474 default:
2475 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
2476 return 1;
2477 }
2478
2479 *pdata = data;
2480 return 0;
2481 }
2482
2483 static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2484 {
2485 u64 data = 0;
2486
2487 switch (msr) {
2488 case HV_X64_MSR_VP_INDEX: {
2489 int r;
2490 struct kvm_vcpu *v;
2491 kvm_for_each_vcpu(r, v, vcpu->kvm) {
2492 if (v == vcpu) {
2493 data = r;
2494 break;
2495 }
2496 }
2497 break;
2498 }
2499 case HV_X64_MSR_EOI:
2500 return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata);
2501 case HV_X64_MSR_ICR:
2502 return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata);
2503 case HV_X64_MSR_TPR:
2504 return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata);
2505 case HV_X64_MSR_APIC_ASSIST_PAGE:
2506 data = vcpu->arch.hv_vapic;
2507 break;
2508 default:
2509 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
2510 return 1;
2511 }
2512 *pdata = data;
2513 return 0;
2514 }
2515
2516 int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2517 {
2518 u64 data;
2519
2520 switch (msr) {
2521 case MSR_IA32_PLATFORM_ID:
2522 case MSR_IA32_EBL_CR_POWERON:
2523 case MSR_IA32_DEBUGCTLMSR:
2524 case MSR_IA32_LASTBRANCHFROMIP:
2525 case MSR_IA32_LASTBRANCHTOIP:
2526 case MSR_IA32_LASTINTFROMIP:
2527 case MSR_IA32_LASTINTTOIP:
2528 case MSR_K8_SYSCFG:
2529 case MSR_K7_HWCR:
2530 case MSR_VM_HSAVE_PA:
2531 case MSR_K7_EVNTSEL0:
2532 case MSR_K7_EVNTSEL1:
2533 case MSR_K7_EVNTSEL2:
2534 case MSR_K7_EVNTSEL3:
2535 case MSR_K7_PERFCTR0:
2536 case MSR_K7_PERFCTR1:
2537 case MSR_K7_PERFCTR2:
2538 case MSR_K7_PERFCTR3:
2539 case MSR_K8_INT_PENDING_MSG:
2540 case MSR_AMD64_NB_CFG:
2541 case MSR_FAM10H_MMIO_CONF_BASE:
2542 case MSR_AMD64_BU_CFG2:
2543 data = 0;
2544 break;
2545 case MSR_P6_PERFCTR0:
2546 case MSR_P6_PERFCTR1:
2547 case MSR_P6_EVNTSEL0:
2548 case MSR_P6_EVNTSEL1:
2549 if (kvm_pmu_msr(vcpu, msr))
2550 return kvm_pmu_get_msr(vcpu, msr, pdata);
2551 data = 0;
2552 break;
2553 case MSR_IA32_UCODE_REV:
2554 data = 0x100000000ULL;
2555 break;
2556 case MSR_MTRRcap:
2557 data = 0x500 | KVM_NR_VAR_MTRR;
2558 break;
2559 case 0x200 ... 0x2ff:
2560 return get_msr_mtrr(vcpu, msr, pdata);
2561 case 0xcd: /* fsb frequency */
2562 data = 3;
2563 break;
2564 /*
2565 * MSR_EBC_FREQUENCY_ID
2566 * Conservative value valid for even the basic CPU models.
2567 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2568 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2569 * and 266MHz for model 3, or 4. Set Core Clock
2570 * Frequency to System Bus Frequency Ratio to 1 (bits
2571 * 31:24) even though these are only valid for CPU
2572 * models > 2, however guests may end up dividing or
2573 * multiplying by zero otherwise.
2574 */
2575 case MSR_EBC_FREQUENCY_ID:
2576 data = 1 << 24;
2577 break;
2578 case MSR_IA32_APICBASE:
2579 data = kvm_get_apic_base(vcpu);
2580 break;
2581 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2582 return kvm_x2apic_msr_read(vcpu, msr, pdata);
2583 break;
2584 case MSR_IA32_TSCDEADLINE:
2585 data = kvm_get_lapic_tscdeadline_msr(vcpu);
2586 break;
2587 case MSR_IA32_TSC_ADJUST:
2588 data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
2589 break;
2590 case MSR_IA32_MISC_ENABLE:
2591 data = vcpu->arch.ia32_misc_enable_msr;
2592 break;
2593 case MSR_IA32_PERF_STATUS:
2594 /* TSC increment by tick */
2595 data = 1000ULL;
2596 /* CPU multiplier */
2597 data |= (((uint64_t)4ULL) << 40);
2598 break;
2599 case MSR_EFER:
2600 data = vcpu->arch.efer;
2601 break;
2602 case MSR_KVM_WALL_CLOCK:
2603 case MSR_KVM_WALL_CLOCK_NEW:
2604 data = vcpu->kvm->arch.wall_clock;
2605 break;
2606 case MSR_KVM_SYSTEM_TIME:
2607 case MSR_KVM_SYSTEM_TIME_NEW:
2608 data = vcpu->arch.time;
2609 break;
2610 case MSR_KVM_ASYNC_PF_EN:
2611 data = vcpu->arch.apf.msr_val;
2612 break;
2613 case MSR_KVM_STEAL_TIME:
2614 data = vcpu->arch.st.msr_val;
2615 break;
2616 case MSR_KVM_PV_EOI_EN:
2617 data = vcpu->arch.pv_eoi.msr_val;
2618 break;
2619 case MSR_IA32_P5_MC_ADDR:
2620 case MSR_IA32_P5_MC_TYPE:
2621 case MSR_IA32_MCG_CAP:
2622 case MSR_IA32_MCG_CTL:
2623 case MSR_IA32_MCG_STATUS:
2624 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
2625 return get_msr_mce(vcpu, msr, pdata);
2626 case MSR_K7_CLK_CTL:
2627 /*
2628 * Provide expected ramp-up count for K7. All other
2629 * are set to zero, indicating minimum divisors for
2630 * every field.
2631 *
2632 * This prevents guest kernels on AMD host with CPU
2633 * type 6, model 8 and higher from exploding due to
2634 * the rdmsr failing.
2635 */
2636 data = 0x20000000;
2637 break;
2638 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2639 if (kvm_hv_msr_partition_wide(msr)) {
2640 int r;
2641 mutex_lock(&vcpu->kvm->lock);
2642 r = get_msr_hyperv_pw(vcpu, msr, pdata);
2643 mutex_unlock(&vcpu->kvm->lock);
2644 return r;
2645 } else
2646 return get_msr_hyperv(vcpu, msr, pdata);
2647 break;
2648 case MSR_IA32_BBL_CR_CTL3:
2649 /* This legacy MSR exists but isn't fully documented in current
2650 * silicon. It is however accessed by winxp in very narrow
2651 * scenarios where it sets bit #19, itself documented as
2652 * a "reserved" bit. Best effort attempt to source coherent
2653 * read data here should the balance of the register be
2654 * interpreted by the guest:
2655 *
2656 * L2 cache control register 3: 64GB range, 256KB size,
2657 * enabled, latency 0x1, configured
2658 */
2659 data = 0xbe702111;
2660 break;
2661 case MSR_AMD64_OSVW_ID_LENGTH:
2662 if (!guest_cpuid_has_osvw(vcpu))
2663 return 1;
2664 data = vcpu->arch.osvw.length;
2665 break;
2666 case MSR_AMD64_OSVW_STATUS:
2667 if (!guest_cpuid_has_osvw(vcpu))
2668 return 1;
2669 data = vcpu->arch.osvw.status;
2670 break;
2671 default:
2672 if (kvm_pmu_msr(vcpu, msr))
2673 return kvm_pmu_get_msr(vcpu, msr, pdata);
2674 if (!ignore_msrs) {
2675 vcpu_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
2676 return 1;
2677 } else {
2678 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
2679 data = 0;
2680 }
2681 break;
2682 }
2683 *pdata = data;
2684 return 0;
2685 }
2686 EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2687
2688 /*
2689 * Read or write a bunch of msrs. All parameters are kernel addresses.
2690 *
2691 * @return number of msrs set successfully.
2692 */
2693 static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2694 struct kvm_msr_entry *entries,
2695 int (*do_msr)(struct kvm_vcpu *vcpu,
2696 unsigned index, u64 *data))
2697 {
2698 int i, idx;
2699
2700 idx = srcu_read_lock(&vcpu->kvm->srcu);
2701 for (i = 0; i < msrs->nmsrs; ++i)
2702 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2703 break;
2704 srcu_read_unlock(&vcpu->kvm->srcu, idx);
2705
2706 return i;
2707 }
2708
2709 /*
2710 * Read or write a bunch of msrs. Parameters are user addresses.
2711 *
2712 * @return number of msrs set successfully.
2713 */
2714 static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2715 int (*do_msr)(struct kvm_vcpu *vcpu,
2716 unsigned index, u64 *data),
2717 int writeback)
2718 {
2719 struct kvm_msrs msrs;
2720 struct kvm_msr_entry *entries;
2721 int r, n;
2722 unsigned size;
2723
2724 r = -EFAULT;
2725 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2726 goto out;
2727
2728 r = -E2BIG;
2729 if (msrs.nmsrs >= MAX_IO_MSRS)
2730 goto out;
2731
2732 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
2733 entries = memdup_user(user_msrs->entries, size);
2734 if (IS_ERR(entries)) {
2735 r = PTR_ERR(entries);
2736 goto out;
2737 }
2738
2739 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2740 if (r < 0)
2741 goto out_free;
2742
2743 r = -EFAULT;
2744 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2745 goto out_free;
2746
2747 r = n;
2748
2749 out_free:
2750 kfree(entries);
2751 out:
2752 return r;
2753 }
2754
2755 int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
2756 {
2757 int r;
2758
2759 switch (ext) {
2760 case KVM_CAP_IRQCHIP:
2761 case KVM_CAP_HLT:
2762 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
2763 case KVM_CAP_SET_TSS_ADDR:
2764 case KVM_CAP_EXT_CPUID:
2765 case KVM_CAP_EXT_EMUL_CPUID:
2766 case KVM_CAP_CLOCKSOURCE:
2767 case KVM_CAP_PIT:
2768 case KVM_CAP_NOP_IO_DELAY:
2769 case KVM_CAP_MP_STATE:
2770 case KVM_CAP_SYNC_MMU:
2771 case KVM_CAP_USER_NMI:
2772 case KVM_CAP_REINJECT_CONTROL:
2773 case KVM_CAP_IRQ_INJECT_STATUS:
2774 case KVM_CAP_IOEVENTFD:
2775 case KVM_CAP_IOEVENTFD_NO_LENGTH:
2776 case KVM_CAP_PIT2:
2777 case KVM_CAP_PIT_STATE2:
2778 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
2779 case KVM_CAP_XEN_HVM:
2780 case KVM_CAP_ADJUST_CLOCK:
2781 case KVM_CAP_VCPU_EVENTS:
2782 case KVM_CAP_HYPERV:
2783 case KVM_CAP_HYPERV_VAPIC:
2784 case KVM_CAP_HYPERV_SPIN:
2785 case KVM_CAP_PCI_SEGMENT:
2786 case KVM_CAP_DEBUGREGS:
2787 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2788 case KVM_CAP_XSAVE:
2789 case KVM_CAP_ASYNC_PF:
2790 case KVM_CAP_GET_TSC_KHZ:
2791 case KVM_CAP_KVMCLOCK_CTRL:
2792 case KVM_CAP_READONLY_MEM:
2793 case KVM_CAP_HYPERV_TIME:
2794 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
2795 case KVM_CAP_TSC_DEADLINE_TIMER:
2796 #ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
2797 case KVM_CAP_ASSIGN_DEV_IRQ:
2798 case KVM_CAP_PCI_2_3:
2799 #endif
2800 r = 1;
2801 break;
2802 case KVM_CAP_COALESCED_MMIO:
2803 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
2804 break;
2805 case KVM_CAP_VAPIC:
2806 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2807 break;
2808 case KVM_CAP_NR_VCPUS:
2809 r = KVM_SOFT_MAX_VCPUS;
2810 break;
2811 case KVM_CAP_MAX_VCPUS:
2812 r = KVM_MAX_VCPUS;
2813 break;
2814 case KVM_CAP_NR_MEMSLOTS:
2815 r = KVM_USER_MEM_SLOTS;
2816 break;
2817 case KVM_CAP_PV_MMU: /* obsolete */
2818 r = 0;
2819 break;
2820 #ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
2821 case KVM_CAP_IOMMU:
2822 r = iommu_present(&pci_bus_type);
2823 break;
2824 #endif
2825 case KVM_CAP_MCE:
2826 r = KVM_MAX_MCE_BANKS;
2827 break;
2828 case KVM_CAP_XCRS:
2829 r = cpu_has_xsave;
2830 break;
2831 case KVM_CAP_TSC_CONTROL:
2832 r = kvm_has_tsc_control;
2833 break;
2834 default:
2835 r = 0;
2836 break;
2837 }
2838 return r;
2839
2840 }
2841
2842 long kvm_arch_dev_ioctl(struct file *filp,
2843 unsigned int ioctl, unsigned long arg)
2844 {
2845 void __user *argp = (void __user *)arg;
2846 long r;
2847
2848 switch (ioctl) {
2849 case KVM_GET_MSR_INDEX_LIST: {
2850 struct kvm_msr_list __user *user_msr_list = argp;
2851 struct kvm_msr_list msr_list;
2852 unsigned n;
2853
2854 r = -EFAULT;
2855 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2856 goto out;
2857 n = msr_list.nmsrs;
2858 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
2859 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2860 goto out;
2861 r = -E2BIG;
2862 if (n < msr_list.nmsrs)
2863 goto out;
2864 r = -EFAULT;
2865 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2866 num_msrs_to_save * sizeof(u32)))
2867 goto out;
2868 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
2869 &emulated_msrs,
2870 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
2871 goto out;
2872 r = 0;
2873 break;
2874 }
2875 case KVM_GET_SUPPORTED_CPUID:
2876 case KVM_GET_EMULATED_CPUID: {
2877 struct kvm_cpuid2 __user *cpuid_arg = argp;
2878 struct kvm_cpuid2 cpuid;
2879
2880 r = -EFAULT;
2881 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2882 goto out;
2883
2884 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
2885 ioctl);
2886 if (r)
2887 goto out;
2888
2889 r = -EFAULT;
2890 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2891 goto out;
2892 r = 0;
2893 break;
2894 }
2895 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2896 u64 mce_cap;
2897
2898 mce_cap = KVM_MCE_CAP_SUPPORTED;
2899 r = -EFAULT;
2900 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
2901 goto out;
2902 r = 0;
2903 break;
2904 }
2905 default:
2906 r = -EINVAL;
2907 }
2908 out:
2909 return r;
2910 }
2911
2912 static void wbinvd_ipi(void *garbage)
2913 {
2914 wbinvd();
2915 }
2916
2917 static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2918 {
2919 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
2920 }
2921
2922 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2923 {
2924 /* Address WBINVD may be executed by guest */
2925 if (need_emulate_wbinvd(vcpu)) {
2926 if (kvm_x86_ops->has_wbinvd_exit())
2927 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2928 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2929 smp_call_function_single(vcpu->cpu,
2930 wbinvd_ipi, NULL, 1);
2931 }
2932
2933 kvm_x86_ops->vcpu_load(vcpu, cpu);
2934
2935 /* Apply any externally detected TSC adjustments (due to suspend) */
2936 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2937 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2938 vcpu->arch.tsc_offset_adjustment = 0;
2939 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2940 }
2941
2942 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
2943 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
2944 native_read_tsc() - vcpu->arch.last_host_tsc;
2945 if (tsc_delta < 0)
2946 mark_tsc_unstable("KVM discovered backwards TSC");
2947 if (check_tsc_unstable()) {
2948 u64 offset = kvm_x86_ops->compute_tsc_offset(vcpu,
2949 vcpu->arch.last_guest_tsc);
2950 kvm_x86_ops->write_tsc_offset(vcpu, offset);
2951 vcpu->arch.tsc_catchup = 1;
2952 }
2953 /*
2954 * On a host with synchronized TSC, there is no need to update
2955 * kvmclock on vcpu->cpu migration
2956 */
2957 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
2958 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
2959 if (vcpu->cpu != cpu)
2960 kvm_migrate_timers(vcpu);
2961 vcpu->cpu = cpu;
2962 }
2963
2964 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2965 }
2966
2967 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2968 {
2969 kvm_x86_ops->vcpu_put(vcpu);
2970 kvm_put_guest_fpu(vcpu);
2971 vcpu->arch.last_host_tsc = native_read_tsc();
2972 }
2973
2974 static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2975 struct kvm_lapic_state *s)
2976 {
2977 kvm_x86_ops->sync_pir_to_irr(vcpu);
2978 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
2979
2980 return 0;
2981 }
2982
2983 static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2984 struct kvm_lapic_state *s)
2985 {
2986 kvm_apic_post_state_restore(vcpu, s);
2987 update_cr8_intercept(vcpu);
2988
2989 return 0;
2990 }
2991
2992 static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2993 struct kvm_interrupt *irq)
2994 {
2995 if (irq->irq >= KVM_NR_INTERRUPTS)
2996 return -EINVAL;
2997 if (irqchip_in_kernel(vcpu->kvm))
2998 return -ENXIO;
2999
3000 kvm_queue_interrupt(vcpu, irq->irq, false);
3001 kvm_make_request(KVM_REQ_EVENT, vcpu);
3002
3003 return 0;
3004 }
3005
3006 static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
3007 {
3008 kvm_inject_nmi(vcpu);
3009
3010 return 0;
3011 }
3012
3013 static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
3014 struct kvm_tpr_access_ctl *tac)
3015 {
3016 if (tac->flags)
3017 return -EINVAL;
3018 vcpu->arch.tpr_access_reporting = !!tac->enabled;
3019 return 0;
3020 }
3021
3022 static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
3023 u64 mcg_cap)
3024 {
3025 int r;
3026 unsigned bank_num = mcg_cap & 0xff, bank;
3027
3028 r = -EINVAL;
3029 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
3030 goto out;
3031 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
3032 goto out;
3033 r = 0;
3034 vcpu->arch.mcg_cap = mcg_cap;
3035 /* Init IA32_MCG_CTL to all 1s */
3036 if (mcg_cap & MCG_CTL_P)
3037 vcpu->arch.mcg_ctl = ~(u64)0;
3038 /* Init IA32_MCi_CTL to all 1s */
3039 for (bank = 0; bank < bank_num; bank++)
3040 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
3041 out:
3042 return r;
3043 }
3044
3045 static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
3046 struct kvm_x86_mce *mce)
3047 {
3048 u64 mcg_cap = vcpu->arch.mcg_cap;
3049 unsigned bank_num = mcg_cap & 0xff;
3050 u64 *banks = vcpu->arch.mce_banks;
3051
3052 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
3053 return -EINVAL;
3054 /*
3055 * if IA32_MCG_CTL is not all 1s, the uncorrected error
3056 * reporting is disabled
3057 */
3058 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
3059 vcpu->arch.mcg_ctl != ~(u64)0)
3060 return 0;
3061 banks += 4 * mce->bank;
3062 /*
3063 * if IA32_MCi_CTL is not all 1s, the uncorrected error
3064 * reporting is disabled for the bank
3065 */
3066 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
3067 return 0;
3068 if (mce->status & MCI_STATUS_UC) {
3069 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
3070 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
3071 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3072 return 0;
3073 }
3074 if (banks[1] & MCI_STATUS_VAL)
3075 mce->status |= MCI_STATUS_OVER;
3076 banks[2] = mce->addr;
3077 banks[3] = mce->misc;
3078 vcpu->arch.mcg_status = mce->mcg_status;
3079 banks[1] = mce->status;
3080 kvm_queue_exception(vcpu, MC_VECTOR);
3081 } else if (!(banks[1] & MCI_STATUS_VAL)
3082 || !(banks[1] & MCI_STATUS_UC)) {
3083 if (banks[1] & MCI_STATUS_VAL)
3084 mce->status |= MCI_STATUS_OVER;
3085 banks[2] = mce->addr;
3086 banks[3] = mce->misc;
3087 banks[1] = mce->status;
3088 } else
3089 banks[1] |= MCI_STATUS_OVER;
3090 return 0;
3091 }
3092
3093 static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
3094 struct kvm_vcpu_events *events)
3095 {
3096 process_nmi(vcpu);
3097 events->exception.injected =
3098 vcpu->arch.exception.pending &&
3099 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3100 events->exception.nr = vcpu->arch.exception.nr;
3101 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
3102 events->exception.pad = 0;
3103 events->exception.error_code = vcpu->arch.exception.error_code;
3104
3105 events->interrupt.injected =
3106 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3107 events->interrupt.nr = vcpu->arch.interrupt.nr;
3108 events->interrupt.soft = 0;
3109 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
3110
3111 events->nmi.injected = vcpu->arch.nmi_injected;
3112 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3113 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
3114 events->nmi.pad = 0;
3115
3116 events->sipi_vector = 0; /* never valid when reporting to user space */
3117
3118 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
3119 | KVM_VCPUEVENT_VALID_SHADOW);
3120 memset(&events->reserved, 0, sizeof(events->reserved));
3121 }
3122
3123 static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
3124 struct kvm_vcpu_events *events)
3125 {
3126 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
3127 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
3128 | KVM_VCPUEVENT_VALID_SHADOW))
3129 return -EINVAL;
3130
3131 process_nmi(vcpu);
3132 vcpu->arch.exception.pending = events->exception.injected;
3133 vcpu->arch.exception.nr = events->exception.nr;
3134 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
3135 vcpu->arch.exception.error_code = events->exception.error_code;
3136
3137 vcpu->arch.interrupt.pending = events->interrupt.injected;
3138 vcpu->arch.interrupt.nr = events->interrupt.nr;
3139 vcpu->arch.interrupt.soft = events->interrupt.soft;
3140 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
3141 kvm_x86_ops->set_interrupt_shadow(vcpu,
3142 events->interrupt.shadow);
3143
3144 vcpu->arch.nmi_injected = events->nmi.injected;
3145 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
3146 vcpu->arch.nmi_pending = events->nmi.pending;
3147 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
3148
3149 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
3150 kvm_vcpu_has_lapic(vcpu))
3151 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3152
3153 kvm_make_request(KVM_REQ_EVENT, vcpu);
3154
3155 return 0;
3156 }
3157
3158 static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3159 struct kvm_debugregs *dbgregs)
3160 {
3161 unsigned long val;
3162
3163 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
3164 kvm_get_dr(vcpu, 6, &val);
3165 dbgregs->dr6 = val;
3166 dbgregs->dr7 = vcpu->arch.dr7;
3167 dbgregs->flags = 0;
3168 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
3169 }
3170
3171 static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3172 struct kvm_debugregs *dbgregs)
3173 {
3174 if (dbgregs->flags)
3175 return -EINVAL;
3176
3177 if (dbgregs->dr6 & ~0xffffffffull)
3178 return -EINVAL;
3179 if (dbgregs->dr7 & ~0xffffffffull)
3180 return -EINVAL;
3181
3182 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
3183 kvm_update_dr0123(vcpu);
3184 vcpu->arch.dr6 = dbgregs->dr6;
3185 kvm_update_dr6(vcpu);
3186 vcpu->arch.dr7 = dbgregs->dr7;
3187 kvm_update_dr7(vcpu);
3188
3189 return 0;
3190 }
3191
3192 #define XSTATE_COMPACTION_ENABLED (1ULL << 63)
3193
3194 static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
3195 {
3196 struct xsave_struct *xsave = &vcpu->arch.guest_fpu.state->xsave;
3197 u64 xstate_bv = xsave->xsave_hdr.xstate_bv;
3198 u64 valid;
3199
3200 /*
3201 * Copy legacy XSAVE area, to avoid complications with CPUID
3202 * leaves 0 and 1 in the loop below.
3203 */
3204 memcpy(dest, xsave, XSAVE_HDR_OFFSET);
3205
3206 /* Set XSTATE_BV */
3207 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
3208
3209 /*
3210 * Copy each region from the possibly compacted offset to the
3211 * non-compacted offset.
3212 */
3213 valid = xstate_bv & ~XSTATE_FPSSE;
3214 while (valid) {
3215 u64 feature = valid & -valid;
3216 int index = fls64(feature) - 1;
3217 void *src = get_xsave_addr(xsave, feature);
3218
3219 if (src) {
3220 u32 size, offset, ecx, edx;
3221 cpuid_count(XSTATE_CPUID, index,
3222 &size, &offset, &ecx, &edx);
3223 memcpy(dest + offset, src, size);
3224 }
3225
3226 valid -= feature;
3227 }
3228 }
3229
3230 static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
3231 {
3232 struct xsave_struct *xsave = &vcpu->arch.guest_fpu.state->xsave;
3233 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
3234 u64 valid;
3235
3236 /*
3237 * Copy legacy XSAVE area, to avoid complications with CPUID
3238 * leaves 0 and 1 in the loop below.
3239 */
3240 memcpy(xsave, src, XSAVE_HDR_OFFSET);
3241
3242 /* Set XSTATE_BV and possibly XCOMP_BV. */
3243 xsave->xsave_hdr.xstate_bv = xstate_bv;
3244 if (cpu_has_xsaves)
3245 xsave->xsave_hdr.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
3246
3247 /*
3248 * Copy each region from the non-compacted offset to the
3249 * possibly compacted offset.
3250 */
3251 valid = xstate_bv & ~XSTATE_FPSSE;
3252 while (valid) {
3253 u64 feature = valid & -valid;
3254 int index = fls64(feature) - 1;
3255 void *dest = get_xsave_addr(xsave, feature);
3256
3257 if (dest) {
3258 u32 size, offset, ecx, edx;
3259 cpuid_count(XSTATE_CPUID, index,
3260 &size, &offset, &ecx, &edx);
3261 memcpy(dest, src + offset, size);
3262 } else
3263 WARN_ON_ONCE(1);
3264
3265 valid -= feature;
3266 }
3267 }
3268
3269 static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3270 struct kvm_xsave *guest_xsave)
3271 {
3272 if (cpu_has_xsave) {
3273 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
3274 fill_xsave((u8 *) guest_xsave->region, vcpu);
3275 } else {
3276 memcpy(guest_xsave->region,
3277 &vcpu->arch.guest_fpu.state->fxsave,
3278 sizeof(struct i387_fxsave_struct));
3279 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
3280 XSTATE_FPSSE;
3281 }
3282 }
3283
3284 static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3285 struct kvm_xsave *guest_xsave)
3286 {
3287 u64 xstate_bv =
3288 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
3289
3290 if (cpu_has_xsave) {
3291 /*
3292 * Here we allow setting states that are not present in
3293 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3294 * with old userspace.
3295 */
3296 if (xstate_bv & ~kvm_supported_xcr0())
3297 return -EINVAL;
3298 load_xsave(vcpu, (u8 *)guest_xsave->region);
3299 } else {
3300 if (xstate_bv & ~XSTATE_FPSSE)
3301 return -EINVAL;
3302 memcpy(&vcpu->arch.guest_fpu.state->fxsave,
3303 guest_xsave->region, sizeof(struct i387_fxsave_struct));
3304 }
3305 return 0;
3306 }
3307
3308 static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3309 struct kvm_xcrs *guest_xcrs)
3310 {
3311 if (!cpu_has_xsave) {
3312 guest_xcrs->nr_xcrs = 0;
3313 return;
3314 }
3315
3316 guest_xcrs->nr_xcrs = 1;
3317 guest_xcrs->flags = 0;
3318 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3319 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3320 }
3321
3322 static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3323 struct kvm_xcrs *guest_xcrs)
3324 {
3325 int i, r = 0;
3326
3327 if (!cpu_has_xsave)
3328 return -EINVAL;
3329
3330 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3331 return -EINVAL;
3332
3333 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3334 /* Only support XCR0 currently */
3335 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
3336 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
3337 guest_xcrs->xcrs[i].value);
3338 break;
3339 }
3340 if (r)
3341 r = -EINVAL;
3342 return r;
3343 }
3344
3345 /*
3346 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3347 * stopped by the hypervisor. This function will be called from the host only.
3348 * EINVAL is returned when the host attempts to set the flag for a guest that
3349 * does not support pv clocks.
3350 */
3351 static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3352 {
3353 if (!vcpu->arch.pv_time_enabled)
3354 return -EINVAL;
3355 vcpu->arch.pvclock_set_guest_stopped_request = true;
3356 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3357 return 0;
3358 }
3359
3360 long kvm_arch_vcpu_ioctl(struct file *filp,
3361 unsigned int ioctl, unsigned long arg)
3362 {
3363 struct kvm_vcpu *vcpu = filp->private_data;
3364 void __user *argp = (void __user *)arg;
3365 int r;
3366 union {
3367 struct kvm_lapic_state *lapic;
3368 struct kvm_xsave *xsave;
3369 struct kvm_xcrs *xcrs;
3370 void *buffer;
3371 } u;
3372
3373 u.buffer = NULL;
3374 switch (ioctl) {
3375 case KVM_GET_LAPIC: {
3376 r = -EINVAL;
3377 if (!vcpu->arch.apic)
3378 goto out;
3379 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
3380
3381 r = -ENOMEM;
3382 if (!u.lapic)
3383 goto out;
3384 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
3385 if (r)
3386 goto out;
3387 r = -EFAULT;
3388 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
3389 goto out;
3390 r = 0;
3391 break;
3392 }
3393 case KVM_SET_LAPIC: {
3394 r = -EINVAL;
3395 if (!vcpu->arch.apic)
3396 goto out;
3397 u.lapic = memdup_user(argp, sizeof(*u.lapic));
3398 if (IS_ERR(u.lapic))
3399 return PTR_ERR(u.lapic);
3400
3401 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
3402 break;
3403 }
3404 case KVM_INTERRUPT: {
3405 struct kvm_interrupt irq;
3406
3407 r = -EFAULT;
3408 if (copy_from_user(&irq, argp, sizeof irq))
3409 goto out;
3410 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
3411 break;
3412 }
3413 case KVM_NMI: {
3414 r = kvm_vcpu_ioctl_nmi(vcpu);
3415 break;
3416 }
3417 case KVM_SET_CPUID: {
3418 struct kvm_cpuid __user *cpuid_arg = argp;
3419 struct kvm_cpuid cpuid;
3420
3421 r = -EFAULT;
3422 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3423 goto out;
3424 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
3425 break;
3426 }
3427 case KVM_SET_CPUID2: {
3428 struct kvm_cpuid2 __user *cpuid_arg = argp;
3429 struct kvm_cpuid2 cpuid;
3430
3431 r = -EFAULT;
3432 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3433 goto out;
3434 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
3435 cpuid_arg->entries);
3436 break;
3437 }
3438 case KVM_GET_CPUID2: {
3439 struct kvm_cpuid2 __user *cpuid_arg = argp;
3440 struct kvm_cpuid2 cpuid;
3441
3442 r = -EFAULT;
3443 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3444 goto out;
3445 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
3446 cpuid_arg->entries);
3447 if (r)
3448 goto out;
3449 r = -EFAULT;
3450 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3451 goto out;
3452 r = 0;
3453 break;
3454 }
3455 case KVM_GET_MSRS:
3456 r = msr_io(vcpu, argp, kvm_get_msr, 1);
3457 break;
3458 case KVM_SET_MSRS:
3459 r = msr_io(vcpu, argp, do_set_msr, 0);
3460 break;
3461 case KVM_TPR_ACCESS_REPORTING: {
3462 struct kvm_tpr_access_ctl tac;
3463
3464 r = -EFAULT;
3465 if (copy_from_user(&tac, argp, sizeof tac))
3466 goto out;
3467 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3468 if (r)
3469 goto out;
3470 r = -EFAULT;
3471 if (copy_to_user(argp, &tac, sizeof tac))
3472 goto out;
3473 r = 0;
3474 break;
3475 };
3476 case KVM_SET_VAPIC_ADDR: {
3477 struct kvm_vapic_addr va;
3478
3479 r = -EINVAL;
3480 if (!irqchip_in_kernel(vcpu->kvm))
3481 goto out;
3482 r = -EFAULT;
3483 if (copy_from_user(&va, argp, sizeof va))
3484 goto out;
3485 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
3486 break;
3487 }
3488 case KVM_X86_SETUP_MCE: {
3489 u64 mcg_cap;
3490
3491 r = -EFAULT;
3492 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3493 goto out;
3494 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3495 break;
3496 }
3497 case KVM_X86_SET_MCE: {
3498 struct kvm_x86_mce mce;
3499
3500 r = -EFAULT;
3501 if (copy_from_user(&mce, argp, sizeof mce))
3502 goto out;
3503 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3504 break;
3505 }
3506 case KVM_GET_VCPU_EVENTS: {
3507 struct kvm_vcpu_events events;
3508
3509 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3510
3511 r = -EFAULT;
3512 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3513 break;
3514 r = 0;
3515 break;
3516 }
3517 case KVM_SET_VCPU_EVENTS: {
3518 struct kvm_vcpu_events events;
3519
3520 r = -EFAULT;
3521 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3522 break;
3523
3524 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3525 break;
3526 }
3527 case KVM_GET_DEBUGREGS: {
3528 struct kvm_debugregs dbgregs;
3529
3530 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3531
3532 r = -EFAULT;
3533 if (copy_to_user(argp, &dbgregs,
3534 sizeof(struct kvm_debugregs)))
3535 break;
3536 r = 0;
3537 break;
3538 }
3539 case KVM_SET_DEBUGREGS: {
3540 struct kvm_debugregs dbgregs;
3541
3542 r = -EFAULT;
3543 if (copy_from_user(&dbgregs, argp,
3544 sizeof(struct kvm_debugregs)))
3545 break;
3546
3547 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3548 break;
3549 }
3550 case KVM_GET_XSAVE: {
3551 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
3552 r = -ENOMEM;
3553 if (!u.xsave)
3554 break;
3555
3556 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
3557
3558 r = -EFAULT;
3559 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
3560 break;
3561 r = 0;
3562 break;
3563 }
3564 case KVM_SET_XSAVE: {
3565 u.xsave = memdup_user(argp, sizeof(*u.xsave));
3566 if (IS_ERR(u.xsave))
3567 return PTR_ERR(u.xsave);
3568
3569 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
3570 break;
3571 }
3572 case KVM_GET_XCRS: {
3573 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
3574 r = -ENOMEM;
3575 if (!u.xcrs)
3576 break;
3577
3578 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
3579
3580 r = -EFAULT;
3581 if (copy_to_user(argp, u.xcrs,
3582 sizeof(struct kvm_xcrs)))
3583 break;
3584 r = 0;
3585 break;
3586 }
3587 case KVM_SET_XCRS: {
3588 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
3589 if (IS_ERR(u.xcrs))
3590 return PTR_ERR(u.xcrs);
3591
3592 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
3593 break;
3594 }
3595 case KVM_SET_TSC_KHZ: {
3596 u32 user_tsc_khz;
3597
3598 r = -EINVAL;
3599 user_tsc_khz = (u32)arg;
3600
3601 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3602 goto out;
3603
3604 if (user_tsc_khz == 0)
3605 user_tsc_khz = tsc_khz;
3606
3607 kvm_set_tsc_khz(vcpu, user_tsc_khz);
3608
3609 r = 0;
3610 goto out;
3611 }
3612 case KVM_GET_TSC_KHZ: {
3613 r = vcpu->arch.virtual_tsc_khz;
3614 goto out;
3615 }
3616 case KVM_KVMCLOCK_CTRL: {
3617 r = kvm_set_guest_paused(vcpu);
3618 goto out;
3619 }
3620 default:
3621 r = -EINVAL;
3622 }
3623 out:
3624 kfree(u.buffer);
3625 return r;
3626 }
3627
3628 int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3629 {
3630 return VM_FAULT_SIGBUS;
3631 }
3632
3633 static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3634 {
3635 int ret;
3636
3637 if (addr > (unsigned int)(-3 * PAGE_SIZE))
3638 return -EINVAL;
3639 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3640 return ret;
3641 }
3642
3643 static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3644 u64 ident_addr)
3645 {
3646 kvm->arch.ept_identity_map_addr = ident_addr;
3647 return 0;
3648 }
3649
3650 static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3651 u32 kvm_nr_mmu_pages)
3652 {
3653 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3654 return -EINVAL;
3655
3656 mutex_lock(&kvm->slots_lock);
3657
3658 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
3659 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
3660
3661 mutex_unlock(&kvm->slots_lock);
3662 return 0;
3663 }
3664
3665 static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3666 {
3667 return kvm->arch.n_max_mmu_pages;
3668 }
3669
3670 static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3671 {
3672 int r;
3673
3674 r = 0;
3675 switch (chip->chip_id) {
3676 case KVM_IRQCHIP_PIC_MASTER:
3677 memcpy(&chip->chip.pic,
3678 &pic_irqchip(kvm)->pics[0],
3679 sizeof(struct kvm_pic_state));
3680 break;
3681 case KVM_IRQCHIP_PIC_SLAVE:
3682 memcpy(&chip->chip.pic,
3683 &pic_irqchip(kvm)->pics[1],
3684 sizeof(struct kvm_pic_state));
3685 break;
3686 case KVM_IRQCHIP_IOAPIC:
3687 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
3688 break;
3689 default:
3690 r = -EINVAL;
3691 break;
3692 }
3693 return r;
3694 }
3695
3696 static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3697 {
3698 int r;
3699
3700 r = 0;
3701 switch (chip->chip_id) {
3702 case KVM_IRQCHIP_PIC_MASTER:
3703 spin_lock(&pic_irqchip(kvm)->lock);
3704 memcpy(&pic_irqchip(kvm)->pics[0],
3705 &chip->chip.pic,
3706 sizeof(struct kvm_pic_state));
3707 spin_unlock(&pic_irqchip(kvm)->lock);
3708 break;
3709 case KVM_IRQCHIP_PIC_SLAVE:
3710 spin_lock(&pic_irqchip(kvm)->lock);
3711 memcpy(&pic_irqchip(kvm)->pics[1],
3712 &chip->chip.pic,
3713 sizeof(struct kvm_pic_state));
3714 spin_unlock(&pic_irqchip(kvm)->lock);
3715 break;
3716 case KVM_IRQCHIP_IOAPIC:
3717 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
3718 break;
3719 default:
3720 r = -EINVAL;
3721 break;
3722 }
3723 kvm_pic_update_irq(pic_irqchip(kvm));
3724 return r;
3725 }
3726
3727 static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3728 {
3729 int r = 0;
3730
3731 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3732 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
3733 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3734 return r;
3735 }
3736
3737 static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3738 {
3739 int i;
3740 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3741 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
3742 for (i = 0; i < 3; i++)
3743 kvm_pit_load_count(kvm, i, ps->channels[i].count, 0);
3744 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3745 return 0;
3746 }
3747
3748 static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3749 {
3750 int r = 0;
3751
3752 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3753 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3754 sizeof(ps->channels));
3755 ps->flags = kvm->arch.vpit->pit_state.flags;
3756 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3757 memset(&ps->reserved, 0, sizeof(ps->reserved));
3758 return r;
3759 }
3760
3761 static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3762 {
3763 int r = 0, start = 0;
3764 int i;
3765 u32 prev_legacy, cur_legacy;
3766 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3767 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3768 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3769 if (!prev_legacy && cur_legacy)
3770 start = 1;
3771 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
3772 sizeof(kvm->arch.vpit->pit_state.channels));
3773 kvm->arch.vpit->pit_state.flags = ps->flags;
3774 for (i = 0; i < 3; i++)
3775 kvm_pit_load_count(kvm, i, kvm->arch.vpit->pit_state.channels[i].count, start);
3776 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3777 return r;
3778 }
3779
3780 static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3781 struct kvm_reinject_control *control)
3782 {
3783 if (!kvm->arch.vpit)
3784 return -ENXIO;
3785 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3786 kvm->arch.vpit->pit_state.reinject = control->pit_reinject;
3787 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3788 return 0;
3789 }
3790
3791 /**
3792 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3793 * @kvm: kvm instance
3794 * @log: slot id and address to which we copy the log
3795 *
3796 * Steps 1-4 below provide general overview of dirty page logging. See
3797 * kvm_get_dirty_log_protect() function description for additional details.
3798 *
3799 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we
3800 * always flush the TLB (step 4) even if previous step failed and the dirty
3801 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API
3802 * does not preclude user space subsequent dirty log read. Flushing TLB ensures
3803 * writes will be marked dirty for next log read.
3804 *
3805 * 1. Take a snapshot of the bit and clear it if needed.
3806 * 2. Write protect the corresponding page.
3807 * 3. Copy the snapshot to the userspace.
3808 * 4. Flush TLB's if needed.
3809 */
3810 int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
3811 {
3812 bool is_dirty = false;
3813 int r;
3814
3815 mutex_lock(&kvm->slots_lock);
3816
3817 /*
3818 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
3819 */
3820 if (kvm_x86_ops->flush_log_dirty)
3821 kvm_x86_ops->flush_log_dirty(kvm);
3822
3823 r = kvm_get_dirty_log_protect(kvm, log, &is_dirty);
3824
3825 /*
3826 * All the TLBs can be flushed out of mmu lock, see the comments in
3827 * kvm_mmu_slot_remove_write_access().
3828 */
3829 lockdep_assert_held(&kvm->slots_lock);
3830 if (is_dirty)
3831 kvm_flush_remote_tlbs(kvm);
3832
3833 mutex_unlock(&kvm->slots_lock);
3834 return r;
3835 }
3836
3837 int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
3838 bool line_status)
3839 {
3840 if (!irqchip_in_kernel(kvm))
3841 return -ENXIO;
3842
3843 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
3844 irq_event->irq, irq_event->level,
3845 line_status);
3846 return 0;
3847 }
3848
3849 long kvm_arch_vm_ioctl(struct file *filp,
3850 unsigned int ioctl, unsigned long arg)
3851 {
3852 struct kvm *kvm = filp->private_data;
3853 void __user *argp = (void __user *)arg;
3854 int r = -ENOTTY;
3855 /*
3856 * This union makes it completely explicit to gcc-3.x
3857 * that these two variables' stack usage should be
3858 * combined, not added together.
3859 */
3860 union {
3861 struct kvm_pit_state ps;
3862 struct kvm_pit_state2 ps2;
3863 struct kvm_pit_config pit_config;
3864 } u;
3865
3866 switch (ioctl) {
3867 case KVM_SET_TSS_ADDR:
3868 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
3869 break;
3870 case KVM_SET_IDENTITY_MAP_ADDR: {
3871 u64 ident_addr;
3872
3873 r = -EFAULT;
3874 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3875 goto out;
3876 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
3877 break;
3878 }
3879 case KVM_SET_NR_MMU_PAGES:
3880 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
3881 break;
3882 case KVM_GET_NR_MMU_PAGES:
3883 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3884 break;
3885 case KVM_CREATE_IRQCHIP: {
3886 struct kvm_pic *vpic;
3887
3888 mutex_lock(&kvm->lock);
3889 r = -EEXIST;
3890 if (kvm->arch.vpic)
3891 goto create_irqchip_unlock;
3892 r = -EINVAL;
3893 if (atomic_read(&kvm->online_vcpus))
3894 goto create_irqchip_unlock;
3895 r = -ENOMEM;
3896 vpic = kvm_create_pic(kvm);
3897 if (vpic) {
3898 r = kvm_ioapic_init(kvm);
3899 if (r) {
3900 mutex_lock(&kvm->slots_lock);
3901 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3902 &vpic->dev_master);
3903 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3904 &vpic->dev_slave);
3905 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3906 &vpic->dev_eclr);
3907 mutex_unlock(&kvm->slots_lock);
3908 kfree(vpic);
3909 goto create_irqchip_unlock;
3910 }
3911 } else
3912 goto create_irqchip_unlock;
3913 smp_wmb();
3914 kvm->arch.vpic = vpic;
3915 smp_wmb();
3916 r = kvm_setup_default_irq_routing(kvm);
3917 if (r) {
3918 mutex_lock(&kvm->slots_lock);
3919 mutex_lock(&kvm->irq_lock);
3920 kvm_ioapic_destroy(kvm);
3921 kvm_destroy_pic(kvm);
3922 mutex_unlock(&kvm->irq_lock);
3923 mutex_unlock(&kvm->slots_lock);
3924 }
3925 create_irqchip_unlock:
3926 mutex_unlock(&kvm->lock);
3927 break;
3928 }
3929 case KVM_CREATE_PIT:
3930 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3931 goto create_pit;
3932 case KVM_CREATE_PIT2:
3933 r = -EFAULT;
3934 if (copy_from_user(&u.pit_config, argp,
3935 sizeof(struct kvm_pit_config)))
3936 goto out;
3937 create_pit:
3938 mutex_lock(&kvm->slots_lock);
3939 r = -EEXIST;
3940 if (kvm->arch.vpit)
3941 goto create_pit_unlock;
3942 r = -ENOMEM;
3943 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
3944 if (kvm->arch.vpit)
3945 r = 0;
3946 create_pit_unlock:
3947 mutex_unlock(&kvm->slots_lock);
3948 break;
3949 case KVM_GET_IRQCHIP: {
3950 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
3951 struct kvm_irqchip *chip;
3952
3953 chip = memdup_user(argp, sizeof(*chip));
3954 if (IS_ERR(chip)) {
3955 r = PTR_ERR(chip);
3956 goto out;
3957 }
3958
3959 r = -ENXIO;
3960 if (!irqchip_in_kernel(kvm))
3961 goto get_irqchip_out;
3962 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
3963 if (r)
3964 goto get_irqchip_out;
3965 r = -EFAULT;
3966 if (copy_to_user(argp, chip, sizeof *chip))
3967 goto get_irqchip_out;
3968 r = 0;
3969 get_irqchip_out:
3970 kfree(chip);
3971 break;
3972 }
3973 case KVM_SET_IRQCHIP: {
3974 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
3975 struct kvm_irqchip *chip;
3976
3977 chip = memdup_user(argp, sizeof(*chip));
3978 if (IS_ERR(chip)) {
3979 r = PTR_ERR(chip);
3980 goto out;
3981 }
3982
3983 r = -ENXIO;
3984 if (!irqchip_in_kernel(kvm))
3985 goto set_irqchip_out;
3986 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
3987 if (r)
3988 goto set_irqchip_out;
3989 r = 0;
3990 set_irqchip_out:
3991 kfree(chip);
3992 break;
3993 }
3994 case KVM_GET_PIT: {
3995 r = -EFAULT;
3996 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
3997 goto out;
3998 r = -ENXIO;
3999 if (!kvm->arch.vpit)
4000 goto out;
4001 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
4002 if (r)
4003 goto out;
4004 r = -EFAULT;
4005 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
4006 goto out;
4007 r = 0;
4008 break;
4009 }
4010 case KVM_SET_PIT: {
4011 r = -EFAULT;
4012 if (copy_from_user(&u.ps, argp, sizeof u.ps))
4013 goto out;
4014 r = -ENXIO;
4015 if (!kvm->arch.vpit)
4016 goto out;
4017 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
4018 break;
4019 }
4020 case KVM_GET_PIT2: {
4021 r = -ENXIO;
4022 if (!kvm->arch.vpit)
4023 goto out;
4024 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
4025 if (r)
4026 goto out;
4027 r = -EFAULT;
4028 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
4029 goto out;
4030 r = 0;
4031 break;
4032 }
4033 case KVM_SET_PIT2: {
4034 r = -EFAULT;
4035 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
4036 goto out;
4037 r = -ENXIO;
4038 if (!kvm->arch.vpit)
4039 goto out;
4040 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
4041 break;
4042 }
4043 case KVM_REINJECT_CONTROL: {
4044 struct kvm_reinject_control control;
4045 r = -EFAULT;
4046 if (copy_from_user(&control, argp, sizeof(control)))
4047 goto out;
4048 r = kvm_vm_ioctl_reinject(kvm, &control);
4049 break;
4050 }
4051 case KVM_XEN_HVM_CONFIG: {
4052 r = -EFAULT;
4053 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
4054 sizeof(struct kvm_xen_hvm_config)))
4055 goto out;
4056 r = -EINVAL;
4057 if (kvm->arch.xen_hvm_config.flags)
4058 goto out;
4059 r = 0;
4060 break;
4061 }
4062 case KVM_SET_CLOCK: {
4063 struct kvm_clock_data user_ns;
4064 u64 now_ns;
4065 s64 delta;
4066
4067 r = -EFAULT;
4068 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
4069 goto out;
4070
4071 r = -EINVAL;
4072 if (user_ns.flags)
4073 goto out;
4074
4075 r = 0;
4076 local_irq_disable();
4077 now_ns = get_kernel_ns();
4078 delta = user_ns.clock - now_ns;
4079 local_irq_enable();
4080 kvm->arch.kvmclock_offset = delta;
4081 kvm_gen_update_masterclock(kvm);
4082 break;
4083 }
4084 case KVM_GET_CLOCK: {
4085 struct kvm_clock_data user_ns;
4086 u64 now_ns;
4087
4088 local_irq_disable();
4089 now_ns = get_kernel_ns();
4090 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
4091 local_irq_enable();
4092 user_ns.flags = 0;
4093 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
4094
4095 r = -EFAULT;
4096 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
4097 goto out;
4098 r = 0;
4099 break;
4100 }
4101
4102 default:
4103 r = kvm_vm_ioctl_assigned_device(kvm, ioctl, arg);
4104 }
4105 out:
4106 return r;
4107 }
4108
4109 static void kvm_init_msr_list(void)
4110 {
4111 u32 dummy[2];
4112 unsigned i, j;
4113
4114 /* skip the first msrs in the list. KVM-specific */
4115 for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) {
4116 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
4117 continue;
4118
4119 /*
4120 * Even MSRs that are valid in the host may not be exposed
4121 * to the guests in some cases.
4122 */
4123 switch (msrs_to_save[i]) {
4124 case MSR_IA32_BNDCFGS:
4125 if (!kvm_x86_ops->mpx_supported())
4126 continue;
4127 break;
4128 case MSR_TSC_AUX:
4129 if (!kvm_x86_ops->rdtscp_supported())
4130 continue;
4131 break;
4132 default:
4133 break;
4134 }
4135
4136 if (j < i)
4137 msrs_to_save[j] = msrs_to_save[i];
4138 j++;
4139 }
4140 num_msrs_to_save = j;
4141 }
4142
4143 static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
4144 const void *v)
4145 {
4146 int handled = 0;
4147 int n;
4148
4149 do {
4150 n = min(len, 8);
4151 if (!(vcpu->arch.apic &&
4152 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
4153 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
4154 break;
4155 handled += n;
4156 addr += n;
4157 len -= n;
4158 v += n;
4159 } while (len);
4160
4161 return handled;
4162 }
4163
4164 static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
4165 {
4166 int handled = 0;
4167 int n;
4168
4169 do {
4170 n = min(len, 8);
4171 if (!(vcpu->arch.apic &&
4172 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
4173 addr, n, v))
4174 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
4175 break;
4176 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
4177 handled += n;
4178 addr += n;
4179 len -= n;
4180 v += n;
4181 } while (len);
4182
4183 return handled;
4184 }
4185
4186 static void kvm_set_segment(struct kvm_vcpu *vcpu,
4187 struct kvm_segment *var, int seg)
4188 {
4189 kvm_x86_ops->set_segment(vcpu, var, seg);
4190 }
4191
4192 void kvm_get_segment(struct kvm_vcpu *vcpu,
4193 struct kvm_segment *var, int seg)
4194 {
4195 kvm_x86_ops->get_segment(vcpu, var, seg);
4196 }
4197
4198 gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
4199 struct x86_exception *exception)
4200 {
4201 gpa_t t_gpa;
4202
4203 BUG_ON(!mmu_is_nested(vcpu));
4204
4205 /* NPT walks are always user-walks */
4206 access |= PFERR_USER_MASK;
4207 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, exception);
4208
4209 return t_gpa;
4210 }
4211
4212 gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
4213 struct x86_exception *exception)
4214 {
4215 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4216 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4217 }
4218
4219 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
4220 struct x86_exception *exception)
4221 {
4222 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4223 access |= PFERR_FETCH_MASK;
4224 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4225 }
4226
4227 gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
4228 struct x86_exception *exception)
4229 {
4230 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4231 access |= PFERR_WRITE_MASK;
4232 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4233 }
4234
4235 /* uses this to access any guest's mapped memory without checking CPL */
4236 gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
4237 struct x86_exception *exception)
4238 {
4239 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
4240 }
4241
4242 static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
4243 struct kvm_vcpu *vcpu, u32 access,
4244 struct x86_exception *exception)
4245 {
4246 void *data = val;
4247 int r = X86EMUL_CONTINUE;
4248
4249 while (bytes) {
4250 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
4251 exception);
4252 unsigned offset = addr & (PAGE_SIZE-1);
4253 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
4254 int ret;
4255
4256 if (gpa == UNMAPPED_GVA)
4257 return X86EMUL_PROPAGATE_FAULT;
4258 ret = kvm_read_guest_page(vcpu->kvm, gpa >> PAGE_SHIFT, data,
4259 offset, toread);
4260 if (ret < 0) {
4261 r = X86EMUL_IO_NEEDED;
4262 goto out;
4263 }
4264
4265 bytes -= toread;
4266 data += toread;
4267 addr += toread;
4268 }
4269 out:
4270 return r;
4271 }
4272
4273 /* used for instruction fetching */
4274 static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
4275 gva_t addr, void *val, unsigned int bytes,
4276 struct x86_exception *exception)
4277 {
4278 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4279 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4280 unsigned offset;
4281 int ret;
4282
4283 /* Inline kvm_read_guest_virt_helper for speed. */
4284 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
4285 exception);
4286 if (unlikely(gpa == UNMAPPED_GVA))
4287 return X86EMUL_PROPAGATE_FAULT;
4288
4289 offset = addr & (PAGE_SIZE-1);
4290 if (WARN_ON(offset + bytes > PAGE_SIZE))
4291 bytes = (unsigned)PAGE_SIZE - offset;
4292 ret = kvm_read_guest_page(vcpu->kvm, gpa >> PAGE_SHIFT, val,
4293 offset, bytes);
4294 if (unlikely(ret < 0))
4295 return X86EMUL_IO_NEEDED;
4296
4297 return X86EMUL_CONTINUE;
4298 }
4299
4300 int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
4301 gva_t addr, void *val, unsigned int bytes,
4302 struct x86_exception *exception)
4303 {
4304 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4305 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4306
4307 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
4308 exception);
4309 }
4310 EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
4311
4312 static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4313 gva_t addr, void *val, unsigned int bytes,
4314 struct x86_exception *exception)
4315 {
4316 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4317 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
4318 }
4319
4320 int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4321 gva_t addr, void *val,
4322 unsigned int bytes,
4323 struct x86_exception *exception)
4324 {
4325 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4326 void *data = val;
4327 int r = X86EMUL_CONTINUE;
4328
4329 while (bytes) {
4330 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
4331 PFERR_WRITE_MASK,
4332 exception);
4333 unsigned offset = addr & (PAGE_SIZE-1);
4334 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
4335 int ret;
4336
4337 if (gpa == UNMAPPED_GVA)
4338 return X86EMUL_PROPAGATE_FAULT;
4339 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
4340 if (ret < 0) {
4341 r = X86EMUL_IO_NEEDED;
4342 goto out;
4343 }
4344
4345 bytes -= towrite;
4346 data += towrite;
4347 addr += towrite;
4348 }
4349 out:
4350 return r;
4351 }
4352 EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
4353
4354 static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4355 gpa_t *gpa, struct x86_exception *exception,
4356 bool write)
4357 {
4358 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
4359 | (write ? PFERR_WRITE_MASK : 0);
4360
4361 if (vcpu_match_mmio_gva(vcpu, gva)
4362 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
4363 vcpu->arch.access, access)) {
4364 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
4365 (gva & (PAGE_SIZE - 1));
4366 trace_vcpu_match_mmio(gva, *gpa, write, false);
4367 return 1;
4368 }
4369
4370 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4371
4372 if (*gpa == UNMAPPED_GVA)
4373 return -1;
4374
4375 /* For APIC access vmexit */
4376 if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4377 return 1;
4378
4379 if (vcpu_match_mmio_gpa(vcpu, *gpa)) {
4380 trace_vcpu_match_mmio(gva, *gpa, write, true);
4381 return 1;
4382 }
4383
4384 return 0;
4385 }
4386
4387 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
4388 const void *val, int bytes)
4389 {
4390 int ret;
4391
4392 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
4393 if (ret < 0)
4394 return 0;
4395 kvm_mmu_pte_write(vcpu, gpa, val, bytes);
4396 return 1;
4397 }
4398
4399 struct read_write_emulator_ops {
4400 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4401 int bytes);
4402 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4403 void *val, int bytes);
4404 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4405 int bytes, void *val);
4406 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4407 void *val, int bytes);
4408 bool write;
4409 };
4410
4411 static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4412 {
4413 if (vcpu->mmio_read_completed) {
4414 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
4415 vcpu->mmio_fragments[0].gpa, *(u64 *)val);
4416 vcpu->mmio_read_completed = 0;
4417 return 1;
4418 }
4419
4420 return 0;
4421 }
4422
4423 static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4424 void *val, int bytes)
4425 {
4426 return !kvm_read_guest(vcpu->kvm, gpa, val, bytes);
4427 }
4428
4429 static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4430 void *val, int bytes)
4431 {
4432 return emulator_write_phys(vcpu, gpa, val, bytes);
4433 }
4434
4435 static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4436 {
4437 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
4438 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4439 }
4440
4441 static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4442 void *val, int bytes)
4443 {
4444 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
4445 return X86EMUL_IO_NEEDED;
4446 }
4447
4448 static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4449 void *val, int bytes)
4450 {
4451 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4452
4453 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
4454 return X86EMUL_CONTINUE;
4455 }
4456
4457 static const struct read_write_emulator_ops read_emultor = {
4458 .read_write_prepare = read_prepare,
4459 .read_write_emulate = read_emulate,
4460 .read_write_mmio = vcpu_mmio_read,
4461 .read_write_exit_mmio = read_exit_mmio,
4462 };
4463
4464 static const struct read_write_emulator_ops write_emultor = {
4465 .read_write_emulate = write_emulate,
4466 .read_write_mmio = write_mmio,
4467 .read_write_exit_mmio = write_exit_mmio,
4468 .write = true,
4469 };
4470
4471 static int emulator_read_write_onepage(unsigned long addr, void *val,
4472 unsigned int bytes,
4473 struct x86_exception *exception,
4474 struct kvm_vcpu *vcpu,
4475 const struct read_write_emulator_ops *ops)
4476 {
4477 gpa_t gpa;
4478 int handled, ret;
4479 bool write = ops->write;
4480 struct kvm_mmio_fragment *frag;
4481
4482 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
4483
4484 if (ret < 0)
4485 return X86EMUL_PROPAGATE_FAULT;
4486
4487 /* For APIC access vmexit */
4488 if (ret)
4489 goto mmio;
4490
4491 if (ops->read_write_emulate(vcpu, gpa, val, bytes))
4492 return X86EMUL_CONTINUE;
4493
4494 mmio:
4495 /*
4496 * Is this MMIO handled locally?
4497 */
4498 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
4499 if (handled == bytes)
4500 return X86EMUL_CONTINUE;
4501
4502 gpa += handled;
4503 bytes -= handled;
4504 val += handled;
4505
4506 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
4507 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
4508 frag->gpa = gpa;
4509 frag->data = val;
4510 frag->len = bytes;
4511 return X86EMUL_CONTINUE;
4512 }
4513
4514 static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
4515 unsigned long addr,
4516 void *val, unsigned int bytes,
4517 struct x86_exception *exception,
4518 const struct read_write_emulator_ops *ops)
4519 {
4520 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4521 gpa_t gpa;
4522 int rc;
4523
4524 if (ops->read_write_prepare &&
4525 ops->read_write_prepare(vcpu, val, bytes))
4526 return X86EMUL_CONTINUE;
4527
4528 vcpu->mmio_nr_fragments = 0;
4529
4530 /* Crossing a page boundary? */
4531 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
4532 int now;
4533
4534 now = -addr & ~PAGE_MASK;
4535 rc = emulator_read_write_onepage(addr, val, now, exception,
4536 vcpu, ops);
4537
4538 if (rc != X86EMUL_CONTINUE)
4539 return rc;
4540 addr += now;
4541 if (ctxt->mode != X86EMUL_MODE_PROT64)
4542 addr = (u32)addr;
4543 val += now;
4544 bytes -= now;
4545 }
4546
4547 rc = emulator_read_write_onepage(addr, val, bytes, exception,
4548 vcpu, ops);
4549 if (rc != X86EMUL_CONTINUE)
4550 return rc;
4551
4552 if (!vcpu->mmio_nr_fragments)
4553 return rc;
4554
4555 gpa = vcpu->mmio_fragments[0].gpa;
4556
4557 vcpu->mmio_needed = 1;
4558 vcpu->mmio_cur_fragment = 0;
4559
4560 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
4561 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
4562 vcpu->run->exit_reason = KVM_EXIT_MMIO;
4563 vcpu->run->mmio.phys_addr = gpa;
4564
4565 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
4566 }
4567
4568 static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
4569 unsigned long addr,
4570 void *val,
4571 unsigned int bytes,
4572 struct x86_exception *exception)
4573 {
4574 return emulator_read_write(ctxt, addr, val, bytes,
4575 exception, &read_emultor);
4576 }
4577
4578 static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
4579 unsigned long addr,
4580 const void *val,
4581 unsigned int bytes,
4582 struct x86_exception *exception)
4583 {
4584 return emulator_read_write(ctxt, addr, (void *)val, bytes,
4585 exception, &write_emultor);
4586 }
4587
4588 #define CMPXCHG_TYPE(t, ptr, old, new) \
4589 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
4590
4591 #ifdef CONFIG_X86_64
4592 # define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
4593 #else
4594 # define CMPXCHG64(ptr, old, new) \
4595 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
4596 #endif
4597
4598 static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
4599 unsigned long addr,
4600 const void *old,
4601 const void *new,
4602 unsigned int bytes,
4603 struct x86_exception *exception)
4604 {
4605 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4606 gpa_t gpa;
4607 struct page *page;
4608 char *kaddr;
4609 bool exchanged;
4610
4611 /* guests cmpxchg8b have to be emulated atomically */
4612 if (bytes > 8 || (bytes & (bytes - 1)))
4613 goto emul_write;
4614
4615 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
4616
4617 if (gpa == UNMAPPED_GVA ||
4618 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4619 goto emul_write;
4620
4621 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
4622 goto emul_write;
4623
4624 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
4625 if (is_error_page(page))
4626 goto emul_write;
4627
4628 kaddr = kmap_atomic(page);
4629 kaddr += offset_in_page(gpa);
4630 switch (bytes) {
4631 case 1:
4632 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
4633 break;
4634 case 2:
4635 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
4636 break;
4637 case 4:
4638 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
4639 break;
4640 case 8:
4641 exchanged = CMPXCHG64(kaddr, old, new);
4642 break;
4643 default:
4644 BUG();
4645 }
4646 kunmap_atomic(kaddr);
4647 kvm_release_page_dirty(page);
4648
4649 if (!exchanged)
4650 return X86EMUL_CMPXCHG_FAILED;
4651
4652 mark_page_dirty(vcpu->kvm, gpa >> PAGE_SHIFT);
4653 kvm_mmu_pte_write(vcpu, gpa, new, bytes);
4654
4655 return X86EMUL_CONTINUE;
4656
4657 emul_write:
4658 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
4659
4660 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
4661 }
4662
4663 static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4664 {
4665 /* TODO: String I/O for in kernel device */
4666 int r;
4667
4668 if (vcpu->arch.pio.in)
4669 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
4670 vcpu->arch.pio.size, pd);
4671 else
4672 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
4673 vcpu->arch.pio.port, vcpu->arch.pio.size,
4674 pd);
4675 return r;
4676 }
4677
4678 static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
4679 unsigned short port, void *val,
4680 unsigned int count, bool in)
4681 {
4682 vcpu->arch.pio.port = port;
4683 vcpu->arch.pio.in = in;
4684 vcpu->arch.pio.count = count;
4685 vcpu->arch.pio.size = size;
4686
4687 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
4688 vcpu->arch.pio.count = 0;
4689 return 1;
4690 }
4691
4692 vcpu->run->exit_reason = KVM_EXIT_IO;
4693 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
4694 vcpu->run->io.size = size;
4695 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4696 vcpu->run->io.count = count;
4697 vcpu->run->io.port = port;
4698
4699 return 0;
4700 }
4701
4702 static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4703 int size, unsigned short port, void *val,
4704 unsigned int count)
4705 {
4706 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4707 int ret;
4708
4709 if (vcpu->arch.pio.count)
4710 goto data_avail;
4711
4712 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4713 if (ret) {
4714 data_avail:
4715 memcpy(val, vcpu->arch.pio_data, size * count);
4716 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
4717 vcpu->arch.pio.count = 0;
4718 return 1;
4719 }
4720
4721 return 0;
4722 }
4723
4724 static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4725 int size, unsigned short port,
4726 const void *val, unsigned int count)
4727 {
4728 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4729
4730 memcpy(vcpu->arch.pio_data, val, size * count);
4731 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
4732 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
4733 }
4734
4735 static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4736 {
4737 return kvm_x86_ops->get_segment_base(vcpu, seg);
4738 }
4739
4740 static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
4741 {
4742 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
4743 }
4744
4745 int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
4746 {
4747 if (!need_emulate_wbinvd(vcpu))
4748 return X86EMUL_CONTINUE;
4749
4750 if (kvm_x86_ops->has_wbinvd_exit()) {
4751 int cpu = get_cpu();
4752
4753 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
4754 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4755 wbinvd_ipi, NULL, 1);
4756 put_cpu();
4757 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
4758 } else
4759 wbinvd();
4760 return X86EMUL_CONTINUE;
4761 }
4762
4763 int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4764 {
4765 kvm_x86_ops->skip_emulated_instruction(vcpu);
4766 return kvm_emulate_wbinvd_noskip(vcpu);
4767 }
4768 EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4769
4770
4771
4772 static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4773 {
4774 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
4775 }
4776
4777 static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
4778 unsigned long *dest)
4779 {
4780 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
4781 }
4782
4783 static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
4784 unsigned long value)
4785 {
4786
4787 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
4788 }
4789
4790 static u64 mk_cr_64(u64 curr_cr, u32 new_val)
4791 {
4792 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
4793 }
4794
4795 static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
4796 {
4797 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4798 unsigned long value;
4799
4800 switch (cr) {
4801 case 0:
4802 value = kvm_read_cr0(vcpu);
4803 break;
4804 case 2:
4805 value = vcpu->arch.cr2;
4806 break;
4807 case 3:
4808 value = kvm_read_cr3(vcpu);
4809 break;
4810 case 4:
4811 value = kvm_read_cr4(vcpu);
4812 break;
4813 case 8:
4814 value = kvm_get_cr8(vcpu);
4815 break;
4816 default:
4817 kvm_err("%s: unexpected cr %u\n", __func__, cr);
4818 return 0;
4819 }
4820
4821 return value;
4822 }
4823
4824 static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
4825 {
4826 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4827 int res = 0;
4828
4829 switch (cr) {
4830 case 0:
4831 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
4832 break;
4833 case 2:
4834 vcpu->arch.cr2 = val;
4835 break;
4836 case 3:
4837 res = kvm_set_cr3(vcpu, val);
4838 break;
4839 case 4:
4840 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
4841 break;
4842 case 8:
4843 res = kvm_set_cr8(vcpu, val);
4844 break;
4845 default:
4846 kvm_err("%s: unexpected cr %u\n", __func__, cr);
4847 res = -1;
4848 }
4849
4850 return res;
4851 }
4852
4853 static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
4854 {
4855 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
4856 }
4857
4858 static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4859 {
4860 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
4861 }
4862
4863 static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4864 {
4865 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
4866 }
4867
4868 static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4869 {
4870 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
4871 }
4872
4873 static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4874 {
4875 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
4876 }
4877
4878 static unsigned long emulator_get_cached_segment_base(
4879 struct x86_emulate_ctxt *ctxt, int seg)
4880 {
4881 return get_segment_base(emul_to_vcpu(ctxt), seg);
4882 }
4883
4884 static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
4885 struct desc_struct *desc, u32 *base3,
4886 int seg)
4887 {
4888 struct kvm_segment var;
4889
4890 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
4891 *selector = var.selector;
4892
4893 if (var.unusable) {
4894 memset(desc, 0, sizeof(*desc));
4895 return false;
4896 }
4897
4898 if (var.g)
4899 var.limit >>= 12;
4900 set_desc_limit(desc, var.limit);
4901 set_desc_base(desc, (unsigned long)var.base);
4902 #ifdef CONFIG_X86_64
4903 if (base3)
4904 *base3 = var.base >> 32;
4905 #endif
4906 desc->type = var.type;
4907 desc->s = var.s;
4908 desc->dpl = var.dpl;
4909 desc->p = var.present;
4910 desc->avl = var.avl;
4911 desc->l = var.l;
4912 desc->d = var.db;
4913 desc->g = var.g;
4914
4915 return true;
4916 }
4917
4918 static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
4919 struct desc_struct *desc, u32 base3,
4920 int seg)
4921 {
4922 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4923 struct kvm_segment var;
4924
4925 var.selector = selector;
4926 var.base = get_desc_base(desc);
4927 #ifdef CONFIG_X86_64
4928 var.base |= ((u64)base3) << 32;
4929 #endif
4930 var.limit = get_desc_limit(desc);
4931 if (desc->g)
4932 var.limit = (var.limit << 12) | 0xfff;
4933 var.type = desc->type;
4934 var.dpl = desc->dpl;
4935 var.db = desc->d;
4936 var.s = desc->s;
4937 var.l = desc->l;
4938 var.g = desc->g;
4939 var.avl = desc->avl;
4940 var.present = desc->p;
4941 var.unusable = !var.present;
4942 var.padding = 0;
4943
4944 kvm_set_segment(vcpu, &var, seg);
4945 return;
4946 }
4947
4948 static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
4949 u32 msr_index, u64 *pdata)
4950 {
4951 return kvm_get_msr(emul_to_vcpu(ctxt), msr_index, pdata);
4952 }
4953
4954 static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
4955 u32 msr_index, u64 data)
4956 {
4957 struct msr_data msr;
4958
4959 msr.data = data;
4960 msr.index = msr_index;
4961 msr.host_initiated = false;
4962 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
4963 }
4964
4965 static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
4966 u32 pmc)
4967 {
4968 return kvm_pmu_check_pmc(emul_to_vcpu(ctxt), pmc);
4969 }
4970
4971 static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
4972 u32 pmc, u64 *pdata)
4973 {
4974 return kvm_pmu_read_pmc(emul_to_vcpu(ctxt), pmc, pdata);
4975 }
4976
4977 static void emulator_halt(struct x86_emulate_ctxt *ctxt)
4978 {
4979 emul_to_vcpu(ctxt)->arch.halt_request = 1;
4980 }
4981
4982 static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
4983 {
4984 preempt_disable();
4985 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
4986 /*
4987 * CR0.TS may reference the host fpu state, not the guest fpu state,
4988 * so it may be clear at this point.
4989 */
4990 clts();
4991 }
4992
4993 static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
4994 {
4995 preempt_enable();
4996 }
4997
4998 static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
4999 struct x86_instruction_info *info,
5000 enum x86_intercept_stage stage)
5001 {
5002 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
5003 }
5004
5005 static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
5006 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx)
5007 {
5008 kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx);
5009 }
5010
5011 static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
5012 {
5013 return kvm_register_read(emul_to_vcpu(ctxt), reg);
5014 }
5015
5016 static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
5017 {
5018 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
5019 }
5020
5021 static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
5022 {
5023 kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked);
5024 }
5025
5026 static const struct x86_emulate_ops emulate_ops = {
5027 .read_gpr = emulator_read_gpr,
5028 .write_gpr = emulator_write_gpr,
5029 .read_std = kvm_read_guest_virt_system,
5030 .write_std = kvm_write_guest_virt_system,
5031 .fetch = kvm_fetch_guest_virt,
5032 .read_emulated = emulator_read_emulated,
5033 .write_emulated = emulator_write_emulated,
5034 .cmpxchg_emulated = emulator_cmpxchg_emulated,
5035 .invlpg = emulator_invlpg,
5036 .pio_in_emulated = emulator_pio_in_emulated,
5037 .pio_out_emulated = emulator_pio_out_emulated,
5038 .get_segment = emulator_get_segment,
5039 .set_segment = emulator_set_segment,
5040 .get_cached_segment_base = emulator_get_cached_segment_base,
5041 .get_gdt = emulator_get_gdt,
5042 .get_idt = emulator_get_idt,
5043 .set_gdt = emulator_set_gdt,
5044 .set_idt = emulator_set_idt,
5045 .get_cr = emulator_get_cr,
5046 .set_cr = emulator_set_cr,
5047 .cpl = emulator_get_cpl,
5048 .get_dr = emulator_get_dr,
5049 .set_dr = emulator_set_dr,
5050 .set_msr = emulator_set_msr,
5051 .get_msr = emulator_get_msr,
5052 .check_pmc = emulator_check_pmc,
5053 .read_pmc = emulator_read_pmc,
5054 .halt = emulator_halt,
5055 .wbinvd = emulator_wbinvd,
5056 .fix_hypercall = emulator_fix_hypercall,
5057 .get_fpu = emulator_get_fpu,
5058 .put_fpu = emulator_put_fpu,
5059 .intercept = emulator_intercept,
5060 .get_cpuid = emulator_get_cpuid,
5061 .set_nmi_mask = emulator_set_nmi_mask,
5062 };
5063
5064 static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
5065 {
5066 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
5067 /*
5068 * an sti; sti; sequence only disable interrupts for the first
5069 * instruction. So, if the last instruction, be it emulated or
5070 * not, left the system with the INT_STI flag enabled, it
5071 * means that the last instruction is an sti. We should not
5072 * leave the flag on in this case. The same goes for mov ss
5073 */
5074 if (int_shadow & mask)
5075 mask = 0;
5076 if (unlikely(int_shadow || mask)) {
5077 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
5078 if (!mask)
5079 kvm_make_request(KVM_REQ_EVENT, vcpu);
5080 }
5081 }
5082
5083 static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
5084 {
5085 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5086 if (ctxt->exception.vector == PF_VECTOR)
5087 return kvm_propagate_fault(vcpu, &ctxt->exception);
5088
5089 if (ctxt->exception.error_code_valid)
5090 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
5091 ctxt->exception.error_code);
5092 else
5093 kvm_queue_exception(vcpu, ctxt->exception.vector);
5094 return false;
5095 }
5096
5097 static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
5098 {
5099 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5100 int cs_db, cs_l;
5101
5102 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
5103
5104 ctxt->eflags = kvm_get_rflags(vcpu);
5105 ctxt->eip = kvm_rip_read(vcpu);
5106 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
5107 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
5108 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
5109 cs_db ? X86EMUL_MODE_PROT32 :
5110 X86EMUL_MODE_PROT16;
5111 ctxt->guest_mode = is_guest_mode(vcpu);
5112
5113 init_decode_cache(ctxt);
5114 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
5115 }
5116
5117 int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
5118 {
5119 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5120 int ret;
5121
5122 init_emulate_ctxt(vcpu);
5123
5124 ctxt->op_bytes = 2;
5125 ctxt->ad_bytes = 2;
5126 ctxt->_eip = ctxt->eip + inc_eip;
5127 ret = emulate_int_real(ctxt, irq);
5128
5129 if (ret != X86EMUL_CONTINUE)
5130 return EMULATE_FAIL;
5131
5132 ctxt->eip = ctxt->_eip;
5133 kvm_rip_write(vcpu, ctxt->eip);
5134 kvm_set_rflags(vcpu, ctxt->eflags);
5135
5136 if (irq == NMI_VECTOR)
5137 vcpu->arch.nmi_pending = 0;
5138 else
5139 vcpu->arch.interrupt.pending = false;
5140
5141 return EMULATE_DONE;
5142 }
5143 EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
5144
5145 static int handle_emulation_failure(struct kvm_vcpu *vcpu)
5146 {
5147 int r = EMULATE_DONE;
5148
5149 ++vcpu->stat.insn_emulation_fail;
5150 trace_kvm_emulate_insn_failed(vcpu);
5151 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) {
5152 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5153 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5154 vcpu->run->internal.ndata = 0;
5155 r = EMULATE_FAIL;
5156 }
5157 kvm_queue_exception(vcpu, UD_VECTOR);
5158
5159 return r;
5160 }
5161
5162 static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
5163 bool write_fault_to_shadow_pgtable,
5164 int emulation_type)
5165 {
5166 gpa_t gpa = cr2;
5167 pfn_t pfn;
5168
5169 if (emulation_type & EMULTYPE_NO_REEXECUTE)
5170 return false;
5171
5172 if (!vcpu->arch.mmu.direct_map) {
5173 /*
5174 * Write permission should be allowed since only
5175 * write access need to be emulated.
5176 */
5177 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5178
5179 /*
5180 * If the mapping is invalid in guest, let cpu retry
5181 * it to generate fault.
5182 */
5183 if (gpa == UNMAPPED_GVA)
5184 return true;
5185 }
5186
5187 /*
5188 * Do not retry the unhandleable instruction if it faults on the
5189 * readonly host memory, otherwise it will goto a infinite loop:
5190 * retry instruction -> write #PF -> emulation fail -> retry
5191 * instruction -> ...
5192 */
5193 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
5194
5195 /*
5196 * If the instruction failed on the error pfn, it can not be fixed,
5197 * report the error to userspace.
5198 */
5199 if (is_error_noslot_pfn(pfn))
5200 return false;
5201
5202 kvm_release_pfn_clean(pfn);
5203
5204 /* The instructions are well-emulated on direct mmu. */
5205 if (vcpu->arch.mmu.direct_map) {
5206 unsigned int indirect_shadow_pages;
5207
5208 spin_lock(&vcpu->kvm->mmu_lock);
5209 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
5210 spin_unlock(&vcpu->kvm->mmu_lock);
5211
5212 if (indirect_shadow_pages)
5213 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5214
5215 return true;
5216 }
5217
5218 /*
5219 * if emulation was due to access to shadowed page table
5220 * and it failed try to unshadow page and re-enter the
5221 * guest to let CPU execute the instruction.
5222 */
5223 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5224
5225 /*
5226 * If the access faults on its page table, it can not
5227 * be fixed by unprotecting shadow page and it should
5228 * be reported to userspace.
5229 */
5230 return !write_fault_to_shadow_pgtable;
5231 }
5232
5233 static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
5234 unsigned long cr2, int emulation_type)
5235 {
5236 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5237 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
5238
5239 last_retry_eip = vcpu->arch.last_retry_eip;
5240 last_retry_addr = vcpu->arch.last_retry_addr;
5241
5242 /*
5243 * If the emulation is caused by #PF and it is non-page_table
5244 * writing instruction, it means the VM-EXIT is caused by shadow
5245 * page protected, we can zap the shadow page and retry this
5246 * instruction directly.
5247 *
5248 * Note: if the guest uses a non-page-table modifying instruction
5249 * on the PDE that points to the instruction, then we will unmap
5250 * the instruction and go to an infinite loop. So, we cache the
5251 * last retried eip and the last fault address, if we meet the eip
5252 * and the address again, we can break out of the potential infinite
5253 * loop.
5254 */
5255 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
5256
5257 if (!(emulation_type & EMULTYPE_RETRY))
5258 return false;
5259
5260 if (x86_page_table_writing_insn(ctxt))
5261 return false;
5262
5263 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
5264 return false;
5265
5266 vcpu->arch.last_retry_eip = ctxt->eip;
5267 vcpu->arch.last_retry_addr = cr2;
5268
5269 if (!vcpu->arch.mmu.direct_map)
5270 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5271
5272 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5273
5274 return true;
5275 }
5276
5277 static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
5278 static int complete_emulated_pio(struct kvm_vcpu *vcpu);
5279
5280 static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
5281 unsigned long *db)
5282 {
5283 u32 dr6 = 0;
5284 int i;
5285 u32 enable, rwlen;
5286
5287 enable = dr7;
5288 rwlen = dr7 >> 16;
5289 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
5290 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
5291 dr6 |= (1 << i);
5292 return dr6;
5293 }
5294
5295 static void kvm_vcpu_check_singlestep(struct kvm_vcpu *vcpu, unsigned long rflags, int *r)
5296 {
5297 struct kvm_run *kvm_run = vcpu->run;
5298
5299 /*
5300 * rflags is the old, "raw" value of the flags. The new value has
5301 * not been saved yet.
5302 *
5303 * This is correct even for TF set by the guest, because "the
5304 * processor will not generate this exception after the instruction
5305 * that sets the TF flag".
5306 */
5307 if (unlikely(rflags & X86_EFLAGS_TF)) {
5308 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
5309 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 |
5310 DR6_RTM;
5311 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
5312 kvm_run->debug.arch.exception = DB_VECTOR;
5313 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5314 *r = EMULATE_USER_EXIT;
5315 } else {
5316 vcpu->arch.emulate_ctxt.eflags &= ~X86_EFLAGS_TF;
5317 /*
5318 * "Certain debug exceptions may clear bit 0-3. The
5319 * remaining contents of the DR6 register are never
5320 * cleared by the processor".
5321 */
5322 vcpu->arch.dr6 &= ~15;
5323 vcpu->arch.dr6 |= DR6_BS | DR6_RTM;
5324 kvm_queue_exception(vcpu, DB_VECTOR);
5325 }
5326 }
5327 }
5328
5329 static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
5330 {
5331 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
5332 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
5333 struct kvm_run *kvm_run = vcpu->run;
5334 unsigned long eip = kvm_get_linear_rip(vcpu);
5335 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
5336 vcpu->arch.guest_debug_dr7,
5337 vcpu->arch.eff_db);
5338
5339 if (dr6 != 0) {
5340 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
5341 kvm_run->debug.arch.pc = eip;
5342 kvm_run->debug.arch.exception = DB_VECTOR;
5343 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5344 *r = EMULATE_USER_EXIT;
5345 return true;
5346 }
5347 }
5348
5349 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
5350 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
5351 unsigned long eip = kvm_get_linear_rip(vcpu);
5352 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
5353 vcpu->arch.dr7,
5354 vcpu->arch.db);
5355
5356 if (dr6 != 0) {
5357 vcpu->arch.dr6 &= ~15;
5358 vcpu->arch.dr6 |= dr6 | DR6_RTM;
5359 kvm_queue_exception(vcpu, DB_VECTOR);
5360 *r = EMULATE_DONE;
5361 return true;
5362 }
5363 }
5364
5365 return false;
5366 }
5367
5368 int x86_emulate_instruction(struct kvm_vcpu *vcpu,
5369 unsigned long cr2,
5370 int emulation_type,
5371 void *insn,
5372 int insn_len)
5373 {
5374 int r;
5375 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5376 bool writeback = true;
5377 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
5378
5379 /*
5380 * Clear write_fault_to_shadow_pgtable here to ensure it is
5381 * never reused.
5382 */
5383 vcpu->arch.write_fault_to_shadow_pgtable = false;
5384 kvm_clear_exception_queue(vcpu);
5385
5386 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
5387 init_emulate_ctxt(vcpu);
5388
5389 /*
5390 * We will reenter on the same instruction since
5391 * we do not set complete_userspace_io. This does not
5392 * handle watchpoints yet, those would be handled in
5393 * the emulate_ops.
5394 */
5395 if (kvm_vcpu_check_breakpoint(vcpu, &r))
5396 return r;
5397
5398 ctxt->interruptibility = 0;
5399 ctxt->have_exception = false;
5400 ctxt->exception.vector = -1;
5401 ctxt->perm_ok = false;
5402
5403 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
5404
5405 r = x86_decode_insn(ctxt, insn, insn_len);
5406
5407 trace_kvm_emulate_insn_start(vcpu);
5408 ++vcpu->stat.insn_emulation;
5409 if (r != EMULATION_OK) {
5410 if (emulation_type & EMULTYPE_TRAP_UD)
5411 return EMULATE_FAIL;
5412 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5413 emulation_type))
5414 return EMULATE_DONE;
5415 if (emulation_type & EMULTYPE_SKIP)
5416 return EMULATE_FAIL;
5417 return handle_emulation_failure(vcpu);
5418 }
5419 }
5420
5421 if (emulation_type & EMULTYPE_SKIP) {
5422 kvm_rip_write(vcpu, ctxt->_eip);
5423 if (ctxt->eflags & X86_EFLAGS_RF)
5424 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
5425 return EMULATE_DONE;
5426 }
5427
5428 if (retry_instruction(ctxt, cr2, emulation_type))
5429 return EMULATE_DONE;
5430
5431 /* this is needed for vmware backdoor interface to work since it
5432 changes registers values during IO operation */
5433 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
5434 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
5435 emulator_invalidate_register_cache(ctxt);
5436 }
5437
5438 restart:
5439 r = x86_emulate_insn(ctxt);
5440
5441 if (r == EMULATION_INTERCEPTED)
5442 return EMULATE_DONE;
5443
5444 if (r == EMULATION_FAILED) {
5445 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5446 emulation_type))
5447 return EMULATE_DONE;
5448
5449 return handle_emulation_failure(vcpu);
5450 }
5451
5452 if (ctxt->have_exception) {
5453 r = EMULATE_DONE;
5454 if (inject_emulated_exception(vcpu))
5455 return r;
5456 } else if (vcpu->arch.pio.count) {
5457 if (!vcpu->arch.pio.in) {
5458 /* FIXME: return into emulator if single-stepping. */
5459 vcpu->arch.pio.count = 0;
5460 } else {
5461 writeback = false;
5462 vcpu->arch.complete_userspace_io = complete_emulated_pio;
5463 }
5464 r = EMULATE_USER_EXIT;
5465 } else if (vcpu->mmio_needed) {
5466 if (!vcpu->mmio_is_write)
5467 writeback = false;
5468 r = EMULATE_USER_EXIT;
5469 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
5470 } else if (r == EMULATION_RESTART)
5471 goto restart;
5472 else
5473 r = EMULATE_DONE;
5474
5475 if (writeback) {
5476 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
5477 toggle_interruptibility(vcpu, ctxt->interruptibility);
5478 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
5479 kvm_rip_write(vcpu, ctxt->eip);
5480 if (r == EMULATE_DONE)
5481 kvm_vcpu_check_singlestep(vcpu, rflags, &r);
5482 if (!ctxt->have_exception ||
5483 exception_type(ctxt->exception.vector) == EXCPT_TRAP)
5484 __kvm_set_rflags(vcpu, ctxt->eflags);
5485
5486 /*
5487 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
5488 * do nothing, and it will be requested again as soon as
5489 * the shadow expires. But we still need to check here,
5490 * because POPF has no interrupt shadow.
5491 */
5492 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
5493 kvm_make_request(KVM_REQ_EVENT, vcpu);
5494 } else
5495 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
5496
5497 return r;
5498 }
5499 EXPORT_SYMBOL_GPL(x86_emulate_instruction);
5500
5501 int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
5502 {
5503 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
5504 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
5505 size, port, &val, 1);
5506 /* do not return to emulator after return from userspace */
5507 vcpu->arch.pio.count = 0;
5508 return ret;
5509 }
5510 EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
5511
5512 static void tsc_bad(void *info)
5513 {
5514 __this_cpu_write(cpu_tsc_khz, 0);
5515 }
5516
5517 static void tsc_khz_changed(void *data)
5518 {
5519 struct cpufreq_freqs *freq = data;
5520 unsigned long khz = 0;
5521
5522 if (data)
5523 khz = freq->new;
5524 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5525 khz = cpufreq_quick_get(raw_smp_processor_id());
5526 if (!khz)
5527 khz = tsc_khz;
5528 __this_cpu_write(cpu_tsc_khz, khz);
5529 }
5530
5531 static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
5532 void *data)
5533 {
5534 struct cpufreq_freqs *freq = data;
5535 struct kvm *kvm;
5536 struct kvm_vcpu *vcpu;
5537 int i, send_ipi = 0;
5538
5539 /*
5540 * We allow guests to temporarily run on slowing clocks,
5541 * provided we notify them after, or to run on accelerating
5542 * clocks, provided we notify them before. Thus time never
5543 * goes backwards.
5544 *
5545 * However, we have a problem. We can't atomically update
5546 * the frequency of a given CPU from this function; it is
5547 * merely a notifier, which can be called from any CPU.
5548 * Changing the TSC frequency at arbitrary points in time
5549 * requires a recomputation of local variables related to
5550 * the TSC for each VCPU. We must flag these local variables
5551 * to be updated and be sure the update takes place with the
5552 * new frequency before any guests proceed.
5553 *
5554 * Unfortunately, the combination of hotplug CPU and frequency
5555 * change creates an intractable locking scenario; the order
5556 * of when these callouts happen is undefined with respect to
5557 * CPU hotplug, and they can race with each other. As such,
5558 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
5559 * undefined; you can actually have a CPU frequency change take
5560 * place in between the computation of X and the setting of the
5561 * variable. To protect against this problem, all updates of
5562 * the per_cpu tsc_khz variable are done in an interrupt
5563 * protected IPI, and all callers wishing to update the value
5564 * must wait for a synchronous IPI to complete (which is trivial
5565 * if the caller is on the CPU already). This establishes the
5566 * necessary total order on variable updates.
5567 *
5568 * Note that because a guest time update may take place
5569 * anytime after the setting of the VCPU's request bit, the
5570 * correct TSC value must be set before the request. However,
5571 * to ensure the update actually makes it to any guest which
5572 * starts running in hardware virtualization between the set
5573 * and the acquisition of the spinlock, we must also ping the
5574 * CPU after setting the request bit.
5575 *
5576 */
5577
5578 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
5579 return 0;
5580 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
5581 return 0;
5582
5583 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
5584
5585 spin_lock(&kvm_lock);
5586 list_for_each_entry(kvm, &vm_list, vm_list) {
5587 kvm_for_each_vcpu(i, vcpu, kvm) {
5588 if (vcpu->cpu != freq->cpu)
5589 continue;
5590 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
5591 if (vcpu->cpu != smp_processor_id())
5592 send_ipi = 1;
5593 }
5594 }
5595 spin_unlock(&kvm_lock);
5596
5597 if (freq->old < freq->new && send_ipi) {
5598 /*
5599 * We upscale the frequency. Must make the guest
5600 * doesn't see old kvmclock values while running with
5601 * the new frequency, otherwise we risk the guest sees
5602 * time go backwards.
5603 *
5604 * In case we update the frequency for another cpu
5605 * (which might be in guest context) send an interrupt
5606 * to kick the cpu out of guest context. Next time
5607 * guest context is entered kvmclock will be updated,
5608 * so the guest will not see stale values.
5609 */
5610 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
5611 }
5612 return 0;
5613 }
5614
5615 static struct notifier_block kvmclock_cpufreq_notifier_block = {
5616 .notifier_call = kvmclock_cpufreq_notifier
5617 };
5618
5619 static int kvmclock_cpu_notifier(struct notifier_block *nfb,
5620 unsigned long action, void *hcpu)
5621 {
5622 unsigned int cpu = (unsigned long)hcpu;
5623
5624 switch (action) {
5625 case CPU_ONLINE:
5626 case CPU_DOWN_FAILED:
5627 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
5628 break;
5629 case CPU_DOWN_PREPARE:
5630 smp_call_function_single(cpu, tsc_bad, NULL, 1);
5631 break;
5632 }
5633 return NOTIFY_OK;
5634 }
5635
5636 static struct notifier_block kvmclock_cpu_notifier_block = {
5637 .notifier_call = kvmclock_cpu_notifier,
5638 .priority = -INT_MAX
5639 };
5640
5641 static void kvm_timer_init(void)
5642 {
5643 int cpu;
5644
5645 max_tsc_khz = tsc_khz;
5646
5647 cpu_notifier_register_begin();
5648 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
5649 #ifdef CONFIG_CPU_FREQ
5650 struct cpufreq_policy policy;
5651 memset(&policy, 0, sizeof(policy));
5652 cpu = get_cpu();
5653 cpufreq_get_policy(&policy, cpu);
5654 if (policy.cpuinfo.max_freq)
5655 max_tsc_khz = policy.cpuinfo.max_freq;
5656 put_cpu();
5657 #endif
5658 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
5659 CPUFREQ_TRANSITION_NOTIFIER);
5660 }
5661 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
5662 for_each_online_cpu(cpu)
5663 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
5664
5665 __register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
5666 cpu_notifier_register_done();
5667
5668 }
5669
5670 static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
5671
5672 int kvm_is_in_guest(void)
5673 {
5674 return __this_cpu_read(current_vcpu) != NULL;
5675 }
5676
5677 static int kvm_is_user_mode(void)
5678 {
5679 int user_mode = 3;
5680
5681 if (__this_cpu_read(current_vcpu))
5682 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
5683
5684 return user_mode != 0;
5685 }
5686
5687 static unsigned long kvm_get_guest_ip(void)
5688 {
5689 unsigned long ip = 0;
5690
5691 if (__this_cpu_read(current_vcpu))
5692 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
5693
5694 return ip;
5695 }
5696
5697 static struct perf_guest_info_callbacks kvm_guest_cbs = {
5698 .is_in_guest = kvm_is_in_guest,
5699 .is_user_mode = kvm_is_user_mode,
5700 .get_guest_ip = kvm_get_guest_ip,
5701 };
5702
5703 void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
5704 {
5705 __this_cpu_write(current_vcpu, vcpu);
5706 }
5707 EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
5708
5709 void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
5710 {
5711 __this_cpu_write(current_vcpu, NULL);
5712 }
5713 EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
5714
5715 static void kvm_set_mmio_spte_mask(void)
5716 {
5717 u64 mask;
5718 int maxphyaddr = boot_cpu_data.x86_phys_bits;
5719
5720 /*
5721 * Set the reserved bits and the present bit of an paging-structure
5722 * entry to generate page fault with PFER.RSV = 1.
5723 */
5724 /* Mask the reserved physical address bits. */
5725 mask = rsvd_bits(maxphyaddr, 51);
5726
5727 /* Bit 62 is always reserved for 32bit host. */
5728 mask |= 0x3ull << 62;
5729
5730 /* Set the present bit. */
5731 mask |= 1ull;
5732
5733 #ifdef CONFIG_X86_64
5734 /*
5735 * If reserved bit is not supported, clear the present bit to disable
5736 * mmio page fault.
5737 */
5738 if (maxphyaddr == 52)
5739 mask &= ~1ull;
5740 #endif
5741
5742 kvm_mmu_set_mmio_spte_mask(mask);
5743 }
5744
5745 #ifdef CONFIG_X86_64
5746 static void pvclock_gtod_update_fn(struct work_struct *work)
5747 {
5748 struct kvm *kvm;
5749
5750 struct kvm_vcpu *vcpu;
5751 int i;
5752
5753 spin_lock(&kvm_lock);
5754 list_for_each_entry(kvm, &vm_list, vm_list)
5755 kvm_for_each_vcpu(i, vcpu, kvm)
5756 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
5757 atomic_set(&kvm_guest_has_master_clock, 0);
5758 spin_unlock(&kvm_lock);
5759 }
5760
5761 static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
5762
5763 /*
5764 * Notification about pvclock gtod data update.
5765 */
5766 static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
5767 void *priv)
5768 {
5769 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
5770 struct timekeeper *tk = priv;
5771
5772 update_pvclock_gtod(tk);
5773
5774 /* disable master clock if host does not trust, or does not
5775 * use, TSC clocksource
5776 */
5777 if (gtod->clock.vclock_mode != VCLOCK_TSC &&
5778 atomic_read(&kvm_guest_has_master_clock) != 0)
5779 queue_work(system_long_wq, &pvclock_gtod_work);
5780
5781 return 0;
5782 }
5783
5784 static struct notifier_block pvclock_gtod_notifier = {
5785 .notifier_call = pvclock_gtod_notify,
5786 };
5787 #endif
5788
5789 int kvm_arch_init(void *opaque)
5790 {
5791 int r;
5792 struct kvm_x86_ops *ops = opaque;
5793
5794 if (kvm_x86_ops) {
5795 printk(KERN_ERR "kvm: already loaded the other module\n");
5796 r = -EEXIST;
5797 goto out;
5798 }
5799
5800 if (!ops->cpu_has_kvm_support()) {
5801 printk(KERN_ERR "kvm: no hardware support\n");
5802 r = -EOPNOTSUPP;
5803 goto out;
5804 }
5805 if (ops->disabled_by_bios()) {
5806 printk(KERN_ERR "kvm: disabled by bios\n");
5807 r = -EOPNOTSUPP;
5808 goto out;
5809 }
5810
5811 r = -ENOMEM;
5812 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
5813 if (!shared_msrs) {
5814 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
5815 goto out;
5816 }
5817
5818 r = kvm_mmu_module_init();
5819 if (r)
5820 goto out_free_percpu;
5821
5822 kvm_set_mmio_spte_mask();
5823
5824 kvm_x86_ops = ops;
5825
5826 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
5827 PT_DIRTY_MASK, PT64_NX_MASK, 0);
5828
5829 kvm_timer_init();
5830
5831 perf_register_guest_info_callbacks(&kvm_guest_cbs);
5832
5833 if (cpu_has_xsave)
5834 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
5835
5836 kvm_lapic_init();
5837 #ifdef CONFIG_X86_64
5838 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
5839 #endif
5840
5841 return 0;
5842
5843 out_free_percpu:
5844 free_percpu(shared_msrs);
5845 out:
5846 return r;
5847 }
5848
5849 void kvm_arch_exit(void)
5850 {
5851 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
5852
5853 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5854 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
5855 CPUFREQ_TRANSITION_NOTIFIER);
5856 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
5857 #ifdef CONFIG_X86_64
5858 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
5859 #endif
5860 kvm_x86_ops = NULL;
5861 kvm_mmu_module_exit();
5862 free_percpu(shared_msrs);
5863 }
5864
5865 int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
5866 {
5867 ++vcpu->stat.halt_exits;
5868 if (irqchip_in_kernel(vcpu->kvm)) {
5869 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
5870 return 1;
5871 } else {
5872 vcpu->run->exit_reason = KVM_EXIT_HLT;
5873 return 0;
5874 }
5875 }
5876 EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
5877
5878 int kvm_emulate_halt(struct kvm_vcpu *vcpu)
5879 {
5880 kvm_x86_ops->skip_emulated_instruction(vcpu);
5881 return kvm_vcpu_halt(vcpu);
5882 }
5883 EXPORT_SYMBOL_GPL(kvm_emulate_halt);
5884
5885 int kvm_hv_hypercall(struct kvm_vcpu *vcpu)
5886 {
5887 u64 param, ingpa, outgpa, ret;
5888 uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0;
5889 bool fast, longmode;
5890
5891 /*
5892 * hypercall generates UD from non zero cpl and real mode
5893 * per HYPER-V spec
5894 */
5895 if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) {
5896 kvm_queue_exception(vcpu, UD_VECTOR);
5897 return 0;
5898 }
5899
5900 longmode = is_64_bit_mode(vcpu);
5901
5902 if (!longmode) {
5903 param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) |
5904 (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff);
5905 ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) |
5906 (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff);
5907 outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) |
5908 (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff);
5909 }
5910 #ifdef CONFIG_X86_64
5911 else {
5912 param = kvm_register_read(vcpu, VCPU_REGS_RCX);
5913 ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX);
5914 outgpa = kvm_register_read(vcpu, VCPU_REGS_R8);
5915 }
5916 #endif
5917
5918 code = param & 0xffff;
5919 fast = (param >> 16) & 0x1;
5920 rep_cnt = (param >> 32) & 0xfff;
5921 rep_idx = (param >> 48) & 0xfff;
5922
5923 trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa);
5924
5925 switch (code) {
5926 case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT:
5927 kvm_vcpu_on_spin(vcpu);
5928 break;
5929 default:
5930 res = HV_STATUS_INVALID_HYPERCALL_CODE;
5931 break;
5932 }
5933
5934 ret = res | (((u64)rep_done & 0xfff) << 32);
5935 if (longmode) {
5936 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
5937 } else {
5938 kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32);
5939 kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff);
5940 }
5941
5942 return 1;
5943 }
5944
5945 /*
5946 * kvm_pv_kick_cpu_op: Kick a vcpu.
5947 *
5948 * @apicid - apicid of vcpu to be kicked.
5949 */
5950 static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
5951 {
5952 struct kvm_lapic_irq lapic_irq;
5953
5954 lapic_irq.shorthand = 0;
5955 lapic_irq.dest_mode = 0;
5956 lapic_irq.dest_id = apicid;
5957
5958 lapic_irq.delivery_mode = APIC_DM_REMRD;
5959 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
5960 }
5961
5962 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
5963 {
5964 unsigned long nr, a0, a1, a2, a3, ret;
5965 int op_64_bit, r = 1;
5966
5967 kvm_x86_ops->skip_emulated_instruction(vcpu);
5968
5969 if (kvm_hv_hypercall_enabled(vcpu->kvm))
5970 return kvm_hv_hypercall(vcpu);
5971
5972 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
5973 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
5974 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
5975 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
5976 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
5977
5978 trace_kvm_hypercall(nr, a0, a1, a2, a3);
5979
5980 op_64_bit = is_64_bit_mode(vcpu);
5981 if (!op_64_bit) {
5982 nr &= 0xFFFFFFFF;
5983 a0 &= 0xFFFFFFFF;
5984 a1 &= 0xFFFFFFFF;
5985 a2 &= 0xFFFFFFFF;
5986 a3 &= 0xFFFFFFFF;
5987 }
5988
5989 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
5990 ret = -KVM_EPERM;
5991 goto out;
5992 }
5993
5994 switch (nr) {
5995 case KVM_HC_VAPIC_POLL_IRQ:
5996 ret = 0;
5997 break;
5998 case KVM_HC_KICK_CPU:
5999 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
6000 ret = 0;
6001 break;
6002 default:
6003 ret = -KVM_ENOSYS;
6004 break;
6005 }
6006 out:
6007 if (!op_64_bit)
6008 ret = (u32)ret;
6009 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
6010 ++vcpu->stat.hypercalls;
6011 return r;
6012 }
6013 EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
6014
6015 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
6016 {
6017 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6018 char instruction[3];
6019 unsigned long rip = kvm_rip_read(vcpu);
6020
6021 kvm_x86_ops->patch_hypercall(vcpu, instruction);
6022
6023 return emulator_write_emulated(ctxt, rip, instruction, 3, NULL);
6024 }
6025
6026 /*
6027 * Check if userspace requested an interrupt window, and that the
6028 * interrupt window is open.
6029 *
6030 * No need to exit to userspace if we already have an interrupt queued.
6031 */
6032 static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
6033 {
6034 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
6035 vcpu->run->request_interrupt_window &&
6036 kvm_arch_interrupt_allowed(vcpu));
6037 }
6038
6039 static void post_kvm_run_save(struct kvm_vcpu *vcpu)
6040 {
6041 struct kvm_run *kvm_run = vcpu->run;
6042
6043 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
6044 kvm_run->cr8 = kvm_get_cr8(vcpu);
6045 kvm_run->apic_base = kvm_get_apic_base(vcpu);
6046 if (irqchip_in_kernel(vcpu->kvm))
6047 kvm_run->ready_for_interrupt_injection = 1;
6048 else
6049 kvm_run->ready_for_interrupt_injection =
6050 kvm_arch_interrupt_allowed(vcpu) &&
6051 !kvm_cpu_has_interrupt(vcpu) &&
6052 !kvm_event_needs_reinjection(vcpu);
6053 }
6054
6055 static void update_cr8_intercept(struct kvm_vcpu *vcpu)
6056 {
6057 int max_irr, tpr;
6058
6059 if (!kvm_x86_ops->update_cr8_intercept)
6060 return;
6061
6062 if (!vcpu->arch.apic)
6063 return;
6064
6065 if (!vcpu->arch.apic->vapic_addr)
6066 max_irr = kvm_lapic_find_highest_irr(vcpu);
6067 else
6068 max_irr = -1;
6069
6070 if (max_irr != -1)
6071 max_irr >>= 4;
6072
6073 tpr = kvm_lapic_get_cr8(vcpu);
6074
6075 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
6076 }
6077
6078 static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
6079 {
6080 int r;
6081
6082 /* try to reinject previous events if any */
6083 if (vcpu->arch.exception.pending) {
6084 trace_kvm_inj_exception(vcpu->arch.exception.nr,
6085 vcpu->arch.exception.has_error_code,
6086 vcpu->arch.exception.error_code);
6087
6088 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
6089 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
6090 X86_EFLAGS_RF);
6091
6092 if (vcpu->arch.exception.nr == DB_VECTOR &&
6093 (vcpu->arch.dr7 & DR7_GD)) {
6094 vcpu->arch.dr7 &= ~DR7_GD;
6095 kvm_update_dr7(vcpu);
6096 }
6097
6098 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
6099 vcpu->arch.exception.has_error_code,
6100 vcpu->arch.exception.error_code,
6101 vcpu->arch.exception.reinject);
6102 return 0;
6103 }
6104
6105 if (vcpu->arch.nmi_injected) {
6106 kvm_x86_ops->set_nmi(vcpu);
6107 return 0;
6108 }
6109
6110 if (vcpu->arch.interrupt.pending) {
6111 kvm_x86_ops->set_irq(vcpu);
6112 return 0;
6113 }
6114
6115 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6116 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6117 if (r != 0)
6118 return r;
6119 }
6120
6121 /* try to inject new event if pending */
6122 if (vcpu->arch.nmi_pending && kvm_x86_ops->nmi_allowed(vcpu)) {
6123 --vcpu->arch.nmi_pending;
6124 vcpu->arch.nmi_injected = true;
6125 kvm_x86_ops->set_nmi(vcpu);
6126 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
6127 /*
6128 * Because interrupts can be injected asynchronously, we are
6129 * calling check_nested_events again here to avoid a race condition.
6130 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
6131 * proposal and current concerns. Perhaps we should be setting
6132 * KVM_REQ_EVENT only on certain events and not unconditionally?
6133 */
6134 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6135 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6136 if (r != 0)
6137 return r;
6138 }
6139 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
6140 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
6141 false);
6142 kvm_x86_ops->set_irq(vcpu);
6143 }
6144 }
6145 return 0;
6146 }
6147
6148 static void process_nmi(struct kvm_vcpu *vcpu)
6149 {
6150 unsigned limit = 2;
6151
6152 /*
6153 * x86 is limited to one NMI running, and one NMI pending after it.
6154 * If an NMI is already in progress, limit further NMIs to just one.
6155 * Otherwise, allow two (and we'll inject the first one immediately).
6156 */
6157 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
6158 limit = 1;
6159
6160 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
6161 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
6162 kvm_make_request(KVM_REQ_EVENT, vcpu);
6163 }
6164
6165 static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
6166 {
6167 u64 eoi_exit_bitmap[4];
6168 u32 tmr[8];
6169
6170 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
6171 return;
6172
6173 memset(eoi_exit_bitmap, 0, 32);
6174 memset(tmr, 0, 32);
6175
6176 kvm_ioapic_scan_entry(vcpu, eoi_exit_bitmap, tmr);
6177 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
6178 kvm_apic_update_tmr(vcpu, tmr);
6179 }
6180
6181 static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu)
6182 {
6183 ++vcpu->stat.tlb_flush;
6184 kvm_x86_ops->tlb_flush(vcpu);
6185 }
6186
6187 void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
6188 {
6189 struct page *page = NULL;
6190
6191 if (!irqchip_in_kernel(vcpu->kvm))
6192 return;
6193
6194 if (!kvm_x86_ops->set_apic_access_page_addr)
6195 return;
6196
6197 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
6198 if (is_error_page(page))
6199 return;
6200 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page));
6201
6202 /*
6203 * Do not pin apic access page in memory, the MMU notifier
6204 * will call us again if it is migrated or swapped out.
6205 */
6206 put_page(page);
6207 }
6208 EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page);
6209
6210 void kvm_arch_mmu_notifier_invalidate_page(struct kvm *kvm,
6211 unsigned long address)
6212 {
6213 /*
6214 * The physical address of apic access page is stored in the VMCS.
6215 * Update it when it becomes invalid.
6216 */
6217 if (address == gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT))
6218 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
6219 }
6220
6221 /*
6222 * Returns 1 to let vcpu_run() continue the guest execution loop without
6223 * exiting to the userspace. Otherwise, the value will be returned to the
6224 * userspace.
6225 */
6226 static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
6227 {
6228 int r;
6229 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
6230 vcpu->run->request_interrupt_window;
6231 bool req_immediate_exit = false;
6232
6233 if (vcpu->requests) {
6234 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
6235 kvm_mmu_unload(vcpu);
6236 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
6237 __kvm_migrate_timers(vcpu);
6238 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
6239 kvm_gen_update_masterclock(vcpu->kvm);
6240 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
6241 kvm_gen_kvmclock_update(vcpu);
6242 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
6243 r = kvm_guest_time_update(vcpu);
6244 if (unlikely(r))
6245 goto out;
6246 }
6247 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
6248 kvm_mmu_sync_roots(vcpu);
6249 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
6250 kvm_vcpu_flush_tlb(vcpu);
6251 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
6252 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
6253 r = 0;
6254 goto out;
6255 }
6256 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
6257 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
6258 r = 0;
6259 goto out;
6260 }
6261 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
6262 vcpu->fpu_active = 0;
6263 kvm_x86_ops->fpu_deactivate(vcpu);
6264 }
6265 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
6266 /* Page is swapped out. Do synthetic halt */
6267 vcpu->arch.apf.halted = true;
6268 r = 1;
6269 goto out;
6270 }
6271 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
6272 record_steal_time(vcpu);
6273 if (kvm_check_request(KVM_REQ_NMI, vcpu))
6274 process_nmi(vcpu);
6275 if (kvm_check_request(KVM_REQ_PMU, vcpu))
6276 kvm_handle_pmu_event(vcpu);
6277 if (kvm_check_request(KVM_REQ_PMI, vcpu))
6278 kvm_deliver_pmi(vcpu);
6279 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
6280 vcpu_scan_ioapic(vcpu);
6281 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
6282 kvm_vcpu_reload_apic_access_page(vcpu);
6283 }
6284
6285 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
6286 kvm_apic_accept_events(vcpu);
6287 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
6288 r = 1;
6289 goto out;
6290 }
6291
6292 if (inject_pending_event(vcpu, req_int_win) != 0)
6293 req_immediate_exit = true;
6294 /* enable NMI/IRQ window open exits if needed */
6295 else {
6296 if (vcpu->arch.nmi_pending)
6297 kvm_x86_ops->enable_nmi_window(vcpu);
6298 if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
6299 kvm_x86_ops->enable_irq_window(vcpu);
6300 }
6301
6302 if (kvm_lapic_enabled(vcpu)) {
6303 /*
6304 * Update architecture specific hints for APIC
6305 * virtual interrupt delivery.
6306 */
6307 if (kvm_x86_ops->hwapic_irr_update)
6308 kvm_x86_ops->hwapic_irr_update(vcpu,
6309 kvm_lapic_find_highest_irr(vcpu));
6310 update_cr8_intercept(vcpu);
6311 kvm_lapic_sync_to_vapic(vcpu);
6312 }
6313 }
6314
6315 r = kvm_mmu_reload(vcpu);
6316 if (unlikely(r)) {
6317 goto cancel_injection;
6318 }
6319
6320 preempt_disable();
6321
6322 kvm_x86_ops->prepare_guest_switch(vcpu);
6323 if (vcpu->fpu_active)
6324 kvm_load_guest_fpu(vcpu);
6325 vcpu->mode = IN_GUEST_MODE;
6326
6327 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6328
6329 /* We should set ->mode before check ->requests,
6330 * see the comment in make_all_cpus_request.
6331 */
6332 smp_mb__after_srcu_read_unlock();
6333
6334 local_irq_disable();
6335
6336 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
6337 || need_resched() || signal_pending(current)) {
6338 vcpu->mode = OUTSIDE_GUEST_MODE;
6339 smp_wmb();
6340 local_irq_enable();
6341 preempt_enable();
6342 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6343 r = 1;
6344 goto cancel_injection;
6345 }
6346
6347 kvm_load_guest_xcr0(vcpu);
6348
6349 if (req_immediate_exit)
6350 smp_send_reschedule(vcpu->cpu);
6351
6352 kvm_guest_enter();
6353
6354 if (unlikely(vcpu->arch.switch_db_regs)) {
6355 set_debugreg(0, 7);
6356 set_debugreg(vcpu->arch.eff_db[0], 0);
6357 set_debugreg(vcpu->arch.eff_db[1], 1);
6358 set_debugreg(vcpu->arch.eff_db[2], 2);
6359 set_debugreg(vcpu->arch.eff_db[3], 3);
6360 set_debugreg(vcpu->arch.dr6, 6);
6361 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
6362 }
6363
6364 trace_kvm_entry(vcpu->vcpu_id);
6365 wait_lapic_expire(vcpu);
6366 kvm_x86_ops->run(vcpu);
6367
6368 /*
6369 * Do this here before restoring debug registers on the host. And
6370 * since we do this before handling the vmexit, a DR access vmexit
6371 * can (a) read the correct value of the debug registers, (b) set
6372 * KVM_DEBUGREG_WONT_EXIT again.
6373 */
6374 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
6375 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
6376 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
6377 kvm_update_dr0123(vcpu);
6378 kvm_update_dr6(vcpu);
6379 kvm_update_dr7(vcpu);
6380 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
6381 }
6382
6383 /*
6384 * If the guest has used debug registers, at least dr7
6385 * will be disabled while returning to the host.
6386 * If we don't have active breakpoints in the host, we don't
6387 * care about the messed up debug address registers. But if
6388 * we have some of them active, restore the old state.
6389 */
6390 if (hw_breakpoint_active())
6391 hw_breakpoint_restore();
6392
6393 vcpu->arch.last_guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu,
6394 native_read_tsc());
6395
6396 vcpu->mode = OUTSIDE_GUEST_MODE;
6397 smp_wmb();
6398
6399 kvm_put_guest_xcr0(vcpu);
6400
6401 /* Interrupt is enabled by handle_external_intr() */
6402 kvm_x86_ops->handle_external_intr(vcpu);
6403
6404 ++vcpu->stat.exits;
6405
6406 /*
6407 * We must have an instruction between local_irq_enable() and
6408 * kvm_guest_exit(), so the timer interrupt isn't delayed by
6409 * the interrupt shadow. The stat.exits increment will do nicely.
6410 * But we need to prevent reordering, hence this barrier():
6411 */
6412 barrier();
6413
6414 kvm_guest_exit();
6415
6416 preempt_enable();
6417
6418 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6419
6420 /*
6421 * Profile KVM exit RIPs:
6422 */
6423 if (unlikely(prof_on == KVM_PROFILING)) {
6424 unsigned long rip = kvm_rip_read(vcpu);
6425 profile_hit(KVM_PROFILING, (void *)rip);
6426 }
6427
6428 if (unlikely(vcpu->arch.tsc_always_catchup))
6429 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
6430
6431 if (vcpu->arch.apic_attention)
6432 kvm_lapic_sync_from_vapic(vcpu);
6433
6434 r = kvm_x86_ops->handle_exit(vcpu);
6435 return r;
6436
6437 cancel_injection:
6438 kvm_x86_ops->cancel_injection(vcpu);
6439 if (unlikely(vcpu->arch.apic_attention))
6440 kvm_lapic_sync_from_vapic(vcpu);
6441 out:
6442 return r;
6443 }
6444
6445 static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
6446 {
6447 if (!kvm_arch_vcpu_runnable(vcpu)) {
6448 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
6449 kvm_vcpu_block(vcpu);
6450 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
6451 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
6452 return 1;
6453 }
6454
6455 kvm_apic_accept_events(vcpu);
6456 switch(vcpu->arch.mp_state) {
6457 case KVM_MP_STATE_HALTED:
6458 vcpu->arch.pv.pv_unhalted = false;
6459 vcpu->arch.mp_state =
6460 KVM_MP_STATE_RUNNABLE;
6461 case KVM_MP_STATE_RUNNABLE:
6462 vcpu->arch.apf.halted = false;
6463 break;
6464 case KVM_MP_STATE_INIT_RECEIVED:
6465 break;
6466 default:
6467 return -EINTR;
6468 break;
6469 }
6470 return 1;
6471 }
6472
6473 static int vcpu_run(struct kvm_vcpu *vcpu)
6474 {
6475 int r;
6476 struct kvm *kvm = vcpu->kvm;
6477
6478 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
6479
6480 for (;;) {
6481 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
6482 !vcpu->arch.apf.halted)
6483 r = vcpu_enter_guest(vcpu);
6484 else
6485 r = vcpu_block(kvm, vcpu);
6486 if (r <= 0)
6487 break;
6488
6489 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
6490 if (kvm_cpu_has_pending_timer(vcpu))
6491 kvm_inject_pending_timer_irqs(vcpu);
6492
6493 if (dm_request_for_irq_injection(vcpu)) {
6494 r = -EINTR;
6495 vcpu->run->exit_reason = KVM_EXIT_INTR;
6496 ++vcpu->stat.request_irq_exits;
6497 break;
6498 }
6499
6500 kvm_check_async_pf_completion(vcpu);
6501
6502 if (signal_pending(current)) {
6503 r = -EINTR;
6504 vcpu->run->exit_reason = KVM_EXIT_INTR;
6505 ++vcpu->stat.signal_exits;
6506 break;
6507 }
6508 if (need_resched()) {
6509 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
6510 cond_resched();
6511 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
6512 }
6513 }
6514
6515 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
6516
6517 return r;
6518 }
6519
6520 static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
6521 {
6522 int r;
6523 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6524 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
6525 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6526 if (r != EMULATE_DONE)
6527 return 0;
6528 return 1;
6529 }
6530
6531 static int complete_emulated_pio(struct kvm_vcpu *vcpu)
6532 {
6533 BUG_ON(!vcpu->arch.pio.count);
6534
6535 return complete_emulated_io(vcpu);
6536 }
6537
6538 /*
6539 * Implements the following, as a state machine:
6540 *
6541 * read:
6542 * for each fragment
6543 * for each mmio piece in the fragment
6544 * write gpa, len
6545 * exit
6546 * copy data
6547 * execute insn
6548 *
6549 * write:
6550 * for each fragment
6551 * for each mmio piece in the fragment
6552 * write gpa, len
6553 * copy data
6554 * exit
6555 */
6556 static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
6557 {
6558 struct kvm_run *run = vcpu->run;
6559 struct kvm_mmio_fragment *frag;
6560 unsigned len;
6561
6562 BUG_ON(!vcpu->mmio_needed);
6563
6564 /* Complete previous fragment */
6565 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
6566 len = min(8u, frag->len);
6567 if (!vcpu->mmio_is_write)
6568 memcpy(frag->data, run->mmio.data, len);
6569
6570 if (frag->len <= 8) {
6571 /* Switch to the next fragment. */
6572 frag++;
6573 vcpu->mmio_cur_fragment++;
6574 } else {
6575 /* Go forward to the next mmio piece. */
6576 frag->data += len;
6577 frag->gpa += len;
6578 frag->len -= len;
6579 }
6580
6581 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
6582 vcpu->mmio_needed = 0;
6583
6584 /* FIXME: return into emulator if single-stepping. */
6585 if (vcpu->mmio_is_write)
6586 return 1;
6587 vcpu->mmio_read_completed = 1;
6588 return complete_emulated_io(vcpu);
6589 }
6590
6591 run->exit_reason = KVM_EXIT_MMIO;
6592 run->mmio.phys_addr = frag->gpa;
6593 if (vcpu->mmio_is_write)
6594 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
6595 run->mmio.len = min(8u, frag->len);
6596 run->mmio.is_write = vcpu->mmio_is_write;
6597 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
6598 return 0;
6599 }
6600
6601
6602 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
6603 {
6604 int r;
6605 sigset_t sigsaved;
6606
6607 if (!tsk_used_math(current) && init_fpu(current))
6608 return -ENOMEM;
6609
6610 if (vcpu->sigset_active)
6611 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
6612
6613 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
6614 kvm_vcpu_block(vcpu);
6615 kvm_apic_accept_events(vcpu);
6616 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
6617 r = -EAGAIN;
6618 goto out;
6619 }
6620
6621 /* re-sync apic's tpr */
6622 if (!irqchip_in_kernel(vcpu->kvm)) {
6623 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
6624 r = -EINVAL;
6625 goto out;
6626 }
6627 }
6628
6629 if (unlikely(vcpu->arch.complete_userspace_io)) {
6630 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
6631 vcpu->arch.complete_userspace_io = NULL;
6632 r = cui(vcpu);
6633 if (r <= 0)
6634 goto out;
6635 } else
6636 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
6637
6638 r = vcpu_run(vcpu);
6639
6640 out:
6641 post_kvm_run_save(vcpu);
6642 if (vcpu->sigset_active)
6643 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
6644
6645 return r;
6646 }
6647
6648 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6649 {
6650 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
6651 /*
6652 * We are here if userspace calls get_regs() in the middle of
6653 * instruction emulation. Registers state needs to be copied
6654 * back from emulation context to vcpu. Userspace shouldn't do
6655 * that usually, but some bad designed PV devices (vmware
6656 * backdoor interface) need this to work
6657 */
6658 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
6659 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6660 }
6661 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
6662 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
6663 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
6664 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
6665 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
6666 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
6667 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
6668 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
6669 #ifdef CONFIG_X86_64
6670 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
6671 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
6672 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
6673 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
6674 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
6675 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
6676 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
6677 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
6678 #endif
6679
6680 regs->rip = kvm_rip_read(vcpu);
6681 regs->rflags = kvm_get_rflags(vcpu);
6682
6683 return 0;
6684 }
6685
6686 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6687 {
6688 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
6689 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6690
6691 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
6692 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
6693 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
6694 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
6695 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
6696 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
6697 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
6698 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
6699 #ifdef CONFIG_X86_64
6700 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
6701 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
6702 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
6703 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
6704 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
6705 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
6706 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
6707 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
6708 #endif
6709
6710 kvm_rip_write(vcpu, regs->rip);
6711 kvm_set_rflags(vcpu, regs->rflags);
6712
6713 vcpu->arch.exception.pending = false;
6714
6715 kvm_make_request(KVM_REQ_EVENT, vcpu);
6716
6717 return 0;
6718 }
6719
6720 void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
6721 {
6722 struct kvm_segment cs;
6723
6724 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
6725 *db = cs.db;
6726 *l = cs.l;
6727 }
6728 EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
6729
6730 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
6731 struct kvm_sregs *sregs)
6732 {
6733 struct desc_ptr dt;
6734
6735 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6736 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6737 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6738 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6739 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6740 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
6741
6742 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6743 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
6744
6745 kvm_x86_ops->get_idt(vcpu, &dt);
6746 sregs->idt.limit = dt.size;
6747 sregs->idt.base = dt.address;
6748 kvm_x86_ops->get_gdt(vcpu, &dt);
6749 sregs->gdt.limit = dt.size;
6750 sregs->gdt.base = dt.address;
6751
6752 sregs->cr0 = kvm_read_cr0(vcpu);
6753 sregs->cr2 = vcpu->arch.cr2;
6754 sregs->cr3 = kvm_read_cr3(vcpu);
6755 sregs->cr4 = kvm_read_cr4(vcpu);
6756 sregs->cr8 = kvm_get_cr8(vcpu);
6757 sregs->efer = vcpu->arch.efer;
6758 sregs->apic_base = kvm_get_apic_base(vcpu);
6759
6760 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
6761
6762 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
6763 set_bit(vcpu->arch.interrupt.nr,
6764 (unsigned long *)sregs->interrupt_bitmap);
6765
6766 return 0;
6767 }
6768
6769 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
6770 struct kvm_mp_state *mp_state)
6771 {
6772 kvm_apic_accept_events(vcpu);
6773 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
6774 vcpu->arch.pv.pv_unhalted)
6775 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
6776 else
6777 mp_state->mp_state = vcpu->arch.mp_state;
6778
6779 return 0;
6780 }
6781
6782 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
6783 struct kvm_mp_state *mp_state)
6784 {
6785 if (!kvm_vcpu_has_lapic(vcpu) &&
6786 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
6787 return -EINVAL;
6788
6789 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
6790 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
6791 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
6792 } else
6793 vcpu->arch.mp_state = mp_state->mp_state;
6794 kvm_make_request(KVM_REQ_EVENT, vcpu);
6795 return 0;
6796 }
6797
6798 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
6799 int reason, bool has_error_code, u32 error_code)
6800 {
6801 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
6802 int ret;
6803
6804 init_emulate_ctxt(vcpu);
6805
6806 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
6807 has_error_code, error_code);
6808
6809 if (ret)
6810 return EMULATE_FAIL;
6811
6812 kvm_rip_write(vcpu, ctxt->eip);
6813 kvm_set_rflags(vcpu, ctxt->eflags);
6814 kvm_make_request(KVM_REQ_EVENT, vcpu);
6815 return EMULATE_DONE;
6816 }
6817 EXPORT_SYMBOL_GPL(kvm_task_switch);
6818
6819 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
6820 struct kvm_sregs *sregs)
6821 {
6822 struct msr_data apic_base_msr;
6823 int mmu_reset_needed = 0;
6824 int pending_vec, max_bits, idx;
6825 struct desc_ptr dt;
6826
6827 if (!guest_cpuid_has_xsave(vcpu) && (sregs->cr4 & X86_CR4_OSXSAVE))
6828 return -EINVAL;
6829
6830 dt.size = sregs->idt.limit;
6831 dt.address = sregs->idt.base;
6832 kvm_x86_ops->set_idt(vcpu, &dt);
6833 dt.size = sregs->gdt.limit;
6834 dt.address = sregs->gdt.base;
6835 kvm_x86_ops->set_gdt(vcpu, &dt);
6836
6837 vcpu->arch.cr2 = sregs->cr2;
6838 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
6839 vcpu->arch.cr3 = sregs->cr3;
6840 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
6841
6842 kvm_set_cr8(vcpu, sregs->cr8);
6843
6844 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
6845 kvm_x86_ops->set_efer(vcpu, sregs->efer);
6846 apic_base_msr.data = sregs->apic_base;
6847 apic_base_msr.host_initiated = true;
6848 kvm_set_apic_base(vcpu, &apic_base_msr);
6849
6850 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
6851 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
6852 vcpu->arch.cr0 = sregs->cr0;
6853
6854 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
6855 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
6856 if (sregs->cr4 & X86_CR4_OSXSAVE)
6857 kvm_update_cpuid(vcpu);
6858
6859 idx = srcu_read_lock(&vcpu->kvm->srcu);
6860 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
6861 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
6862 mmu_reset_needed = 1;
6863 }
6864 srcu_read_unlock(&vcpu->kvm->srcu, idx);
6865
6866 if (mmu_reset_needed)
6867 kvm_mmu_reset_context(vcpu);
6868
6869 max_bits = KVM_NR_INTERRUPTS;
6870 pending_vec = find_first_bit(
6871 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
6872 if (pending_vec < max_bits) {
6873 kvm_queue_interrupt(vcpu, pending_vec, false);
6874 pr_debug("Set back pending irq %d\n", pending_vec);
6875 }
6876
6877 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6878 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6879 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6880 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6881 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6882 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
6883
6884 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6885 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
6886
6887 update_cr8_intercept(vcpu);
6888
6889 /* Older userspace won't unhalt the vcpu on reset. */
6890 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
6891 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
6892 !is_protmode(vcpu))
6893 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
6894
6895 kvm_make_request(KVM_REQ_EVENT, vcpu);
6896
6897 return 0;
6898 }
6899
6900 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
6901 struct kvm_guest_debug *dbg)
6902 {
6903 unsigned long rflags;
6904 int i, r;
6905
6906 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
6907 r = -EBUSY;
6908 if (vcpu->arch.exception.pending)
6909 goto out;
6910 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
6911 kvm_queue_exception(vcpu, DB_VECTOR);
6912 else
6913 kvm_queue_exception(vcpu, BP_VECTOR);
6914 }
6915
6916 /*
6917 * Read rflags as long as potentially injected trace flags are still
6918 * filtered out.
6919 */
6920 rflags = kvm_get_rflags(vcpu);
6921
6922 vcpu->guest_debug = dbg->control;
6923 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
6924 vcpu->guest_debug = 0;
6925
6926 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
6927 for (i = 0; i < KVM_NR_DB_REGS; ++i)
6928 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
6929 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
6930 } else {
6931 for (i = 0; i < KVM_NR_DB_REGS; i++)
6932 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
6933 }
6934 kvm_update_dr7(vcpu);
6935
6936 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6937 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
6938 get_segment_base(vcpu, VCPU_SREG_CS);
6939
6940 /*
6941 * Trigger an rflags update that will inject or remove the trace
6942 * flags.
6943 */
6944 kvm_set_rflags(vcpu, rflags);
6945
6946 kvm_x86_ops->update_db_bp_intercept(vcpu);
6947
6948 r = 0;
6949
6950 out:
6951
6952 return r;
6953 }
6954
6955 /*
6956 * Translate a guest virtual address to a guest physical address.
6957 */
6958 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
6959 struct kvm_translation *tr)
6960 {
6961 unsigned long vaddr = tr->linear_address;
6962 gpa_t gpa;
6963 int idx;
6964
6965 idx = srcu_read_lock(&vcpu->kvm->srcu);
6966 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
6967 srcu_read_unlock(&vcpu->kvm->srcu, idx);
6968 tr->physical_address = gpa;
6969 tr->valid = gpa != UNMAPPED_GVA;
6970 tr->writeable = 1;
6971 tr->usermode = 0;
6972
6973 return 0;
6974 }
6975
6976 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
6977 {
6978 struct i387_fxsave_struct *fxsave =
6979 &vcpu->arch.guest_fpu.state->fxsave;
6980
6981 memcpy(fpu->fpr, fxsave->st_space, 128);
6982 fpu->fcw = fxsave->cwd;
6983 fpu->fsw = fxsave->swd;
6984 fpu->ftwx = fxsave->twd;
6985 fpu->last_opcode = fxsave->fop;
6986 fpu->last_ip = fxsave->rip;
6987 fpu->last_dp = fxsave->rdp;
6988 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
6989
6990 return 0;
6991 }
6992
6993 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
6994 {
6995 struct i387_fxsave_struct *fxsave =
6996 &vcpu->arch.guest_fpu.state->fxsave;
6997
6998 memcpy(fxsave->st_space, fpu->fpr, 128);
6999 fxsave->cwd = fpu->fcw;
7000 fxsave->swd = fpu->fsw;
7001 fxsave->twd = fpu->ftwx;
7002 fxsave->fop = fpu->last_opcode;
7003 fxsave->rip = fpu->last_ip;
7004 fxsave->rdp = fpu->last_dp;
7005 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
7006
7007 return 0;
7008 }
7009
7010 int fx_init(struct kvm_vcpu *vcpu)
7011 {
7012 int err;
7013
7014 err = fpu_alloc(&vcpu->arch.guest_fpu);
7015 if (err)
7016 return err;
7017
7018 fpu_finit(&vcpu->arch.guest_fpu);
7019 if (cpu_has_xsaves)
7020 vcpu->arch.guest_fpu.state->xsave.xsave_hdr.xcomp_bv =
7021 host_xcr0 | XSTATE_COMPACTION_ENABLED;
7022
7023 /*
7024 * Ensure guest xcr0 is valid for loading
7025 */
7026 vcpu->arch.xcr0 = XSTATE_FP;
7027
7028 vcpu->arch.cr0 |= X86_CR0_ET;
7029
7030 return 0;
7031 }
7032 EXPORT_SYMBOL_GPL(fx_init);
7033
7034 static void fx_free(struct kvm_vcpu *vcpu)
7035 {
7036 fpu_free(&vcpu->arch.guest_fpu);
7037 }
7038
7039 void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
7040 {
7041 if (vcpu->guest_fpu_loaded)
7042 return;
7043
7044 /*
7045 * Restore all possible states in the guest,
7046 * and assume host would use all available bits.
7047 * Guest xcr0 would be loaded later.
7048 */
7049 vcpu->guest_fpu_loaded = 1;
7050 __kernel_fpu_begin();
7051 fpu_restore_checking(&vcpu->arch.guest_fpu);
7052 trace_kvm_fpu(1);
7053 }
7054
7055 void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
7056 {
7057 if (!vcpu->guest_fpu_loaded)
7058 return;
7059
7060 vcpu->guest_fpu_loaded = 0;
7061 fpu_save_init(&vcpu->arch.guest_fpu);
7062 __kernel_fpu_end();
7063 ++vcpu->stat.fpu_reload;
7064 if (!vcpu->arch.eager_fpu)
7065 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
7066
7067 trace_kvm_fpu(0);
7068 }
7069
7070 void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
7071 {
7072 kvmclock_reset(vcpu);
7073
7074 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
7075 fx_free(vcpu);
7076 kvm_x86_ops->vcpu_free(vcpu);
7077 }
7078
7079 struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
7080 unsigned int id)
7081 {
7082 struct kvm_vcpu *vcpu;
7083
7084 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
7085 printk_once(KERN_WARNING
7086 "kvm: SMP vm created on host with unstable TSC; "
7087 "guest TSC will not be reliable\n");
7088
7089 vcpu = kvm_x86_ops->vcpu_create(kvm, id);
7090
7091 /*
7092 * Activate fpu unconditionally in case the guest needs eager FPU. It will be
7093 * deactivated soon if it doesn't.
7094 */
7095 kvm_x86_ops->fpu_activate(vcpu);
7096 return vcpu;
7097 }
7098
7099 int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
7100 {
7101 int r;
7102
7103 vcpu->arch.mtrr_state.have_fixed = 1;
7104 r = vcpu_load(vcpu);
7105 if (r)
7106 return r;
7107 kvm_vcpu_reset(vcpu);
7108 kvm_mmu_setup(vcpu);
7109 vcpu_put(vcpu);
7110
7111 return r;
7112 }
7113
7114 void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
7115 {
7116 struct msr_data msr;
7117 struct kvm *kvm = vcpu->kvm;
7118
7119 if (vcpu_load(vcpu))
7120 return;
7121 msr.data = 0x0;
7122 msr.index = MSR_IA32_TSC;
7123 msr.host_initiated = true;
7124 kvm_write_tsc(vcpu, &msr);
7125 vcpu_put(vcpu);
7126
7127 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
7128 KVMCLOCK_SYNC_PERIOD);
7129 }
7130
7131 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
7132 {
7133 int r;
7134 vcpu->arch.apf.msr_val = 0;
7135
7136 r = vcpu_load(vcpu);
7137 BUG_ON(r);
7138 kvm_mmu_unload(vcpu);
7139 vcpu_put(vcpu);
7140
7141 fx_free(vcpu);
7142 kvm_x86_ops->vcpu_free(vcpu);
7143 }
7144
7145 void kvm_vcpu_reset(struct kvm_vcpu *vcpu)
7146 {
7147 atomic_set(&vcpu->arch.nmi_queued, 0);
7148 vcpu->arch.nmi_pending = 0;
7149 vcpu->arch.nmi_injected = false;
7150 kvm_clear_interrupt_queue(vcpu);
7151 kvm_clear_exception_queue(vcpu);
7152
7153 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
7154 kvm_update_dr0123(vcpu);
7155 vcpu->arch.dr6 = DR6_INIT;
7156 kvm_update_dr6(vcpu);
7157 vcpu->arch.dr7 = DR7_FIXED_1;
7158 kvm_update_dr7(vcpu);
7159
7160 vcpu->arch.cr2 = 0;
7161
7162 kvm_make_request(KVM_REQ_EVENT, vcpu);
7163 vcpu->arch.apf.msr_val = 0;
7164 vcpu->arch.st.msr_val = 0;
7165
7166 kvmclock_reset(vcpu);
7167
7168 kvm_clear_async_pf_completion_queue(vcpu);
7169 kvm_async_pf_hash_reset(vcpu);
7170 vcpu->arch.apf.halted = false;
7171
7172 kvm_pmu_reset(vcpu);
7173
7174 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
7175 vcpu->arch.regs_avail = ~0;
7176 vcpu->arch.regs_dirty = ~0;
7177
7178 kvm_x86_ops->vcpu_reset(vcpu);
7179 }
7180
7181 void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
7182 {
7183 struct kvm_segment cs;
7184
7185 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
7186 cs.selector = vector << 8;
7187 cs.base = vector << 12;
7188 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
7189 kvm_rip_write(vcpu, 0);
7190 }
7191
7192 int kvm_arch_hardware_enable(void)
7193 {
7194 struct kvm *kvm;
7195 struct kvm_vcpu *vcpu;
7196 int i;
7197 int ret;
7198 u64 local_tsc;
7199 u64 max_tsc = 0;
7200 bool stable, backwards_tsc = false;
7201
7202 kvm_shared_msr_cpu_online();
7203 ret = kvm_x86_ops->hardware_enable();
7204 if (ret != 0)
7205 return ret;
7206
7207 local_tsc = native_read_tsc();
7208 stable = !check_tsc_unstable();
7209 list_for_each_entry(kvm, &vm_list, vm_list) {
7210 kvm_for_each_vcpu(i, vcpu, kvm) {
7211 if (!stable && vcpu->cpu == smp_processor_id())
7212 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
7213 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
7214 backwards_tsc = true;
7215 if (vcpu->arch.last_host_tsc > max_tsc)
7216 max_tsc = vcpu->arch.last_host_tsc;
7217 }
7218 }
7219 }
7220
7221 /*
7222 * Sometimes, even reliable TSCs go backwards. This happens on
7223 * platforms that reset TSC during suspend or hibernate actions, but
7224 * maintain synchronization. We must compensate. Fortunately, we can
7225 * detect that condition here, which happens early in CPU bringup,
7226 * before any KVM threads can be running. Unfortunately, we can't
7227 * bring the TSCs fully up to date with real time, as we aren't yet far
7228 * enough into CPU bringup that we know how much real time has actually
7229 * elapsed; our helper function, get_kernel_ns() will be using boot
7230 * variables that haven't been updated yet.
7231 *
7232 * So we simply find the maximum observed TSC above, then record the
7233 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
7234 * the adjustment will be applied. Note that we accumulate
7235 * adjustments, in case multiple suspend cycles happen before some VCPU
7236 * gets a chance to run again. In the event that no KVM threads get a
7237 * chance to run, we will miss the entire elapsed period, as we'll have
7238 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
7239 * loose cycle time. This isn't too big a deal, since the loss will be
7240 * uniform across all VCPUs (not to mention the scenario is extremely
7241 * unlikely). It is possible that a second hibernate recovery happens
7242 * much faster than a first, causing the observed TSC here to be
7243 * smaller; this would require additional padding adjustment, which is
7244 * why we set last_host_tsc to the local tsc observed here.
7245 *
7246 * N.B. - this code below runs only on platforms with reliable TSC,
7247 * as that is the only way backwards_tsc is set above. Also note
7248 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
7249 * have the same delta_cyc adjustment applied if backwards_tsc
7250 * is detected. Note further, this adjustment is only done once,
7251 * as we reset last_host_tsc on all VCPUs to stop this from being
7252 * called multiple times (one for each physical CPU bringup).
7253 *
7254 * Platforms with unreliable TSCs don't have to deal with this, they
7255 * will be compensated by the logic in vcpu_load, which sets the TSC to
7256 * catchup mode. This will catchup all VCPUs to real time, but cannot
7257 * guarantee that they stay in perfect synchronization.
7258 */
7259 if (backwards_tsc) {
7260 u64 delta_cyc = max_tsc - local_tsc;
7261 backwards_tsc_observed = true;
7262 list_for_each_entry(kvm, &vm_list, vm_list) {
7263 kvm_for_each_vcpu(i, vcpu, kvm) {
7264 vcpu->arch.tsc_offset_adjustment += delta_cyc;
7265 vcpu->arch.last_host_tsc = local_tsc;
7266 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
7267 }
7268
7269 /*
7270 * We have to disable TSC offset matching.. if you were
7271 * booting a VM while issuing an S4 host suspend....
7272 * you may have some problem. Solving this issue is
7273 * left as an exercise to the reader.
7274 */
7275 kvm->arch.last_tsc_nsec = 0;
7276 kvm->arch.last_tsc_write = 0;
7277 }
7278
7279 }
7280 return 0;
7281 }
7282
7283 void kvm_arch_hardware_disable(void)
7284 {
7285 kvm_x86_ops->hardware_disable();
7286 drop_user_return_notifiers();
7287 }
7288
7289 int kvm_arch_hardware_setup(void)
7290 {
7291 int r;
7292
7293 r = kvm_x86_ops->hardware_setup();
7294 if (r != 0)
7295 return r;
7296
7297 kvm_init_msr_list();
7298 return 0;
7299 }
7300
7301 void kvm_arch_hardware_unsetup(void)
7302 {
7303 kvm_x86_ops->hardware_unsetup();
7304 }
7305
7306 void kvm_arch_check_processor_compat(void *rtn)
7307 {
7308 kvm_x86_ops->check_processor_compatibility(rtn);
7309 }
7310
7311 bool kvm_vcpu_compatible(struct kvm_vcpu *vcpu)
7312 {
7313 return irqchip_in_kernel(vcpu->kvm) == (vcpu->arch.apic != NULL);
7314 }
7315
7316 struct static_key kvm_no_apic_vcpu __read_mostly;
7317
7318 int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
7319 {
7320 struct page *page;
7321 struct kvm *kvm;
7322 int r;
7323
7324 BUG_ON(vcpu->kvm == NULL);
7325 kvm = vcpu->kvm;
7326
7327 vcpu->arch.pv.pv_unhalted = false;
7328 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
7329 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_reset_bsp(vcpu))
7330 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7331 else
7332 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
7333
7334 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
7335 if (!page) {
7336 r = -ENOMEM;
7337 goto fail;
7338 }
7339 vcpu->arch.pio_data = page_address(page);
7340
7341 kvm_set_tsc_khz(vcpu, max_tsc_khz);
7342
7343 r = kvm_mmu_create(vcpu);
7344 if (r < 0)
7345 goto fail_free_pio_data;
7346
7347 if (irqchip_in_kernel(kvm)) {
7348 r = kvm_create_lapic(vcpu);
7349 if (r < 0)
7350 goto fail_mmu_destroy;
7351 } else
7352 static_key_slow_inc(&kvm_no_apic_vcpu);
7353
7354 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
7355 GFP_KERNEL);
7356 if (!vcpu->arch.mce_banks) {
7357 r = -ENOMEM;
7358 goto fail_free_lapic;
7359 }
7360 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
7361
7362 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
7363 r = -ENOMEM;
7364 goto fail_free_mce_banks;
7365 }
7366
7367 r = fx_init(vcpu);
7368 if (r)
7369 goto fail_free_wbinvd_dirty_mask;
7370
7371 vcpu->arch.ia32_tsc_adjust_msr = 0x0;
7372 vcpu->arch.pv_time_enabled = false;
7373
7374 vcpu->arch.guest_supported_xcr0 = 0;
7375 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
7376
7377 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
7378
7379 kvm_async_pf_hash_reset(vcpu);
7380 kvm_pmu_init(vcpu);
7381
7382 return 0;
7383 fail_free_wbinvd_dirty_mask:
7384 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
7385 fail_free_mce_banks:
7386 kfree(vcpu->arch.mce_banks);
7387 fail_free_lapic:
7388 kvm_free_lapic(vcpu);
7389 fail_mmu_destroy:
7390 kvm_mmu_destroy(vcpu);
7391 fail_free_pio_data:
7392 free_page((unsigned long)vcpu->arch.pio_data);
7393 fail:
7394 return r;
7395 }
7396
7397 void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
7398 {
7399 int idx;
7400
7401 kvm_pmu_destroy(vcpu);
7402 kfree(vcpu->arch.mce_banks);
7403 kvm_free_lapic(vcpu);
7404 idx = srcu_read_lock(&vcpu->kvm->srcu);
7405 kvm_mmu_destroy(vcpu);
7406 srcu_read_unlock(&vcpu->kvm->srcu, idx);
7407 free_page((unsigned long)vcpu->arch.pio_data);
7408 if (!irqchip_in_kernel(vcpu->kvm))
7409 static_key_slow_dec(&kvm_no_apic_vcpu);
7410 }
7411
7412 void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
7413 {
7414 kvm_x86_ops->sched_in(vcpu, cpu);
7415 }
7416
7417 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
7418 {
7419 if (type)
7420 return -EINVAL;
7421
7422 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
7423 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
7424 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
7425 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
7426 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
7427
7428 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
7429 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7430 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
7431 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
7432 &kvm->arch.irq_sources_bitmap);
7433
7434 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
7435 mutex_init(&kvm->arch.apic_map_lock);
7436 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
7437
7438 pvclock_update_vm_gtod_copy(kvm);
7439
7440 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
7441 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
7442
7443 return 0;
7444 }
7445
7446 static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
7447 {
7448 int r;
7449 r = vcpu_load(vcpu);
7450 BUG_ON(r);
7451 kvm_mmu_unload(vcpu);
7452 vcpu_put(vcpu);
7453 }
7454
7455 static void kvm_free_vcpus(struct kvm *kvm)
7456 {
7457 unsigned int i;
7458 struct kvm_vcpu *vcpu;
7459
7460 /*
7461 * Unpin any mmu pages first.
7462 */
7463 kvm_for_each_vcpu(i, vcpu, kvm) {
7464 kvm_clear_async_pf_completion_queue(vcpu);
7465 kvm_unload_vcpu_mmu(vcpu);
7466 }
7467 kvm_for_each_vcpu(i, vcpu, kvm)
7468 kvm_arch_vcpu_free(vcpu);
7469
7470 mutex_lock(&kvm->lock);
7471 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
7472 kvm->vcpus[i] = NULL;
7473
7474 atomic_set(&kvm->online_vcpus, 0);
7475 mutex_unlock(&kvm->lock);
7476 }
7477
7478 void kvm_arch_sync_events(struct kvm *kvm)
7479 {
7480 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
7481 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
7482 kvm_free_all_assigned_devices(kvm);
7483 kvm_free_pit(kvm);
7484 }
7485
7486 void kvm_arch_destroy_vm(struct kvm *kvm)
7487 {
7488 if (current->mm == kvm->mm) {
7489 /*
7490 * Free memory regions allocated on behalf of userspace,
7491 * unless the the memory map has changed due to process exit
7492 * or fd copying.
7493 */
7494 struct kvm_userspace_memory_region mem;
7495 memset(&mem, 0, sizeof(mem));
7496 mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
7497 kvm_set_memory_region(kvm, &mem);
7498
7499 mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
7500 kvm_set_memory_region(kvm, &mem);
7501
7502 mem.slot = TSS_PRIVATE_MEMSLOT;
7503 kvm_set_memory_region(kvm, &mem);
7504 }
7505 kvm_iommu_unmap_guest(kvm);
7506 kfree(kvm->arch.vpic);
7507 kfree(kvm->arch.vioapic);
7508 kvm_free_vcpus(kvm);
7509 kfree(rcu_dereference_check(kvm->arch.apic_map, 1));
7510 }
7511
7512 void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
7513 struct kvm_memory_slot *dont)
7514 {
7515 int i;
7516
7517 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7518 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
7519 kvfree(free->arch.rmap[i]);
7520 free->arch.rmap[i] = NULL;
7521 }
7522 if (i == 0)
7523 continue;
7524
7525 if (!dont || free->arch.lpage_info[i - 1] !=
7526 dont->arch.lpage_info[i - 1]) {
7527 kvfree(free->arch.lpage_info[i - 1]);
7528 free->arch.lpage_info[i - 1] = NULL;
7529 }
7530 }
7531 }
7532
7533 int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
7534 unsigned long npages)
7535 {
7536 int i;
7537
7538 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7539 unsigned long ugfn;
7540 int lpages;
7541 int level = i + 1;
7542
7543 lpages = gfn_to_index(slot->base_gfn + npages - 1,
7544 slot->base_gfn, level) + 1;
7545
7546 slot->arch.rmap[i] =
7547 kvm_kvzalloc(lpages * sizeof(*slot->arch.rmap[i]));
7548 if (!slot->arch.rmap[i])
7549 goto out_free;
7550 if (i == 0)
7551 continue;
7552
7553 slot->arch.lpage_info[i - 1] = kvm_kvzalloc(lpages *
7554 sizeof(*slot->arch.lpage_info[i - 1]));
7555 if (!slot->arch.lpage_info[i - 1])
7556 goto out_free;
7557
7558 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
7559 slot->arch.lpage_info[i - 1][0].write_count = 1;
7560 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
7561 slot->arch.lpage_info[i - 1][lpages - 1].write_count = 1;
7562 ugfn = slot->userspace_addr >> PAGE_SHIFT;
7563 /*
7564 * If the gfn and userspace address are not aligned wrt each
7565 * other, or if explicitly asked to, disable large page
7566 * support for this slot
7567 */
7568 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
7569 !kvm_largepages_enabled()) {
7570 unsigned long j;
7571
7572 for (j = 0; j < lpages; ++j)
7573 slot->arch.lpage_info[i - 1][j].write_count = 1;
7574 }
7575 }
7576
7577 return 0;
7578
7579 out_free:
7580 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7581 kvfree(slot->arch.rmap[i]);
7582 slot->arch.rmap[i] = NULL;
7583 if (i == 0)
7584 continue;
7585
7586 kvfree(slot->arch.lpage_info[i - 1]);
7587 slot->arch.lpage_info[i - 1] = NULL;
7588 }
7589 return -ENOMEM;
7590 }
7591
7592 void kvm_arch_memslots_updated(struct kvm *kvm)
7593 {
7594 /*
7595 * memslots->generation has been incremented.
7596 * mmio generation may have reached its maximum value.
7597 */
7598 kvm_mmu_invalidate_mmio_sptes(kvm);
7599 }
7600
7601 int kvm_arch_prepare_memory_region(struct kvm *kvm,
7602 struct kvm_memory_slot *memslot,
7603 struct kvm_userspace_memory_region *mem,
7604 enum kvm_mr_change change)
7605 {
7606 /*
7607 * Only private memory slots need to be mapped here since
7608 * KVM_SET_MEMORY_REGION ioctl is no longer supported.
7609 */
7610 if ((memslot->id >= KVM_USER_MEM_SLOTS) && (change == KVM_MR_CREATE)) {
7611 unsigned long userspace_addr;
7612
7613 /*
7614 * MAP_SHARED to prevent internal slot pages from being moved
7615 * by fork()/COW.
7616 */
7617 userspace_addr = vm_mmap(NULL, 0, memslot->npages * PAGE_SIZE,
7618 PROT_READ | PROT_WRITE,
7619 MAP_SHARED | MAP_ANONYMOUS, 0);
7620
7621 if (IS_ERR((void *)userspace_addr))
7622 return PTR_ERR((void *)userspace_addr);
7623
7624 memslot->userspace_addr = userspace_addr;
7625 }
7626
7627 return 0;
7628 }
7629
7630 static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
7631 struct kvm_memory_slot *new)
7632 {
7633 /* Still write protect RO slot */
7634 if (new->flags & KVM_MEM_READONLY) {
7635 kvm_mmu_slot_remove_write_access(kvm, new);
7636 return;
7637 }
7638
7639 /*
7640 * Call kvm_x86_ops dirty logging hooks when they are valid.
7641 *
7642 * kvm_x86_ops->slot_disable_log_dirty is called when:
7643 *
7644 * - KVM_MR_CREATE with dirty logging is disabled
7645 * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag
7646 *
7647 * The reason is, in case of PML, we need to set D-bit for any slots
7648 * with dirty logging disabled in order to eliminate unnecessary GPA
7649 * logging in PML buffer (and potential PML buffer full VMEXT). This
7650 * guarantees leaving PML enabled during guest's lifetime won't have
7651 * any additonal overhead from PML when guest is running with dirty
7652 * logging disabled for memory slots.
7653 *
7654 * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot
7655 * to dirty logging mode.
7656 *
7657 * If kvm_x86_ops dirty logging hooks are invalid, use write protect.
7658 *
7659 * In case of write protect:
7660 *
7661 * Write protect all pages for dirty logging.
7662 *
7663 * All the sptes including the large sptes which point to this
7664 * slot are set to readonly. We can not create any new large
7665 * spte on this slot until the end of the logging.
7666 *
7667 * See the comments in fast_page_fault().
7668 */
7669 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
7670 if (kvm_x86_ops->slot_enable_log_dirty)
7671 kvm_x86_ops->slot_enable_log_dirty(kvm, new);
7672 else
7673 kvm_mmu_slot_remove_write_access(kvm, new);
7674 } else {
7675 if (kvm_x86_ops->slot_disable_log_dirty)
7676 kvm_x86_ops->slot_disable_log_dirty(kvm, new);
7677 }
7678 }
7679
7680 void kvm_arch_commit_memory_region(struct kvm *kvm,
7681 struct kvm_userspace_memory_region *mem,
7682 const struct kvm_memory_slot *old,
7683 enum kvm_mr_change change)
7684 {
7685 struct kvm_memory_slot *new;
7686 int nr_mmu_pages = 0;
7687
7688 if ((mem->slot >= KVM_USER_MEM_SLOTS) && (change == KVM_MR_DELETE)) {
7689 int ret;
7690
7691 ret = vm_munmap(old->userspace_addr,
7692 old->npages * PAGE_SIZE);
7693 if (ret < 0)
7694 printk(KERN_WARNING
7695 "kvm_vm_ioctl_set_memory_region: "
7696 "failed to munmap memory\n");
7697 }
7698
7699 if (!kvm->arch.n_requested_mmu_pages)
7700 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
7701
7702 if (nr_mmu_pages)
7703 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
7704
7705 /* It's OK to get 'new' slot here as it has already been installed */
7706 new = id_to_memslot(kvm->memslots, mem->slot);
7707
7708 /*
7709 * Dirty logging tracks sptes in 4k granularity, meaning that large
7710 * sptes have to be split. If live migration is successful, the guest
7711 * in the source machine will be destroyed and large sptes will be
7712 * created in the destination. However, if the guest continues to run
7713 * in the source machine (for example if live migration fails), small
7714 * sptes will remain around and cause bad performance.
7715 *
7716 * Scan sptes if dirty logging has been stopped, dropping those
7717 * which can be collapsed into a single large-page spte. Later
7718 * page faults will create the large-page sptes.
7719 */
7720 if ((change != KVM_MR_DELETE) &&
7721 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
7722 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES))
7723 kvm_mmu_zap_collapsible_sptes(kvm, new);
7724
7725 /*
7726 * Set up write protection and/or dirty logging for the new slot.
7727 *
7728 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have
7729 * been zapped so no dirty logging staff is needed for old slot. For
7730 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the
7731 * new and it's also covered when dealing with the new slot.
7732 */
7733 if (change != KVM_MR_DELETE)
7734 kvm_mmu_slot_apply_flags(kvm, new);
7735 }
7736
7737 void kvm_arch_flush_shadow_all(struct kvm *kvm)
7738 {
7739 kvm_mmu_invalidate_zap_all_pages(kvm);
7740 }
7741
7742 void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
7743 struct kvm_memory_slot *slot)
7744 {
7745 kvm_mmu_invalidate_zap_all_pages(kvm);
7746 }
7747
7748 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
7749 {
7750 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
7751 kvm_x86_ops->check_nested_events(vcpu, false);
7752
7753 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
7754 !vcpu->arch.apf.halted)
7755 || !list_empty_careful(&vcpu->async_pf.done)
7756 || kvm_apic_has_events(vcpu)
7757 || vcpu->arch.pv.pv_unhalted
7758 || atomic_read(&vcpu->arch.nmi_queued) ||
7759 (kvm_arch_interrupt_allowed(vcpu) &&
7760 kvm_cpu_has_interrupt(vcpu));
7761 }
7762
7763 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
7764 {
7765 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
7766 }
7767
7768 int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
7769 {
7770 return kvm_x86_ops->interrupt_allowed(vcpu);
7771 }
7772
7773 unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
7774 {
7775 if (is_64_bit_mode(vcpu))
7776 return kvm_rip_read(vcpu);
7777 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
7778 kvm_rip_read(vcpu));
7779 }
7780 EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
7781
7782 bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
7783 {
7784 return kvm_get_linear_rip(vcpu) == linear_rip;
7785 }
7786 EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
7787
7788 unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
7789 {
7790 unsigned long rflags;
7791
7792 rflags = kvm_x86_ops->get_rflags(vcpu);
7793 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
7794 rflags &= ~X86_EFLAGS_TF;
7795 return rflags;
7796 }
7797 EXPORT_SYMBOL_GPL(kvm_get_rflags);
7798
7799 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
7800 {
7801 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
7802 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
7803 rflags |= X86_EFLAGS_TF;
7804 kvm_x86_ops->set_rflags(vcpu, rflags);
7805 }
7806
7807 void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
7808 {
7809 __kvm_set_rflags(vcpu, rflags);
7810 kvm_make_request(KVM_REQ_EVENT, vcpu);
7811 }
7812 EXPORT_SYMBOL_GPL(kvm_set_rflags);
7813
7814 void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
7815 {
7816 int r;
7817
7818 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
7819 work->wakeup_all)
7820 return;
7821
7822 r = kvm_mmu_reload(vcpu);
7823 if (unlikely(r))
7824 return;
7825
7826 if (!vcpu->arch.mmu.direct_map &&
7827 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
7828 return;
7829
7830 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
7831 }
7832
7833 static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
7834 {
7835 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
7836 }
7837
7838 static inline u32 kvm_async_pf_next_probe(u32 key)
7839 {
7840 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
7841 }
7842
7843 static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7844 {
7845 u32 key = kvm_async_pf_hash_fn(gfn);
7846
7847 while (vcpu->arch.apf.gfns[key] != ~0)
7848 key = kvm_async_pf_next_probe(key);
7849
7850 vcpu->arch.apf.gfns[key] = gfn;
7851 }
7852
7853 static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
7854 {
7855 int i;
7856 u32 key = kvm_async_pf_hash_fn(gfn);
7857
7858 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
7859 (vcpu->arch.apf.gfns[key] != gfn &&
7860 vcpu->arch.apf.gfns[key] != ~0); i++)
7861 key = kvm_async_pf_next_probe(key);
7862
7863 return key;
7864 }
7865
7866 bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7867 {
7868 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
7869 }
7870
7871 static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7872 {
7873 u32 i, j, k;
7874
7875 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
7876 while (true) {
7877 vcpu->arch.apf.gfns[i] = ~0;
7878 do {
7879 j = kvm_async_pf_next_probe(j);
7880 if (vcpu->arch.apf.gfns[j] == ~0)
7881 return;
7882 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
7883 /*
7884 * k lies cyclically in ]i,j]
7885 * | i.k.j |
7886 * |....j i.k.| or |.k..j i...|
7887 */
7888 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
7889 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
7890 i = j;
7891 }
7892 }
7893
7894 static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
7895 {
7896
7897 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
7898 sizeof(val));
7899 }
7900
7901 void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
7902 struct kvm_async_pf *work)
7903 {
7904 struct x86_exception fault;
7905
7906 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
7907 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7908
7909 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
7910 (vcpu->arch.apf.send_user_only &&
7911 kvm_x86_ops->get_cpl(vcpu) == 0))
7912 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
7913 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
7914 fault.vector = PF_VECTOR;
7915 fault.error_code_valid = true;
7916 fault.error_code = 0;
7917 fault.nested_page_fault = false;
7918 fault.address = work->arch.token;
7919 kvm_inject_page_fault(vcpu, &fault);
7920 }
7921 }
7922
7923 void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
7924 struct kvm_async_pf *work)
7925 {
7926 struct x86_exception fault;
7927
7928 trace_kvm_async_pf_ready(work->arch.token, work->gva);
7929 if (work->wakeup_all)
7930 work->arch.token = ~0; /* broadcast wakeup */
7931 else
7932 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
7933
7934 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
7935 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
7936 fault.vector = PF_VECTOR;
7937 fault.error_code_valid = true;
7938 fault.error_code = 0;
7939 fault.nested_page_fault = false;
7940 fault.address = work->arch.token;
7941 kvm_inject_page_fault(vcpu, &fault);
7942 }
7943 vcpu->arch.apf.halted = false;
7944 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7945 }
7946
7947 bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
7948 {
7949 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
7950 return true;
7951 else
7952 return !kvm_event_needs_reinjection(vcpu) &&
7953 kvm_x86_ops->interrupt_allowed(vcpu);
7954 }
7955
7956 void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
7957 {
7958 atomic_inc(&kvm->arch.noncoherent_dma_count);
7959 }
7960 EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
7961
7962 void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
7963 {
7964 atomic_dec(&kvm->arch.noncoherent_dma_count);
7965 }
7966 EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
7967
7968 bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
7969 {
7970 return atomic_read(&kvm->arch.noncoherent_dma_count);
7971 }
7972 EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
7973
7974 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
7975 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
7976 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
7977 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
7978 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
7979 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
7980 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
7981 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
7982 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
7983 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
7984 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
7985 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
7986 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
7987 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window);
7988 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
Linux with added FPC-III support