drivers/clocksource/nomadik-mtu.c

   1 /*
   2  * Copyright (C) 2008 STMicroelectronics
   3  * Copyright (C) 2010 Alessandro Rubini
   4  * Copyright (C) 2010 Linus Walleij for ST-Ericsson
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2, as
   8  * published by the Free Software Foundation.
   9  */
  10 #include <linux/init.h>
  11 #include <linux/interrupt.h>
  12 #include <linux/irq.h>
  13 #include <linux/io.h>
  14 #include <linux/clockchips.h>
  15 #include <linux/clocksource.h>
  16 #include <linux/of_address.h>
  17 #include <linux/of_irq.h>
  18 #include <linux/of_platform.h>
  19 #include <linux/clk.h>
  20 #include <linux/jiffies.h>
  21 #include <linux/delay.h>
  22 #include <linux/err.h>
  23 #include <linux/sched_clock.h>
  24 #include <asm/mach/time.h>
  25
  26 /*
  27  * The MTU device hosts four different counters, with 4 set of
  28  * registers. These are register names.
  29  */
  30
  31 #define MTU_IMSC        0x00    /* Interrupt mask set/clear */
  32 #define MTU_RIS         0x04    /* Raw interrupt status */
  33 #define MTU_MIS         0x08    /* Masked interrupt status */
  34 #define MTU_ICR         0x0C    /* Interrupt clear register */
  35
  36 /* per-timer registers take 0..3 as argument */
  37 #define MTU_LR(x)       (0x10 + 0x10 * (x) + 0x00)      /* Load value */
  38 #define MTU_VAL(x)      (0x10 + 0x10 * (x) + 0x04)      /* Current value */
  39 #define MTU_CR(x)       (0x10 + 0x10 * (x) + 0x08)      /* Control reg */
  40 #define MTU_BGLR(x)     (0x10 + 0x10 * (x) + 0x0c)      /* At next overflow */
  41
  42 /* bits for the control register */
  43 #define MTU_CRn_ENA             0x80
  44 #define MTU_CRn_PERIODIC        0x40    /* if 0 = free-running */
  45 #define MTU_CRn_PRESCALE_MASK   0x0c
  46 #define MTU_CRn_PRESCALE_1              0x00
  47 #define MTU_CRn_PRESCALE_16             0x04
  48 #define MTU_CRn_PRESCALE_256            0x08
  49 #define MTU_CRn_32BITS          0x02
  50 #define MTU_CRn_ONESHOT         0x01    /* if 0 = wraps reloading from BGLR*/
  51
  52 /* Other registers are usual amba/primecell registers, currently not used */
  53 #define MTU_ITCR        0xff0
  54 #define MTU_ITOP        0xff4
  55
  56 #define MTU_PERIPH_ID0  0xfe0
  57 #define MTU_PERIPH_ID1  0xfe4
  58 #define MTU_PERIPH_ID2  0xfe8
  59 #define MTU_PERIPH_ID3  0xfeC
  60
  61 #define MTU_PCELL0      0xff0
  62 #define MTU_PCELL1      0xff4
  63 #define MTU_PCELL2      0xff8
  64 #define MTU_PCELL3      0xffC
  65
  66 static void __iomem *mtu_base;
  67 static bool clkevt_periodic;
  68 static u32 clk_prescale;
  69 static u32 nmdk_cycle;          /* write-once */
  70 static struct delay_timer mtu_delay_timer;
  71
  72 /*
  73  * Override the global weak sched_clock symbol with this
  74  * local implementation which uses the clocksource to get some
  75  * better resolution when scheduling the kernel.
  76  */
  77 static u64 notrace nomadik_read_sched_clock(void)
  78 {
  79         if (unlikely(!mtu_base))
  80                 return 0;
  81
  82         return -readl(mtu_base + MTU_VAL(0));
  83 }
  84
  85 static unsigned long nmdk_timer_read_current_timer(void)
  86 {
  87         return ~readl_relaxed(mtu_base + MTU_VAL(0));
  88 }
  89
  90 /* Clockevent device: use one-shot mode */
  91 static int nmdk_clkevt_next(unsigned long evt, struct clock_event_device *ev)
  92 {
  93         writel(1 << 1, mtu_base + MTU_IMSC);
  94         writel(evt, mtu_base + MTU_LR(1));
  95         /* Load highest value, enable device, enable interrupts */
  96         writel(MTU_CRn_ONESHOT | clk_prescale |
  97                MTU_CRn_32BITS | MTU_CRn_ENA,
  98                mtu_base + MTU_CR(1));
  99
 100         return 0;
 101 }
 102
 103 static void nmdk_clkevt_reset(void)
 104 {
 105         if (clkevt_periodic) {
 106                 /* Timer: configure load and background-load, and fire it up */
 107                 writel(nmdk_cycle, mtu_base + MTU_LR(1));
 108                 writel(nmdk_cycle, mtu_base + MTU_BGLR(1));
 109
 110                 writel(MTU_CRn_PERIODIC | clk_prescale |
 111                        MTU_CRn_32BITS | MTU_CRn_ENA,
 112                        mtu_base + MTU_CR(1));
 113                 writel(1 << 1, mtu_base + MTU_IMSC);
 114         } else {
 115                 /* Generate an interrupt to start the clockevent again */
 116                 (void) nmdk_clkevt_next(nmdk_cycle, NULL);
 117         }
 118 }
 119
 120 static int nmdk_clkevt_shutdown(struct clock_event_device *evt)
 121 {
 122         writel(0, mtu_base + MTU_IMSC);
 123         /* disable timer */
 124         writel(0, mtu_base + MTU_CR(1));
 125         /* load some high default value */
 126         writel(0xffffffff, mtu_base + MTU_LR(1));
 127         return 0;
 128 }
 129
 130 static int nmdk_clkevt_set_oneshot(struct clock_event_device *evt)
 131 {
 132         clkevt_periodic = false;
 133         return 0;
 134 }
 135
 136 static int nmdk_clkevt_set_periodic(struct clock_event_device *evt)
 137 {
 138         clkevt_periodic = true;
 139         nmdk_clkevt_reset();
 140         return 0;
 141 }
 142
 143 static void nmdk_clksrc_reset(void)
 144 {
 145         /* Disable */
 146         writel(0, mtu_base + MTU_CR(0));
 147
 148         /* ClockSource: configure load and background-load, and fire it up */
 149         writel(nmdk_cycle, mtu_base + MTU_LR(0));
 150         writel(nmdk_cycle, mtu_base + MTU_BGLR(0));
 151
 152         writel(clk_prescale | MTU_CRn_32BITS | MTU_CRn_ENA,
 153                mtu_base + MTU_CR(0));
 154 }
 155
 156 static void nmdk_clkevt_resume(struct clock_event_device *cedev)
 157 {
 158         nmdk_clkevt_reset();
 159         nmdk_clksrc_reset();
 160 }
 161
 162 static struct clock_event_device nmdk_clkevt = {
 163         .name                   = "mtu_1",
 164         .features               = CLOCK_EVT_FEAT_ONESHOT |
 165                                   CLOCK_EVT_FEAT_PERIODIC |
 166                                   CLOCK_EVT_FEAT_DYNIRQ,
 167         .rating                 = 200,
 168         .set_state_shutdown     = nmdk_clkevt_shutdown,
 169         .set_state_periodic     = nmdk_clkevt_set_periodic,
 170         .set_state_oneshot      = nmdk_clkevt_set_oneshot,
 171         .set_next_event         = nmdk_clkevt_next,
 172         .resume                 = nmdk_clkevt_resume,
 173 };
 174
 175 /*
 176  * IRQ Handler for timer 1 of the MTU block.
 177  */
 178 static irqreturn_t nmdk_timer_interrupt(int irq, void *dev_id)
 179 {
 180         struct clock_event_device *evdev = dev_id;
 181
 182         writel(1 << 1, mtu_base + MTU_ICR); /* Interrupt clear reg */
 183         evdev->event_handler(evdev);
 184         return IRQ_HANDLED;
 185 }
 186
 187 static struct irqaction nmdk_timer_irq = {
 188         .name           = "Nomadik Timer Tick",
 189         .flags          = IRQF_TIMER,
 190         .handler        = nmdk_timer_interrupt,
 191         .dev_id         = &nmdk_clkevt,
 192 };
 193
 194 static int __init nmdk_timer_init(void __iomem *base, int irq,
 195                                    struct clk *pclk, struct clk *clk)
 196 {
 197         unsigned long rate;
 198         int ret;
 199
 200         mtu_base = base;
 201
 202         BUG_ON(clk_prepare_enable(pclk));
 203         BUG_ON(clk_prepare_enable(clk));
 204
 205         /*
 206          * Tick rate is 2.4MHz for Nomadik and 2.4Mhz, 100MHz or 133 MHz
 207          * for ux500.
 208          * Use a divide-by-16 counter if the tick rate is more than 32MHz.
 209          * At 32 MHz, the timer (with 32 bit counter) can be programmed
 210          * to wake-up at a max 127s a head in time. Dividing a 2.4 MHz timer
 211          * with 16 gives too low timer resolution.
 212          */
 213         rate = clk_get_rate(clk);
 214         if (rate > 32000000) {
 215                 rate /= 16;
 216                 clk_prescale = MTU_CRn_PRESCALE_16;
 217         } else {
 218                 clk_prescale = MTU_CRn_PRESCALE_1;
 219         }
 220
 221         /* Cycles for periodic mode */
 222         nmdk_cycle = DIV_ROUND_CLOSEST(rate, HZ);
 223
 224
 225         /* Timer 0 is the free running clocksource */
 226         nmdk_clksrc_reset();
 227
 228         ret = clocksource_mmio_init(mtu_base + MTU_VAL(0), "mtu_0",
 229                                     rate, 200, 32, clocksource_mmio_readl_down);
 230         if (ret) {
 231                 pr_err("timer: failed to initialize clock source %s\n", "mtu_0");
 232                 return ret;
 233         }
 234
 235         sched_clock_register(nomadik_read_sched_clock, 32, rate);
 236
 237         /* Timer 1 is used for events, register irq and clockevents */
 238         setup_irq(irq, &nmdk_timer_irq);
 239         nmdk_clkevt.cpumask = cpumask_of(0);
 240         nmdk_clkevt.irq = irq;
 241         clockevents_config_and_register(&nmdk_clkevt, rate, 2, 0xffffffffU);
 242
 243         mtu_delay_timer.read_current_timer = &nmdk_timer_read_current_timer;
 244         mtu_delay_timer.freq = rate;
 245         register_current_timer_delay(&mtu_delay_timer);
 246
 247         return 0;
 248 }
 249
 250 static int __init nmdk_timer_of_init(struct device_node *node)
 251 {
 252         struct clk *pclk;
 253         struct clk *clk;
 254         void __iomem *base;
 255         int irq;
 256
 257         base = of_iomap(node, 0);
 258         if (!base) {
 259                 pr_err("Can't remap registers\n");
 260                 return -ENXIO;
 261         }
 262
 263         pclk = of_clk_get_by_name(node, "apb_pclk");
 264         if (IS_ERR(pclk)) {
 265                 pr_err("could not get apb_pclk\n");
 266                 return PTR_ERR(pclk);
 267         }
 268
 269         clk = of_clk_get_by_name(node, "timclk");
 270         if (IS_ERR(clk)) {
 271                 pr_err("could not get timclk\n");
 272                 return PTR_ERR(clk);
 273         }
 274
 275         irq = irq_of_parse_and_map(node, 0);
 276         if (irq <= 0) {
 277                 pr_err("Can't parse IRQ\n");
 278                 return -EINVAL;
 279         }
 280
 281         return nmdk_timer_init(base, irq, pclk, clk);
 282 }
 283 TIMER_OF_DECLARE(nomadik_mtu, "st,nomadik-mtu",
 284                        nmdk_timer_of_init);