drivers/crypto/cavium/nitrox/nitrox_csr.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 #ifndef __NITROX_CSR_H
   3 #define __NITROX_CSR_H
   4
   5 #include <asm/byteorder.h>
   6 #include <linux/types.h>
   7
   8 /* EMU clusters */
   9 #define NR_CLUSTERS             4
  10 /* Maximum cores per cluster,
  11  * varies based on partname
  12  */
  13 #define AE_CORES_PER_CLUSTER    20
  14 #define SE_CORES_PER_CLUSTER    16
  15
  16 #define AE_MAX_CORES    (AE_CORES_PER_CLUSTER * NR_CLUSTERS)
  17 #define SE_MAX_CORES    (SE_CORES_PER_CLUSTER * NR_CLUSTERS)
  18 #define ZIP_MAX_CORES   5
  19
  20 /* BIST registers */
  21 #define EMU_BIST_STATUSX(_i)    (0x1402700 + ((_i) * 0x40000))
  22 #define UCD_BIST_STATUS         0x12C0070
  23 #define NPS_CORE_BIST_REG       0x10000E8
  24 #define NPS_CORE_NPC_BIST_REG   0x1000128
  25 #define NPS_PKT_SLC_BIST_REG    0x1040088
  26 #define NPS_PKT_IN_BIST_REG     0x1040100
  27 #define POM_BIST_REG            0x11C0100
  28 #define BMI_BIST_REG            0x1140080
  29 #define EFL_CORE_BIST_REGX(_i)  (0x1240100 + ((_i) * 0x400))
  30 #define EFL_TOP_BIST_STAT       0x1241090
  31 #define BMO_BIST_REG            0x1180080
  32 #define LBC_BIST_STATUS         0x1200020
  33 #define PEM_BIST_STATUSX(_i)    (0x1080468 | ((_i) << 18))
  34
  35 /* EMU registers */
  36 #define EMU_SE_ENABLEX(_i)      (0x1400000 + ((_i) * 0x40000))
  37 #define EMU_AE_ENABLEX(_i)      (0x1400008 + ((_i) * 0x40000))
  38 #define EMU_WD_INT_ENA_W1SX(_i) (0x1402318 + ((_i) * 0x40000))
  39 #define EMU_GE_INT_ENA_W1SX(_i) (0x1402518 + ((_i) * 0x40000))
  40 #define EMU_FUSE_MAPX(_i)       (0x1402708 + ((_i) * 0x40000))
  41
  42 /* UCD registers */
  43 #define UCD_UCODE_LOAD_BLOCK_NUM        0x12C0010
  44 #define UCD_UCODE_LOAD_IDX_DATAX(_i)    (0x12C0018 + ((_i) * 0x20))
  45 #define UCD_SE_EID_UCODE_BLOCK_NUMX(_i) (0x12C0000 + ((_i) * 0x1000))
  46
  47 /* NPS core registers */
  48 #define NPS_CORE_GBL_VFCFG      0x1000000
  49 #define NPS_CORE_CONTROL        0x1000008
  50 #define NPS_CORE_INT_ACTIVE     0x1000080
  51 #define NPS_CORE_INT            0x10000A0
  52 #define NPS_CORE_INT_ENA_W1S    0x10000B8
  53 #define NPS_STATS_PKT_DMA_RD_CNT        0x1000180
  54 #define NPS_STATS_PKT_DMA_WR_CNT        0x1000190
  55
  56 /* NPS packet registers */
  57 #define NPS_PKT_INT                     0x1040018
  58 #define NPS_PKT_MBOX_INT_LO             0x1040020
  59 #define NPS_PKT_MBOX_INT_LO_ENA_W1C     0x1040030
  60 #define NPS_PKT_MBOX_INT_LO_ENA_W1S     0x1040038
  61 #define NPS_PKT_MBOX_INT_HI             0x1040040
  62 #define NPS_PKT_MBOX_INT_HI_ENA_W1C     0x1040050
  63 #define NPS_PKT_MBOX_INT_HI_ENA_W1S     0x1040058
  64 #define NPS_PKT_IN_RERR_HI              0x1040108
  65 #define NPS_PKT_IN_RERR_HI_ENA_W1S      0x1040120
  66 #define NPS_PKT_IN_RERR_LO              0x1040128
  67 #define NPS_PKT_IN_RERR_LO_ENA_W1S      0x1040140
  68 #define NPS_PKT_IN_ERR_TYPE             0x1040148
  69 #define NPS_PKT_IN_ERR_TYPE_ENA_W1S     0x1040160
  70 #define NPS_PKT_IN_INSTR_CTLX(_i)       (0x10060 + ((_i) * 0x40000))
  71 #define NPS_PKT_IN_INSTR_BADDRX(_i)     (0x10068 + ((_i) * 0x40000))
  72 #define NPS_PKT_IN_INSTR_RSIZEX(_i)     (0x10070 + ((_i) * 0x40000))
  73 #define NPS_PKT_IN_DONE_CNTSX(_i)       (0x10080 + ((_i) * 0x40000))
  74 #define NPS_PKT_IN_INSTR_BAOFF_DBELLX(_i)       (0x10078 + ((_i) * 0x40000))
  75 #define NPS_PKT_IN_INT_LEVELSX(_i)              (0x10088 + ((_i) * 0x40000))
  76
  77 #define NPS_PKT_SLC_RERR_HI             0x1040208
  78 #define NPS_PKT_SLC_RERR_HI_ENA_W1S     0x1040220
  79 #define NPS_PKT_SLC_RERR_LO             0x1040228
  80 #define NPS_PKT_SLC_RERR_LO_ENA_W1S     0x1040240
  81 #define NPS_PKT_SLC_ERR_TYPE            0x1040248
  82 #define NPS_PKT_SLC_ERR_TYPE_ENA_W1S    0x1040260
  83 /* Mailbox PF->VF PF Accessible Data registers */
  84 #define NPS_PKT_MBOX_PF_VF_PFDATAX(_i)  (0x1040800 + ((_i) * 0x8))
  85 #define NPS_PKT_MBOX_VF_PF_PFDATAX(_i)  (0x1040C00 + ((_i) * 0x8))
  86
  87 #define NPS_PKT_SLC_CTLX(_i)            (0x10000 + ((_i) * 0x40000))
  88 #define NPS_PKT_SLC_CNTSX(_i)           (0x10008 + ((_i) * 0x40000))
  89 #define NPS_PKT_SLC_INT_LEVELSX(_i)     (0x10010 + ((_i) * 0x40000))
  90
  91 /* POM registers */
  92 #define POM_INT_ENA_W1S         0x11C0018
  93 #define POM_GRP_EXECMASKX(_i)   (0x11C1100 | ((_i) * 8))
  94 #define POM_INT         0x11C0000
  95 #define POM_PERF_CTL    0x11CC400
  96
  97 /* BMI registers */
  98 #define BMI_INT         0x1140000
  99 #define BMI_CTL         0x1140020
 100 #define BMI_INT_ENA_W1S 0x1140018
 101 #define BMI_NPS_PKT_CNT 0x1140070
 102
 103 /* EFL registers */
 104 #define EFL_CORE_INT_ENA_W1SX(_i)               (0x1240018 + ((_i) * 0x400))
 105 #define EFL_CORE_VF_ERR_INT0X(_i)               (0x1240050 + ((_i) * 0x400))
 106 #define EFL_CORE_VF_ERR_INT0_ENA_W1SX(_i)       (0x1240068 + ((_i) * 0x400))
 107 #define EFL_CORE_VF_ERR_INT1X(_i)               (0x1240070 + ((_i) * 0x400))
 108 #define EFL_CORE_VF_ERR_INT1_ENA_W1SX(_i)       (0x1240088 + ((_i) * 0x400))
 109 #define EFL_CORE_SE_ERR_INTX(_i)                (0x12400A0 + ((_i) * 0x400))
 110 #define EFL_RNM_CTL_STATUS                      0x1241800
 111 #define EFL_CORE_INTX(_i)                       (0x1240000 + ((_i) * 0x400))
 112
 113 /* BMO registers */
 114 #define BMO_CTL2                0x1180028
 115 #define BMO_NPS_SLC_PKT_CNT     0x1180078
 116
 117 /* LBC registers */
 118 #define LBC_INT                 0x1200000
 119 #define LBC_INVAL_CTL           0x1201010
 120 #define LBC_PLM_VF1_64_INT      0x1202008
 121 #define LBC_INVAL_STATUS        0x1202010
 122 #define LBC_INT_ENA_W1S         0x1203000
 123 #define LBC_PLM_VF1_64_INT_ENA_W1S      0x1205008
 124 #define LBC_PLM_VF65_128_INT            0x1206008
 125 #define LBC_ELM_VF1_64_INT              0x1208000
 126 #define LBC_PLM_VF65_128_INT_ENA_W1S    0x1209008
 127 #define LBC_ELM_VF1_64_INT_ENA_W1S      0x120B000
 128 #define LBC_ELM_VF65_128_INT            0x120C000
 129 #define LBC_ELM_VF65_128_INT_ENA_W1S    0x120F000
 130
 131 #define RST_BOOT        0x10C1600
 132 #define FUS_DAT1        0x10C1408
 133
 134 /* PEM registers */
 135 #define PEM0_INT 0x1080428
 136
 137 /**
 138  * struct emu_fuse_map - EMU Fuse Map Registers
 139  * @ae_fuse: Fuse settings for AE 19..0
 140  * @se_fuse: Fuse settings for SE 15..0
 141  *
 142  * A set bit indicates the unit is fuse disabled.
 143  */
 144 union emu_fuse_map {
 145         u64 value;
 146         struct {
 147 #if (defined(__BIG_ENDIAN_BITFIELD))
 148                 u64 valid : 1;
 149                 u64 raz_52_62 : 11;
 150                 u64 ae_fuse : 20;
 151                 u64 raz_16_31 : 16;
 152                 u64 se_fuse : 16;
 153 #else
 154                 u64 se_fuse : 16;
 155                 u64 raz_16_31 : 16;
 156                 u64 ae_fuse : 20;
 157                 u64 raz_52_62 : 11;
 158                 u64 valid : 1;
 159 #endif
 160         } s;
 161 };
 162
 163 /**
 164  * struct emu_se_enable - Symmetric Engine Enable Registers
 165  * @enable: Individual enables for each of the clusters
 166  *   16 symmetric engines.
 167  */
 168 union emu_se_enable {
 169         u64 value;
 170         struct {
 171 #if (defined(__BIG_ENDIAN_BITFIELD))
 172                 u64 raz : 48;
 173                 u64 enable : 16;
 174 #else
 175                 u64 enable : 16;
 176                 u64 raz : 48;
 177 #endif
 178         } s;
 179 };
 180
 181 /**
 182  * struct emu_ae_enable - EMU Asymmetric engines.
 183  * @enable: Individual enables for each of the cluster's
 184  *   20 Asymmetric Engines.
 185  */
 186 union emu_ae_enable {
 187         u64 value;
 188         struct {
 189 #if (defined(__BIG_ENDIAN_BITFIELD))
 190                 u64 raz : 44;
 191                 u64 enable : 20;
 192 #else
 193                 u64 enable : 20;
 194                 u64 raz : 44;
 195 #endif
 196         } s;
 197 };
 198
 199 /**
 200  * struct emu_wd_int_ena_w1s - EMU Interrupt Enable Registers
 201  * @ae_wd: Reads or sets enable for EMU(0..3)_WD_INT[AE_WD]
 202  * @se_wd: Reads or sets enable for EMU(0..3)_WD_INT[SE_WD]
 203  */
 204 union emu_wd_int_ena_w1s {
 205         u64 value;
 206         struct {
 207 #if (defined(__BIG_ENDIAN_BITFIELD))
 208                 u64 raz2 : 12;
 209                 u64 ae_wd : 20;
 210                 u64 raz1 : 16;
 211                 u64 se_wd : 16;
 212 #else
 213                 u64 se_wd : 16;
 214                 u64 raz1 : 16;
 215                 u64 ae_wd : 20;
 216                 u64 raz2 : 12;
 217 #endif
 218         } s;
 219 };
 220
 221 /**
 222  * struct emu_ge_int_ena_w1s - EMU Interrupt Enable set registers
 223  * @ae_ge: Reads or sets enable for EMU(0..3)_GE_INT[AE_GE]
 224  * @se_ge: Reads or sets enable for EMU(0..3)_GE_INT[SE_GE]
 225  */
 226 union emu_ge_int_ena_w1s {
 227         u64 value;
 228         struct {
 229 #if (defined(__BIG_ENDIAN_BITFIELD))
 230                 u64 raz_52_63 : 12;
 231                 u64 ae_ge : 20;
 232                 u64 raz_16_31: 16;
 233                 u64 se_ge : 16;
 234 #else
 235                 u64 se_ge : 16;
 236                 u64 raz_16_31: 16;
 237                 u64 ae_ge : 20;
 238                 u64 raz_52_63 : 12;
 239 #endif
 240         } s;
 241 };
 242
 243 /**
 244  * struct nps_pkt_slc_ctl - Solicited Packet Out Control Registers
 245  * @rh: Indicates whether to remove or include the response header
 246  *   1 = Include, 0 = Remove
 247  * @z: If set, 8 trailing 0x00 bytes will be added to the end of the
 248  *   outgoing packet.
 249  * @enb: Enable for this port.
 250  */
 251 union nps_pkt_slc_ctl {
 252         u64 value;
 253         struct {
 254 #if defined(__BIG_ENDIAN_BITFIELD)
 255                 u64 raz : 61;
 256                 u64 rh : 1;
 257                 u64 z : 1;
 258                 u64 enb : 1;
 259 #else
 260                 u64 enb : 1;
 261                 u64 z : 1;
 262                 u64 rh : 1;
 263                 u64 raz : 61;
 264 #endif
 265         } s;
 266 };
 267
 268 /**
 269  * struct nps_pkt_slc_cnts - Solicited Packet Out Count Registers
 270  * @slc_int: Returns a 1 when:
 271  *   NPS_PKT_SLC(i)_CNTS[CNT] > NPS_PKT_SLC(i)_INT_LEVELS[CNT], or
 272  *   NPS_PKT_SLC(i)_CNTS[TIMER] > NPS_PKT_SLC(i)_INT_LEVELS[TIMET].
 273  *   To clear the bit, the CNTS register must be written to clear.
 274  * @in_int: Returns a 1 when:
 275  *   NPS_PKT_IN(i)_DONE_CNTS[CNT] > NPS_PKT_IN(i)_INT_LEVELS[CNT].
 276  *   To clear the bit, the DONE_CNTS register must be written to clear.
 277  * @mbox_int: Returns a 1 when:
 278  *   NPS_PKT_MBOX_PF_VF(i)_INT[INTR] is set. To clear the bit,
 279  *   write NPS_PKT_MBOX_PF_VF(i)_INT[INTR] with 1.
 280  * @timer: Timer, incremented every 2048 coprocessor clock cycles
 281  *   when [CNT] is not zero. The hardware clears both [TIMER] and
 282  *   [INT] when [CNT] goes to 0.
 283  * @cnt: Packet counter. Hardware adds to [CNT] as it sends packets out.
 284  *   On a write to this CSR, hardware subtracts the amount written to the
 285  *   [CNT] field from [CNT].
 286  */
 287 union nps_pkt_slc_cnts {
 288         u64 value;
 289         struct {
 290 #if defined(__BIG_ENDIAN_BITFIELD)
 291                 u64 slc_int : 1;
 292                 u64 uns_int : 1;
 293                 u64 in_int : 1;
 294                 u64 mbox_int : 1;
 295                 u64 resend : 1;
 296                 u64 raz : 5;
 297                 u64 timer : 22;
 298                 u64 cnt : 32;
 299 #else
 300                 u64 cnt : 32;
 301                 u64 timer : 22;
 302                 u64 raz : 5;
 303                 u64 resend : 1;
 304                 u64 mbox_int : 1;
 305                 u64 in_int : 1;
 306                 u64 uns_int : 1;
 307                 u64 slc_int : 1;
 308 #endif
 309         } s;
 310 };
 311
 312 /**
 313  * struct nps_pkt_slc_int_levels - Solicited Packet Out Interrupt Levels
 314  *   Registers.
 315  * @bmode: Determines whether NPS_PKT_SLC_CNTS[CNT] is a byte or
 316  *   packet counter.
 317  * @timet: Output port counter time interrupt threshold.
 318  * @cnt: Output port counter interrupt threshold.
 319  */
 320 union nps_pkt_slc_int_levels {
 321         u64 value;
 322         struct {
 323 #if defined(__BIG_ENDIAN_BITFIELD)
 324                 u64 bmode : 1;
 325                 u64 raz : 9;
 326                 u64 timet : 22;
 327                 u64 cnt : 32;
 328 #else
 329                 u64 cnt : 32;
 330                 u64 timet : 22;
 331                 u64 raz : 9;
 332                 u64 bmode : 1;
 333 #endif
 334         } s;
 335 };
 336
 337 /**
 338  * struct nps_pkt_inst - NPS Packet Interrupt Register
 339  * @in_err: Set when any NPS_PKT_IN_RERR_HI/LO bit and
 340  *    corresponding NPS_PKT_IN_RERR_*_ENA_* bit are bot set.
 341  * @uns_err: Set when any NSP_PKT_UNS_RERR_HI/LO bit and
 342  *    corresponding NPS_PKT_UNS_RERR_*_ENA_* bit are both set.
 343  * @slc_er: Set when any NSP_PKT_SLC_RERR_HI/LO bit and
 344  *    corresponding NPS_PKT_SLC_RERR_*_ENA_* bit are both set.
 345  */
 346 union nps_pkt_int {
 347         u64 value;
 348         struct {
 349 #if defined(__BIG_ENDIAN_BITFIELD)
 350                 u64 raz : 54;
 351                 u64 uns_wto : 1;
 352                 u64 in_err : 1;
 353                 u64 uns_err : 1;
 354                 u64 slc_err : 1;
 355                 u64 in_dbe : 1;
 356                 u64 in_sbe : 1;
 357                 u64 uns_dbe : 1;
 358                 u64 uns_sbe : 1;
 359                 u64 slc_dbe : 1;
 360                 u64 slc_sbe : 1;
 361 #else
 362                 u64 slc_sbe : 1;
 363                 u64 slc_dbe : 1;
 364                 u64 uns_sbe : 1;
 365                 u64 uns_dbe : 1;
 366                 u64 in_sbe : 1;
 367                 u64 in_dbe : 1;
 368                 u64 slc_err : 1;
 369                 u64 uns_err : 1;
 370                 u64 in_err : 1;
 371                 u64 uns_wto : 1;
 372                 u64 raz : 54;
 373 #endif
 374         } s;
 375 };
 376
 377 /**
 378  * struct nps_pkt_in_done_cnts - Input instruction ring counts registers
 379  * @slc_cnt: Returns a 1 when:
 380  *    NPS_PKT_SLC(i)_CNTS[CNT] > NPS_PKT_SLC(i)_INT_LEVELS[CNT], or
 381  *    NPS_PKT_SLC(i)_CNTS[TIMER] > NPS_PKT_SCL(i)_INT_LEVELS[TIMET]
 382  *    To clear the bit, the CNTS register must be
 383  *    written to clear the underlying condition
 384  * @uns_int: Return a 1 when:
 385  *    NPS_PKT_UNS(i)_CNTS[CNT] > NPS_PKT_UNS(i)_INT_LEVELS[CNT], or
 386  *    NPS_PKT_UNS(i)_CNTS[TIMER] > NPS_PKT_UNS(i)_INT_LEVELS[TIMET]
 387  *    To clear the bit, the CNTS register must be
 388  *    written to clear the underlying condition
 389  * @in_int: Returns a 1 when:
 390  *    NPS_PKT_IN(i)_DONE_CNTS[CNT] > NPS_PKT_IN(i)_INT_LEVELS[CNT]
 391  *    To clear the bit, the DONE_CNTS register
 392  *    must be written to clear the underlying condition
 393  * @mbox_int: Returns a 1 when:
 394  *    NPS_PKT_MBOX_PF_VF(i)_INT[INTR] is set.
 395  *    To clear the bit, write NPS_PKT_MBOX_PF_VF(i)_INT[INTR]
 396  *    with 1.
 397  * @resend: A write of 1 will resend an MSI-X interrupt message if any
 398  *    of the following conditions are true for this ring "i".
 399  *    NPS_PKT_SLC(i)_CNTS[CNT] > NPS_PKT_SLC(i)_INT_LEVELS[CNT]
 400  *    NPS_PKT_SLC(i)_CNTS[TIMER] > NPS_PKT_SLC(i)_INT_LEVELS[TIMET]
 401  *    NPS_PKT_UNS(i)_CNTS[CNT] > NPS_PKT_UNS(i)_INT_LEVELS[CNT]
 402  *    NPS_PKT_UNS(i)_CNTS[TIMER] > NPS_PKT_UNS(i)_INT_LEVELS[TIMET]
 403  *    NPS_PKT_IN(i)_DONE_CNTS[CNT] > NPS_PKT_IN(i)_INT_LEVELS[CNT]
 404  *    NPS_PKT_MBOX_PF_VF(i)_INT[INTR] is set
 405  * @cnt: Packet counter. Hardware adds to [CNT] as it reads
 406  *    packets. On a write to this CSR, hardware substracts the
 407  *    amount written to the [CNT] field from [CNT], which will
 408  *    clear PKT_IN(i)_INT_STATUS[INTR] if [CNT] becomes <=
 409  *    NPS_PKT_IN(i)_INT_LEVELS[CNT]. This register should be
 410  *    cleared before enabling a ring by reading the current
 411  *    value and writing it back.
 412  */
 413 union nps_pkt_in_done_cnts {
 414         u64 value;
 415         struct {
 416 #if defined(__BIG_ENDIAN_BITFIELD)
 417                 u64 slc_int : 1;
 418                 u64 uns_int : 1;
 419                 u64 in_int : 1;
 420                 u64 mbox_int : 1;
 421                 u64 resend : 1;
 422                 u64 raz : 27;
 423                 u64 cnt : 32;
 424 #else
 425                 u64 cnt : 32;
 426                 u64 raz : 27;
 427                 u64 resend : 1;
 428                 u64 mbox_int : 1;
 429                 u64 in_int : 1;
 430                 u64 uns_int : 1;
 431                 u64 slc_int : 1;
 432 #endif
 433         } s;
 434 };
 435
 436 /**
 437  * struct nps_pkt_in_instr_ctl - Input Instruction Ring Control Registers.
 438  * @is64b: If 1, the ring uses 64-byte instructions. If 0, the
 439  *   ring uses 32-byte instructions.
 440  * @enb: Enable for the input ring.
 441  */
 442 union nps_pkt_in_instr_ctl {
 443         u64 value;
 444         struct {
 445 #if (defined(__BIG_ENDIAN_BITFIELD))
 446                 u64 raz : 62;
 447                 u64 is64b : 1;
 448                 u64 enb : 1;
 449 #else
 450                 u64 enb : 1;
 451                 u64 is64b : 1;
 452                 u64 raz : 62;
 453 #endif
 454         } s;
 455 };
 456
 457 /**
 458  * struct nps_pkt_in_instr_rsize - Input instruction ring size registers
 459  * @rsize: Ring size (number of instructions)
 460  */
 461 union nps_pkt_in_instr_rsize {
 462         u64 value;
 463         struct {
 464 #if (defined(__BIG_ENDIAN_BITFIELD))
 465                 u64 raz : 32;
 466                 u64 rsize : 32;
 467 #else
 468                 u64 rsize : 32;
 469                 u64 raz : 32;
 470 #endif
 471         } s;
 472 };
 473
 474 /**
 475  * struct nps_pkt_in_instr_baoff_dbell - Input instruction ring
 476  *   base address offset and doorbell registers
 477  * @aoff: Address offset. The offset from the NPS_PKT_IN_INSTR_BADDR
 478  *   where the next pointer is read.
 479  * @dbell: Pointer list doorbell count. Write operations to this field
 480  *   increments the present value here. Read operations return the
 481  *   present value.
 482  */
 483 union nps_pkt_in_instr_baoff_dbell {
 484         u64 value;
 485         struct {
 486 #if (defined(__BIG_ENDIAN_BITFIELD))
 487                 u64 aoff : 32;
 488                 u64 dbell : 32;
 489 #else
 490                 u64 dbell : 32;
 491                 u64 aoff : 32;
 492 #endif
 493         } s;
 494 };
 495
 496 /**
 497  * struct nps_core_int_ena_w1s - NPS core interrupt enable set register
 498  * @host_nps_wr_err: Reads or sets enable for
 499  *   NPS_CORE_INT[HOST_NPS_WR_ERR].
 500  * @npco_dma_malform: Reads or sets enable for
 501  *   NPS_CORE_INT[NPCO_DMA_MALFORM].
 502  * @exec_wr_timeout: Reads or sets enable for
 503  *   NPS_CORE_INT[EXEC_WR_TIMEOUT].
 504  * @host_wr_timeout: Reads or sets enable for
 505  *   NPS_CORE_INT[HOST_WR_TIMEOUT].
 506  * @host_wr_err: Reads or sets enable for
 507  *   NPS_CORE_INT[HOST_WR_ERR]
 508  */
 509 union nps_core_int_ena_w1s {
 510         u64 value;
 511         struct {
 512 #if (defined(__BIG_ENDIAN_BITFIELD))
 513                 u64 raz4 : 55;
 514                 u64 host_nps_wr_err : 1;
 515                 u64 npco_dma_malform : 1;
 516                 u64 exec_wr_timeout : 1;
 517                 u64 host_wr_timeout : 1;
 518                 u64 host_wr_err : 1;
 519                 u64 raz3 : 1;
 520                 u64 raz2 : 1;
 521                 u64 raz1 : 1;
 522                 u64 raz0 : 1;
 523 #else
 524                 u64 raz0 : 1;
 525                 u64 raz1 : 1;
 526                 u64 raz2 : 1;
 527                 u64 raz3 : 1;
 528                 u64 host_wr_err : 1;
 529                 u64 host_wr_timeout : 1;
 530                 u64 exec_wr_timeout : 1;
 531                 u64 npco_dma_malform : 1;
 532                 u64 host_nps_wr_err : 1;
 533                 u64 raz4 : 55;
 534 #endif
 535         } s;
 536 };
 537
 538 /**
 539  * struct nps_core_gbl_vfcfg - Global VF Configuration Register.
 540  * @ilk_disable: When set, this bit indicates that the ILK interface has
 541  *    been disabled.
 542  * @obaf: BMO allocation control
 543  *    0 = allocate per queue
 544  *    1 = allocate per VF
 545  * @ibaf: BMI allocation control
 546  *    0 = allocate per queue
 547  *    1 = allocate per VF
 548  * @zaf: ZIP allocation control
 549  *    0 = allocate per queue
 550  *    1 = allocate per VF
 551  * @aeaf: AE allocation control
 552  *    0 = allocate per queue
 553  *    1 = allocate per VF
 554  * @seaf: SE allocation control
 555  *    0 = allocation per queue
 556  *    1 = allocate per VF
 557  * @cfg: VF/PF mode.
 558  */
 559 union nps_core_gbl_vfcfg {
 560         u64 value;
 561         struct {
 562 #if (defined(__BIG_ENDIAN_BITFIELD))
 563                 u64  raz :55;
 564                 u64  ilk_disable :1;
 565                 u64  obaf :1;
 566                 u64  ibaf :1;
 567                 u64  zaf :1;
 568                 u64  aeaf :1;
 569                 u64  seaf :1;
 570                 u64  cfg :3;
 571 #else
 572                 u64  cfg :3;
 573                 u64  seaf :1;
 574                 u64  aeaf :1;
 575                 u64  zaf :1;
 576                 u64  ibaf :1;
 577                 u64  obaf :1;
 578                 u64  ilk_disable :1;
 579                 u64  raz :55;
 580 #endif
 581         } s;
 582 };
 583
 584 /**
 585  * struct nps_core_int_active - NPS Core Interrupt Active Register
 586  * @resend: Resend MSI-X interrupt if needs to handle interrupts
 587  *    Sofware can set this bit and then exit the ISR.
 588  * @ocla: Set when any OCLA(0)_INT and corresponding OCLA(0_INT_ENA_W1C
 589  *    bit are set
 590  * @mbox: Set when any NPS_PKT_MBOX_INT_LO/HI and corresponding
 591  *    NPS_PKT_MBOX_INT_LO_ENA_W1C/HI_ENA_W1C bits are set
 592  * @emu: bit i is set in [EMU] when any EMU(i)_INT bit is set
 593  * @bmo: Set when any BMO_INT bit is set
 594  * @bmi: Set when any BMI_INT bit is set or when any non-RO
 595  *    BMI_INT and corresponding BMI_INT_ENA_W1C bits are both set
 596  * @aqm: Set when any AQM_INT bit is set
 597  * @zqm: Set when any ZQM_INT bit is set
 598  * @efl: Set when any EFL_INT RO bit is set or when any non-RO EFL_INT
 599  *    and corresponding EFL_INT_ENA_W1C bits are both set
 600  * @ilk: Set when any ILK_INT bit is set
 601  * @lbc: Set when any LBC_INT RO bit is set or when any non-RO LBC_INT
 602  *    and corresponding LBC_INT_ENA_W1C bits are bot set
 603  * @pem: Set when any PEM(0)_INT RO bit is set or when any non-RO
 604  *    PEM(0)_INT and corresponding PEM(0)_INT_ENA_W1C bit are both set
 605  * @ucd: Set when any UCD_INT bit is set
 606  * @zctl: Set when any ZIP_INT RO bit is set or when any non-RO ZIP_INT
 607  *    and corresponding ZIP_INT_ENA_W1C bits are both set
 608  * @lbm: Set when any LBM_INT bit is set
 609  * @nps_pkt: Set when any NPS_PKT_INT bit is set
 610  * @nps_core: Set when any NPS_CORE_INT RO bit is set or when non-RO
 611  *    NPS_CORE_INT and corresponding NSP_CORE_INT_ENA_W1C bits are both set
 612  */
 613 union nps_core_int_active {
 614         u64 value;
 615         struct {
 616 #if (defined(__BIG_ENDIAN_BITFIELD))
 617                 u64 resend : 1;
 618                 u64 raz : 43;
 619                 u64 ocla : 1;
 620                 u64 mbox : 1;
 621                 u64 emu : 4;
 622                 u64 bmo : 1;
 623                 u64 bmi : 1;
 624                 u64 aqm : 1;
 625                 u64 zqm : 1;
 626                 u64 efl : 1;
 627                 u64 ilk : 1;
 628                 u64 lbc : 1;
 629                 u64 pem : 1;
 630                 u64 pom : 1;
 631                 u64 ucd : 1;
 632                 u64 zctl : 1;
 633                 u64 lbm : 1;
 634                 u64 nps_pkt : 1;
 635                 u64 nps_core : 1;
 636 #else
 637                 u64 nps_core : 1;
 638                 u64 nps_pkt : 1;
 639                 u64 lbm : 1;
 640                 u64 zctl: 1;
 641                 u64 ucd : 1;
 642                 u64 pom : 1;
 643                 u64 pem : 1;
 644                 u64 lbc : 1;
 645                 u64 ilk : 1;
 646                 u64 efl : 1;
 647                 u64 zqm : 1;
 648                 u64 aqm : 1;
 649                 u64 bmi : 1;
 650                 u64 bmo : 1;
 651                 u64 emu : 4;
 652                 u64 mbox : 1;
 653                 u64 ocla : 1;
 654                 u64 raz : 43;
 655                 u64 resend : 1;
 656 #endif
 657         } s;
 658 };
 659
 660 /**
 661  * struct efl_core_int - EFL Interrupt Registers
 662  * @epci_decode_err: EPCI decoded a transacation that was unknown
 663  *    This error should only occurred when there is a micrcode/SE error
 664  *    and should be considered fatal
 665  * @ae_err: An AE uncorrectable error occurred.
 666  *    See EFL_CORE(0..3)_AE_ERR_INT
 667  * @se_err: An SE uncorrectable error occurred.
 668  *    See EFL_CORE(0..3)_SE_ERR_INT
 669  * @dbe: Double-bit error occurred in EFL
 670  * @sbe: Single-bit error occurred in EFL
 671  * @d_left: Asserted when new POM-Header-BMI-data is
 672  *    being sent to an Exec, and that Exec has Not read all BMI
 673  *    data associated with the previous POM header
 674  * @len_ovr: Asserted when an Exec-Read is issued that is more than
 675  *    14 greater in length that the BMI data left to be read
 676  */
 677 union efl_core_int {
 678         u64 value;
 679         struct {
 680 #if (defined(__BIG_ENDIAN_BITFIELD))
 681                 u64 raz : 57;
 682                 u64 epci_decode_err : 1;
 683                 u64 ae_err : 1;
 684                 u64 se_err : 1;
 685                 u64 dbe : 1;
 686                 u64 sbe : 1;
 687                 u64 d_left : 1;
 688                 u64 len_ovr : 1;
 689 #else
 690                 u64 len_ovr : 1;
 691                 u64 d_left : 1;
 692                 u64 sbe : 1;
 693                 u64 dbe : 1;
 694                 u64 se_err : 1;
 695                 u64 ae_err : 1;
 696                 u64 epci_decode_err  : 1;
 697                 u64 raz : 57;
 698 #endif
 699         } s;
 700 };
 701
 702 /**
 703  * struct efl_core_int_ena_w1s - EFL core interrupt enable set register
 704  * @epci_decode_err: Reads or sets enable for
 705  *   EFL_CORE(0..3)_INT[EPCI_DECODE_ERR].
 706  * @d_left: Reads or sets enable for
 707  *   EFL_CORE(0..3)_INT[D_LEFT].
 708  * @len_ovr: Reads or sets enable for
 709  *   EFL_CORE(0..3)_INT[LEN_OVR].
 710  */
 711 union efl_core_int_ena_w1s {
 712         u64 value;
 713         struct {
 714 #if (defined(__BIG_ENDIAN_BITFIELD))
 715                 u64 raz_7_63 : 57;
 716                 u64 epci_decode_err : 1;
 717                 u64 raz_2_5 : 4;
 718                 u64 d_left : 1;
 719                 u64 len_ovr : 1;
 720 #else
 721                 u64 len_ovr : 1;
 722                 u64 d_left : 1;
 723                 u64 raz_2_5 : 4;
 724                 u64 epci_decode_err : 1;
 725                 u64 raz_7_63 : 57;
 726 #endif
 727         } s;
 728 };
 729
 730 /**
 731  * struct efl_rnm_ctl_status - RNM Control and Status Register
 732  * @ent_sel: Select input to RNM FIFO
 733  * @exp_ent: Exported entropy enable for random number generator
 734  * @rng_rst: Reset to RNG. Setting this bit to 1 cancels the generation
 735  *    of the current random number.
 736  * @rnm_rst: Reset the RNM. Setting this bit to 1 clears all sorted numbers
 737  *    in the random number memory.
 738  * @rng_en: Enabled the output of the RNG.
 739  * @ent_en: Entropy enable for random number generator.
 740  */
 741 union efl_rnm_ctl_status {
 742         u64 value;
 743         struct {
 744 #if (defined(__BIG_ENDIAN_BITFIELD))
 745                 u64 raz_9_63 : 55;
 746                 u64 ent_sel : 4;
 747                 u64 exp_ent : 1;
 748                 u64 rng_rst : 1;
 749                 u64 rnm_rst : 1;
 750                 u64 rng_en : 1;
 751                 u64 ent_en : 1;
 752 #else
 753                 u64 ent_en : 1;
 754                 u64 rng_en : 1;
 755                 u64 rnm_rst : 1;
 756                 u64 rng_rst : 1;
 757                 u64 exp_ent : 1;
 758                 u64 ent_sel : 4;
 759                 u64 raz_9_63 : 55;
 760 #endif
 761         } s;
 762 };
 763
 764 /**
 765  * struct bmi_ctl - BMI control register
 766  * @ilk_hdrq_thrsh: Maximum number of header queue locations
 767  *   that ILK packets may consume. When the threshold is
 768  *   exceeded ILK_XOFF is sent to the BMI_X2P_ARB.
 769  * @nps_hdrq_thrsh: Maximum number of header queue locations
 770  *   that NPS packets may consume. When the threshold is
 771  *   exceeded NPS_XOFF is sent to the BMI_X2P_ARB.
 772  * @totl_hdrq_thrsh: Maximum number of header queue locations
 773  *   that the sum of ILK and NPS packets may consume.
 774  * @ilk_free_thrsh: Maximum number of buffers that ILK packet
 775  *   flows may consume before ILK_XOFF is sent to the BMI_X2P_ARB.
 776  * @nps_free_thrsh: Maximum number of buffers that NPS packet
 777  *   flows may consume before NPS XOFF is sent to the BMI_X2p_ARB.
 778  * @totl_free_thrsh: Maximum number of buffers that bot ILK and NPS
 779  *   packet flows may consume before both NPS_XOFF and ILK_XOFF
 780  *   are asserted to the BMI_X2P_ARB.
 781  * @max_pkt_len: Maximum packet length, integral number of 256B
 782  *   buffers.
 783  */
 784 union bmi_ctl {
 785         u64 value;
 786         struct {
 787 #if (defined(__BIG_ENDIAN_BITFIELD))
 788                 u64 raz_56_63 : 8;
 789                 u64 ilk_hdrq_thrsh : 8;
 790                 u64 nps_hdrq_thrsh : 8;
 791                 u64 totl_hdrq_thrsh : 8;
 792                 u64 ilk_free_thrsh : 8;
 793                 u64 nps_free_thrsh : 8;
 794                 u64 totl_free_thrsh : 8;
 795                 u64 max_pkt_len : 8;
 796 #else
 797                 u64 max_pkt_len : 8;
 798                 u64 totl_free_thrsh : 8;
 799                 u64 nps_free_thrsh : 8;
 800                 u64 ilk_free_thrsh : 8;
 801                 u64 totl_hdrq_thrsh : 8;
 802                 u64 nps_hdrq_thrsh : 8;
 803                 u64 ilk_hdrq_thrsh : 8;
 804                 u64 raz_56_63 : 8;
 805 #endif
 806         } s;
 807 };
 808
 809 /**
 810  * struct bmi_int_ena_w1s - BMI interrupt enable set register
 811  * @ilk_req_oflw: Reads or sets enable for
 812  *   BMI_INT[ILK_REQ_OFLW].
 813  * @nps_req_oflw: Reads or sets enable for
 814  *   BMI_INT[NPS_REQ_OFLW].
 815  * @fpf_undrrn: Reads or sets enable for
 816  *   BMI_INT[FPF_UNDRRN].
 817  * @eop_err_ilk: Reads or sets enable for
 818  *   BMI_INT[EOP_ERR_ILK].
 819  * @eop_err_nps: Reads or sets enable for
 820  *   BMI_INT[EOP_ERR_NPS].
 821  * @sop_err_ilk: Reads or sets enable for
 822  *   BMI_INT[SOP_ERR_ILK].
 823  * @sop_err_nps: Reads or sets enable for
 824  *   BMI_INT[SOP_ERR_NPS].
 825  * @pkt_rcv_err_ilk: Reads or sets enable for
 826  *   BMI_INT[PKT_RCV_ERR_ILK].
 827  * @pkt_rcv_err_nps: Reads or sets enable for
 828  *   BMI_INT[PKT_RCV_ERR_NPS].
 829  * @max_len_err_ilk: Reads or sets enable for
 830  *   BMI_INT[MAX_LEN_ERR_ILK].
 831  * @max_len_err_nps: Reads or sets enable for
 832  *   BMI_INT[MAX_LEN_ERR_NPS].
 833  */
 834 union bmi_int_ena_w1s {
 835         u64 value;
 836         struct {
 837 #if (defined(__BIG_ENDIAN_BITFIELD))
 838                 u64 raz_13_63   : 51;
 839                 u64 ilk_req_oflw : 1;
 840                 u64 nps_req_oflw : 1;
 841                 u64 raz_10 : 1;
 842                 u64 raz_9 : 1;
 843                 u64 fpf_undrrn  : 1;
 844                 u64 eop_err_ilk : 1;
 845                 u64 eop_err_nps : 1;
 846                 u64 sop_err_ilk : 1;
 847                 u64 sop_err_nps : 1;
 848                 u64 pkt_rcv_err_ilk : 1;
 849                 u64 pkt_rcv_err_nps : 1;
 850                 u64 max_len_err_ilk : 1;
 851                 u64 max_len_err_nps : 1;
 852 #else
 853                 u64 max_len_err_nps : 1;
 854                 u64 max_len_err_ilk : 1;
 855                 u64 pkt_rcv_err_nps : 1;
 856                 u64 pkt_rcv_err_ilk : 1;
 857                 u64 sop_err_nps : 1;
 858                 u64 sop_err_ilk : 1;
 859                 u64 eop_err_nps : 1;
 860                 u64 eop_err_ilk : 1;
 861                 u64 fpf_undrrn  : 1;
 862                 u64 raz_9 : 1;
 863                 u64 raz_10 : 1;
 864                 u64 nps_req_oflw : 1;
 865                 u64 ilk_req_oflw : 1;
 866                 u64 raz_13_63 : 51;
 867 #endif
 868         } s;
 869 };
 870
 871 /**
 872  * struct bmo_ctl2 - BMO Control2 Register
 873  * @arb_sel: Determines P2X Arbitration
 874  * @ilk_buf_thrsh: Maximum number of buffers that the
 875  *    ILK packet flows may consume before ILK XOFF is
 876  *    asserted to the POM.
 877  * @nps_slc_buf_thrsh: Maximum number of buffers that the
 878  *    NPS_SLC packet flow may consume before NPS_SLC XOFF is
 879  *    asserted to the POM.
 880  * @nps_uns_buf_thrsh: Maximum number of buffers that the
 881  *    NPS_UNS packet flow may consume before NPS_UNS XOFF is
 882  *    asserted to the POM.
 883  * @totl_buf_thrsh: Maximum number of buffers that ILK, NPS_UNS and
 884  *    NPS_SLC packet flows may consume before NPS_UNS XOFF, NSP_SLC and
 885  *    ILK_XOFF are all asserted POM.
 886  */
 887 union bmo_ctl2 {
 888         u64 value;
 889         struct {
 890 #if (defined(__BIG_ENDIAN_BITFIELD))
 891                 u64 arb_sel : 1;
 892                 u64 raz_32_62 : 31;
 893                 u64 ilk_buf_thrsh : 8;
 894                 u64 nps_slc_buf_thrsh : 8;
 895                 u64 nps_uns_buf_thrsh : 8;
 896                 u64 totl_buf_thrsh : 8;
 897 #else
 898                 u64 totl_buf_thrsh : 8;
 899                 u64 nps_uns_buf_thrsh : 8;
 900                 u64 nps_slc_buf_thrsh : 8;
 901                 u64 ilk_buf_thrsh : 8;
 902                 u64 raz_32_62 : 31;
 903                 u64 arb_sel : 1;
 904 #endif
 905         } s;
 906 };
 907
 908 /**
 909  * struct pom_int_ena_w1s - POM interrupt enable set register
 910  * @illegal_intf: Reads or sets enable for POM_INT[ILLEGAL_INTF].
 911  * @illegal_dport: Reads or sets enable for POM_INT[ILLEGAL_DPORT].
 912  */
 913 union pom_int_ena_w1s {
 914         u64 value;
 915         struct {
 916 #if (defined(__BIG_ENDIAN_BITFIELD))
 917                 u64 raz2 : 60;
 918                 u64 illegal_intf : 1;
 919                 u64 illegal_dport : 1;
 920                 u64 raz1 : 1;
 921                 u64 raz0 : 1;
 922 #else
 923                 u64 raz0 : 1;
 924                 u64 raz1 : 1;
 925                 u64 illegal_dport : 1;
 926                 u64 illegal_intf : 1;
 927                 u64 raz2 : 60;
 928 #endif
 929         } s;
 930 };
 931
 932 /**
 933  * struct lbc_inval_ctl - LBC invalidation control register
 934  * @wait_timer: Wait timer for wait state. [WAIT_TIMER] must
 935  *   always be written with its reset value.
 936  * @cam_inval_start: Software should write [CAM_INVAL_START]=1
 937  *   to initiate an LBC cache invalidation. After this, software
 938  *   should read LBC_INVAL_STATUS until LBC_INVAL_STATUS[DONE] is set.
 939  *   LBC hardware clears [CAVM_INVAL_START] before software can
 940  *   observed LBC_INVAL_STATUS[DONE] to be set
 941  */
 942 union lbc_inval_ctl {
 943         u64 value;
 944         struct {
 945 #if (defined(__BIG_ENDIAN_BITFIELD))
 946                 u64 raz2 : 48;
 947                 u64 wait_timer : 8;
 948                 u64 raz1 : 6;
 949                 u64 cam_inval_start : 1;
 950                 u64 raz0 : 1;
 951 #else
 952                 u64 raz0 : 1;
 953                 u64 cam_inval_start : 1;
 954                 u64 raz1 : 6;
 955                 u64 wait_timer : 8;
 956                 u64 raz2 : 48;
 957 #endif
 958         } s;
 959 };
 960
 961 /**
 962  * struct lbc_int_ena_w1s - LBC interrupt enable set register
 963  * @cam_hard_err: Reads or sets enable for LBC_INT[CAM_HARD_ERR].
 964  * @cam_inval_abort: Reads or sets enable for LBC_INT[CAM_INVAL_ABORT].
 965  * @over_fetch_err: Reads or sets enable for LBC_INT[OVER_FETCH_ERR].
 966  * @cache_line_to_err: Reads or sets enable for
 967  *   LBC_INT[CACHE_LINE_TO_ERR].
 968  * @cam_soft_err: Reads or sets enable for
 969  *   LBC_INT[CAM_SOFT_ERR].
 970  * @dma_rd_err: Reads or sets enable for
 971  *   LBC_INT[DMA_RD_ERR].
 972  */
 973 union lbc_int_ena_w1s {
 974         u64 value;
 975         struct {
 976 #if (defined(__BIG_ENDIAN_BITFIELD))
 977                 u64 raz_10_63 : 54;
 978                 u64 cam_hard_err : 1;
 979                 u64 cam_inval_abort : 1;
 980                 u64 over_fetch_err : 1;
 981                 u64 cache_line_to_err : 1;
 982                 u64 raz_2_5 : 4;
 983                 u64 cam_soft_err : 1;
 984                 u64 dma_rd_err : 1;
 985 #else
 986                 u64 dma_rd_err : 1;
 987                 u64 cam_soft_err : 1;
 988                 u64 raz_2_5 : 4;
 989                 u64 cache_line_to_err : 1;
 990                 u64 over_fetch_err : 1;
 991                 u64 cam_inval_abort : 1;
 992                 u64 cam_hard_err : 1;
 993                 u64 raz_10_63 : 54;
 994 #endif
 995         } s;
 996 };
 997
 998 /**
 999  * struct lbc_int - LBC interrupt summary register
1000  * @cam_hard_err: indicates a fatal hardware error.
1001  *   It requires system reset.
1002  *   When [CAM_HARD_ERR] is set, LBC stops logging any new information in
1003  *   LBC_POM_MISS_INFO_LOG,
1004  *   LBC_POM_MISS_ADDR_LOG,
1005  *   LBC_EFL_MISS_INFO_LOG, and
1006  *   LBC_EFL_MISS_ADDR_LOG.
1007  *   Software should sample them.
1008  * @cam_inval_abort: indicates a fatal hardware error.
1009  *   System reset is required.
1010  * @over_fetch_err: indicates a fatal hardware error
1011  *   System reset is required
1012  * @cache_line_to_err: is a debug feature.
1013  *   This timeout interrupt bit tells the software that
1014  *   a cacheline in LBC has non-zero usage and the context
1015  *   has not been used for greater than the
1016  *   LBC_TO_CNT[TO_CNT] time interval.
1017  * @sbe: Memory SBE error. This is recoverable via ECC.
1018  *   See LBC_ECC_INT for more details.
1019  * @dbe: Memory DBE error. This is a fatal and requires a
1020  *   system reset.
1021  * @pref_dat_len_mismatch_err: Summary bit for context length
1022  *   mismatch errors.
1023  * @rd_dat_len_mismatch_err: Summary bit for SE read data length
1024  *   greater than data prefect length errors.
1025  * @cam_soft_err: is recoverable. Software must complete a
1026  *   LBC_INVAL_CTL[CAM_INVAL_START] invalidation sequence and
1027  *   then clear [CAM_SOFT_ERR].
1028  * @dma_rd_err: A context prefect read of host memory returned with
1029  *   a read error.
1030  */
1031 union lbc_int {
1032         u64 value;
1033         struct {
1034 #if (defined(__BIG_ENDIAN_BITFIELD))
1035                 u64 raz_10_63 : 54;
1036                 u64 cam_hard_err : 1;
1037                 u64 cam_inval_abort : 1;
1038                 u64 over_fetch_err : 1;
1039                 u64 cache_line_to_err : 1;
1040                 u64 sbe : 1;
1041                 u64 dbe : 1;
1042                 u64 pref_dat_len_mismatch_err : 1;
1043                 u64 rd_dat_len_mismatch_err : 1;
1044                 u64 cam_soft_err : 1;
1045                 u64 dma_rd_err : 1;
1046 #else
1047                 u64 dma_rd_err : 1;
1048                 u64 cam_soft_err : 1;
1049                 u64 rd_dat_len_mismatch_err : 1;
1050                 u64 pref_dat_len_mismatch_err : 1;
1051                 u64 dbe : 1;
1052                 u64 sbe : 1;
1053                 u64 cache_line_to_err : 1;
1054                 u64 over_fetch_err : 1;
1055                 u64 cam_inval_abort : 1;
1056                 u64 cam_hard_err : 1;
1057                 u64 raz_10_63 : 54;
1058 #endif
1059         } s;
1060 };
1061
1062 /**
1063  * struct lbc_inval_status: LBC Invalidation status register
1064  * @cam_clean_entry_complete_cnt: The number of entries that are
1065  *   cleaned up successfully.
1066  * @cam_clean_entry_cnt: The number of entries that have the CAM
1067  *   inval command issued.
1068  * @cam_inval_state: cam invalidation FSM state
1069  * @cam_inval_abort: cam invalidation abort
1070  * @cam_rst_rdy: lbc_cam reset ready
1071  * @done: LBC clears [DONE] when
1072  *   LBC_INVAL_CTL[CAM_INVAL_START] is written with a one,
1073  *   and sets [DONE] when it completes the invalidation
1074  *   sequence.
1075  */
1076 union lbc_inval_status {
1077         u64 value;
1078         struct {
1079 #if (defined(__BIG_ENDIAN_BITFIELD))
1080                 u64 raz3 : 23;
1081                 u64 cam_clean_entry_complete_cnt : 9;
1082                 u64 raz2 : 7;
1083                 u64 cam_clean_entry_cnt : 9;
1084                 u64 raz1 : 5;
1085                 u64 cam_inval_state : 3;
1086                 u64 raz0 : 5;
1087                 u64 cam_inval_abort : 1;
1088                 u64 cam_rst_rdy : 1;
1089                 u64 done : 1;
1090 #else
1091                 u64 done : 1;
1092                 u64 cam_rst_rdy : 1;
1093                 u64 cam_inval_abort : 1;
1094                 u64 raz0 : 5;
1095                 u64 cam_inval_state : 3;
1096                 u64 raz1 : 5;
1097                 u64 cam_clean_entry_cnt : 9;
1098                 u64 raz2 : 7;
1099                 u64 cam_clean_entry_complete_cnt : 9;
1100                 u64 raz3 : 23;
1101 #endif
1102         } s;
1103 };
1104
1105 /**
1106  * struct rst_boot: RST Boot Register
1107  * @jtcsrdis: when set, internal CSR access via JTAG TAP controller
1108  *   is disabled
1109  * @jt_tst_mode: JTAG test mode
1110  * @io_supply: I/O power supply setting based on IO_VDD_SELECT pin:
1111  *    0x1 = 1.8V
1112  *    0x2 = 2.5V
1113  *    0x4 = 3.3V
1114  *    All other values are reserved
1115  * @pnr_mul: clock multiplier
1116  * @lboot: last boot cause mask, resets only with PLL_DC_OK
1117  * @rboot: determines whether core 0 remains in reset after
1118  *    chip cold or warm or soft reset
1119  * @rboot_pin: read only access to REMOTE_BOOT pin
1120  */
1121 union rst_boot {
1122         u64 value;
1123         struct {
1124 #if (defined(__BIG_ENDIAN_BITFIELD))
1125                 u64 raz_63 : 1;
1126                 u64 jtcsrdis : 1;
1127                 u64 raz_59_61 : 3;
1128                 u64 jt_tst_mode : 1;
1129                 u64 raz_40_57 : 18;
1130                 u64 io_supply : 3;
1131                 u64 raz_30_36 : 7;
1132                 u64 pnr_mul : 6;
1133                 u64 raz_12_23 : 12;
1134                 u64 lboot : 10;
1135                 u64 rboot : 1;
1136                 u64 rboot_pin : 1;
1137 #else
1138                 u64 rboot_pin : 1;
1139                 u64 rboot : 1;
1140                 u64 lboot : 10;
1141                 u64 raz_12_23 : 12;
1142                 u64 pnr_mul : 6;
1143                 u64 raz_30_36 : 7;
1144                 u64 io_supply : 3;
1145                 u64 raz_40_57 : 18;
1146                 u64 jt_tst_mode : 1;
1147                 u64 raz_59_61 : 3;
1148                 u64 jtcsrdis : 1;
1149                 u64 raz_63 : 1;
1150 #endif
1151         };
1152 };
1153
1154 /**
1155  * struct fus_dat1: Fuse Data 1 Register
1156  * @pll_mul: main clock PLL multiplier hardware limit
1157  * @pll_half_dis: main clock PLL control
1158  * @efus_lck: efuse lockdown
1159  * @zip_info: ZIP information
1160  * @bar2_sz_conf: when zero, BAR2 size conforms to
1161  *    PCIe specification
1162  * @efus_ign: efuse ignore
1163  * @nozip: ZIP disable
1164  * @pll_alt_matrix: select alternate PLL matrix
1165  * @pll_bwadj_denom: select CLKF denominator for
1166  *    BWADJ value
1167  * @chip_id: chip ID
1168  */
1169 union fus_dat1 {
1170         u64 value;
1171         struct {
1172 #if (defined(__BIG_ENDIAN_BITFIELD))
1173                 u64 raz_57_63 : 7;
1174                 u64 pll_mul : 3;
1175                 u64 pll_half_dis : 1;
1176                 u64 raz_43_52 : 10;
1177                 u64 efus_lck : 3;
1178                 u64 raz_26_39 : 14;
1179                 u64 zip_info : 5;
1180                 u64 bar2_sz_conf : 1;
1181                 u64 efus_ign : 1;
1182                 u64 nozip : 1;
1183                 u64 raz_11_17 : 7;
1184                 u64 pll_alt_matrix : 1;
1185                 u64 pll_bwadj_denom : 2;
1186                 u64 chip_id : 8;
1187 #else
1188                 u64 chip_id : 8;
1189                 u64 pll_bwadj_denom : 2;
1190                 u64 pll_alt_matrix : 1;
1191                 u64 raz_11_17 : 7;
1192                 u64 nozip : 1;
1193                 u64 efus_ign : 1;
1194                 u64 bar2_sz_conf : 1;
1195                 u64 zip_info : 5;
1196                 u64 raz_26_39 : 14;
1197                 u64 efus_lck : 3;
1198                 u64 raz_43_52 : 10;
1199                 u64 pll_half_dis : 1;
1200                 u64 pll_mul : 3;
1201                 u64 raz_57_63 : 7;
1202 #endif
1203         };
1204 };
1205
1206 #endif /* __NITROX_CSR_H */