drivers/crypto/cavium/nitrox/nitrox_dev.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 #ifndef __NITROX_DEV_H
   3 #define __NITROX_DEV_H
   4
   5 #include <linux/dma-mapping.h>
   6 #include <linux/interrupt.h>
   7 #include <linux/pci.h>
   8 #include <linux/if.h>
   9
  10 #define VERSION_LEN 32
  11 /* Maximum queues in PF mode */
  12 #define MAX_PF_QUEUES   64
  13
  14 /**
  15  * struct nitrox_cmdq - NITROX command queue
  16  * @cmd_qlock: command queue lock
  17  * @resp_qlock: response queue lock
  18  * @backlog_qlock: backlog queue lock
  19  * @ndev: NITROX device
  20  * @response_head: submitted request list
  21  * @backlog_head: backlog queue
  22  * @dbell_csr_addr: doorbell register address for this queue
  23  * @compl_cnt_csr_addr: completion count register address of the slc port
  24  * @base: command queue base address
  25  * @dma: dma address of the base
  26  * @pending_count: request pending at device
  27  * @backlog_count: backlog request count
  28  * @write_idx: next write index for the command
  29  * @instr_size: command size
  30  * @qno: command queue number
  31  * @qsize: command queue size
  32  * @unalign_base: unaligned base address
  33  * @unalign_dma: unaligned dma address
  34  */
  35 struct nitrox_cmdq {
  36         spinlock_t cmd_qlock;
  37         spinlock_t resp_qlock;
  38         spinlock_t backlog_qlock;
  39
  40         struct nitrox_device *ndev;
  41         struct list_head response_head;
  42         struct list_head backlog_head;
  43
  44         u8 __iomem *dbell_csr_addr;
  45         u8 __iomem *compl_cnt_csr_addr;
  46         u8 *base;
  47         dma_addr_t dma;
  48
  49         struct work_struct backlog_qflush;
  50
  51         atomic_t pending_count;
  52         atomic_t backlog_count;
  53
  54         int write_idx;
  55         u8 instr_size;
  56         u8 qno;
  57         u32 qsize;
  58
  59         u8 *unalign_base;
  60         dma_addr_t unalign_dma;
  61 };
  62
  63 /**
  64  * struct nitrox_hw - NITROX hardware information
  65  * @partname: partname ex: CNN55xxx-xxx
  66  * @fw_name: firmware version
  67  * @freq: NITROX frequency
  68  * @vendor_id: vendor ID
  69  * @device_id: device ID
  70  * @revision_id: revision ID
  71  * @se_cores: number of symmetric cores
  72  * @ae_cores: number of asymmetric cores
  73  * @zip_cores: number of zip cores
  74  */
  75 struct nitrox_hw {
  76         char partname[IFNAMSIZ * 2];
  77         char fw_name[VERSION_LEN];
  78
  79         int freq;
  80         u16 vendor_id;
  81         u16 device_id;
  82         u8 revision_id;
  83
  84         u8 se_cores;
  85         u8 ae_cores;
  86         u8 zip_cores;
  87 };
  88
  89 struct nitrox_stats {
  90         atomic64_t posted;
  91         atomic64_t completed;
  92         atomic64_t dropped;
  93 };
  94
  95 #define IRQ_NAMESZ      32
  96
  97 struct nitrox_q_vector {
  98         char name[IRQ_NAMESZ];
  99         bool valid;
 100         int ring;
 101         struct tasklet_struct resp_tasklet;
 102         union {
 103                 struct nitrox_cmdq *cmdq;
 104                 struct nitrox_device *ndev;
 105         };
 106 };
 107
 108 /**
 109  * mbox_msg - Mailbox message data
 110  * @type: message type
 111  * @opcode: message opcode
 112  * @data: message data
 113  */
 114 union mbox_msg {
 115         u64 value;
 116         struct {
 117                 u64 type: 2;
 118                 u64 opcode: 6;
 119                 u64 data: 58;
 120         };
 121         struct {
 122                 u64 type: 2;
 123                 u64 opcode: 6;
 124                 u64 chipid: 8;
 125                 u64 vfid: 8;
 126         } id;
 127 };
 128
 129 /**
 130  * nitrox_vfdev - NITROX VF device instance in PF
 131  * @state: VF device state
 132  * @vfno: VF number
 133  * @nr_queues: number of queues enabled in VF
 134  * @ring: ring to communicate with VF
 135  * @msg: Mailbox message data from VF
 136  * @mbx_resp: Mailbox counters
 137  */
 138 struct nitrox_vfdev {
 139         atomic_t state;
 140         int vfno;
 141         int nr_queues;
 142         int ring;
 143         union mbox_msg msg;
 144         atomic64_t mbx_resp;
 145 };
 146
 147 /**
 148  * struct nitrox_iov - SR-IOV information
 149  * @num_vfs: number of VF(s) enabled
 150  * @max_vf_queues: Maximum number of queues allowed for VF
 151  * @vfdev: VF(s) devices
 152  * @pf2vf_wq: workqueue for PF2VF communication
 153  * @msix: MSI-X entry for PF in SR-IOV case
 154  */
 155 struct nitrox_iov {
 156         int num_vfs;
 157         int max_vf_queues;
 158         struct nitrox_vfdev *vfdev;
 159         struct workqueue_struct *pf2vf_wq;
 160         struct msix_entry msix;
 161 };
 162
 163 /*
 164  * NITROX Device states
 165  */
 166 enum ndev_state {
 167         __NDEV_NOT_READY,
 168         __NDEV_READY,
 169         __NDEV_IN_RESET,
 170 };
 171
 172 /* NITROX support modes for VF(s) */
 173 enum vf_mode {
 174         __NDEV_MODE_PF,
 175         __NDEV_MODE_VF16,
 176         __NDEV_MODE_VF32,
 177         __NDEV_MODE_VF64,
 178         __NDEV_MODE_VF128,
 179 };
 180
 181 #define __NDEV_SRIOV_BIT 0
 182
 183 /* command queue size */
 184 #define DEFAULT_CMD_QLEN 2048
 185 /* command timeout in milliseconds */
 186 #define CMD_TIMEOUT 2000
 187
 188 #define DEV(ndev) ((struct device *)(&(ndev)->pdev->dev))
 189
 190 #define NITROX_CSR_ADDR(ndev, offset) \
 191         ((ndev)->bar_addr + (offset))
 192
 193 /**
 194  * struct nitrox_device - NITROX Device Information.
 195  * @list: pointer to linked list of devices
 196  * @bar_addr: iomap address
 197  * @pdev: PCI device information
 198  * @state: NITROX device state
 199  * @flags: flags to indicate device the features
 200  * @timeout: Request timeout in jiffies
 201  * @refcnt: Device usage count
 202  * @idx: device index (0..N)
 203  * @node: NUMA node id attached
 204  * @qlen: Command queue length
 205  * @nr_queues: Number of command queues
 206  * @mode: Device mode PF/VF
 207  * @ctx_pool: DMA pool for crypto context
 208  * @pkt_inq: Packet input rings
 209  * @qvec: MSI-X queue vectors information
 210  * @iov: SR-IOV informatin
 211  * @num_vecs: number of MSI-X vectors
 212  * @stats: request statistics
 213  * @hw: hardware information
 214  * @debugfs_dir: debugfs directory
 215  */
 216 struct nitrox_device {
 217         struct list_head list;
 218
 219         u8 __iomem *bar_addr;
 220         struct pci_dev *pdev;
 221
 222         atomic_t state;
 223         unsigned long flags;
 224         unsigned long timeout;
 225         refcount_t refcnt;
 226
 227         u8 idx;
 228         int node;
 229         u16 qlen;
 230         u16 nr_queues;
 231         enum vf_mode mode;
 232
 233         struct dma_pool *ctx_pool;
 234         struct nitrox_cmdq *pkt_inq;
 235
 236         struct nitrox_q_vector *qvec;
 237         struct nitrox_iov iov;
 238         int num_vecs;
 239
 240         struct nitrox_stats stats;
 241         struct nitrox_hw hw;
 242 #if IS_ENABLED(CONFIG_DEBUG_FS)
 243         struct dentry *debugfs_dir;
 244 #endif
 245 };
 246
 247 /**
 248  * nitrox_read_csr - Read from device register
 249  * @ndev: NITROX device
 250  * @offset: offset of the register to read
 251  *
 252  * Returns: value read
 253  */
 254 static inline u64 nitrox_read_csr(struct nitrox_device *ndev, u64 offset)
 255 {
 256         return readq(ndev->bar_addr + offset);
 257 }
 258
 259 /**
 260  * nitrox_write_csr - Write to device register
 261  * @ndev: NITROX device
 262  * @offset: offset of the register to write
 263  * @value: value to write
 264  */
 265 static inline void nitrox_write_csr(struct nitrox_device *ndev, u64 offset,
 266                                     u64 value)
 267 {
 268         writeq(value, (ndev->bar_addr + offset));
 269 }
 270
 271 static inline bool nitrox_ready(struct nitrox_device *ndev)
 272 {
 273         return atomic_read(&ndev->state) == __NDEV_READY;
 274 }
 275
 276 static inline bool nitrox_vfdev_ready(struct nitrox_vfdev *vfdev)
 277 {
 278         return atomic_read(&vfdev->state) == __NDEV_READY;
 279 }
 280
 281 #endif /* __NITROX_DEV_H */