drivers/crypto/mediatek/mtk-platform.c

   1 /*
   2  * Driver for EIP97 cryptographic accelerator.
   3  *
   4  * Copyright (c) 2016 Ryder Lee <ryder.lee@mediatek.com>
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  *
  10  */
  11
  12 #include <linux/clk.h>
  13 #include <linux/init.h>
  14 #include <linux/kernel.h>
  15 #include <linux/module.h>
  16 #include <linux/mod_devicetable.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/pm_runtime.h>
  19 #include "mtk-platform.h"
  20
  21 #define MTK_BURST_SIZE_MSK              GENMASK(7, 4)
  22 #define MTK_BURST_SIZE(x)               ((x) << 4)
  23 #define MTK_DESC_SIZE(x)                ((x) << 0)
  24 #define MTK_DESC_OFFSET(x)              ((x) << 16)
  25 #define MTK_DESC_FETCH_SIZE(x)          ((x) << 0)
  26 #define MTK_DESC_FETCH_THRESH(x)        ((x) << 16)
  27 #define MTK_DESC_OVL_IRQ_EN             BIT(25)
  28 #define MTK_DESC_ATP_PRESENT            BIT(30)
  29
  30 #define MTK_DFSE_IDLE                   GENMASK(3, 0)
  31 #define MTK_DFSE_THR_CTRL_EN            BIT(30)
  32 #define MTK_DFSE_THR_CTRL_RESET         BIT(31)
  33 #define MTK_DFSE_RING_ID(x)             (((x) >> 12) & GENMASK(3, 0))
  34 #define MTK_DFSE_MIN_DATA(x)            ((x) << 0)
  35 #define MTK_DFSE_MAX_DATA(x)            ((x) << 8)
  36 #define MTK_DFE_MIN_CTRL(x)             ((x) << 16)
  37 #define MTK_DFE_MAX_CTRL(x)             ((x) << 24)
  38
  39 #define MTK_IN_BUF_MIN_THRESH(x)        ((x) << 8)
  40 #define MTK_IN_BUF_MAX_THRESH(x)        ((x) << 12)
  41 #define MTK_OUT_BUF_MIN_THRESH(x)       ((x) << 0)
  42 #define MTK_OUT_BUF_MAX_THRESH(x)       ((x) << 4)
  43 #define MTK_IN_TBUF_SIZE(x)             (((x) >> 4) & GENMASK(3, 0))
  44 #define MTK_IN_DBUF_SIZE(x)             (((x) >> 8) & GENMASK(3, 0))
  45 #define MTK_OUT_DBUF_SIZE(x)            (((x) >> 16) & GENMASK(3, 0))
  46 #define MTK_CMD_FIFO_SIZE(x)            (((x) >> 8) & GENMASK(3, 0))
  47 #define MTK_RES_FIFO_SIZE(x)            (((x) >> 12) & GENMASK(3, 0))
  48
  49 #define MTK_PE_TK_LOC_AVL               BIT(2)
  50 #define MTK_PE_PROC_HELD                BIT(14)
  51 #define MTK_PE_TK_TIMEOUT_EN            BIT(22)
  52 #define MTK_PE_INPUT_DMA_ERR            BIT(0)
  53 #define MTK_PE_OUTPUT_DMA_ERR           BIT(1)
  54 #define MTK_PE_PKT_PORC_ERR             BIT(2)
  55 #define MTK_PE_PKT_TIMEOUT              BIT(3)
  56 #define MTK_PE_FATAL_ERR                BIT(14)
  57 #define MTK_PE_INPUT_DMA_ERR_EN         BIT(16)
  58 #define MTK_PE_OUTPUT_DMA_ERR_EN        BIT(17)
  59 #define MTK_PE_PKT_PORC_ERR_EN          BIT(18)
  60 #define MTK_PE_PKT_TIMEOUT_EN           BIT(19)
  61 #define MTK_PE_FATAL_ERR_EN             BIT(30)
  62 #define MTK_PE_INT_OUT_EN               BIT(31)
  63
  64 #define MTK_HIA_SIGNATURE               ((u16)0x35ca)
  65 #define MTK_HIA_DATA_WIDTH(x)           (((x) >> 25) & GENMASK(1, 0))
  66 #define MTK_HIA_DMA_LENGTH(x)           (((x) >> 20) & GENMASK(4, 0))
  67 #define MTK_CDR_STAT_CLR                GENMASK(4, 0)
  68 #define MTK_RDR_STAT_CLR                GENMASK(7, 0)
  69
  70 #define MTK_AIC_INT_MSK                 GENMASK(5, 0)
  71 #define MTK_AIC_VER_MSK                 (GENMASK(15, 0) | GENMASK(27, 20))
  72 #define MTK_AIC_VER11                   0x011036c9
  73 #define MTK_AIC_VER12                   0x012036c9
  74 #define MTK_AIC_G_CLR                   GENMASK(30, 20)
  75
  76 /**
  77  * EIP97 is an integrated security subsystem to accelerate cryptographic
  78  * functions and protocols to offload the host processor.
  79  * Some important hardware modules are briefly introduced below:
  80  *
  81  * Host Interface Adapter(HIA) - the main interface between the host
  82  * system and the hardware subsystem. It is responsible for attaching
  83  * processing engine to the specific host bus interface and provides a
  84  * standardized software view for off loading tasks to the engine.
  85  *
  86  * Command Descriptor Ring Manager(CDR Manager) - keeps track of how many
  87  * CD the host has prepared in the CDR. It monitors the fill level of its
  88  * CD-FIFO and if there's sufficient space for the next block of descriptors,
  89  * then it fires off a DMA request to fetch a block of CDs.
  90  *
  91  * Data fetch engine(DFE) - It is responsible for parsing the CD and
  92  * setting up the required control and packet data DMA transfers from
  93  * system memory to the processing engine.
  94  *
  95  * Result Descriptor Ring Manager(RDR Manager) - same as CDR Manager,
  96  * but target is result descriptors, Moreover, it also handles the RD
  97  * updates under control of the DSE. For each packet data segment
  98  * processed, the DSE triggers the RDR Manager to write the updated RD.
  99  * If triggered to update, the RDR Manager sets up a DMA operation to
 100  * copy the RD from the DSE to the correct location in the RDR.
 101  *
 102  * Data Store Engine(DSE) - It is responsible for parsing the prepared RD
 103  * and setting up the required control and packet data DMA transfers from
 104  * the processing engine to system memory.
 105  *
 106  * Advanced Interrupt Controllers(AICs) - receive interrupt request signals
 107  * from various sources and combine them into one interrupt output.
 108  * The AICs are used by:
 109  * - One for the HIA global and processing engine interrupts.
 110  * - The others for the descriptor ring interrupts.
 111  */
 112
 113 /* Cryptographic engine capabilities */
 114 struct mtk_sys_cap {
 115         /* host interface adapter */
 116         u32 hia_ver;
 117         u32 hia_opt;
 118         /* packet engine */
 119         u32 pkt_eng_opt;
 120         /* global hardware */
 121         u32 hw_opt;
 122 };
 123
 124 static void mtk_desc_ring_link(struct mtk_cryp *cryp, u32 mask)
 125 {
 126         /* Assign rings to DFE/DSE thread and enable it */
 127         writel(MTK_DFSE_THR_CTRL_EN | mask, cryp->base + DFE_THR_CTRL);
 128         writel(MTK_DFSE_THR_CTRL_EN | mask, cryp->base + DSE_THR_CTRL);
 129 }
 130
 131 static void mtk_dfe_dse_buf_setup(struct mtk_cryp *cryp,
 132                                   struct mtk_sys_cap *cap)
 133 {
 134         u32 width = MTK_HIA_DATA_WIDTH(cap->hia_opt) + 2;
 135         u32 len = MTK_HIA_DMA_LENGTH(cap->hia_opt) - 1;
 136         u32 ipbuf = min((u32)MTK_IN_DBUF_SIZE(cap->hw_opt) + width, len);
 137         u32 opbuf = min((u32)MTK_OUT_DBUF_SIZE(cap->hw_opt) + width, len);
 138         u32 itbuf = min((u32)MTK_IN_TBUF_SIZE(cap->hw_opt) + width, len);
 139
 140         writel(MTK_DFSE_MIN_DATA(ipbuf - 1) |
 141                MTK_DFSE_MAX_DATA(ipbuf) |
 142                MTK_DFE_MIN_CTRL(itbuf - 1) |
 143                MTK_DFE_MAX_CTRL(itbuf),
 144                cryp->base + DFE_CFG);
 145
 146         writel(MTK_DFSE_MIN_DATA(opbuf - 1) |
 147                MTK_DFSE_MAX_DATA(opbuf),
 148                cryp->base + DSE_CFG);
 149
 150         writel(MTK_IN_BUF_MIN_THRESH(ipbuf - 1) |
 151                MTK_IN_BUF_MAX_THRESH(ipbuf),
 152                cryp->base + PE_IN_DBUF_THRESH);
 153
 154         writel(MTK_IN_BUF_MIN_THRESH(itbuf - 1) |
 155                MTK_IN_BUF_MAX_THRESH(itbuf),
 156                cryp->base + PE_IN_TBUF_THRESH);
 157
 158         writel(MTK_OUT_BUF_MIN_THRESH(opbuf - 1) |
 159                MTK_OUT_BUF_MAX_THRESH(opbuf),
 160                cryp->base + PE_OUT_DBUF_THRESH);
 161
 162         writel(0, cryp->base + PE_OUT_TBUF_THRESH);
 163         writel(0, cryp->base + PE_OUT_BUF_CTRL);
 164 }
 165
 166 static int mtk_dfe_dse_state_check(struct mtk_cryp *cryp)
 167 {
 168         int ret = -EINVAL;
 169         u32 val;
 170
 171         /* Check for completion of all DMA transfers */
 172         val = readl(cryp->base + DFE_THR_STAT);
 173         if (MTK_DFSE_RING_ID(val) == MTK_DFSE_IDLE) {
 174                 val = readl(cryp->base + DSE_THR_STAT);
 175                 if (MTK_DFSE_RING_ID(val) == MTK_DFSE_IDLE)
 176                         ret = 0;
 177         }
 178
 179         if (!ret) {
 180                 /* Take DFE/DSE thread out of reset */
 181                 writel(0, cryp->base + DFE_THR_CTRL);
 182                 writel(0, cryp->base + DSE_THR_CTRL);
 183         } else {
 184                 return -EBUSY;
 185         }
 186
 187         return 0;
 188 }
 189
 190 static int mtk_dfe_dse_reset(struct mtk_cryp *cryp)
 191 {
 192         int err;
 193
 194         /* Reset DSE/DFE and correct system priorities for all rings. */
 195         writel(MTK_DFSE_THR_CTRL_RESET, cryp->base + DFE_THR_CTRL);
 196         writel(0, cryp->base + DFE_PRIO_0);
 197         writel(0, cryp->base + DFE_PRIO_1);
 198         writel(0, cryp->base + DFE_PRIO_2);
 199         writel(0, cryp->base + DFE_PRIO_3);
 200
 201         writel(MTK_DFSE_THR_CTRL_RESET, cryp->base + DSE_THR_CTRL);
 202         writel(0, cryp->base + DSE_PRIO_0);
 203         writel(0, cryp->base + DSE_PRIO_1);
 204         writel(0, cryp->base + DSE_PRIO_2);
 205         writel(0, cryp->base + DSE_PRIO_3);
 206
 207         err = mtk_dfe_dse_state_check(cryp);
 208         if (err)
 209                 return err;
 210
 211         return 0;
 212 }
 213
 214 static void mtk_cmd_desc_ring_setup(struct mtk_cryp *cryp,
 215                                     int i, struct mtk_sys_cap *cap)
 216 {
 217         /* Full descriptor that fits FIFO minus one */
 218         u32 count =
 219                 ((1 << MTK_CMD_FIFO_SIZE(cap->hia_opt)) / MTK_DESC_SZ) - 1;
 220
 221         /* Temporarily disable external triggering */
 222         writel(0, cryp->base + CDR_CFG(i));
 223
 224         /* Clear CDR count */
 225         writel(MTK_CNT_RST, cryp->base + CDR_PREP_COUNT(i));
 226         writel(MTK_CNT_RST, cryp->base + CDR_PROC_COUNT(i));
 227
 228         writel(0, cryp->base + CDR_PREP_PNTR(i));
 229         writel(0, cryp->base + CDR_PROC_PNTR(i));
 230         writel(0, cryp->base + CDR_DMA_CFG(i));
 231
 232         /* Configure CDR host address space */
 233         writel(0, cryp->base + CDR_BASE_ADDR_HI(i));
 234         writel(cryp->ring[i]->cmd_dma, cryp->base + CDR_BASE_ADDR_LO(i));
 235
 236         writel(MTK_DESC_RING_SZ, cryp->base + CDR_RING_SIZE(i));
 237
 238         /* Clear and disable all CDR interrupts */
 239         writel(MTK_CDR_STAT_CLR, cryp->base + CDR_STAT(i));
 240
 241         /*
 242          * Set command descriptor offset and enable additional
 243          * token present in descriptor.
 244          */
 245         writel(MTK_DESC_SIZE(MTK_DESC_SZ) |
 246                    MTK_DESC_OFFSET(MTK_DESC_OFF) |
 247                MTK_DESC_ATP_PRESENT,
 248                cryp->base + CDR_DESC_SIZE(i));
 249
 250         writel(MTK_DESC_FETCH_SIZE(count * MTK_DESC_OFF) |
 251                    MTK_DESC_FETCH_THRESH(count * MTK_DESC_SZ),
 252                    cryp->base + CDR_CFG(i));
 253 }
 254
 255 static void mtk_res_desc_ring_setup(struct mtk_cryp *cryp,
 256                                     int i, struct mtk_sys_cap *cap)
 257 {
 258         u32 rndup = 2;
 259         u32 count = ((1 << MTK_RES_FIFO_SIZE(cap->hia_opt)) / rndup) - 1;
 260
 261         /* Temporarily disable external triggering */
 262         writel(0, cryp->base + RDR_CFG(i));
 263
 264         /* Clear RDR count */
 265         writel(MTK_CNT_RST, cryp->base + RDR_PREP_COUNT(i));
 266         writel(MTK_CNT_RST, cryp->base + RDR_PROC_COUNT(i));
 267
 268         writel(0, cryp->base + RDR_PREP_PNTR(i));
 269         writel(0, cryp->base + RDR_PROC_PNTR(i));
 270         writel(0, cryp->base + RDR_DMA_CFG(i));
 271
 272         /* Configure RDR host address space */
 273         writel(0, cryp->base + RDR_BASE_ADDR_HI(i));
 274         writel(cryp->ring[i]->res_dma, cryp->base + RDR_BASE_ADDR_LO(i));
 275
 276         writel(MTK_DESC_RING_SZ, cryp->base + RDR_RING_SIZE(i));
 277         writel(MTK_RDR_STAT_CLR, cryp->base + RDR_STAT(i));
 278
 279         /*
 280          * RDR manager generates update interrupts on a per-completed-packet,
 281          * and the rd_proc_thresh_irq interrupt is fired when proc_pkt_count
 282          * for the RDR exceeds the number of packets.
 283          */
 284         writel(MTK_RDR_PROC_THRESH | MTK_RDR_PROC_MODE,
 285                cryp->base + RDR_THRESH(i));
 286
 287         /*
 288          * Configure a threshold and time-out value for the processed
 289          * result descriptors (or complete packets) that are written to
 290          * the RDR.
 291          */
 292         writel(MTK_DESC_SIZE(MTK_DESC_SZ) | MTK_DESC_OFFSET(MTK_DESC_OFF),
 293                cryp->base + RDR_DESC_SIZE(i));
 294
 295         /*
 296          * Configure HIA fetch size and fetch threshold that are used to
 297          * fetch blocks of multiple descriptors.
 298          */
 299         writel(MTK_DESC_FETCH_SIZE(count * MTK_DESC_OFF) |
 300                MTK_DESC_FETCH_THRESH(count * rndup) |
 301                MTK_DESC_OVL_IRQ_EN,
 302                    cryp->base + RDR_CFG(i));
 303 }
 304
 305 static int mtk_packet_engine_setup(struct mtk_cryp *cryp)
 306 {
 307         struct mtk_sys_cap cap;
 308         int i, err;
 309         u32 val;
 310
 311         cap.hia_ver = readl(cryp->base + HIA_VERSION);
 312         cap.hia_opt = readl(cryp->base + HIA_OPTIONS);
 313         cap.hw_opt = readl(cryp->base + EIP97_OPTIONS);
 314
 315         if (!(((u16)cap.hia_ver) == MTK_HIA_SIGNATURE))
 316                 return -EINVAL;
 317
 318         /* Configure endianness conversion method for master (DMA) interface */
 319         writel(0, cryp->base + EIP97_MST_CTRL);
 320
 321         /* Set HIA burst size */
 322         val = readl(cryp->base + HIA_MST_CTRL);
 323         val &= ~MTK_BURST_SIZE_MSK;
 324         val |= MTK_BURST_SIZE(5);
 325         writel(val, cryp->base + HIA_MST_CTRL);
 326
 327         err = mtk_dfe_dse_reset(cryp);
 328         if (err) {
 329                 dev_err(cryp->dev, "Failed to reset DFE and DSE.\n");
 330                 return err;
 331         }
 332
 333         mtk_dfe_dse_buf_setup(cryp, &cap);
 334
 335         /* Enable the 4 rings for the packet engines. */
 336         mtk_desc_ring_link(cryp, 0xf);
 337
 338         for (i = 0; i < MTK_RING_MAX; i++) {
 339                 mtk_cmd_desc_ring_setup(cryp, i, &cap);
 340                 mtk_res_desc_ring_setup(cryp, i, &cap);
 341         }
 342
 343         writel(MTK_PE_TK_LOC_AVL | MTK_PE_PROC_HELD | MTK_PE_TK_TIMEOUT_EN,
 344                cryp->base + PE_TOKEN_CTRL_STAT);
 345
 346         /* Clear all pending interrupts */
 347         writel(MTK_AIC_G_CLR, cryp->base + AIC_G_ACK);
 348         writel(MTK_PE_INPUT_DMA_ERR | MTK_PE_OUTPUT_DMA_ERR |
 349                MTK_PE_PKT_PORC_ERR | MTK_PE_PKT_TIMEOUT |
 350                MTK_PE_FATAL_ERR | MTK_PE_INPUT_DMA_ERR_EN |
 351                MTK_PE_OUTPUT_DMA_ERR_EN | MTK_PE_PKT_PORC_ERR_EN |
 352                MTK_PE_PKT_TIMEOUT_EN | MTK_PE_FATAL_ERR_EN |
 353                MTK_PE_INT_OUT_EN,
 354                cryp->base + PE_INTERRUPT_CTRL_STAT);
 355
 356         return 0;
 357 }
 358
 359 static int mtk_aic_cap_check(struct mtk_cryp *cryp, int hw)
 360 {
 361         u32 val;
 362
 363         if (hw == MTK_RING_MAX)
 364                 val = readl(cryp->base + AIC_G_VERSION);
 365         else
 366                 val = readl(cryp->base + AIC_VERSION(hw));
 367
 368         val &= MTK_AIC_VER_MSK;
 369         if (val != MTK_AIC_VER11 && val != MTK_AIC_VER12)
 370                 return -ENXIO;
 371
 372         if (hw == MTK_RING_MAX)
 373                 val = readl(cryp->base + AIC_G_OPTIONS);
 374         else
 375                 val = readl(cryp->base + AIC_OPTIONS(hw));
 376
 377         val &= MTK_AIC_INT_MSK;
 378         if (!val || val > 32)
 379                 return -ENXIO;
 380
 381         return 0;
 382 }
 383
 384 static int mtk_aic_init(struct mtk_cryp *cryp, int hw)
 385 {
 386         int err;
 387
 388         err = mtk_aic_cap_check(cryp, hw);
 389         if (err)
 390                 return err;
 391
 392         /* Disable all interrupts and set initial configuration */
 393         if (hw == MTK_RING_MAX) {
 394                 writel(0, cryp->base + AIC_G_ENABLE_CTRL);
 395                 writel(0, cryp->base + AIC_G_POL_CTRL);
 396                 writel(0, cryp->base + AIC_G_TYPE_CTRL);
 397                 writel(0, cryp->base + AIC_G_ENABLE_SET);
 398         } else {
 399                 writel(0, cryp->base + AIC_ENABLE_CTRL(hw));
 400                 writel(0, cryp->base + AIC_POL_CTRL(hw));
 401                 writel(0, cryp->base + AIC_TYPE_CTRL(hw));
 402                 writel(0, cryp->base + AIC_ENABLE_SET(hw));
 403         }
 404
 405         return 0;
 406 }
 407
 408 static int mtk_accelerator_init(struct mtk_cryp *cryp)
 409 {
 410         int i, err;
 411
 412         /* Initialize advanced interrupt controller(AIC) */
 413         for (i = 0; i < MTK_IRQ_NUM; i++) {
 414                 err = mtk_aic_init(cryp, i);
 415                 if (err) {
 416                         dev_err(cryp->dev, "Failed to initialize AIC.\n");
 417                         return err;
 418                 }
 419         }
 420
 421         /* Initialize packet engine */
 422         err = mtk_packet_engine_setup(cryp);
 423         if (err) {
 424                 dev_err(cryp->dev, "Failed to configure packet engine.\n");
 425                 return err;
 426         }
 427
 428         return 0;
 429 }
 430
 431 static void mtk_desc_dma_free(struct mtk_cryp *cryp)
 432 {
 433         int i;
 434
 435         for (i = 0; i < MTK_RING_MAX; i++) {
 436                 dma_free_coherent(cryp->dev, MTK_DESC_RING_SZ,
 437                                   cryp->ring[i]->res_base,
 438                                   cryp->ring[i]->res_dma);
 439                 dma_free_coherent(cryp->dev, MTK_DESC_RING_SZ,
 440                                   cryp->ring[i]->cmd_base,
 441                                   cryp->ring[i]->cmd_dma);
 442                 kfree(cryp->ring[i]);
 443         }
 444 }
 445
 446 static int mtk_desc_ring_alloc(struct mtk_cryp *cryp)
 447 {
 448         struct mtk_ring **ring = cryp->ring;
 449         int i, err = ENOMEM;
 450
 451         for (i = 0; i < MTK_RING_MAX; i++) {
 452                 ring[i] = kzalloc(sizeof(**ring), GFP_KERNEL);
 453                 if (!ring[i])
 454                         goto err_cleanup;
 455
 456                 ring[i]->cmd_base = dma_alloc_coherent(cryp->dev,
 457                                                        MTK_DESC_RING_SZ,
 458                                                        &ring[i]->cmd_dma,
 459                                                        GFP_KERNEL);
 460                 if (!ring[i]->cmd_base)
 461                         goto err_cleanup;
 462
 463                 ring[i]->res_base = dma_alloc_coherent(cryp->dev,
 464                                                        MTK_DESC_RING_SZ,
 465                                                        &ring[i]->res_dma,
 466                                                        GFP_KERNEL);
 467                 if (!ring[i]->res_base)
 468                         goto err_cleanup;
 469
 470                 ring[i]->cmd_next = ring[i]->cmd_base;
 471                 ring[i]->res_next = ring[i]->res_base;
 472         }
 473         return 0;
 474
 475 err_cleanup:
 476         for (; i--; ) {
 477                 dma_free_coherent(cryp->dev, MTK_DESC_RING_SZ,
 478                                   ring[i]->res_base, ring[i]->res_dma);
 479                 dma_free_coherent(cryp->dev, MTK_DESC_RING_SZ,
 480                                   ring[i]->cmd_base, ring[i]->cmd_dma);
 481                 kfree(ring[i]);
 482         }
 483         return err;
 484 }
 485
 486 static int mtk_crypto_probe(struct platform_device *pdev)
 487 {
 488         struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 489         struct mtk_cryp *cryp;
 490         int i, err;
 491
 492         cryp = devm_kzalloc(&pdev->dev, sizeof(*cryp), GFP_KERNEL);
 493         if (!cryp)
 494                 return -ENOMEM;
 495
 496         cryp->base = devm_ioremap_resource(&pdev->dev, res);
 497         if (IS_ERR(cryp->base))
 498                 return PTR_ERR(cryp->base);
 499
 500         for (i = 0; i < MTK_IRQ_NUM; i++) {
 501                 cryp->irq[i] = platform_get_irq(pdev, i);
 502                 if (cryp->irq[i] < 0) {
 503                         dev_err(cryp->dev, "no IRQ:%d resource info\n", i);
 504                         return cryp->irq[i];
 505                 }
 506         }
 507
 508         cryp->clk_cryp = devm_clk_get(&pdev->dev, "cryp");
 509         if (IS_ERR(cryp->clk_cryp))
 510                 return -EPROBE_DEFER;
 511
 512         cryp->dev = &pdev->dev;
 513         pm_runtime_enable(cryp->dev);
 514         pm_runtime_get_sync(cryp->dev);
 515
 516         err = clk_prepare_enable(cryp->clk_cryp);
 517         if (err)
 518                 goto err_clk_cryp;
 519
 520         /* Allocate four command/result descriptor rings */
 521         err = mtk_desc_ring_alloc(cryp);
 522         if (err) {
 523                 dev_err(cryp->dev, "Unable to allocate descriptor rings.\n");
 524                 goto err_resource;
 525         }
 526
 527         /* Initialize hardware modules */
 528         err = mtk_accelerator_init(cryp);
 529         if (err) {
 530                 dev_err(cryp->dev, "Failed to initialize cryptographic engine.\n");
 531                 goto err_engine;
 532         }
 533
 534         err = mtk_cipher_alg_register(cryp);
 535         if (err) {
 536                 dev_err(cryp->dev, "Unable to register cipher algorithm.\n");
 537                 goto err_cipher;
 538         }
 539
 540         err = mtk_hash_alg_register(cryp);
 541         if (err) {
 542                 dev_err(cryp->dev, "Unable to register hash algorithm.\n");
 543                 goto err_hash;
 544         }
 545
 546         platform_set_drvdata(pdev, cryp);
 547         return 0;
 548
 549 err_hash:
 550         mtk_cipher_alg_release(cryp);
 551 err_cipher:
 552         mtk_dfe_dse_reset(cryp);
 553 err_engine:
 554         mtk_desc_dma_free(cryp);
 555 err_resource:
 556         clk_disable_unprepare(cryp->clk_cryp);
 557 err_clk_cryp:
 558         pm_runtime_put_sync(cryp->dev);
 559         pm_runtime_disable(cryp->dev);
 560
 561         return err;
 562 }
 563
 564 static int mtk_crypto_remove(struct platform_device *pdev)
 565 {
 566         struct mtk_cryp *cryp = platform_get_drvdata(pdev);
 567
 568         mtk_hash_alg_release(cryp);
 569         mtk_cipher_alg_release(cryp);
 570         mtk_desc_dma_free(cryp);
 571
 572         clk_disable_unprepare(cryp->clk_cryp);
 573
 574         pm_runtime_put_sync(cryp->dev);
 575         pm_runtime_disable(cryp->dev);
 576         platform_set_drvdata(pdev, NULL);
 577
 578         return 0;
 579 }
 580
 581 static const struct of_device_id of_crypto_id[] = {
 582         { .compatible = "mediatek,eip97-crypto" },
 583         {},
 584 };
 585 MODULE_DEVICE_TABLE(of, of_crypto_id);
 586
 587 static struct platform_driver mtk_crypto_driver = {
 588         .probe = mtk_crypto_probe,
 589         .remove = mtk_crypto_remove,
 590         .driver = {
 591                    .name = "mtk-crypto",
 592                    .of_match_table = of_crypto_id,
 593         },
 594 };
 595 module_platform_driver(mtk_crypto_driver);
 596
 597 MODULE_LICENSE("GPL");
 598 MODULE_AUTHOR("Ryder Lee <ryder.lee@mediatek.com>");
 599 MODULE_DESCRIPTION("Cryptographic accelerator driver for EIP97");