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Linux 5.1.15
[linux/fpc-iii.git] / drivers / iommu / intel_irq_remapping.c
blob2d74641b7f7bc5aa51a524e9a018e84cdb8fac9a
1 // SPDX-License-Identifier: GPL-2.0
2
3 #define pr_fmt(fmt) "DMAR-IR: " fmt
4
5 #include <linux/interrupt.h>
6 #include <linux/dmar.h>
7 #include <linux/spinlock.h>
8 #include <linux/slab.h>
9 #include <linux/jiffies.h>
10 #include <linux/hpet.h>
11 #include <linux/pci.h>
12 #include <linux/irq.h>
13 #include <linux/intel-iommu.h>
14 #include <linux/acpi.h>
15 #include <linux/irqdomain.h>
16 #include <linux/crash_dump.h>
17 #include <asm/io_apic.h>
18 #include <asm/smp.h>
19 #include <asm/cpu.h>
20 #include <asm/irq_remapping.h>
21 #include <asm/pci-direct.h>
22 #include <asm/msidef.h>
23
24 #include "irq_remapping.h"
25
26 enum irq_mode {
27 IRQ_REMAPPING,
28 IRQ_POSTING,
29 };
30
31 struct ioapic_scope {
32 struct intel_iommu *iommu;
33 unsigned int id;
34 unsigned int bus; /* PCI bus number */
35 unsigned int devfn; /* PCI devfn number */
36 };
37
38 struct hpet_scope {
39 struct intel_iommu *iommu;
40 u8 id;
41 unsigned int bus;
42 unsigned int devfn;
43 };
44
45 struct irq_2_iommu {
46 struct intel_iommu *iommu;
47 u16 irte_index;
48 u16 sub_handle;
49 u8 irte_mask;
50 enum irq_mode mode;
51 };
52
53 struct intel_ir_data {
54 struct irq_2_iommu irq_2_iommu;
55 struct irte irte_entry;
56 union {
57 struct msi_msg msi_entry;
58 };
59 };
60
61 #define IR_X2APIC_MODE(mode) (mode ? (1 << 11) : 0)
62 #define IRTE_DEST(dest) ((eim_mode) ? dest : dest << 8)
63
64 static int __read_mostly eim_mode;
65 static struct ioapic_scope ir_ioapic[MAX_IO_APICS];
66 static struct hpet_scope ir_hpet[MAX_HPET_TBS];
67
68 /*
69 * Lock ordering:
70 * ->dmar_global_lock
71 * ->irq_2_ir_lock
72 * ->qi->q_lock
73 * ->iommu->register_lock
74 * Note:
75 * intel_irq_remap_ops.{supported,prepare,enable,disable,reenable} are called
76 * in single-threaded environment with interrupt disabled, so no need to tabke
77 * the dmar_global_lock.
78 */
79 DEFINE_RAW_SPINLOCK(irq_2_ir_lock);
80 static const struct irq_domain_ops intel_ir_domain_ops;
81
82 static void iommu_disable_irq_remapping(struct intel_iommu *iommu);
83 static int __init parse_ioapics_under_ir(void);
84
85 static bool ir_pre_enabled(struct intel_iommu *iommu)
86 {
87 return (iommu->flags & VTD_FLAG_IRQ_REMAP_PRE_ENABLED);
88 }
89
90 static void clear_ir_pre_enabled(struct intel_iommu *iommu)
91 {
92 iommu->flags &= ~VTD_FLAG_IRQ_REMAP_PRE_ENABLED;
93 }
94
95 static void init_ir_status(struct intel_iommu *iommu)
96 {
97 u32 gsts;
98
99 gsts = readl(iommu->reg + DMAR_GSTS_REG);
100 if (gsts & DMA_GSTS_IRES)
101 iommu->flags |= VTD_FLAG_IRQ_REMAP_PRE_ENABLED;
102 }
103
104 static int alloc_irte(struct intel_iommu *iommu, int irq,
105 struct irq_2_iommu *irq_iommu, u16 count)
106 {
107 struct ir_table *table = iommu->ir_table;
108 unsigned int mask = 0;
109 unsigned long flags;
110 int index;
111
112 if (!count || !irq_iommu)
113 return -1;
114
115 if (count > 1) {
116 count = __roundup_pow_of_two(count);
117 mask = ilog2(count);
118 }
119
120 if (mask > ecap_max_handle_mask(iommu->ecap)) {
121 pr_err("Requested mask %x exceeds the max invalidation handle"
122 " mask value %Lx\n", mask,
123 ecap_max_handle_mask(iommu->ecap));
124 return -1;
125 }
126
127 raw_spin_lock_irqsave(&irq_2_ir_lock, flags);
128 index = bitmap_find_free_region(table->bitmap,
129 INTR_REMAP_TABLE_ENTRIES, mask);
130 if (index < 0) {
131 pr_warn("IR%d: can't allocate an IRTE\n", iommu->seq_id);
132 } else {
133 irq_iommu->iommu = iommu;
134 irq_iommu->irte_index = index;
135 irq_iommu->sub_handle = 0;
136 irq_iommu->irte_mask = mask;
137 irq_iommu->mode = IRQ_REMAPPING;
138 }
139 raw_spin_unlock_irqrestore(&irq_2_ir_lock, flags);
140
141 return index;
142 }
143
144 static int qi_flush_iec(struct intel_iommu *iommu, int index, int mask)
145 {
146 struct qi_desc desc;
147
148 desc.qw0 = QI_IEC_IIDEX(index) | QI_IEC_TYPE | QI_IEC_IM(mask)
149 | QI_IEC_SELECTIVE;
150 desc.qw1 = 0;
151 desc.qw2 = 0;
152 desc.qw3 = 0;
153
154 return qi_submit_sync(&desc, iommu);
155 }
156
157 static int modify_irte(struct irq_2_iommu *irq_iommu,
158 struct irte *irte_modified)
159 {
160 struct intel_iommu *iommu;
161 unsigned long flags;
162 struct irte *irte;
163 int rc, index;
164
165 if (!irq_iommu)
166 return -1;
167
168 raw_spin_lock_irqsave(&irq_2_ir_lock, flags);
169
170 iommu = irq_iommu->iommu;
171
172 index = irq_iommu->irte_index + irq_iommu->sub_handle;
173 irte = &iommu->ir_table->base[index];
174
175 #if defined(CONFIG_HAVE_CMPXCHG_DOUBLE)
176 if ((irte->pst == 1) || (irte_modified->pst == 1)) {
177 bool ret;
178
179 ret = cmpxchg_double(&irte->low, &irte->high,
180 irte->low, irte->high,
181 irte_modified->low, irte_modified->high);
182 /*
183 * We use cmpxchg16 to atomically update the 128-bit IRTE,
184 * and it cannot be updated by the hardware or other processors
185 * behind us, so the return value of cmpxchg16 should be the
186 * same as the old value.
187 */
188 WARN_ON(!ret);
189 } else
190 #endif
191 {
192 set_64bit(&irte->low, irte_modified->low);
193 set_64bit(&irte->high, irte_modified->high);
194 }
195 __iommu_flush_cache(iommu, irte, sizeof(*irte));
196
197 rc = qi_flush_iec(iommu, index, 0);
198
199 /* Update iommu mode according to the IRTE mode */
200 irq_iommu->mode = irte->pst ? IRQ_POSTING : IRQ_REMAPPING;
201 raw_spin_unlock_irqrestore(&irq_2_ir_lock, flags);
202
203 return rc;
204 }
205
206 static struct intel_iommu *map_hpet_to_ir(u8 hpet_id)
207 {
208 int i;
209
210 for (i = 0; i < MAX_HPET_TBS; i++)
211 if (ir_hpet[i].id == hpet_id && ir_hpet[i].iommu)
212 return ir_hpet[i].iommu;
213 return NULL;
214 }
215
216 static struct intel_iommu *map_ioapic_to_ir(int apic)
217 {
218 int i;
219
220 for (i = 0; i < MAX_IO_APICS; i++)
221 if (ir_ioapic[i].id == apic && ir_ioapic[i].iommu)
222 return ir_ioapic[i].iommu;
223 return NULL;
224 }
225
226 static struct intel_iommu *map_dev_to_ir(struct pci_dev *dev)
227 {
228 struct dmar_drhd_unit *drhd;
229
230 drhd = dmar_find_matched_drhd_unit(dev);
231 if (!drhd)
232 return NULL;
233
234 return drhd->iommu;
235 }
236
237 static int clear_entries(struct irq_2_iommu *irq_iommu)
238 {
239 struct irte *start, *entry, *end;
240 struct intel_iommu *iommu;
241 int index;
242
243 if (irq_iommu->sub_handle)
244 return 0;
245
246 iommu = irq_iommu->iommu;
247 index = irq_iommu->irte_index;
248
249 start = iommu->ir_table->base + index;
250 end = start + (1 << irq_iommu->irte_mask);
251
252 for (entry = start; entry < end; entry++) {
253 set_64bit(&entry->low, 0);
254 set_64bit(&entry->high, 0);
255 }
256 bitmap_release_region(iommu->ir_table->bitmap, index,
257 irq_iommu->irte_mask);
258
259 return qi_flush_iec(iommu, index, irq_iommu->irte_mask);
260 }
261
262 /*
263 * source validation type
264 */
265 #define SVT_NO_VERIFY 0x0 /* no verification is required */
266 #define SVT_VERIFY_SID_SQ 0x1 /* verify using SID and SQ fields */
267 #define SVT_VERIFY_BUS 0x2 /* verify bus of request-id */
268
269 /*
270 * source-id qualifier
271 */
272 #define SQ_ALL_16 0x0 /* verify all 16 bits of request-id */
273 #define SQ_13_IGNORE_1 0x1 /* verify most significant 13 bits, ignore
274 * the third least significant bit
275 */
276 #define SQ_13_IGNORE_2 0x2 /* verify most significant 13 bits, ignore
277 * the second and third least significant bits
278 */
279 #define SQ_13_IGNORE_3 0x3 /* verify most significant 13 bits, ignore
280 * the least three significant bits
281 */
282
283 /*
284 * set SVT, SQ and SID fields of irte to verify
285 * source ids of interrupt requests
286 */
287 static void set_irte_sid(struct irte *irte, unsigned int svt,
288 unsigned int sq, unsigned int sid)
289 {
290 if (disable_sourceid_checking)
291 svt = SVT_NO_VERIFY;
292 irte->svt = svt;
293 irte->sq = sq;
294 irte->sid = sid;
295 }
296
297 /*
298 * Set an IRTE to match only the bus number. Interrupt requests that reference
299 * this IRTE must have a requester-id whose bus number is between or equal
300 * to the start_bus and end_bus arguments.
301 */
302 static void set_irte_verify_bus(struct irte *irte, unsigned int start_bus,
303 unsigned int end_bus)
304 {
305 set_irte_sid(irte, SVT_VERIFY_BUS, SQ_ALL_16,
306 (start_bus << 8) | end_bus);
307 }
308
309 static int set_ioapic_sid(struct irte *irte, int apic)
310 {
311 int i;
312 u16 sid = 0;
313
314 if (!irte)
315 return -1;
316
317 down_read(&dmar_global_lock);
318 for (i = 0; i < MAX_IO_APICS; i++) {
319 if (ir_ioapic[i].iommu && ir_ioapic[i].id == apic) {
320 sid = (ir_ioapic[i].bus << 8) | ir_ioapic[i].devfn;
321 break;
322 }
323 }
324 up_read(&dmar_global_lock);
325
326 if (sid == 0) {
327 pr_warn("Failed to set source-id of IOAPIC (%d)\n", apic);
328 return -1;
329 }
330
331 set_irte_sid(irte, SVT_VERIFY_SID_SQ, SQ_ALL_16, sid);
332
333 return 0;
334 }
335
336 static int set_hpet_sid(struct irte *irte, u8 id)
337 {
338 int i;
339 u16 sid = 0;
340
341 if (!irte)
342 return -1;
343
344 down_read(&dmar_global_lock);
345 for (i = 0; i < MAX_HPET_TBS; i++) {
346 if (ir_hpet[i].iommu && ir_hpet[i].id == id) {
347 sid = (ir_hpet[i].bus << 8) | ir_hpet[i].devfn;
348 break;
349 }
350 }
351 up_read(&dmar_global_lock);
352
353 if (sid == 0) {
354 pr_warn("Failed to set source-id of HPET block (%d)\n", id);
355 return -1;
356 }
357
358 /*
359 * Should really use SQ_ALL_16. Some platforms are broken.
360 * While we figure out the right quirks for these broken platforms, use
361 * SQ_13_IGNORE_3 for now.
362 */
363 set_irte_sid(irte, SVT_VERIFY_SID_SQ, SQ_13_IGNORE_3, sid);
364
365 return 0;
366 }
367
368 struct set_msi_sid_data {
369 struct pci_dev *pdev;
370 u16 alias;
371 int count;
372 int busmatch_count;
373 };
374
375 static int set_msi_sid_cb(struct pci_dev *pdev, u16 alias, void *opaque)
376 {
377 struct set_msi_sid_data *data = opaque;
378
379 data->pdev = pdev;
380 data->alias = alias;
381 data->count++;
382
383 if (PCI_BUS_NUM(alias) == pdev->bus->number)
384 data->busmatch_count++;
385
386 return 0;
387 }
388
389 static int set_msi_sid(struct irte *irte, struct pci_dev *dev)
390 {
391 struct set_msi_sid_data data;
392
393 if (!irte || !dev)
394 return -1;
395
396 data.count = 0;
397 data.busmatch_count = 0;
398 pci_for_each_dma_alias(dev, set_msi_sid_cb, &data);
399
400 /*
401 * DMA alias provides us with a PCI device and alias. The only case
402 * where the it will return an alias on a different bus than the
403 * device is the case of a PCIe-to-PCI bridge, where the alias is for
404 * the subordinate bus. In this case we can only verify the bus.
405 *
406 * If there are multiple aliases, all with the same bus number,
407 * then all we can do is verify the bus. This is typical in NTB
408 * hardware which use proxy IDs where the device will generate traffic
409 * from multiple devfn numbers on the same bus.
410 *
411 * If the alias device is on a different bus than our source device
412 * then we have a topology based alias, use it.
413 *
414 * Otherwise, the alias is for a device DMA quirk and we cannot
415 * assume that MSI uses the same requester ID. Therefore use the
416 * original device.
417 */
418 if (PCI_BUS_NUM(data.alias) != data.pdev->bus->number)
419 set_irte_verify_bus(irte, PCI_BUS_NUM(data.alias),
420 dev->bus->number);
421 else if (data.count >= 2 && data.busmatch_count == data.count)
422 set_irte_verify_bus(irte, dev->bus->number, dev->bus->number);
423 else if (data.pdev->bus->number != dev->bus->number)
424 set_irte_sid(irte, SVT_VERIFY_SID_SQ, SQ_ALL_16, data.alias);
425 else
426 set_irte_sid(irte, SVT_VERIFY_SID_SQ, SQ_ALL_16,
427 PCI_DEVID(dev->bus->number, dev->devfn));
428
429 return 0;
430 }
431
432 static int iommu_load_old_irte(struct intel_iommu *iommu)
433 {
434 struct irte *old_ir_table;
435 phys_addr_t irt_phys;
436 unsigned int i;
437 size_t size;
438 u64 irta;
439
440 /* Check whether the old ir-table has the same size as ours */
441 irta = dmar_readq(iommu->reg + DMAR_IRTA_REG);
442 if ((irta & INTR_REMAP_TABLE_REG_SIZE_MASK)
443 != INTR_REMAP_TABLE_REG_SIZE)
444 return -EINVAL;
445
446 irt_phys = irta & VTD_PAGE_MASK;
447 size = INTR_REMAP_TABLE_ENTRIES*sizeof(struct irte);
448
449 /* Map the old IR table */
450 old_ir_table = memremap(irt_phys, size, MEMREMAP_WB);
451 if (!old_ir_table)
452 return -ENOMEM;
453
454 /* Copy data over */
455 memcpy(iommu->ir_table->base, old_ir_table, size);
456
457 __iommu_flush_cache(iommu, iommu->ir_table->base, size);
458
459 /*
460 * Now check the table for used entries and mark those as
461 * allocated in the bitmap
462 */
463 for (i = 0; i < INTR_REMAP_TABLE_ENTRIES; i++) {
464 if (iommu->ir_table->base[i].present)
465 bitmap_set(iommu->ir_table->bitmap, i, 1);
466 }
467
468 memunmap(old_ir_table);
469
470 return 0;
471 }
472
473
474 static void iommu_set_irq_remapping(struct intel_iommu *iommu, int mode)
475 {
476 unsigned long flags;
477 u64 addr;
478 u32 sts;
479
480 addr = virt_to_phys((void *)iommu->ir_table->base);
481
482 raw_spin_lock_irqsave(&iommu->register_lock, flags);
483
484 dmar_writeq(iommu->reg + DMAR_IRTA_REG,
485 (addr) | IR_X2APIC_MODE(mode) | INTR_REMAP_TABLE_REG_SIZE);
486
487 /* Set interrupt-remapping table pointer */
488 writel(iommu->gcmd | DMA_GCMD_SIRTP, iommu->reg + DMAR_GCMD_REG);
489
490 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
491 readl, (sts & DMA_GSTS_IRTPS), sts);
492 raw_spin_unlock_irqrestore(&iommu->register_lock, flags);
493
494 /*
495 * Global invalidation of interrupt entry cache to make sure the
496 * hardware uses the new irq remapping table.
497 */
498 qi_global_iec(iommu);
499 }
500
501 static void iommu_enable_irq_remapping(struct intel_iommu *iommu)
502 {
503 unsigned long flags;
504 u32 sts;
505
506 raw_spin_lock_irqsave(&iommu->register_lock, flags);
507
508 /* Enable interrupt-remapping */
509 iommu->gcmd |= DMA_GCMD_IRE;
510 iommu->gcmd &= ~DMA_GCMD_CFI; /* Block compatibility-format MSIs */
511 writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
512
513 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
514 readl, (sts & DMA_GSTS_IRES), sts);
515
516 /*
517 * With CFI clear in the Global Command register, we should be
518 * protected from dangerous (i.e. compatibility) interrupts
519 * regardless of x2apic status. Check just to be sure.
520 */
521 if (sts & DMA_GSTS_CFIS)
522 WARN(1, KERN_WARNING
523 "Compatibility-format IRQs enabled despite intr remapping;\n"
524 "you are vulnerable to IRQ injection.\n");
525
526 raw_spin_unlock_irqrestore(&iommu->register_lock, flags);
527 }
528
529 static int intel_setup_irq_remapping(struct intel_iommu *iommu)
530 {
531 struct ir_table *ir_table;
532 struct fwnode_handle *fn;
533 unsigned long *bitmap;
534 struct page *pages;
535
536 if (iommu->ir_table)
537 return 0;
538
539 ir_table = kzalloc(sizeof(struct ir_table), GFP_KERNEL);
540 if (!ir_table)
541 return -ENOMEM;
542
543 pages = alloc_pages_node(iommu->node, GFP_KERNEL | __GFP_ZERO,
544 INTR_REMAP_PAGE_ORDER);
545 if (!pages) {
546 pr_err("IR%d: failed to allocate pages of order %d\n",
547 iommu->seq_id, INTR_REMAP_PAGE_ORDER);
548 goto out_free_table;
549 }
550
551 bitmap = kcalloc(BITS_TO_LONGS(INTR_REMAP_TABLE_ENTRIES),
552 sizeof(long), GFP_ATOMIC);
553 if (bitmap == NULL) {
554 pr_err("IR%d: failed to allocate bitmap\n", iommu->seq_id);
555 goto out_free_pages;
556 }
557
558 fn = irq_domain_alloc_named_id_fwnode("INTEL-IR", iommu->seq_id);
559 if (!fn)
560 goto out_free_bitmap;
561
562 iommu->ir_domain =
563 irq_domain_create_hierarchy(arch_get_ir_parent_domain(),
564 0, INTR_REMAP_TABLE_ENTRIES,
565 fn, &intel_ir_domain_ops,
566 iommu);
567 irq_domain_free_fwnode(fn);
568 if (!iommu->ir_domain) {
569 pr_err("IR%d: failed to allocate irqdomain\n", iommu->seq_id);
570 goto out_free_bitmap;
571 }
572 iommu->ir_msi_domain =
573 arch_create_remap_msi_irq_domain(iommu->ir_domain,
574 "INTEL-IR-MSI",
575 iommu->seq_id);
576
577 ir_table->base = page_address(pages);
578 ir_table->bitmap = bitmap;
579 iommu->ir_table = ir_table;
580
581 /*
582 * If the queued invalidation is already initialized,
583 * shouldn't disable it.
584 */
585 if (!iommu->qi) {
586 /*
587 * Clear previous faults.
588 */
589 dmar_fault(-1, iommu);
590 dmar_disable_qi(iommu);
591
592 if (dmar_enable_qi(iommu)) {
593 pr_err("Failed to enable queued invalidation\n");
594 goto out_free_bitmap;
595 }
596 }
597
598 init_ir_status(iommu);
599
600 if (ir_pre_enabled(iommu)) {
601 if (!is_kdump_kernel()) {
602 pr_warn("IRQ remapping was enabled on %s but we are not in kdump mode\n",
603 iommu->name);
604 clear_ir_pre_enabled(iommu);
605 iommu_disable_irq_remapping(iommu);
606 } else if (iommu_load_old_irte(iommu))
607 pr_err("Failed to copy IR table for %s from previous kernel\n",
608 iommu->name);
609 else
610 pr_info("Copied IR table for %s from previous kernel\n",
611 iommu->name);
612 }
613
614 iommu_set_irq_remapping(iommu, eim_mode);
615
616 return 0;
617
618 out_free_bitmap:
619 kfree(bitmap);
620 out_free_pages:
621 __free_pages(pages, INTR_REMAP_PAGE_ORDER);
622 out_free_table:
623 kfree(ir_table);
624
625 iommu->ir_table = NULL;
626
627 return -ENOMEM;
628 }
629
630 static void intel_teardown_irq_remapping(struct intel_iommu *iommu)
631 {
632 if (iommu && iommu->ir_table) {
633 if (iommu->ir_msi_domain) {
634 irq_domain_remove(iommu->ir_msi_domain);
635 iommu->ir_msi_domain = NULL;
636 }
637 if (iommu->ir_domain) {
638 irq_domain_remove(iommu->ir_domain);
639 iommu->ir_domain = NULL;
640 }
641 free_pages((unsigned long)iommu->ir_table->base,
642 INTR_REMAP_PAGE_ORDER);
643 kfree(iommu->ir_table->bitmap);
644 kfree(iommu->ir_table);
645 iommu->ir_table = NULL;
646 }
647 }
648
649 /*
650 * Disable Interrupt Remapping.
651 */
652 static void iommu_disable_irq_remapping(struct intel_iommu *iommu)
653 {
654 unsigned long flags;
655 u32 sts;
656
657 if (!ecap_ir_support(iommu->ecap))
658 return;
659
660 /*
661 * global invalidation of interrupt entry cache before disabling
662 * interrupt-remapping.
663 */
664 qi_global_iec(iommu);
665
666 raw_spin_lock_irqsave(&iommu->register_lock, flags);
667
668 sts = readl(iommu->reg + DMAR_GSTS_REG);
669 if (!(sts & DMA_GSTS_IRES))
670 goto end;
671
672 iommu->gcmd &= ~DMA_GCMD_IRE;
673 writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
674
675 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
676 readl, !(sts & DMA_GSTS_IRES), sts);
677
678 end:
679 raw_spin_unlock_irqrestore(&iommu->register_lock, flags);
680 }
681
682 static int __init dmar_x2apic_optout(void)
683 {
684 struct acpi_table_dmar *dmar;
685 dmar = (struct acpi_table_dmar *)dmar_tbl;
686 if (!dmar || no_x2apic_optout)
687 return 0;
688 return dmar->flags & DMAR_X2APIC_OPT_OUT;
689 }
690
691 static void __init intel_cleanup_irq_remapping(void)
692 {
693 struct dmar_drhd_unit *drhd;
694 struct intel_iommu *iommu;
695
696 for_each_iommu(iommu, drhd) {
697 if (ecap_ir_support(iommu->ecap)) {
698 iommu_disable_irq_remapping(iommu);
699 intel_teardown_irq_remapping(iommu);
700 }
701 }
702
703 if (x2apic_supported())
704 pr_warn("Failed to enable irq remapping. You are vulnerable to irq-injection attacks.\n");
705 }
706
707 static int __init intel_prepare_irq_remapping(void)
708 {
709 struct dmar_drhd_unit *drhd;
710 struct intel_iommu *iommu;
711 int eim = 0;
712
713 if (irq_remap_broken) {
714 pr_warn("This system BIOS has enabled interrupt remapping\n"
715 "on a chipset that contains an erratum making that\n"
716 "feature unstable. To maintain system stability\n"
717 "interrupt remapping is being disabled. Please\n"
718 "contact your BIOS vendor for an update\n");
719 add_taint(TAINT_FIRMWARE_WORKAROUND, LOCKDEP_STILL_OK);
720 return -ENODEV;
721 }
722
723 if (dmar_table_init() < 0)
724 return -ENODEV;
725
726 if (!dmar_ir_support())
727 return -ENODEV;
728
729 if (parse_ioapics_under_ir()) {
730 pr_info("Not enabling interrupt remapping\n");
731 goto error;
732 }
733
734 /* First make sure all IOMMUs support IRQ remapping */
735 for_each_iommu(iommu, drhd)
736 if (!ecap_ir_support(iommu->ecap))
737 goto error;
738
739 /* Detect remapping mode: lapic or x2apic */
740 if (x2apic_supported()) {
741 eim = !dmar_x2apic_optout();
742 if (!eim) {
743 pr_info("x2apic is disabled because BIOS sets x2apic opt out bit.");
744 pr_info("Use 'intremap=no_x2apic_optout' to override the BIOS setting.\n");
745 }
746 }
747
748 for_each_iommu(iommu, drhd) {
749 if (eim && !ecap_eim_support(iommu->ecap)) {
750 pr_info("%s does not support EIM\n", iommu->name);
751 eim = 0;
752 }
753 }
754
755 eim_mode = eim;
756 if (eim)
757 pr_info("Queued invalidation will be enabled to support x2apic and Intr-remapping.\n");
758
759 /* Do the initializations early */
760 for_each_iommu(iommu, drhd) {
761 if (intel_setup_irq_remapping(iommu)) {
762 pr_err("Failed to setup irq remapping for %s\n",
763 iommu->name);
764 goto error;
765 }
766 }
767
768 return 0;
769
770 error:
771 intel_cleanup_irq_remapping();
772 return -ENODEV;
773 }
774
775 /*
776 * Set Posted-Interrupts capability.
777 */
778 static inline void set_irq_posting_cap(void)
779 {
780 struct dmar_drhd_unit *drhd;
781 struct intel_iommu *iommu;
782
783 if (!disable_irq_post) {
784 /*
785 * If IRTE is in posted format, the 'pda' field goes across the
786 * 64-bit boundary, we need use cmpxchg16b to atomically update
787 * it. We only expose posted-interrupt when X86_FEATURE_CX16
788 * is supported. Actually, hardware platforms supporting PI
789 * should have X86_FEATURE_CX16 support, this has been confirmed
790 * with Intel hardware guys.
791 */
792 if (boot_cpu_has(X86_FEATURE_CX16))
793 intel_irq_remap_ops.capability |= 1 << IRQ_POSTING_CAP;
794
795 for_each_iommu(iommu, drhd)
796 if (!cap_pi_support(iommu->cap)) {
797 intel_irq_remap_ops.capability &=
798 ~(1 << IRQ_POSTING_CAP);
799 break;
800 }
801 }
802 }
803
804 static int __init intel_enable_irq_remapping(void)
805 {
806 struct dmar_drhd_unit *drhd;
807 struct intel_iommu *iommu;
808 bool setup = false;
809
810 /*
811 * Setup Interrupt-remapping for all the DRHD's now.
812 */
813 for_each_iommu(iommu, drhd) {
814 if (!ir_pre_enabled(iommu))
815 iommu_enable_irq_remapping(iommu);
816 setup = true;
817 }
818
819 if (!setup)
820 goto error;
821
822 irq_remapping_enabled = 1;
823
824 set_irq_posting_cap();
825
826 pr_info("Enabled IRQ remapping in %s mode\n", eim_mode ? "x2apic" : "xapic");
827
828 return eim_mode ? IRQ_REMAP_X2APIC_MODE : IRQ_REMAP_XAPIC_MODE;
829
830 error:
831 intel_cleanup_irq_remapping();
832 return -1;
833 }
834
835 static int ir_parse_one_hpet_scope(struct acpi_dmar_device_scope *scope,
836 struct intel_iommu *iommu,
837 struct acpi_dmar_hardware_unit *drhd)
838 {
839 struct acpi_dmar_pci_path *path;
840 u8 bus;
841 int count, free = -1;
842
843 bus = scope->bus;
844 path = (struct acpi_dmar_pci_path *)(scope + 1);
845 count = (scope->length - sizeof(struct acpi_dmar_device_scope))
846 / sizeof(struct acpi_dmar_pci_path);
847
848 while (--count > 0) {
849 /*
850 * Access PCI directly due to the PCI
851 * subsystem isn't initialized yet.
852 */
853 bus = read_pci_config_byte(bus, path->device, path->function,
854 PCI_SECONDARY_BUS);
855 path++;
856 }
857
858 for (count = 0; count < MAX_HPET_TBS; count++) {
859 if (ir_hpet[count].iommu == iommu &&
860 ir_hpet[count].id == scope->enumeration_id)
861 return 0;
862 else if (ir_hpet[count].iommu == NULL && free == -1)
863 free = count;
864 }
865 if (free == -1) {
866 pr_warn("Exceeded Max HPET blocks\n");
867 return -ENOSPC;
868 }
869
870 ir_hpet[free].iommu = iommu;
871 ir_hpet[free].id = scope->enumeration_id;
872 ir_hpet[free].bus = bus;
873 ir_hpet[free].devfn = PCI_DEVFN(path->device, path->function);
874 pr_info("HPET id %d under DRHD base 0x%Lx\n",
875 scope->enumeration_id, drhd->address);
876
877 return 0;
878 }
879
880 static int ir_parse_one_ioapic_scope(struct acpi_dmar_device_scope *scope,
881 struct intel_iommu *iommu,
882 struct acpi_dmar_hardware_unit *drhd)
883 {
884 struct acpi_dmar_pci_path *path;
885 u8 bus;
886 int count, free = -1;
887
888 bus = scope->bus;
889 path = (struct acpi_dmar_pci_path *)(scope + 1);
890 count = (scope->length - sizeof(struct acpi_dmar_device_scope))
891 / sizeof(struct acpi_dmar_pci_path);
892
893 while (--count > 0) {
894 /*
895 * Access PCI directly due to the PCI
896 * subsystem isn't initialized yet.
897 */
898 bus = read_pci_config_byte(bus, path->device, path->function,
899 PCI_SECONDARY_BUS);
900 path++;
901 }
902
903 for (count = 0; count < MAX_IO_APICS; count++) {
904 if (ir_ioapic[count].iommu == iommu &&
905 ir_ioapic[count].id == scope->enumeration_id)
906 return 0;
907 else if (ir_ioapic[count].iommu == NULL && free == -1)
908 free = count;
909 }
910 if (free == -1) {
911 pr_warn("Exceeded Max IO APICS\n");
912 return -ENOSPC;
913 }
914
915 ir_ioapic[free].bus = bus;
916 ir_ioapic[free].devfn = PCI_DEVFN(path->device, path->function);
917 ir_ioapic[free].iommu = iommu;
918 ir_ioapic[free].id = scope->enumeration_id;
919 pr_info("IOAPIC id %d under DRHD base 0x%Lx IOMMU %d\n",
920 scope->enumeration_id, drhd->address, iommu->seq_id);
921
922 return 0;
923 }
924
925 static int ir_parse_ioapic_hpet_scope(struct acpi_dmar_header *header,
926 struct intel_iommu *iommu)
927 {
928 int ret = 0;
929 struct acpi_dmar_hardware_unit *drhd;
930 struct acpi_dmar_device_scope *scope;
931 void *start, *end;
932
933 drhd = (struct acpi_dmar_hardware_unit *)header;
934 start = (void *)(drhd + 1);
935 end = ((void *)drhd) + header->length;
936
937 while (start < end && ret == 0) {
938 scope = start;
939 if (scope->entry_type == ACPI_DMAR_SCOPE_TYPE_IOAPIC)
940 ret = ir_parse_one_ioapic_scope(scope, iommu, drhd);
941 else if (scope->entry_type == ACPI_DMAR_SCOPE_TYPE_HPET)
942 ret = ir_parse_one_hpet_scope(scope, iommu, drhd);
943 start += scope->length;
944 }
945
946 return ret;
947 }
948
949 static void ir_remove_ioapic_hpet_scope(struct intel_iommu *iommu)
950 {
951 int i;
952
953 for (i = 0; i < MAX_HPET_TBS; i++)
954 if (ir_hpet[i].iommu == iommu)
955 ir_hpet[i].iommu = NULL;
956
957 for (i = 0; i < MAX_IO_APICS; i++)
958 if (ir_ioapic[i].iommu == iommu)
959 ir_ioapic[i].iommu = NULL;
960 }
961
962 /*
963 * Finds the assocaition between IOAPIC's and its Interrupt-remapping
964 * hardware unit.
965 */
966 static int __init parse_ioapics_under_ir(void)
967 {
968 struct dmar_drhd_unit *drhd;
969 struct intel_iommu *iommu;
970 bool ir_supported = false;
971 int ioapic_idx;
972
973 for_each_iommu(iommu, drhd) {
974 int ret;
975
976 if (!ecap_ir_support(iommu->ecap))
977 continue;
978
979 ret = ir_parse_ioapic_hpet_scope(drhd->hdr, iommu);
980 if (ret)
981 return ret;
982
983 ir_supported = true;
984 }
985
986 if (!ir_supported)
987 return -ENODEV;
988
989 for (ioapic_idx = 0; ioapic_idx < nr_ioapics; ioapic_idx++) {
990 int ioapic_id = mpc_ioapic_id(ioapic_idx);
991 if (!map_ioapic_to_ir(ioapic_id)) {
992 pr_err(FW_BUG "ioapic %d has no mapping iommu, "
993 "interrupt remapping will be disabled\n",
994 ioapic_id);
995 return -1;
996 }
997 }
998
999 return 0;
1000 }
1001
1002 static int __init ir_dev_scope_init(void)
1003 {
1004 int ret;
1005
1006 if (!irq_remapping_enabled)
1007 return 0;
1008
1009 down_write(&dmar_global_lock);
1010 ret = dmar_dev_scope_init();
1011 up_write(&dmar_global_lock);
1012
1013 return ret;
1014 }
1015 rootfs_initcall(ir_dev_scope_init);
1016
1017 static void disable_irq_remapping(void)
1018 {
1019 struct dmar_drhd_unit *drhd;
1020 struct intel_iommu *iommu = NULL;
1021
1022 /*
1023 * Disable Interrupt-remapping for all the DRHD's now.
1024 */
1025 for_each_iommu(iommu, drhd) {
1026 if (!ecap_ir_support(iommu->ecap))
1027 continue;
1028
1029 iommu_disable_irq_remapping(iommu);
1030 }
1031
1032 /*
1033 * Clear Posted-Interrupts capability.
1034 */
1035 if (!disable_irq_post)
1036 intel_irq_remap_ops.capability &= ~(1 << IRQ_POSTING_CAP);
1037 }
1038
1039 static int reenable_irq_remapping(int eim)
1040 {
1041 struct dmar_drhd_unit *drhd;
1042 bool setup = false;
1043 struct intel_iommu *iommu = NULL;
1044
1045 for_each_iommu(iommu, drhd)
1046 if (iommu->qi)
1047 dmar_reenable_qi(iommu);
1048
1049 /*
1050 * Setup Interrupt-remapping for all the DRHD's now.
1051 */
1052 for_each_iommu(iommu, drhd) {
1053 if (!ecap_ir_support(iommu->ecap))
1054 continue;
1055
1056 /* Set up interrupt remapping for iommu.*/
1057 iommu_set_irq_remapping(iommu, eim);
1058 iommu_enable_irq_remapping(iommu);
1059 setup = true;
1060 }
1061
1062 if (!setup)
1063 goto error;
1064
1065 set_irq_posting_cap();
1066
1067 return 0;
1068
1069 error:
1070 /*
1071 * handle error condition gracefully here!
1072 */
1073 return -1;
1074 }
1075
1076 static void prepare_irte(struct irte *irte, int vector, unsigned int dest)
1077 {
1078 memset(irte, 0, sizeof(*irte));
1079
1080 irte->present = 1;
1081 irte->dst_mode = apic->irq_dest_mode;
1082 /*
1083 * Trigger mode in the IRTE will always be edge, and for IO-APIC, the
1084 * actual level or edge trigger will be setup in the IO-APIC
1085 * RTE. This will help simplify level triggered irq migration.
1086 * For more details, see the comments (in io_apic.c) explainig IO-APIC
1087 * irq migration in the presence of interrupt-remapping.
1088 */
1089 irte->trigger_mode = 0;
1090 irte->dlvry_mode = apic->irq_delivery_mode;
1091 irte->vector = vector;
1092 irte->dest_id = IRTE_DEST(dest);
1093 irte->redir_hint = 1;
1094 }
1095
1096 static struct irq_domain *intel_get_ir_irq_domain(struct irq_alloc_info *info)
1097 {
1098 struct intel_iommu *iommu = NULL;
1099
1100 if (!info)
1101 return NULL;
1102
1103 switch (info->type) {
1104 case X86_IRQ_ALLOC_TYPE_IOAPIC:
1105 iommu = map_ioapic_to_ir(info->ioapic_id);
1106 break;
1107 case X86_IRQ_ALLOC_TYPE_HPET:
1108 iommu = map_hpet_to_ir(info->hpet_id);
1109 break;
1110 case X86_IRQ_ALLOC_TYPE_MSI:
1111 case X86_IRQ_ALLOC_TYPE_MSIX:
1112 iommu = map_dev_to_ir(info->msi_dev);
1113 break;
1114 default:
1115 BUG_ON(1);
1116 break;
1117 }
1118
1119 return iommu ? iommu->ir_domain : NULL;
1120 }
1121
1122 static struct irq_domain *intel_get_irq_domain(struct irq_alloc_info *info)
1123 {
1124 struct intel_iommu *iommu;
1125
1126 if (!info)
1127 return NULL;
1128
1129 switch (info->type) {
1130 case X86_IRQ_ALLOC_TYPE_MSI:
1131 case X86_IRQ_ALLOC_TYPE_MSIX:
1132 iommu = map_dev_to_ir(info->msi_dev);
1133 if (iommu)
1134 return iommu->ir_msi_domain;
1135 break;
1136 default:
1137 break;
1138 }
1139
1140 return NULL;
1141 }
1142
1143 struct irq_remap_ops intel_irq_remap_ops = {
1144 .prepare = intel_prepare_irq_remapping,
1145 .enable = intel_enable_irq_remapping,
1146 .disable = disable_irq_remapping,
1147 .reenable = reenable_irq_remapping,
1148 .enable_faulting = enable_drhd_fault_handling,
1149 .get_ir_irq_domain = intel_get_ir_irq_domain,
1150 .get_irq_domain = intel_get_irq_domain,
1151 };
1152
1153 static void intel_ir_reconfigure_irte(struct irq_data *irqd, bool force)
1154 {
1155 struct intel_ir_data *ir_data = irqd->chip_data;
1156 struct irte *irte = &ir_data->irte_entry;
1157 struct irq_cfg *cfg = irqd_cfg(irqd);
1158
1159 /*
1160 * Atomically updates the IRTE with the new destination, vector
1161 * and flushes the interrupt entry cache.
1162 */
1163 irte->vector = cfg->vector;
1164 irte->dest_id = IRTE_DEST(cfg->dest_apicid);
1165
1166 /* Update the hardware only if the interrupt is in remapped mode. */
1167 if (force || ir_data->irq_2_iommu.mode == IRQ_REMAPPING)
1168 modify_irte(&ir_data->irq_2_iommu, irte);
1169 }
1170
1171 /*
1172 * Migrate the IO-APIC irq in the presence of intr-remapping.
1173 *
1174 * For both level and edge triggered, irq migration is a simple atomic
1175 * update(of vector and cpu destination) of IRTE and flush the hardware cache.
1176 *
1177 * For level triggered, we eliminate the io-apic RTE modification (with the
1178 * updated vector information), by using a virtual vector (io-apic pin number).
1179 * Real vector that is used for interrupting cpu will be coming from
1180 * the interrupt-remapping table entry.
1181 *
1182 * As the migration is a simple atomic update of IRTE, the same mechanism
1183 * is used to migrate MSI irq's in the presence of interrupt-remapping.
1184 */
1185 static int
1186 intel_ir_set_affinity(struct irq_data *data, const struct cpumask *mask,
1187 bool force)
1188 {
1189 struct irq_data *parent = data->parent_data;
1190 struct irq_cfg *cfg = irqd_cfg(data);
1191 int ret;
1192
1193 ret = parent->chip->irq_set_affinity(parent, mask, force);
1194 if (ret < 0 || ret == IRQ_SET_MASK_OK_DONE)
1195 return ret;
1196
1197 intel_ir_reconfigure_irte(data, false);
1198 /*
1199 * After this point, all the interrupts will start arriving
1200 * at the new destination. So, time to cleanup the previous
1201 * vector allocation.
1202 */
1203 send_cleanup_vector(cfg);
1204
1205 return IRQ_SET_MASK_OK_DONE;
1206 }
1207
1208 static void intel_ir_compose_msi_msg(struct irq_data *irq_data,
1209 struct msi_msg *msg)
1210 {
1211 struct intel_ir_data *ir_data = irq_data->chip_data;
1212
1213 *msg = ir_data->msi_entry;
1214 }
1215
1216 static int intel_ir_set_vcpu_affinity(struct irq_data *data, void *info)
1217 {
1218 struct intel_ir_data *ir_data = data->chip_data;
1219 struct vcpu_data *vcpu_pi_info = info;
1220
1221 /* stop posting interrupts, back to remapping mode */
1222 if (!vcpu_pi_info) {
1223 modify_irte(&ir_data->irq_2_iommu, &ir_data->irte_entry);
1224 } else {
1225 struct irte irte_pi;
1226
1227 /*
1228 * We are not caching the posted interrupt entry. We
1229 * copy the data from the remapped entry and modify
1230 * the fields which are relevant for posted mode. The
1231 * cached remapped entry is used for switching back to
1232 * remapped mode.
1233 */
1234 memset(&irte_pi, 0, sizeof(irte_pi));
1235 dmar_copy_shared_irte(&irte_pi, &ir_data->irte_entry);
1236
1237 /* Update the posted mode fields */
1238 irte_pi.p_pst = 1;
1239 irte_pi.p_urgent = 0;
1240 irte_pi.p_vector = vcpu_pi_info->vector;
1241 irte_pi.pda_l = (vcpu_pi_info->pi_desc_addr >>
1242 (32 - PDA_LOW_BIT)) & ~(-1UL << PDA_LOW_BIT);
1243 irte_pi.pda_h = (vcpu_pi_info->pi_desc_addr >> 32) &
1244 ~(-1UL << PDA_HIGH_BIT);
1245
1246 modify_irte(&ir_data->irq_2_iommu, &irte_pi);
1247 }
1248
1249 return 0;
1250 }
1251
1252 static struct irq_chip intel_ir_chip = {
1253 .name = "INTEL-IR",
1254 .irq_ack = apic_ack_irq,
1255 .irq_set_affinity = intel_ir_set_affinity,
1256 .irq_compose_msi_msg = intel_ir_compose_msi_msg,
1257 .irq_set_vcpu_affinity = intel_ir_set_vcpu_affinity,
1258 };
1259
1260 static void intel_irq_remapping_prepare_irte(struct intel_ir_data *data,
1261 struct irq_cfg *irq_cfg,
1262 struct irq_alloc_info *info,
1263 int index, int sub_handle)
1264 {
1265 struct IR_IO_APIC_route_entry *entry;
1266 struct irte *irte = &data->irte_entry;
1267 struct msi_msg *msg = &data->msi_entry;
1268
1269 prepare_irte(irte, irq_cfg->vector, irq_cfg->dest_apicid);
1270 switch (info->type) {
1271 case X86_IRQ_ALLOC_TYPE_IOAPIC:
1272 /* Set source-id of interrupt request */
1273 set_ioapic_sid(irte, info->ioapic_id);
1274 apic_printk(APIC_VERBOSE, KERN_DEBUG "IOAPIC[%d]: Set IRTE entry (P:%d FPD:%d Dst_Mode:%d Redir_hint:%d Trig_Mode:%d Dlvry_Mode:%X Avail:%X Vector:%02X Dest:%08X SID:%04X SQ:%X SVT:%X)\n",
1275 info->ioapic_id, irte->present, irte->fpd,
1276 irte->dst_mode, irte->redir_hint,
1277 irte->trigger_mode, irte->dlvry_mode,
1278 irte->avail, irte->vector, irte->dest_id,
1279 irte->sid, irte->sq, irte->svt);
1280
1281 entry = (struct IR_IO_APIC_route_entry *)info->ioapic_entry;
1282 info->ioapic_entry = NULL;
1283 memset(entry, 0, sizeof(*entry));
1284 entry->index2 = (index >> 15) & 0x1;
1285 entry->zero = 0;
1286 entry->format = 1;
1287 entry->index = (index & 0x7fff);
1288 /*
1289 * IO-APIC RTE will be configured with virtual vector.
1290 * irq handler will do the explicit EOI to the io-apic.
1291 */
1292 entry->vector = info->ioapic_pin;
1293 entry->mask = 0; /* enable IRQ */
1294 entry->trigger = info->ioapic_trigger;
1295 entry->polarity = info->ioapic_polarity;
1296 if (info->ioapic_trigger)
1297 entry->mask = 1; /* Mask level triggered irqs. */
1298 break;
1299
1300 case X86_IRQ_ALLOC_TYPE_HPET:
1301 case X86_IRQ_ALLOC_TYPE_MSI:
1302 case X86_IRQ_ALLOC_TYPE_MSIX:
1303 if (info->type == X86_IRQ_ALLOC_TYPE_HPET)
1304 set_hpet_sid(irte, info->hpet_id);
1305 else
1306 set_msi_sid(irte, info->msi_dev);
1307
1308 msg->address_hi = MSI_ADDR_BASE_HI;
1309 msg->data = sub_handle;
1310 msg->address_lo = MSI_ADDR_BASE_LO | MSI_ADDR_IR_EXT_INT |
1311 MSI_ADDR_IR_SHV |
1312 MSI_ADDR_IR_INDEX1(index) |
1313 MSI_ADDR_IR_INDEX2(index);
1314 break;
1315
1316 default:
1317 BUG_ON(1);
1318 break;
1319 }
1320 }
1321
1322 static void intel_free_irq_resources(struct irq_domain *domain,
1323 unsigned int virq, unsigned int nr_irqs)
1324 {
1325 struct irq_data *irq_data;
1326 struct intel_ir_data *data;
1327 struct irq_2_iommu *irq_iommu;
1328 unsigned long flags;
1329 int i;
1330 for (i = 0; i < nr_irqs; i++) {
1331 irq_data = irq_domain_get_irq_data(domain, virq + i);
1332 if (irq_data && irq_data->chip_data) {
1333 data = irq_data->chip_data;
1334 irq_iommu = &data->irq_2_iommu;
1335 raw_spin_lock_irqsave(&irq_2_ir_lock, flags);
1336 clear_entries(irq_iommu);
1337 raw_spin_unlock_irqrestore(&irq_2_ir_lock, flags);
1338 irq_domain_reset_irq_data(irq_data);
1339 kfree(data);
1340 }
1341 }
1342 }
1343
1344 static int intel_irq_remapping_alloc(struct irq_domain *domain,
1345 unsigned int virq, unsigned int nr_irqs,
1346 void *arg)
1347 {
1348 struct intel_iommu *iommu = domain->host_data;
1349 struct irq_alloc_info *info = arg;
1350 struct intel_ir_data *data, *ird;
1351 struct irq_data *irq_data;
1352 struct irq_cfg *irq_cfg;
1353 int i, ret, index;
1354
1355 if (!info || !iommu)
1356 return -EINVAL;
1357 if (nr_irqs > 1 && info->type != X86_IRQ_ALLOC_TYPE_MSI &&
1358 info->type != X86_IRQ_ALLOC_TYPE_MSIX)
1359 return -EINVAL;
1360
1361 /*
1362 * With IRQ remapping enabled, don't need contiguous CPU vectors
1363 * to support multiple MSI interrupts.
1364 */
1365 if (info->type == X86_IRQ_ALLOC_TYPE_MSI)
1366 info->flags &= ~X86_IRQ_ALLOC_CONTIGUOUS_VECTORS;
1367
1368 ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, arg);
1369 if (ret < 0)
1370 return ret;
1371
1372 ret = -ENOMEM;
1373 data = kzalloc(sizeof(*data), GFP_KERNEL);
1374 if (!data)
1375 goto out_free_parent;
1376
1377 down_read(&dmar_global_lock);
1378 index = alloc_irte(iommu, virq, &data->irq_2_iommu, nr_irqs);
1379 up_read(&dmar_global_lock);
1380 if (index < 0) {
1381 pr_warn("Failed to allocate IRTE\n");
1382 kfree(data);
1383 goto out_free_parent;
1384 }
1385
1386 for (i = 0; i < nr_irqs; i++) {
1387 irq_data = irq_domain_get_irq_data(domain, virq + i);
1388 irq_cfg = irqd_cfg(irq_data);
1389 if (!irq_data || !irq_cfg) {
1390 ret = -EINVAL;
1391 goto out_free_data;
1392 }
1393
1394 if (i > 0) {
1395 ird = kzalloc(sizeof(*ird), GFP_KERNEL);
1396 if (!ird)
1397 goto out_free_data;
1398 /* Initialize the common data */
1399 ird->irq_2_iommu = data->irq_2_iommu;
1400 ird->irq_2_iommu.sub_handle = i;
1401 } else {
1402 ird = data;
1403 }
1404
1405 irq_data->hwirq = (index << 16) + i;
1406 irq_data->chip_data = ird;
1407 irq_data->chip = &intel_ir_chip;
1408 intel_irq_remapping_prepare_irte(ird, irq_cfg, info, index, i);
1409 irq_set_status_flags(virq + i, IRQ_MOVE_PCNTXT);
1410 }
1411 return 0;
1412
1413 out_free_data:
1414 intel_free_irq_resources(domain, virq, i);
1415 out_free_parent:
1416 irq_domain_free_irqs_common(domain, virq, nr_irqs);
1417 return ret;
1418 }
1419
1420 static void intel_irq_remapping_free(struct irq_domain *domain,
1421 unsigned int virq, unsigned int nr_irqs)
1422 {
1423 intel_free_irq_resources(domain, virq, nr_irqs);
1424 irq_domain_free_irqs_common(domain, virq, nr_irqs);
1425 }
1426
1427 static int intel_irq_remapping_activate(struct irq_domain *domain,
1428 struct irq_data *irq_data, bool reserve)
1429 {
1430 intel_ir_reconfigure_irte(irq_data, true);
1431 return 0;
1432 }
1433
1434 static void intel_irq_remapping_deactivate(struct irq_domain *domain,
1435 struct irq_data *irq_data)
1436 {
1437 struct intel_ir_data *data = irq_data->chip_data;
1438 struct irte entry;
1439
1440 memset(&entry, 0, sizeof(entry));
1441 modify_irte(&data->irq_2_iommu, &entry);
1442 }
1443
1444 static const struct irq_domain_ops intel_ir_domain_ops = {
1445 .alloc = intel_irq_remapping_alloc,
1446 .free = intel_irq_remapping_free,
1447 .activate = intel_irq_remapping_activate,
1448 .deactivate = intel_irq_remapping_deactivate,
1449 };
1450
1451 /*
1452 * Support of Interrupt Remapping Unit Hotplug
1453 */
1454 static int dmar_ir_add(struct dmar_drhd_unit *dmaru, struct intel_iommu *iommu)
1455 {
1456 int ret;
1457 int eim = x2apic_enabled();
1458
1459 if (eim && !ecap_eim_support(iommu->ecap)) {
1460 pr_info("DRHD %Lx: EIM not supported by DRHD, ecap %Lx\n",
1461 iommu->reg_phys, iommu->ecap);
1462 return -ENODEV;
1463 }
1464
1465 if (ir_parse_ioapic_hpet_scope(dmaru->hdr, iommu)) {
1466 pr_warn("DRHD %Lx: failed to parse managed IOAPIC/HPET\n",
1467 iommu->reg_phys);
1468 return -ENODEV;
1469 }
1470
1471 /* TODO: check all IOAPICs are covered by IOMMU */
1472
1473 /* Setup Interrupt-remapping now. */
1474 ret = intel_setup_irq_remapping(iommu);
1475 if (ret) {
1476 pr_err("Failed to setup irq remapping for %s\n",
1477 iommu->name);
1478 intel_teardown_irq_remapping(iommu);
1479 ir_remove_ioapic_hpet_scope(iommu);
1480 } else {
1481 iommu_enable_irq_remapping(iommu);
1482 }
1483
1484 return ret;
1485 }
1486
1487 int dmar_ir_hotplug(struct dmar_drhd_unit *dmaru, bool insert)
1488 {
1489 int ret = 0;
1490 struct intel_iommu *iommu = dmaru->iommu;
1491
1492 if (!irq_remapping_enabled)
1493 return 0;
1494 if (iommu == NULL)
1495 return -EINVAL;
1496 if (!ecap_ir_support(iommu->ecap))
1497 return 0;
1498 if (irq_remapping_cap(IRQ_POSTING_CAP) &&
1499 !cap_pi_support(iommu->cap))
1500 return -EBUSY;
1501
1502 if (insert) {
1503 if (!iommu->ir_table)
1504 ret = dmar_ir_add(dmaru, iommu);
1505 } else {
1506 if (iommu->ir_table) {
1507 if (!bitmap_empty(iommu->ir_table->bitmap,
1508 INTR_REMAP_TABLE_ENTRIES)) {
1509 ret = -EBUSY;
1510 } else {
1511 iommu_disable_irq_remapping(iommu);
1512 intel_teardown_irq_remapping(iommu);
1513 ir_remove_ioapic_hpet_scope(iommu);
1514 }
1515 }
1516 }
1517
1518 return ret;
1519 }
Linux with added FPC-III support