1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
4 #include <linux/kernel.h>
5 #include <linux/init.h>
7 #include <linux/of_address.h>
8 #include <linux/module.h>
9 #include <linux/irqdomain.h>
10 #include <linux/irqchip.h>
11 #include <linux/irq.h>
12 #include <linux/interrupt.h>
13 #include <linux/smp.h>
16 #include <asm/traps.h>
17 #include <asm/reg_ops.h>
19 static struct irq_domain
*root_domain
;
20 static void __iomem
*INTCG_base
;
21 static void __iomem
*INTCL_base
;
25 #define COMM_IRQ_BASE 32
27 #define INTCG_SIZE 0x8000
28 #define INTCL_SIZE 0x1000
30 #define INTCG_ICTLR 0x0
31 #define INTCG_CICFGR 0x100
32 #define INTCG_CIDSTR 0x1000
34 #define INTCL_PICTLR 0x0
35 #define INTCL_SIGR 0x60
36 #define INTCL_HPPIR 0x68
37 #define INTCL_RDYIR 0x6c
38 #define INTCL_SENR 0xa0
39 #define INTCL_CENR 0xa4
40 #define INTCL_CACR 0xb4
42 static DEFINE_PER_CPU(void __iomem
*, intcl_reg
);
44 static void csky_mpintc_handler(struct pt_regs
*regs
)
46 void __iomem
*reg_base
= this_cpu_read(intcl_reg
);
49 handle_domain_irq(root_domain
,
50 readl_relaxed(reg_base
+ INTCL_RDYIR
),
52 } while (readl_relaxed(reg_base
+ INTCL_HPPIR
) & BIT(31));
55 static void csky_mpintc_enable(struct irq_data
*d
)
57 void __iomem
*reg_base
= this_cpu_read(intcl_reg
);
59 writel_relaxed(d
->hwirq
, reg_base
+ INTCL_SENR
);
62 static void csky_mpintc_disable(struct irq_data
*d
)
64 void __iomem
*reg_base
= this_cpu_read(intcl_reg
);
66 writel_relaxed(d
->hwirq
, reg_base
+ INTCL_CENR
);
69 static void csky_mpintc_eoi(struct irq_data
*d
)
71 void __iomem
*reg_base
= this_cpu_read(intcl_reg
);
73 writel_relaxed(d
->hwirq
, reg_base
+ INTCL_CACR
);
77 static int csky_irq_set_affinity(struct irq_data
*d
,
78 const struct cpumask
*mask_val
,
82 unsigned int offset
= 4 * (d
->hwirq
- COMM_IRQ_BASE
);
85 cpu
= cpumask_any_and(mask_val
, cpu_online_mask
);
87 cpu
= cpumask_first(mask_val
);
89 if (cpu
>= nr_cpu_ids
)
92 /* Enable interrupt destination */
95 writel_relaxed(cpu
, INTCG_base
+ INTCG_CIDSTR
+ offset
);
97 irq_data_update_effective_affinity(d
, cpumask_of(cpu
));
99 return IRQ_SET_MASK_OK_DONE
;
103 static struct irq_chip csky_irq_chip
= {
104 .name
= "C-SKY SMP Intc",
105 .irq_eoi
= csky_mpintc_eoi
,
106 .irq_enable
= csky_mpintc_enable
,
107 .irq_disable
= csky_mpintc_disable
,
109 .irq_set_affinity
= csky_irq_set_affinity
,
113 static int csky_irqdomain_map(struct irq_domain
*d
, unsigned int irq
,
114 irq_hw_number_t hwirq
)
116 if (hwirq
< COMM_IRQ_BASE
) {
117 irq_set_percpu_devid(irq
);
118 irq_set_chip_and_handler(irq
, &csky_irq_chip
,
121 irq_set_chip_and_handler(irq
, &csky_irq_chip
,
128 static const struct irq_domain_ops csky_irqdomain_ops
= {
129 .map
= csky_irqdomain_map
,
130 .xlate
= irq_domain_xlate_onecell
,
134 static void csky_mpintc_send_ipi(const struct cpumask
*mask
)
136 void __iomem
*reg_base
= this_cpu_read(intcl_reg
);
139 * INTCL_SIGR[3:0] INTID
140 * INTCL_SIGR[8:15] CPUMASK
142 writel_relaxed((*cpumask_bits(mask
)) << 8 | IPI_IRQ
,
143 reg_base
+ INTCL_SIGR
);
147 /* C-SKY multi processor interrupt controller */
149 csky_mpintc_init(struct device_node
*node
, struct device_node
*parent
)
152 unsigned int cpu
, nr_irq
;
154 unsigned int ipi_irq
;
160 ret
= of_property_read_u32(node
, "csky,num-irqs", &nr_irq
);
164 if (INTCG_base
== NULL
) {
165 INTCG_base
= ioremap(mfcr("cr<31, 14>"),
166 INTCL_SIZE
*nr_cpu_ids
+ INTCG_SIZE
);
167 if (INTCG_base
== NULL
)
170 INTCL_base
= INTCG_base
+ INTCG_SIZE
;
172 writel_relaxed(BIT(0), INTCG_base
+ INTCG_ICTLR
);
175 root_domain
= irq_domain_add_linear(node
, nr_irq
, &csky_irqdomain_ops
,
181 for_each_present_cpu(cpu
) {
182 per_cpu(intcl_reg
, cpu
) = INTCL_base
+ (INTCL_SIZE
* cpu
);
183 writel_relaxed(BIT(0), per_cpu(intcl_reg
, cpu
) + INTCL_PICTLR
);
186 set_handle_irq(&csky_mpintc_handler
);
189 ipi_irq
= irq_create_mapping(root_domain
, IPI_IRQ
);
193 set_send_ipi(&csky_mpintc_send_ipi
, ipi_irq
);
198 IRQCHIP_DECLARE(csky_mpintc
, "csky,mpintc", csky_mpintc_init
);