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Linux 5.1.15
[linux/fpc-iii.git] / drivers / irqchip / irq-renesas-intc-irqpin.c
blob8c039525703f7c9a4426a0b129cc26a9a41c7192
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Renesas INTC External IRQ Pin Driver
4 *
5 * Copyright (C) 2013 Magnus Damm
6 */
7
8 #include <linux/init.h>
9 #include <linux/of.h>
10 #include <linux/platform_device.h>
11 #include <linux/spinlock.h>
12 #include <linux/interrupt.h>
13 #include <linux/ioport.h>
14 #include <linux/io.h>
15 #include <linux/irq.h>
16 #include <linux/irqdomain.h>
17 #include <linux/err.h>
18 #include <linux/slab.h>
19 #include <linux/module.h>
20 #include <linux/of_device.h>
21 #include <linux/pm_runtime.h>
22
23 #define INTC_IRQPIN_MAX 8 /* maximum 8 interrupts per driver instance */
24
25 #define INTC_IRQPIN_REG_SENSE 0 /* ICRn */
26 #define INTC_IRQPIN_REG_PRIO 1 /* INTPRInn */
27 #define INTC_IRQPIN_REG_SOURCE 2 /* INTREQnn */
28 #define INTC_IRQPIN_REG_MASK 3 /* INTMSKnn */
29 #define INTC_IRQPIN_REG_CLEAR 4 /* INTMSKCLRnn */
30 #define INTC_IRQPIN_REG_NR_MANDATORY 5
31 #define INTC_IRQPIN_REG_IRLM 5 /* ICR0 with IRLM bit (optional) */
32 #define INTC_IRQPIN_REG_NR 6
33
34 /* INTC external IRQ PIN hardware register access:
35 *
36 * SENSE is read-write 32-bit with 2-bits or 4-bits per IRQ (*)
37 * PRIO is read-write 32-bit with 4-bits per IRQ (**)
38 * SOURCE is read-only 32-bit or 8-bit with 1-bit per IRQ (***)
39 * MASK is write-only 32-bit or 8-bit with 1-bit per IRQ (***)
40 * CLEAR is write-only 32-bit or 8-bit with 1-bit per IRQ (***)
41 *
42 * (*) May be accessed by more than one driver instance - lock needed
43 * (**) Read-modify-write access by one driver instance - lock needed
44 * (***) Accessed by one driver instance only - no locking needed
45 */
46
47 struct intc_irqpin_iomem {
48 void __iomem *iomem;
49 unsigned long (*read)(void __iomem *iomem);
50 void (*write)(void __iomem *iomem, unsigned long data);
51 int width;
52 };
53
54 struct intc_irqpin_irq {
55 int hw_irq;
56 int requested_irq;
57 int domain_irq;
58 struct intc_irqpin_priv *p;
59 };
60
61 struct intc_irqpin_priv {
62 struct intc_irqpin_iomem iomem[INTC_IRQPIN_REG_NR];
63 struct intc_irqpin_irq irq[INTC_IRQPIN_MAX];
64 unsigned int sense_bitfield_width;
65 struct platform_device *pdev;
66 struct irq_chip irq_chip;
67 struct irq_domain *irq_domain;
68 atomic_t wakeup_path;
69 unsigned shared_irqs:1;
70 u8 shared_irq_mask;
71 };
72
73 struct intc_irqpin_config {
74 unsigned int irlm_bit;
75 unsigned needs_irlm:1;
76 };
77
78 static unsigned long intc_irqpin_read32(void __iomem *iomem)
79 {
80 return ioread32(iomem);
81 }
82
83 static unsigned long intc_irqpin_read8(void __iomem *iomem)
84 {
85 return ioread8(iomem);
86 }
87
88 static void intc_irqpin_write32(void __iomem *iomem, unsigned long data)
89 {
90 iowrite32(data, iomem);
91 }
92
93 static void intc_irqpin_write8(void __iomem *iomem, unsigned long data)
94 {
95 iowrite8(data, iomem);
96 }
97
98 static inline unsigned long intc_irqpin_read(struct intc_irqpin_priv *p,
99 int reg)
100 {
101 struct intc_irqpin_iomem *i = &p->iomem[reg];
102
103 return i->read(i->iomem);
104 }
105
106 static inline void intc_irqpin_write(struct intc_irqpin_priv *p,
107 int reg, unsigned long data)
108 {
109 struct intc_irqpin_iomem *i = &p->iomem[reg];
110
111 i->write(i->iomem, data);
112 }
113
114 static inline unsigned long intc_irqpin_hwirq_mask(struct intc_irqpin_priv *p,
115 int reg, int hw_irq)
116 {
117 return BIT((p->iomem[reg].width - 1) - hw_irq);
118 }
119
120 static inline void intc_irqpin_irq_write_hwirq(struct intc_irqpin_priv *p,
121 int reg, int hw_irq)
122 {
123 intc_irqpin_write(p, reg, intc_irqpin_hwirq_mask(p, reg, hw_irq));
124 }
125
126 static DEFINE_RAW_SPINLOCK(intc_irqpin_lock); /* only used by slow path */
127
128 static void intc_irqpin_read_modify_write(struct intc_irqpin_priv *p,
129 int reg, int shift,
130 int width, int value)
131 {
132 unsigned long flags;
133 unsigned long tmp;
134
135 raw_spin_lock_irqsave(&intc_irqpin_lock, flags);
136
137 tmp = intc_irqpin_read(p, reg);
138 tmp &= ~(((1 << width) - 1) << shift);
139 tmp |= value << shift;
140 intc_irqpin_write(p, reg, tmp);
141
142 raw_spin_unlock_irqrestore(&intc_irqpin_lock, flags);
143 }
144
145 static void intc_irqpin_mask_unmask_prio(struct intc_irqpin_priv *p,
146 int irq, int do_mask)
147 {
148 /* The PRIO register is assumed to be 32-bit with fixed 4-bit fields. */
149 int bitfield_width = 4;
150 int shift = 32 - (irq + 1) * bitfield_width;
151
152 intc_irqpin_read_modify_write(p, INTC_IRQPIN_REG_PRIO,
153 shift, bitfield_width,
154 do_mask ? 0 : (1 << bitfield_width) - 1);
155 }
156
157 static int intc_irqpin_set_sense(struct intc_irqpin_priv *p, int irq, int value)
158 {
159 /* The SENSE register is assumed to be 32-bit. */
160 int bitfield_width = p->sense_bitfield_width;
161 int shift = 32 - (irq + 1) * bitfield_width;
162
163 dev_dbg(&p->pdev->dev, "sense irq = %d, mode = %d\n", irq, value);
164
165 if (value >= (1 << bitfield_width))
166 return -EINVAL;
167
168 intc_irqpin_read_modify_write(p, INTC_IRQPIN_REG_SENSE, shift,
169 bitfield_width, value);
170 return 0;
171 }
172
173 static void intc_irqpin_dbg(struct intc_irqpin_irq *i, char *str)
174 {
175 dev_dbg(&i->p->pdev->dev, "%s (%d:%d:%d)\n",
176 str, i->requested_irq, i->hw_irq, i->domain_irq);
177 }
178
179 static void intc_irqpin_irq_enable(struct irq_data *d)
180 {
181 struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
182 int hw_irq = irqd_to_hwirq(d);
183
184 intc_irqpin_dbg(&p->irq[hw_irq], "enable");
185 intc_irqpin_irq_write_hwirq(p, INTC_IRQPIN_REG_CLEAR, hw_irq);
186 }
187
188 static void intc_irqpin_irq_disable(struct irq_data *d)
189 {
190 struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
191 int hw_irq = irqd_to_hwirq(d);
192
193 intc_irqpin_dbg(&p->irq[hw_irq], "disable");
194 intc_irqpin_irq_write_hwirq(p, INTC_IRQPIN_REG_MASK, hw_irq);
195 }
196
197 static void intc_irqpin_shared_irq_enable(struct irq_data *d)
198 {
199 struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
200 int hw_irq = irqd_to_hwirq(d);
201
202 intc_irqpin_dbg(&p->irq[hw_irq], "shared enable");
203 intc_irqpin_irq_write_hwirq(p, INTC_IRQPIN_REG_CLEAR, hw_irq);
204
205 p->shared_irq_mask &= ~BIT(hw_irq);
206 }
207
208 static void intc_irqpin_shared_irq_disable(struct irq_data *d)
209 {
210 struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
211 int hw_irq = irqd_to_hwirq(d);
212
213 intc_irqpin_dbg(&p->irq[hw_irq], "shared disable");
214 intc_irqpin_irq_write_hwirq(p, INTC_IRQPIN_REG_MASK, hw_irq);
215
216 p->shared_irq_mask |= BIT(hw_irq);
217 }
218
219 static void intc_irqpin_irq_enable_force(struct irq_data *d)
220 {
221 struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
222 int irq = p->irq[irqd_to_hwirq(d)].requested_irq;
223
224 intc_irqpin_irq_enable(d);
225
226 /* enable interrupt through parent interrupt controller,
227 * assumes non-shared interrupt with 1:1 mapping
228 * needed for busted IRQs on some SoCs like sh73a0
229 */
230 irq_get_chip(irq)->irq_unmask(irq_get_irq_data(irq));
231 }
232
233 static void intc_irqpin_irq_disable_force(struct irq_data *d)
234 {
235 struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
236 int irq = p->irq[irqd_to_hwirq(d)].requested_irq;
237
238 /* disable interrupt through parent interrupt controller,
239 * assumes non-shared interrupt with 1:1 mapping
240 * needed for busted IRQs on some SoCs like sh73a0
241 */
242 irq_get_chip(irq)->irq_mask(irq_get_irq_data(irq));
243 intc_irqpin_irq_disable(d);
244 }
245
246 #define INTC_IRQ_SENSE_VALID 0x10
247 #define INTC_IRQ_SENSE(x) (x + INTC_IRQ_SENSE_VALID)
248
249 static unsigned char intc_irqpin_sense[IRQ_TYPE_SENSE_MASK + 1] = {
250 [IRQ_TYPE_EDGE_FALLING] = INTC_IRQ_SENSE(0x00),
251 [IRQ_TYPE_EDGE_RISING] = INTC_IRQ_SENSE(0x01),
252 [IRQ_TYPE_LEVEL_LOW] = INTC_IRQ_SENSE(0x02),
253 [IRQ_TYPE_LEVEL_HIGH] = INTC_IRQ_SENSE(0x03),
254 [IRQ_TYPE_EDGE_BOTH] = INTC_IRQ_SENSE(0x04),
255 };
256
257 static int intc_irqpin_irq_set_type(struct irq_data *d, unsigned int type)
258 {
259 unsigned char value = intc_irqpin_sense[type & IRQ_TYPE_SENSE_MASK];
260 struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
261
262 if (!(value & INTC_IRQ_SENSE_VALID))
263 return -EINVAL;
264
265 return intc_irqpin_set_sense(p, irqd_to_hwirq(d),
266 value ^ INTC_IRQ_SENSE_VALID);
267 }
268
269 static int intc_irqpin_irq_set_wake(struct irq_data *d, unsigned int on)
270 {
271 struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
272 int hw_irq = irqd_to_hwirq(d);
273
274 irq_set_irq_wake(p->irq[hw_irq].requested_irq, on);
275 if (on)
276 atomic_inc(&p->wakeup_path);
277 else
278 atomic_dec(&p->wakeup_path);
279
280 return 0;
281 }
282
283 static irqreturn_t intc_irqpin_irq_handler(int irq, void *dev_id)
284 {
285 struct intc_irqpin_irq *i = dev_id;
286 struct intc_irqpin_priv *p = i->p;
287 unsigned long bit;
288
289 intc_irqpin_dbg(i, "demux1");
290 bit = intc_irqpin_hwirq_mask(p, INTC_IRQPIN_REG_SOURCE, i->hw_irq);
291
292 if (intc_irqpin_read(p, INTC_IRQPIN_REG_SOURCE) & bit) {
293 intc_irqpin_write(p, INTC_IRQPIN_REG_SOURCE, ~bit);
294 intc_irqpin_dbg(i, "demux2");
295 generic_handle_irq(i->domain_irq);
296 return IRQ_HANDLED;
297 }
298 return IRQ_NONE;
299 }
300
301 static irqreturn_t intc_irqpin_shared_irq_handler(int irq, void *dev_id)
302 {
303 struct intc_irqpin_priv *p = dev_id;
304 unsigned int reg_source = intc_irqpin_read(p, INTC_IRQPIN_REG_SOURCE);
305 irqreturn_t status = IRQ_NONE;
306 int k;
307
308 for (k = 0; k < 8; k++) {
309 if (reg_source & BIT(7 - k)) {
310 if (BIT(k) & p->shared_irq_mask)
311 continue;
312
313 status |= intc_irqpin_irq_handler(irq, &p->irq[k]);
314 }
315 }
316
317 return status;
318 }
319
320 /*
321 * This lock class tells lockdep that INTC External IRQ Pin irqs are in a
322 * different category than their parents, so it won't report false recursion.
323 */
324 static struct lock_class_key intc_irqpin_irq_lock_class;
325
326 /* And this is for the request mutex */
327 static struct lock_class_key intc_irqpin_irq_request_class;
328
329 static int intc_irqpin_irq_domain_map(struct irq_domain *h, unsigned int virq,
330 irq_hw_number_t hw)
331 {
332 struct intc_irqpin_priv *p = h->host_data;
333
334 p->irq[hw].domain_irq = virq;
335 p->irq[hw].hw_irq = hw;
336
337 intc_irqpin_dbg(&p->irq[hw], "map");
338 irq_set_chip_data(virq, h->host_data);
339 irq_set_lockdep_class(virq, &intc_irqpin_irq_lock_class,
340 &intc_irqpin_irq_request_class);
341 irq_set_chip_and_handler(virq, &p->irq_chip, handle_level_irq);
342 return 0;
343 }
344
345 static const struct irq_domain_ops intc_irqpin_irq_domain_ops = {
346 .map = intc_irqpin_irq_domain_map,
347 .xlate = irq_domain_xlate_twocell,
348 };
349
350 static const struct intc_irqpin_config intc_irqpin_irlm_r8a777x = {
351 .irlm_bit = 23, /* ICR0.IRLM0 */
352 .needs_irlm = 1,
353 };
354
355 static const struct intc_irqpin_config intc_irqpin_rmobile = {
356 .needs_irlm = 0,
357 };
358
359 static const struct of_device_id intc_irqpin_dt_ids[] = {
360 { .compatible = "renesas,intc-irqpin", },
361 { .compatible = "renesas,intc-irqpin-r8a7778",
362 .data = &intc_irqpin_irlm_r8a777x },
363 { .compatible = "renesas,intc-irqpin-r8a7779",
364 .data = &intc_irqpin_irlm_r8a777x },
365 { .compatible = "renesas,intc-irqpin-r8a7740",
366 .data = &intc_irqpin_rmobile },
367 { .compatible = "renesas,intc-irqpin-sh73a0",
368 .data = &intc_irqpin_rmobile },
369 {},
370 };
371 MODULE_DEVICE_TABLE(of, intc_irqpin_dt_ids);
372
373 static int intc_irqpin_probe(struct platform_device *pdev)
374 {
375 const struct intc_irqpin_config *config;
376 struct device *dev = &pdev->dev;
377 struct intc_irqpin_priv *p;
378 struct intc_irqpin_iomem *i;
379 struct resource *io[INTC_IRQPIN_REG_NR];
380 struct resource *irq;
381 struct irq_chip *irq_chip;
382 void (*enable_fn)(struct irq_data *d);
383 void (*disable_fn)(struct irq_data *d);
384 const char *name = dev_name(dev);
385 bool control_parent;
386 unsigned int nirqs;
387 int ref_irq;
388 int ret;
389 int k;
390
391 p = devm_kzalloc(dev, sizeof(*p), GFP_KERNEL);
392 if (!p) {
393 dev_err(dev, "failed to allocate driver data\n");
394 return -ENOMEM;
395 }
396
397 /* deal with driver instance configuration */
398 of_property_read_u32(dev->of_node, "sense-bitfield-width",
399 &p->sense_bitfield_width);
400 control_parent = of_property_read_bool(dev->of_node, "control-parent");
401 if (!p->sense_bitfield_width)
402 p->sense_bitfield_width = 4; /* default to 4 bits */
403
404 p->pdev = pdev;
405 platform_set_drvdata(pdev, p);
406
407 config = of_device_get_match_data(dev);
408
409 pm_runtime_enable(dev);
410 pm_runtime_get_sync(dev);
411
412 /* get hold of register banks */
413 memset(io, 0, sizeof(io));
414 for (k = 0; k < INTC_IRQPIN_REG_NR; k++) {
415 io[k] = platform_get_resource(pdev, IORESOURCE_MEM, k);
416 if (!io[k] && k < INTC_IRQPIN_REG_NR_MANDATORY) {
417 dev_err(dev, "not enough IOMEM resources\n");
418 ret = -EINVAL;
419 goto err0;
420 }
421 }
422
423 /* allow any number of IRQs between 1 and INTC_IRQPIN_MAX */
424 for (k = 0; k < INTC_IRQPIN_MAX; k++) {
425 irq = platform_get_resource(pdev, IORESOURCE_IRQ, k);
426 if (!irq)
427 break;
428
429 p->irq[k].p = p;
430 p->irq[k].requested_irq = irq->start;
431 }
432
433 nirqs = k;
434 if (nirqs < 1) {
435 dev_err(dev, "not enough IRQ resources\n");
436 ret = -EINVAL;
437 goto err0;
438 }
439
440 /* ioremap IOMEM and setup read/write callbacks */
441 for (k = 0; k < INTC_IRQPIN_REG_NR; k++) {
442 i = &p->iomem[k];
443
444 /* handle optional registers */
445 if (!io[k])
446 continue;
447
448 switch (resource_size(io[k])) {
449 case 1:
450 i->width = 8;
451 i->read = intc_irqpin_read8;
452 i->write = intc_irqpin_write8;
453 break;
454 case 4:
455 i->width = 32;
456 i->read = intc_irqpin_read32;
457 i->write = intc_irqpin_write32;
458 break;
459 default:
460 dev_err(dev, "IOMEM size mismatch\n");
461 ret = -EINVAL;
462 goto err0;
463 }
464
465 i->iomem = devm_ioremap_nocache(dev, io[k]->start,
466 resource_size(io[k]));
467 if (!i->iomem) {
468 dev_err(dev, "failed to remap IOMEM\n");
469 ret = -ENXIO;
470 goto err0;
471 }
472 }
473
474 /* configure "individual IRQ mode" where needed */
475 if (config && config->needs_irlm) {
476 if (io[INTC_IRQPIN_REG_IRLM])
477 intc_irqpin_read_modify_write(p, INTC_IRQPIN_REG_IRLM,
478 config->irlm_bit, 1, 1);
479 else
480 dev_warn(dev, "unable to select IRLM mode\n");
481 }
482
483 /* mask all interrupts using priority */
484 for (k = 0; k < nirqs; k++)
485 intc_irqpin_mask_unmask_prio(p, k, 1);
486
487 /* clear all pending interrupts */
488 intc_irqpin_write(p, INTC_IRQPIN_REG_SOURCE, 0x0);
489
490 /* scan for shared interrupt lines */
491 ref_irq = p->irq[0].requested_irq;
492 p->shared_irqs = 1;
493 for (k = 1; k < nirqs; k++) {
494 if (ref_irq != p->irq[k].requested_irq) {
495 p->shared_irqs = 0;
496 break;
497 }
498 }
499
500 /* use more severe masking method if requested */
501 if (control_parent) {
502 enable_fn = intc_irqpin_irq_enable_force;
503 disable_fn = intc_irqpin_irq_disable_force;
504 } else if (!p->shared_irqs) {
505 enable_fn = intc_irqpin_irq_enable;
506 disable_fn = intc_irqpin_irq_disable;
507 } else {
508 enable_fn = intc_irqpin_shared_irq_enable;
509 disable_fn = intc_irqpin_shared_irq_disable;
510 }
511
512 irq_chip = &p->irq_chip;
513 irq_chip->name = name;
514 irq_chip->irq_mask = disable_fn;
515 irq_chip->irq_unmask = enable_fn;
516 irq_chip->irq_set_type = intc_irqpin_irq_set_type;
517 irq_chip->irq_set_wake = intc_irqpin_irq_set_wake;
518 irq_chip->flags = IRQCHIP_MASK_ON_SUSPEND;
519
520 p->irq_domain = irq_domain_add_simple(dev->of_node, nirqs, 0,
521 &intc_irqpin_irq_domain_ops, p);
522 if (!p->irq_domain) {
523 ret = -ENXIO;
524 dev_err(dev, "cannot initialize irq domain\n");
525 goto err0;
526 }
527
528 if (p->shared_irqs) {
529 /* request one shared interrupt */
530 if (devm_request_irq(dev, p->irq[0].requested_irq,
531 intc_irqpin_shared_irq_handler,
532 IRQF_SHARED, name, p)) {
533 dev_err(dev, "failed to request low IRQ\n");
534 ret = -ENOENT;
535 goto err1;
536 }
537 } else {
538 /* request interrupts one by one */
539 for (k = 0; k < nirqs; k++) {
540 if (devm_request_irq(dev, p->irq[k].requested_irq,
541 intc_irqpin_irq_handler, 0, name,
542 &p->irq[k])) {
543 dev_err(dev, "failed to request low IRQ\n");
544 ret = -ENOENT;
545 goto err1;
546 }
547 }
548 }
549
550 /* unmask all interrupts on prio level */
551 for (k = 0; k < nirqs; k++)
552 intc_irqpin_mask_unmask_prio(p, k, 0);
553
554 dev_info(dev, "driving %d irqs\n", nirqs);
555
556 return 0;
557
558 err1:
559 irq_domain_remove(p->irq_domain);
560 err0:
561 pm_runtime_put(dev);
562 pm_runtime_disable(dev);
563 return ret;
564 }
565
566 static int intc_irqpin_remove(struct platform_device *pdev)
567 {
568 struct intc_irqpin_priv *p = platform_get_drvdata(pdev);
569
570 irq_domain_remove(p->irq_domain);
571 pm_runtime_put(&pdev->dev);
572 pm_runtime_disable(&pdev->dev);
573 return 0;
574 }
575
576 static int __maybe_unused intc_irqpin_suspend(struct device *dev)
577 {
578 struct intc_irqpin_priv *p = dev_get_drvdata(dev);
579
580 if (atomic_read(&p->wakeup_path))
581 device_set_wakeup_path(dev);
582
583 return 0;
584 }
585
586 static SIMPLE_DEV_PM_OPS(intc_irqpin_pm_ops, intc_irqpin_suspend, NULL);
587
588 static struct platform_driver intc_irqpin_device_driver = {
589 .probe = intc_irqpin_probe,
590 .remove = intc_irqpin_remove,
591 .driver = {
592 .name = "renesas_intc_irqpin",
593 .of_match_table = intc_irqpin_dt_ids,
594 .pm = &intc_irqpin_pm_ops,
595 }
596 };
597
598 static int __init intc_irqpin_init(void)
599 {
600 return platform_driver_register(&intc_irqpin_device_driver);
601 }
602 postcore_initcall(intc_irqpin_init);
603
604 static void __exit intc_irqpin_exit(void)
605 {
606 platform_driver_unregister(&intc_irqpin_device_driver);
607 }
608 module_exit(intc_irqpin_exit);
609
610 MODULE_AUTHOR("Magnus Damm");
611 MODULE_DESCRIPTION("Renesas INTC External IRQ Pin Driver");
612 MODULE_LICENSE("GPL v2");
Linux with added FPC-III support