2 * SN Platform GRU Driver
4 * MMUOPS callbacks + TLB flushing
6 * This file handles emu notifier callbacks from the core kernel. The callbacks
7 * are used to update the TLB in the GRU as a result of changes in the
8 * state of a process address space. This file also handles TLB invalidates
11 * Copyright (c) 2008 Silicon Graphics, Inc. All Rights Reserved.
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2 of the License, or
16 * (at your option) any later version.
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
28 #include <linux/kernel.h>
29 #include <linux/list.h>
30 #include <linux/spinlock.h>
32 #include <linux/slab.h>
33 #include <linux/device.h>
34 #include <linux/hugetlb.h>
35 #include <linux/delay.h>
36 #include <linux/timex.h>
37 #include <linux/srcu.h>
38 #include <asm/processor.h>
40 #include "grutables.h"
41 #include <asm/uv/uv_hub.h>
43 #define gru_random() get_cycles()
45 /* ---------------------------------- TLB Invalidation functions --------
48 * Find a TGH to use for issuing a TLB invalidate. For GRUs that are on the
49 * local blade, use a fixed TGH that is a function of the blade-local cpu
50 * number. Normally, this TGH is private to the cpu & no contention occurs for
51 * the TGH. For offblade GRUs, select a random TGH in the range above the
52 * private TGHs. A spinlock is required to access this TGH & the lock must be
53 * released when the invalidate is completes. This sucks, but it is the best we
56 * Note that the spinlock is IN the TGH handle so locking does not involve
57 * additional cache lines.
60 static inline int get_off_blade_tgh(struct gru_state
*gru
)
64 n
= GRU_NUM_TGH
- gru
->gs_tgh_first_remote
;
66 n
+= gru
->gs_tgh_first_remote
;
70 static inline int get_on_blade_tgh(struct gru_state
*gru
)
72 return uv_blade_processor_id() >> gru
->gs_tgh_local_shift
;
75 static struct gru_tlb_global_handle
*get_lock_tgh_handle(struct gru_state
78 struct gru_tlb_global_handle
*tgh
;
82 if (uv_numa_blade_id() == gru
->gs_blade_id
)
83 n
= get_on_blade_tgh(gru
);
85 n
= get_off_blade_tgh(gru
);
86 tgh
= get_tgh_by_index(gru
, n
);
92 static void get_unlock_tgh_handle(struct gru_tlb_global_handle
*tgh
)
94 unlock_tgh_handle(tgh
);
101 * General purpose TLB invalidation function. This function scans every GRU in
102 * the ENTIRE system (partition) looking for GRUs where the specified MM has
103 * been accessed by the GRU. For each GRU found, the TLB must be invalidated OR
104 * the ASID invalidated. Invalidating an ASID causes a new ASID to be assigned
105 * on the next fault. This effectively flushes the ENTIRE TLB for the MM at the
106 * cost of (possibly) a large number of future TLBmisses.
108 * The current algorithm is optimized based on the following (somewhat true)
110 * - GRU contexts are not loaded into a GRU unless a reference is made to
111 * the data segment or control block (this is true, not an assumption).
112 * If a DS/CB is referenced, the user will also issue instructions that
113 * cause TLBmisses. It is not necessary to optimize for the case where
114 * contexts are loaded but no instructions cause TLB misses. (I know
115 * this will happen but I'm not optimizing for it).
116 * - GRU instructions to invalidate TLB entries are SLOOOOWWW - normally
117 * a few usec but in unusual cases, it could be longer. Avoid if
119 * - intrablade process migration between cpus is not frequent but is
121 * - a GRU context is not typically migrated to a different GRU on the
122 * blade because of intrablade migration
123 * - interblade migration is rare. Processes migrate their GRU context to
125 * - if interblade migration occurs, migration back to the original blade
126 * is very very rare (ie., no optimization for this case)
127 * - most GRU instruction operate on a subset of the user REGIONS. Code
128 * & shared library regions are not likely targets of GRU instructions.
130 * To help improve the efficiency of TLB invalidation, the GMS data
131 * structure is maintained for EACH address space (MM struct). The GMS is
132 * also the structure that contains the pointer to the mmu callout
133 * functions. This structure is linked to the mm_struct for the address space
134 * using the mmu "register" function. The mmu interfaces are used to
135 * provide the callbacks for TLB invalidation. The GMS contains:
137 * - asid[maxgrus] array. ASIDs are assigned to a GRU when a context is
138 * loaded into the GRU.
139 * - asidmap[maxgrus]. bitmap to make it easier to find non-zero asids in
141 * - ctxbitmap[maxgrus]. Indicates the contexts that are currently active
142 * in the GRU for the address space. This bitmap must be passed to the
143 * GRU to do an invalidate.
145 * The current algorithm for invalidating TLBs is:
146 * - scan the asidmap for GRUs where the context has been loaded, ie,
148 * - for each gru found:
149 * - if the ctxtmap is non-zero, there are active contexts in the
150 * GRU. TLB invalidate instructions must be issued to the GRU.
151 * - if the ctxtmap is zero, no context is active. Set the ASID to
152 * zero to force a full TLB invalidation. This is fast but will
153 * cause a lot of TLB misses if the context is reloaded onto the
158 void gru_flush_tlb_range(struct gru_mm_struct
*gms
, unsigned long start
,
161 struct gru_state
*gru
;
162 struct gru_mm_tracker
*asids
;
163 struct gru_tlb_global_handle
*tgh
;
165 int grupagesize
, pagesize
, pageshift
, gid
, asid
;
167 /* ZZZ TODO - handle huge pages */
168 pageshift
= PAGE_SHIFT
;
169 pagesize
= (1UL << pageshift
);
170 grupagesize
= GRU_PAGESIZE(pageshift
);
171 num
= min(((len
+ pagesize
- 1) >> pageshift
), GRUMAXINVAL
);
174 gru_dbg(grudev
, "gms %p, start 0x%lx, len 0x%lx, asidmap 0x%lx\n", gms
,
175 start
, len
, gms
->ms_asidmap
[0]);
177 spin_lock(&gms
->ms_asid_lock
);
178 for_each_gru_in_bitmap(gid
, gms
->ms_asidmap
) {
180 gru
= GID_TO_GRU(gid
);
181 asids
= gms
->ms_asids
+ gid
;
182 asid
= asids
->mt_asid
;
183 if (asids
->mt_ctxbitmap
&& asid
) {
184 STAT(flush_tlb_gru_tgh
);
185 asid
= GRUASID(asid
, start
);
187 " FLUSH gruid %d, asid 0x%x, vaddr 0x%lx, vamask 0x%x, num %ld, cbmap 0x%x\n",
188 gid
, asid
, start
, grupagesize
, num
, asids
->mt_ctxbitmap
);
189 tgh
= get_lock_tgh_handle(gru
);
190 tgh_invalidate(tgh
, start
, ~0, asid
, grupagesize
, 0,
191 num
- 1, asids
->mt_ctxbitmap
);
192 get_unlock_tgh_handle(tgh
);
194 STAT(flush_tlb_gru_zero_asid
);
196 __clear_bit(gru
->gs_gid
, gms
->ms_asidmap
);
198 " CLEARASID gruid %d, asid 0x%x, cbtmap 0x%x, asidmap 0x%lx\n",
199 gid
, asid
, asids
->mt_ctxbitmap
,
203 spin_unlock(&gms
->ms_asid_lock
);
207 * Flush the entire TLB on a chiplet.
209 void gru_flush_all_tlb(struct gru_state
*gru
)
211 struct gru_tlb_global_handle
*tgh
;
213 gru_dbg(grudev
, "gid %d\n", gru
->gs_gid
);
214 tgh
= get_lock_tgh_handle(gru
);
215 tgh_invalidate(tgh
, 0, ~0, 0, 1, 1, GRUMAXINVAL
- 1, 0xffff);
216 get_unlock_tgh_handle(tgh
);
220 * MMUOPS notifier callout functions
222 static int gru_invalidate_range_start(struct mmu_notifier
*mn
,
223 const struct mmu_notifier_range
*range
)
225 struct gru_mm_struct
*gms
= container_of(mn
, struct gru_mm_struct
,
228 STAT(mmu_invalidate_range
);
229 atomic_inc(&gms
->ms_range_active
);
230 gru_dbg(grudev
, "gms %p, start 0x%lx, end 0x%lx, act %d\n", gms
,
231 range
->start
, range
->end
, atomic_read(&gms
->ms_range_active
));
232 gru_flush_tlb_range(gms
, range
->start
, range
->end
- range
->start
);
237 static void gru_invalidate_range_end(struct mmu_notifier
*mn
,
238 const struct mmu_notifier_range
*range
)
240 struct gru_mm_struct
*gms
= container_of(mn
, struct gru_mm_struct
,
243 /* ..._and_test() provides needed barrier */
244 (void)atomic_dec_and_test(&gms
->ms_range_active
);
246 wake_up_all(&gms
->ms_wait_queue
);
247 gru_dbg(grudev
, "gms %p, start 0x%lx, end 0x%lx\n",
248 gms
, range
->start
, range
->end
);
251 static void gru_release(struct mmu_notifier
*mn
, struct mm_struct
*mm
)
253 struct gru_mm_struct
*gms
= container_of(mn
, struct gru_mm_struct
,
256 gms
->ms_released
= 1;
257 gru_dbg(grudev
, "gms %p\n", gms
);
261 static const struct mmu_notifier_ops gru_mmuops
= {
262 .invalidate_range_start
= gru_invalidate_range_start
,
263 .invalidate_range_end
= gru_invalidate_range_end
,
264 .release
= gru_release
,
267 /* Move this to the basic mmu_notifier file. But for now... */
268 static struct mmu_notifier
*mmu_find_ops(struct mm_struct
*mm
,
269 const struct mmu_notifier_ops
*ops
)
271 struct mmu_notifier
*mn
, *gru_mn
= NULL
;
273 if (mm
->mmu_notifier_mm
) {
275 hlist_for_each_entry_rcu(mn
, &mm
->mmu_notifier_mm
->list
,
277 if (mn
->ops
== ops
) {
286 struct gru_mm_struct
*gru_register_mmu_notifier(void)
288 struct gru_mm_struct
*gms
;
289 struct mmu_notifier
*mn
;
292 mn
= mmu_find_ops(current
->mm
, &gru_mmuops
);
294 gms
= container_of(mn
, struct gru_mm_struct
, ms_notifier
);
295 atomic_inc(&gms
->ms_refcnt
);
297 gms
= kzalloc(sizeof(*gms
), GFP_KERNEL
);
299 return ERR_PTR(-ENOMEM
);
301 spin_lock_init(&gms
->ms_asid_lock
);
302 gms
->ms_notifier
.ops
= &gru_mmuops
;
303 atomic_set(&gms
->ms_refcnt
, 1);
304 init_waitqueue_head(&gms
->ms_wait_queue
);
305 err
= __mmu_notifier_register(&gms
->ms_notifier
, current
->mm
);
310 gru_dbg(grudev
, "gms %p, refcnt %d\n", gms
,
311 atomic_read(&gms
->ms_refcnt
));
318 void gru_drop_mmu_notifier(struct gru_mm_struct
*gms
)
320 gru_dbg(grudev
, "gms %p, refcnt %d, released %d\n", gms
,
321 atomic_read(&gms
->ms_refcnt
), gms
->ms_released
);
322 if (atomic_dec_return(&gms
->ms_refcnt
) == 0) {
323 if (!gms
->ms_released
)
324 mmu_notifier_unregister(&gms
->ms_notifier
, current
->mm
);
331 * Setup TGH parameters. There are:
332 * - 24 TGH handles per GRU chiplet
333 * - a portion (MAX_LOCAL_TGH) of the handles are reserved for
334 * use by blade-local cpus
335 * - the rest are used by off-blade cpus. This usage is
336 * less frequent than blade-local usage.
338 * For now, use 16 handles for local flushes, 8 for remote flushes. If the blade
339 * has less tan or equal to 16 cpus, each cpu has a unique handle that it can
342 #define MAX_LOCAL_TGH 16
344 void gru_tgh_flush_init(struct gru_state
*gru
)
346 int cpus
, shift
= 0, n
;
348 cpus
= uv_blade_nr_possible_cpus(gru
->gs_blade_id
);
350 /* n = cpus rounded up to next power of 2 */
352 n
= 1 << fls(cpus
- 1);
355 * shift count for converting local cpu# to TGH index
356 * 0 if cpus <= MAX_LOCAL_TGH,
357 * 1 if cpus <= 2*MAX_LOCAL_TGH,
360 shift
= max(0, fls(n
- 1) - fls(MAX_LOCAL_TGH
- 1));
362 gru
->gs_tgh_local_shift
= shift
;
364 /* first starting TGH index to use for remote purges */
365 gru
->gs_tgh_first_remote
= (cpus
+ (1 << shift
) - 1) >> shift
;