drivers/parisc/eisa.c

   1 /*
   2  * eisa.c - provide support for EISA adapters in PA-RISC machines
   3  *
   4  * This program is free software; you can redistribute it and/or
   5  * modify it under the terms of the GNU General Public License
   6  * as published by the Free Software Foundation; either version
   7  * 2 of the License, or (at your option) any later version.
   8  *
   9  * Copyright (c) 2001 Matthew Wilcox for Hewlett Packard
  10  * Copyright (c) 2001 Daniel Engstrom <5116@telia.com>
  11  *
  12  * There are two distinct EISA adapters.  Mongoose is found in machines
  13  * before the 712; then the Wax ASIC is used.  To complicate matters, the
  14  * Wax ASIC also includes a PS/2 and RS-232 controller, but those are
  15  * dealt with elsewhere; this file is concerned only with the EISA portions
  16  * of Wax.
  17  *
  18  *
  19  * HINT:
  20  * -----
  21  * To allow an ISA card to work properly in the EISA slot you need to
  22  * set an edge trigger level. This may be done on the palo command line
  23  * by adding the kernel parameter "eisa_irq_edge=n,n2,[...]]", with
  24  * n and n2 as the irq levels you want to use.
  25  *
  26  * Example: "eisa_irq_edge=10,11" allows ISA cards to operate at
  27  * irq levels 10 and 11.
  28  */
  29
  30 #include <linux/init.h>
  31 #include <linux/ioport.h>
  32 #include <linux/interrupt.h>
  33 #include <linux/kernel.h>
  34 #include <linux/module.h>
  35 #include <linux/pci.h>
  36 #include <linux/spinlock.h>
  37 #include <linux/eisa.h>
  38
  39 #include <asm/byteorder.h>
  40 #include <asm/io.h>
  41 #include <asm/hardware.h>
  42 #include <asm/processor.h>
  43 #include <asm/parisc-device.h>
  44 #include <asm/delay.h>
  45 #include <asm/eisa_bus.h>
  46 #include <asm/eisa_eeprom.h>
  47
  48 #include "iommu.h"
  49
  50 #if 0
  51 #define EISA_DBG(msg, arg...) printk(KERN_DEBUG "eisa: " msg, ## arg)
  52 #else
  53 #define EISA_DBG(msg, arg...)
  54 #endif
  55
  56 #define SNAKES_EEPROM_BASE_ADDR 0xF0810400
  57 #define MIRAGE_EEPROM_BASE_ADDR 0xF00C0400
  58
  59 static DEFINE_SPINLOCK(eisa_irq_lock);
  60
  61 void __iomem *eisa_eeprom_addr __read_mostly;
  62
  63 /* We can only have one EISA adapter in the system because neither
  64  * implementation can be flexed.
  65  */
  66 static struct eisa_ba {
  67         struct pci_hba_data     hba;
  68         unsigned long eeprom_addr;
  69         struct eisa_root_device root;
  70 } eisa_dev;
  71
  72 /* Port ops */
  73
  74 static inline unsigned long eisa_permute(unsigned short port)
  75 {
  76         if (port & 0x300) {
  77                 return 0xfc000000 | ((port & 0xfc00) >> 6)
  78                         | ((port & 0x3f8) << 9) | (port & 7);
  79         } else {
  80                 return 0xfc000000 | port;
  81         }
  82 }
  83
  84 unsigned char eisa_in8(unsigned short port)
  85 {
  86         if (EISA_bus)
  87                 return gsc_readb(eisa_permute(port));
  88         return 0xff;
  89 }
  90
  91 unsigned short eisa_in16(unsigned short port)
  92 {
  93         if (EISA_bus)
  94                 return le16_to_cpu(gsc_readw(eisa_permute(port)));
  95         return 0xffff;
  96 }
  97
  98 unsigned int eisa_in32(unsigned short port)
  99 {
 100         if (EISA_bus)
 101                 return le32_to_cpu(gsc_readl(eisa_permute(port)));
 102         return 0xffffffff;
 103 }
 104
 105 void eisa_out8(unsigned char data, unsigned short port)
 106 {
 107         if (EISA_bus)
 108                 gsc_writeb(data, eisa_permute(port));
 109 }
 110
 111 void eisa_out16(unsigned short data, unsigned short port)
 112 {
 113         if (EISA_bus)
 114                 gsc_writew(cpu_to_le16(data), eisa_permute(port));
 115 }
 116
 117 void eisa_out32(unsigned int data, unsigned short port)
 118 {
 119         if (EISA_bus)
 120                 gsc_writel(cpu_to_le32(data), eisa_permute(port));
 121 }
 122
 123 #ifndef CONFIG_PCI
 124 /* We call these directly without PCI.  See asm/io.h. */
 125 EXPORT_SYMBOL(eisa_in8);
 126 EXPORT_SYMBOL(eisa_in16);
 127 EXPORT_SYMBOL(eisa_in32);
 128 EXPORT_SYMBOL(eisa_out8);
 129 EXPORT_SYMBOL(eisa_out16);
 130 EXPORT_SYMBOL(eisa_out32);
 131 #endif
 132
 133 /* Interrupt handling */
 134
 135 /* cached interrupt mask registers */
 136 static int master_mask;
 137 static int slave_mask;
 138
 139 /* the trig level can be set with the
 140  * eisa_irq_edge=n,n,n commandline parameter
 141  * We should really read this from the EEPROM
 142  * in the furure.
 143  */
 144 /* irq 13,8,2,1,0 must be edge */
 145 static unsigned int eisa_irq_level __read_mostly; /* default to edge triggered */
 146
 147
 148 /* called by free irq */
 149 static void eisa_mask_irq(struct irq_data *d)
 150 {
 151         unsigned int irq = d->irq;
 152         unsigned long flags;
 153
 154         EISA_DBG("disable irq %d\n", irq);
 155         /* just mask for now */
 156         spin_lock_irqsave(&eisa_irq_lock, flags);
 157         if (irq & 8) {
 158                 slave_mask |= (1 << (irq&7));
 159                 eisa_out8(slave_mask, 0xa1);
 160         } else {
 161                 master_mask |= (1 << (irq&7));
 162                 eisa_out8(master_mask, 0x21);
 163         }
 164         spin_unlock_irqrestore(&eisa_irq_lock, flags);
 165         EISA_DBG("pic0 mask %02x\n", eisa_in8(0x21));
 166         EISA_DBG("pic1 mask %02x\n", eisa_in8(0xa1));
 167 }
 168
 169 /* called by request irq */
 170 static void eisa_unmask_irq(struct irq_data *d)
 171 {
 172         unsigned int irq = d->irq;
 173         unsigned long flags;
 174         EISA_DBG("enable irq %d\n", irq);
 175
 176         spin_lock_irqsave(&eisa_irq_lock, flags);
 177         if (irq & 8) {
 178                 slave_mask &= ~(1 << (irq&7));
 179                 eisa_out8(slave_mask, 0xa1);
 180         } else {
 181                 master_mask &= ~(1 << (irq&7));
 182                 eisa_out8(master_mask, 0x21);
 183         }
 184         spin_unlock_irqrestore(&eisa_irq_lock, flags);
 185         EISA_DBG("pic0 mask %02x\n", eisa_in8(0x21));
 186         EISA_DBG("pic1 mask %02x\n", eisa_in8(0xa1));
 187 }
 188
 189 static struct irq_chip eisa_interrupt_type = {
 190         .name           =       "EISA",
 191         .irq_unmask     =       eisa_unmask_irq,
 192         .irq_mask       =       eisa_mask_irq,
 193 };
 194
 195 static irqreturn_t eisa_irq(int wax_irq, void *intr_dev)
 196 {
 197         int irq = gsc_readb(0xfc01f000); /* EISA supports 16 irqs */
 198         unsigned long flags;
 199
 200         spin_lock_irqsave(&eisa_irq_lock, flags);
 201         /* read IRR command */
 202         eisa_out8(0x0a, 0x20);
 203         eisa_out8(0x0a, 0xa0);
 204
 205         EISA_DBG("irq IAR %02x 8259-1 irr %02x 8259-2 irr %02x\n",
 206                    irq, eisa_in8(0x20), eisa_in8(0xa0));
 207
 208         /* read ISR command */
 209         eisa_out8(0x0a, 0x20);
 210         eisa_out8(0x0a, 0xa0);
 211         EISA_DBG("irq 8259-1 isr %02x imr %02x 8259-2 isr %02x imr %02x\n",
 212                  eisa_in8(0x20), eisa_in8(0x21), eisa_in8(0xa0), eisa_in8(0xa1));
 213
 214         irq &= 0xf;
 215
 216         /* mask irq and write eoi */
 217         if (irq & 8) {
 218                 slave_mask |= (1 << (irq&7));
 219                 eisa_out8(slave_mask, 0xa1);
 220                 eisa_out8(0x60 | (irq&7),0xa0);/* 'Specific EOI' to slave */
 221                 eisa_out8(0x62, 0x20);  /* 'Specific EOI' to master-IRQ2 */
 222
 223         } else {
 224                 master_mask |= (1 << (irq&7));
 225                 eisa_out8(master_mask, 0x21);
 226                 eisa_out8(0x60|irq, 0x20);      /* 'Specific EOI' to master */
 227         }
 228         spin_unlock_irqrestore(&eisa_irq_lock, flags);
 229
 230         generic_handle_irq(irq);
 231
 232         spin_lock_irqsave(&eisa_irq_lock, flags);
 233         /* unmask */
 234         if (irq & 8) {
 235                 slave_mask &= ~(1 << (irq&7));
 236                 eisa_out8(slave_mask, 0xa1);
 237         } else {
 238                 master_mask &= ~(1 << (irq&7));
 239                 eisa_out8(master_mask, 0x21);
 240         }
 241         spin_unlock_irqrestore(&eisa_irq_lock, flags);
 242         return IRQ_HANDLED;
 243 }
 244
 245 static irqreturn_t dummy_irq2_handler(int _, void *dev)
 246 {
 247         printk(KERN_ALERT "eisa: uhh, irq2?\n");
 248         return IRQ_HANDLED;
 249 }
 250
 251 static struct irqaction irq2_action = {
 252         .handler = dummy_irq2_handler,
 253         .name = "cascade",
 254 };
 255
 256 static void init_eisa_pic(void)
 257 {
 258         unsigned long flags;
 259
 260         spin_lock_irqsave(&eisa_irq_lock, flags);
 261
 262         eisa_out8(0xff, 0x21); /* mask during init */
 263         eisa_out8(0xff, 0xa1); /* mask during init */
 264
 265         /* master pic */
 266         eisa_out8(0x11, 0x20); /* ICW1 */
 267         eisa_out8(0x00, 0x21); /* ICW2 */
 268         eisa_out8(0x04, 0x21); /* ICW3 */
 269         eisa_out8(0x01, 0x21); /* ICW4 */
 270         eisa_out8(0x40, 0x20); /* OCW2 */
 271
 272         /* slave pic */
 273         eisa_out8(0x11, 0xa0); /* ICW1 */
 274         eisa_out8(0x08, 0xa1); /* ICW2 */
 275         eisa_out8(0x02, 0xa1); /* ICW3 */
 276         eisa_out8(0x01, 0xa1); /* ICW4 */
 277         eisa_out8(0x40, 0xa0); /* OCW2 */
 278
 279         udelay(100);
 280
 281         slave_mask = 0xff;
 282         master_mask = 0xfb;
 283         eisa_out8(slave_mask, 0xa1); /* OCW1 */
 284         eisa_out8(master_mask, 0x21); /* OCW1 */
 285
 286         /* setup trig level */
 287         EISA_DBG("EISA edge/level %04x\n", eisa_irq_level);
 288
 289         eisa_out8(eisa_irq_level&0xff, 0x4d0); /* Set all irq's to edge  */
 290         eisa_out8((eisa_irq_level >> 8) & 0xff, 0x4d1);
 291
 292         EISA_DBG("pic0 mask %02x\n", eisa_in8(0x21));
 293         EISA_DBG("pic1 mask %02x\n", eisa_in8(0xa1));
 294         EISA_DBG("pic0 edge/level %02x\n", eisa_in8(0x4d0));
 295         EISA_DBG("pic1 edge/level %02x\n", eisa_in8(0x4d1));
 296
 297         spin_unlock_irqrestore(&eisa_irq_lock, flags);
 298 }
 299
 300 /* Device initialisation */
 301
 302 #define is_mongoose(dev) (dev->id.sversion == 0x00076)
 303
 304 static int __init eisa_probe(struct parisc_device *dev)
 305 {
 306         int i, result;
 307
 308         char *name = is_mongoose(dev) ? "Mongoose" : "Wax";
 309
 310         printk(KERN_INFO "%s EISA Adapter found at 0x%08lx\n",
 311                 name, (unsigned long)dev->hpa.start);
 312
 313         eisa_dev.hba.dev = dev;
 314         eisa_dev.hba.iommu = ccio_get_iommu(dev);
 315
 316         eisa_dev.hba.lmmio_space.name = "EISA";
 317         eisa_dev.hba.lmmio_space.start = F_EXTEND(0xfc000000);
 318         eisa_dev.hba.lmmio_space.end = F_EXTEND(0xffbfffff);
 319         eisa_dev.hba.lmmio_space.flags = IORESOURCE_MEM;
 320         result = ccio_request_resource(dev, &eisa_dev.hba.lmmio_space);
 321         if (result < 0) {
 322                 printk(KERN_ERR "EISA: failed to claim EISA Bus address space!\n");
 323                 return result;
 324         }
 325         eisa_dev.hba.io_space.name = "EISA";
 326         eisa_dev.hba.io_space.start = 0;
 327         eisa_dev.hba.io_space.end = 0xffff;
 328         eisa_dev.hba.lmmio_space.flags = IORESOURCE_IO;
 329         result = request_resource(&ioport_resource, &eisa_dev.hba.io_space);
 330         if (result < 0) {
 331                 printk(KERN_ERR "EISA: failed to claim EISA Bus port space!\n");
 332                 return result;
 333         }
 334         pcibios_register_hba(&eisa_dev.hba);
 335
 336         result = request_irq(dev->irq, eisa_irq, IRQF_SHARED, "EISA", &eisa_dev);
 337         if (result) {
 338                 printk(KERN_ERR "EISA: request_irq failed!\n");
 339                 goto error_release;
 340         }
 341
 342         /* Reserve IRQ2 */
 343         setup_irq(2, &irq2_action);
 344         for (i = 0; i < 16; i++) {
 345                 irq_set_chip_and_handler(i, &eisa_interrupt_type,
 346                                          handle_simple_irq);
 347         }
 348
 349         EISA_bus = 1;
 350
 351         if (dev->num_addrs) {
 352                 /* newer firmware hand out the eeprom address */
 353                 eisa_dev.eeprom_addr = dev->addr[0];
 354         } else {
 355                 /* old firmware, need to figure out the box */
 356                 if (is_mongoose(dev)) {
 357                         eisa_dev.eeprom_addr = SNAKES_EEPROM_BASE_ADDR;
 358                 } else {
 359                         eisa_dev.eeprom_addr = MIRAGE_EEPROM_BASE_ADDR;
 360                 }
 361         }
 362         eisa_eeprom_addr = ioremap_nocache(eisa_dev.eeprom_addr, HPEE_MAX_LENGTH);
 363         if (!eisa_eeprom_addr) {
 364                 result = -ENOMEM;
 365                 printk(KERN_ERR "EISA: ioremap_nocache failed!\n");
 366                 goto error_free_irq;
 367         }
 368         result = eisa_enumerator(eisa_dev.eeprom_addr, &eisa_dev.hba.io_space,
 369                         &eisa_dev.hba.lmmio_space);
 370         init_eisa_pic();
 371
 372         if (result >= 0) {
 373                 /* FIXME : Don't enumerate the bus twice. */
 374                 eisa_dev.root.dev = &dev->dev;
 375                 dev_set_drvdata(&dev->dev, &eisa_dev.root);
 376                 eisa_dev.root.bus_base_addr = 0;
 377                 eisa_dev.root.res = &eisa_dev.hba.io_space;
 378                 eisa_dev.root.slots = result;
 379                 eisa_dev.root.dma_mask = 0xffffffff; /* wild guess */
 380                 if (eisa_root_register (&eisa_dev.root)) {
 381                         printk(KERN_ERR "EISA: Failed to register EISA root\n");
 382                         result = -ENOMEM;
 383                         goto error_iounmap;
 384                 }
 385         }
 386
 387         return 0;
 388
 389 error_iounmap:
 390         iounmap(eisa_eeprom_addr);
 391 error_free_irq:
 392         free_irq(dev->irq, &eisa_dev);
 393 error_release:
 394         release_resource(&eisa_dev.hba.io_space);
 395         return result;
 396 }
 397
 398 static const struct parisc_device_id eisa_tbl[] __initconst = {
 399         { HPHW_BA, HVERSION_REV_ANY_ID, HVERSION_ANY_ID, 0x00076 }, /* Mongoose */
 400         { HPHW_BA, HVERSION_REV_ANY_ID, HVERSION_ANY_ID, 0x00090 }, /* Wax EISA */
 401         { 0, }
 402 };
 403
 404 MODULE_DEVICE_TABLE(parisc, eisa_tbl);
 405
 406 static struct parisc_driver eisa_driver __refdata = {
 407         .name =         "eisa_ba",
 408         .id_table =     eisa_tbl,
 409         .probe =        eisa_probe,
 410 };
 411
 412 void __init eisa_init(void)
 413 {
 414         register_parisc_driver(&eisa_driver);
 415 }
 416
 417
 418 static unsigned int eisa_irq_configured;
 419 void eisa_make_irq_level(int num)
 420 {
 421         if (eisa_irq_configured& (1<<num)) {
 422                 printk(KERN_WARNING
 423                        "IRQ %d polarity configured twice (last to level)\n",
 424                        num);
 425         }
 426         eisa_irq_level |= (1<<num); /* set the corresponding bit */
 427         eisa_irq_configured |= (1<<num); /* set the corresponding bit */
 428 }
 429
 430 void eisa_make_irq_edge(int num)
 431 {
 432         if (eisa_irq_configured& (1<<num)) {
 433                 printk(KERN_WARNING
 434                        "IRQ %d polarity configured twice (last to edge)\n",
 435                        num);
 436         }
 437         eisa_irq_level &= ~(1<<num); /* clear the corresponding bit */
 438         eisa_irq_configured |= (1<<num); /* set the corresponding bit */
 439 }
 440
 441 static int __init eisa_irq_setup(char *str)
 442 {
 443         char *cur = str;
 444         int val;
 445
 446         EISA_DBG("IRQ setup\n");
 447         while (cur != NULL) {
 448                 char *pe;
 449
 450                 val = (int) simple_strtoul(cur, &pe, 0);
 451                 if (val > 15 || val < 0) {
 452                         printk(KERN_ERR "eisa: EISA irq value are 0-15\n");
 453                         continue;
 454                 }
 455                 if (val == 2) {
 456                         val = 9;
 457                 }
 458                 eisa_make_irq_edge(val); /* clear the corresponding bit */
 459                 EISA_DBG("setting IRQ %d to edge-triggered mode\n", val);
 460
 461                 if ((cur = strchr(cur, ','))) {
 462                         cur++;
 463                 } else {
 464                         break;
 465                 }
 466         }
 467         return 1;
 468 }
 469
 470 __setup("eisa_irq_edge=", eisa_irq_setup);
 471