2 * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
3 * Author: Chris Zhong <zyw@rock-chips.com>
4 * Kever Yang <kever.yang@rock-chips.com>
6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * The ROCKCHIP Type-C PHY has two PLL clocks. The first PLL clock
16 * is used for USB3, the second PLL clock is used for DP. This Type-C PHY has
17 * 3 working modes: USB3 only mode, DP only mode, and USB3+DP mode.
18 * At USB3 only mode, both PLL clocks need to be initialized, this allows the
19 * PHY to switch mode between USB3 and USB3+DP, without disconnecting the USB
21 * In The DP only mode, only the DP PLL needs to be powered on, and the 4 lanes
22 * are all used for DP.
24 * This driver gets extcon cable state and property, then decides which mode to
28 * EXTCON_USB or EXTCON_USB_HOST state is true, and
29 * EXTCON_PROP_USB_SS property is true.
30 * EXTCON_DISP_DP state is false.
33 * EXTCON_DISP_DP state is true, and
34 * EXTCON_PROP_USB_SS property is false.
35 * If EXTCON_USB_HOST state is true, it is DP + USB2 mode, since the USB2 phy
36 * is a separate phy, so this case is still DP only mode.
39 * EXTCON_USB_HOST and EXTCON_DISP_DP are both true, and
40 * EXTCON_PROP_USB_SS property is true.
42 * This Type-C PHY driver supports normal and flip orientation. The orientation
43 * is reported by the EXTCON_PROP_USB_TYPEC_POLARITY property: true is flip
44 * orientation, false is normal orientation.
48 #include <linux/clk.h>
49 #include <linux/clk-provider.h>
50 #include <linux/delay.h>
51 #include <linux/extcon.h>
53 #include <linux/iopoll.h>
54 #include <linux/kernel.h>
55 #include <linux/module.h>
56 #include <linux/mutex.h>
58 #include <linux/of_address.h>
59 #include <linux/of_platform.h>
60 #include <linux/platform_device.h>
61 #include <linux/regmap.h>
62 #include <linux/reset.h>
64 #include <linux/mfd/syscon.h>
65 #include <linux/phy/phy.h>
67 #define CMN_SSM_BANDGAP (0x21 << 2)
68 #define CMN_SSM_BIAS (0x22 << 2)
69 #define CMN_PLLSM0_PLLEN (0x29 << 2)
70 #define CMN_PLLSM0_PLLPRE (0x2a << 2)
71 #define CMN_PLLSM0_PLLVREF (0x2b << 2)
72 #define CMN_PLLSM0_PLLLOCK (0x2c << 2)
73 #define CMN_PLLSM1_PLLEN (0x31 << 2)
74 #define CMN_PLLSM1_PLLPRE (0x32 << 2)
75 #define CMN_PLLSM1_PLLVREF (0x33 << 2)
76 #define CMN_PLLSM1_PLLLOCK (0x34 << 2)
77 #define CMN_PLLSM1_USER_DEF_CTRL (0x37 << 2)
78 #define CMN_ICAL_OVRD (0xc1 << 2)
79 #define CMN_PLL0_VCOCAL_OVRD (0x83 << 2)
80 #define CMN_PLL0_VCOCAL_INIT (0x84 << 2)
81 #define CMN_PLL0_VCOCAL_ITER (0x85 << 2)
82 #define CMN_PLL0_LOCK_REFCNT_START (0x90 << 2)
83 #define CMN_PLL0_LOCK_PLLCNT_START (0x92 << 2)
84 #define CMN_PLL0_LOCK_PLLCNT_THR (0x93 << 2)
85 #define CMN_PLL0_INTDIV (0x94 << 2)
86 #define CMN_PLL0_FRACDIV (0x95 << 2)
87 #define CMN_PLL0_HIGH_THR (0x96 << 2)
88 #define CMN_PLL0_DSM_DIAG (0x97 << 2)
89 #define CMN_PLL0_SS_CTRL1 (0x98 << 2)
90 #define CMN_PLL0_SS_CTRL2 (0x99 << 2)
91 #define CMN_PLL1_VCOCAL_START (0xa1 << 2)
92 #define CMN_PLL1_VCOCAL_OVRD (0xa3 << 2)
93 #define CMN_PLL1_VCOCAL_INIT (0xa4 << 2)
94 #define CMN_PLL1_VCOCAL_ITER (0xa5 << 2)
95 #define CMN_PLL1_LOCK_REFCNT_START (0xb0 << 2)
96 #define CMN_PLL1_LOCK_PLLCNT_START (0xb2 << 2)
97 #define CMN_PLL1_LOCK_PLLCNT_THR (0xb3 << 2)
98 #define CMN_PLL1_INTDIV (0xb4 << 2)
99 #define CMN_PLL1_FRACDIV (0xb5 << 2)
100 #define CMN_PLL1_HIGH_THR (0xb6 << 2)
101 #define CMN_PLL1_DSM_DIAG (0xb7 << 2)
102 #define CMN_PLL1_SS_CTRL1 (0xb8 << 2)
103 #define CMN_PLL1_SS_CTRL2 (0xb9 << 2)
104 #define CMN_RXCAL_OVRD (0xd1 << 2)
106 #define CMN_TXPUCAL_CTRL (0xe0 << 2)
107 #define CMN_TXPUCAL_OVRD (0xe1 << 2)
108 #define CMN_TXPDCAL_CTRL (0xf0 << 2)
109 #define CMN_TXPDCAL_OVRD (0xf1 << 2)
111 /* For CMN_TXPUCAL_CTRL, CMN_TXPDCAL_CTRL */
112 #define CMN_TXPXCAL_START BIT(15)
113 #define CMN_TXPXCAL_DONE BIT(14)
114 #define CMN_TXPXCAL_NO_RESPONSE BIT(13)
115 #define CMN_TXPXCAL_CURRENT_RESPONSE BIT(12)
117 #define CMN_TXPU_ADJ_CTRL (0x108 << 2)
118 #define CMN_TXPD_ADJ_CTRL (0x10c << 2)
121 * For CMN_TXPUCAL_CTRL, CMN_TXPDCAL_CTRL,
122 * CMN_TXPU_ADJ_CTRL, CMN_TXPDCAL_CTRL
124 * NOTE: some of these registers are documented to be 2's complement
125 * signed numbers, but then documented to be always positive. Weird.
126 * In such a case, using CMN_CALIB_CODE_POS() avoids the unnecessary
129 #define CMN_CALIB_CODE_WIDTH 7
130 #define CMN_CALIB_CODE_OFFSET 0
131 #define CMN_CALIB_CODE_MASK GENMASK(CMN_CALIB_CODE_WIDTH, 0)
132 #define CMN_CALIB_CODE(x) \
133 sign_extend32((x) >> CMN_CALIB_CODE_OFFSET, CMN_CALIB_CODE_WIDTH)
135 #define CMN_CALIB_CODE_POS_MASK GENMASK(CMN_CALIB_CODE_WIDTH - 1, 0)
136 #define CMN_CALIB_CODE_POS(x) \
137 (((x) >> CMN_CALIB_CODE_OFFSET) & CMN_CALIB_CODE_POS_MASK)
139 #define CMN_DIAG_PLL0_FBH_OVRD (0x1c0 << 2)
140 #define CMN_DIAG_PLL0_FBL_OVRD (0x1c1 << 2)
141 #define CMN_DIAG_PLL0_OVRD (0x1c2 << 2)
142 #define CMN_DIAG_PLL0_V2I_TUNE (0x1c5 << 2)
143 #define CMN_DIAG_PLL0_CP_TUNE (0x1c6 << 2)
144 #define CMN_DIAG_PLL0_LF_PROG (0x1c7 << 2)
145 #define CMN_DIAG_PLL1_FBH_OVRD (0x1d0 << 2)
146 #define CMN_DIAG_PLL1_FBL_OVRD (0x1d1 << 2)
147 #define CMN_DIAG_PLL1_OVRD (0x1d2 << 2)
148 #define CMN_DIAG_PLL1_V2I_TUNE (0x1d5 << 2)
149 #define CMN_DIAG_PLL1_CP_TUNE (0x1d6 << 2)
150 #define CMN_DIAG_PLL1_LF_PROG (0x1d7 << 2)
151 #define CMN_DIAG_PLL1_PTATIS_TUNE1 (0x1d8 << 2)
152 #define CMN_DIAG_PLL1_PTATIS_TUNE2 (0x1d9 << 2)
153 #define CMN_DIAG_PLL1_INCLK_CTRL (0x1da << 2)
154 #define CMN_DIAG_HSCLK_SEL (0x1e0 << 2)
156 #define XCVR_PSM_RCTRL(n) ((0x4001 | ((n) << 9)) << 2)
157 #define XCVR_PSM_CAL_TMR(n) ((0x4002 | ((n) << 9)) << 2)
158 #define XCVR_PSM_A0IN_TMR(n) ((0x4003 | ((n) << 9)) << 2)
159 #define TX_TXCC_CAL_SCLR_MULT(n) ((0x4047 | ((n) << 9)) << 2)
160 #define TX_TXCC_CPOST_MULT_00(n) ((0x404c | ((n) << 9)) << 2)
161 #define TX_TXCC_CPOST_MULT_01(n) ((0x404d | ((n) << 9)) << 2)
162 #define TX_TXCC_CPOST_MULT_10(n) ((0x404e | ((n) << 9)) << 2)
163 #define TX_TXCC_CPOST_MULT_11(n) ((0x404f | ((n) << 9)) << 2)
164 #define TX_TXCC_MGNFS_MULT_000(n) ((0x4050 | ((n) << 9)) << 2)
165 #define TX_TXCC_MGNFS_MULT_001(n) ((0x4051 | ((n) << 9)) << 2)
166 #define TX_TXCC_MGNFS_MULT_010(n) ((0x4052 | ((n) << 9)) << 2)
167 #define TX_TXCC_MGNFS_MULT_011(n) ((0x4053 | ((n) << 9)) << 2)
168 #define TX_TXCC_MGNFS_MULT_100(n) ((0x4054 | ((n) << 9)) << 2)
169 #define TX_TXCC_MGNFS_MULT_101(n) ((0x4055 | ((n) << 9)) << 2)
170 #define TX_TXCC_MGNFS_MULT_110(n) ((0x4056 | ((n) << 9)) << 2)
171 #define TX_TXCC_MGNFS_MULT_111(n) ((0x4057 | ((n) << 9)) << 2)
172 #define TX_TXCC_MGNLS_MULT_000(n) ((0x4058 | ((n) << 9)) << 2)
173 #define TX_TXCC_MGNLS_MULT_001(n) ((0x4059 | ((n) << 9)) << 2)
174 #define TX_TXCC_MGNLS_MULT_010(n) ((0x405a | ((n) << 9)) << 2)
175 #define TX_TXCC_MGNLS_MULT_011(n) ((0x405b | ((n) << 9)) << 2)
176 #define TX_TXCC_MGNLS_MULT_100(n) ((0x405c | ((n) << 9)) << 2)
177 #define TX_TXCC_MGNLS_MULT_101(n) ((0x405d | ((n) << 9)) << 2)
178 #define TX_TXCC_MGNLS_MULT_110(n) ((0x405e | ((n) << 9)) << 2)
179 #define TX_TXCC_MGNLS_MULT_111(n) ((0x405f | ((n) << 9)) << 2)
181 #define XCVR_DIAG_PLLDRC_CTRL(n) ((0x40e0 | ((n) << 9)) << 2)
182 #define XCVR_DIAG_BIDI_CTRL(n) ((0x40e8 | ((n) << 9)) << 2)
183 #define XCVR_DIAG_LANE_FCM_EN_MGN(n) ((0x40f2 | ((n) << 9)) << 2)
184 #define TX_PSC_A0(n) ((0x4100 | ((n) << 9)) << 2)
185 #define TX_PSC_A1(n) ((0x4101 | ((n) << 9)) << 2)
186 #define TX_PSC_A2(n) ((0x4102 | ((n) << 9)) << 2)
187 #define TX_PSC_A3(n) ((0x4103 | ((n) << 9)) << 2)
188 #define TX_RCVDET_CTRL(n) ((0x4120 | ((n) << 9)) << 2)
189 #define TX_RCVDET_EN_TMR(n) ((0x4122 | ((n) << 9)) << 2)
190 #define TX_RCVDET_ST_TMR(n) ((0x4123 | ((n) << 9)) << 2)
191 #define TX_DIAG_TX_DRV(n) ((0x41e1 | ((n) << 9)) << 2)
192 #define TX_DIAG_BGREF_PREDRV_DELAY (0x41e7 << 2)
194 /* Use this for "n" in macros like "_MULT_XXX" to target the aux channel */
195 #define AUX_CH_LANE 8
197 #define TX_ANA_CTRL_REG_1 (0x5020 << 2)
199 #define TXDA_DP_AUX_EN BIT(15)
200 #define AUXDA_SE_EN BIT(14)
201 #define TXDA_CAL_LATCH_EN BIT(13)
202 #define AUXDA_POLARITY BIT(12)
203 #define TXDA_DRV_POWER_ISOLATION_EN BIT(11)
204 #define TXDA_DRV_POWER_EN_PH_2_N BIT(10)
205 #define TXDA_DRV_POWER_EN_PH_1_N BIT(9)
206 #define TXDA_BGREF_EN BIT(8)
207 #define TXDA_DRV_LDO_EN BIT(7)
208 #define TXDA_DECAP_EN_DEL BIT(6)
209 #define TXDA_DECAP_EN BIT(5)
210 #define TXDA_UPHY_SUPPLY_EN_DEL BIT(4)
211 #define TXDA_UPHY_SUPPLY_EN BIT(3)
212 #define TXDA_LOW_LEAKAGE_EN BIT(2)
213 #define TXDA_DRV_IDLE_LOWI_EN BIT(1)
214 #define TXDA_DRV_CMN_MODE_EN BIT(0)
216 #define TX_ANA_CTRL_REG_2 (0x5021 << 2)
218 #define AUXDA_DEBOUNCING_CLK BIT(15)
219 #define TXDA_LPBK_RECOVERED_CLK_EN BIT(14)
220 #define TXDA_LPBK_ISI_GEN_EN BIT(13)
221 #define TXDA_LPBK_SERIAL_EN BIT(12)
222 #define TXDA_LPBK_LINE_EN BIT(11)
223 #define TXDA_DRV_LDO_REDC_SINKIQ BIT(10)
224 #define XCVR_DECAP_EN_DEL BIT(9)
225 #define XCVR_DECAP_EN BIT(8)
226 #define TXDA_MPHY_ENABLE_HS_NT BIT(7)
227 #define TXDA_MPHY_SA_MODE BIT(6)
228 #define TXDA_DRV_LDO_RBYR_FB_EN BIT(5)
229 #define TXDA_DRV_RST_PULL_DOWN BIT(4)
230 #define TXDA_DRV_LDO_BG_FB_EN BIT(3)
231 #define TXDA_DRV_LDO_BG_REF_EN BIT(2)
232 #define TXDA_DRV_PREDRV_EN_DEL BIT(1)
233 #define TXDA_DRV_PREDRV_EN BIT(0)
235 #define TXDA_COEFF_CALC_CTRL (0x5022 << 2)
237 #define TX_HIGH_Z BIT(6)
238 #define TX_VMARGIN_OFFSET 3
239 #define TX_VMARGIN_MASK 0x7
240 #define LOW_POWER_SWING_EN BIT(2)
241 #define TX_FCM_DRV_MAIN_EN BIT(1)
242 #define TX_FCM_FULL_MARGIN BIT(0)
244 #define TX_DIG_CTRL_REG_2 (0x5024 << 2)
246 #define TX_HIGH_Z_TM_EN BIT(15)
247 #define TX_RESCAL_CODE_OFFSET 0
248 #define TX_RESCAL_CODE_MASK 0x3f
250 #define TXDA_CYA_AUXDA_CYA (0x5025 << 2)
251 #define TX_ANA_CTRL_REG_3 (0x5026 << 2)
252 #define TX_ANA_CTRL_REG_4 (0x5027 << 2)
253 #define TX_ANA_CTRL_REG_5 (0x5029 << 2)
255 #define RX_PSC_A0(n) ((0x8000 | ((n) << 9)) << 2)
256 #define RX_PSC_A1(n) ((0x8001 | ((n) << 9)) << 2)
257 #define RX_PSC_A2(n) ((0x8002 | ((n) << 9)) << 2)
258 #define RX_PSC_A3(n) ((0x8003 | ((n) << 9)) << 2)
259 #define RX_PSC_CAL(n) ((0x8006 | ((n) << 9)) << 2)
260 #define RX_PSC_RDY(n) ((0x8007 | ((n) << 9)) << 2)
261 #define RX_IQPI_ILL_CAL_OVRD (0x8023 << 2)
262 #define RX_EPI_ILL_CAL_OVRD (0x8033 << 2)
263 #define RX_SDCAL0_OVRD (0x8041 << 2)
264 #define RX_SDCAL1_OVRD (0x8049 << 2)
265 #define RX_SLC_INIT (0x806d << 2)
266 #define RX_SLC_RUN (0x806e << 2)
267 #define RX_CDRLF_CNFG2 (0x8081 << 2)
268 #define RX_SIGDET_HL_FILT_TMR(n) ((0x8090 | ((n) << 9)) << 2)
269 #define RX_SLC_IOP0_OVRD (0x8101 << 2)
270 #define RX_SLC_IOP1_OVRD (0x8105 << 2)
271 #define RX_SLC_QOP0_OVRD (0x8109 << 2)
272 #define RX_SLC_QOP1_OVRD (0x810d << 2)
273 #define RX_SLC_EOP0_OVRD (0x8111 << 2)
274 #define RX_SLC_EOP1_OVRD (0x8115 << 2)
275 #define RX_SLC_ION0_OVRD (0x8119 << 2)
276 #define RX_SLC_ION1_OVRD (0x811d << 2)
277 #define RX_SLC_QON0_OVRD (0x8121 << 2)
278 #define RX_SLC_QON1_OVRD (0x8125 << 2)
279 #define RX_SLC_EON0_OVRD (0x8129 << 2)
280 #define RX_SLC_EON1_OVRD (0x812d << 2)
281 #define RX_SLC_IEP0_OVRD (0x8131 << 2)
282 #define RX_SLC_IEP1_OVRD (0x8135 << 2)
283 #define RX_SLC_QEP0_OVRD (0x8139 << 2)
284 #define RX_SLC_QEP1_OVRD (0x813d << 2)
285 #define RX_SLC_EEP0_OVRD (0x8141 << 2)
286 #define RX_SLC_EEP1_OVRD (0x8145 << 2)
287 #define RX_SLC_IEN0_OVRD (0x8149 << 2)
288 #define RX_SLC_IEN1_OVRD (0x814d << 2)
289 #define RX_SLC_QEN0_OVRD (0x8151 << 2)
290 #define RX_SLC_QEN1_OVRD (0x8155 << 2)
291 #define RX_SLC_EEN0_OVRD (0x8159 << 2)
292 #define RX_SLC_EEN1_OVRD (0x815d << 2)
293 #define RX_REE_CTRL_DATA_MASK(n) ((0x81bb | ((n) << 9)) << 2)
294 #define RX_DIAG_SIGDET_TUNE(n) ((0x81dc | ((n) << 9)) << 2)
295 #define RX_DIAG_SC2C_DELAY (0x81e1 << 2)
297 #define PMA_LANE_CFG (0xc000 << 2)
298 #define PIPE_CMN_CTRL1 (0xc001 << 2)
299 #define PIPE_CMN_CTRL2 (0xc002 << 2)
300 #define PIPE_COM_LOCK_CFG1 (0xc003 << 2)
301 #define PIPE_COM_LOCK_CFG2 (0xc004 << 2)
302 #define PIPE_RCV_DET_INH (0xc005 << 2)
303 #define DP_MODE_CTL (0xc008 << 2)
304 #define DP_CLK_CTL (0xc009 << 2)
305 #define STS (0xc00F << 2)
306 #define PHY_ISO_CMN_CTRL (0xc010 << 2)
307 #define PHY_DP_TX_CTL (0xc408 << 2)
308 #define PMA_CMN_CTRL1 (0xc800 << 2)
309 #define PHY_PMA_ISO_CMN_CTRL (0xc810 << 2)
310 #define PHY_ISOLATION_CTRL (0xc81f << 2)
311 #define PHY_PMA_ISO_XCVR_CTRL(n) ((0xcc11 | ((n) << 6)) << 2)
312 #define PHY_PMA_ISO_LINK_MODE(n) ((0xcc12 | ((n) << 6)) << 2)
313 #define PHY_PMA_ISO_PWRST_CTRL(n) ((0xcc13 | ((n) << 6)) << 2)
314 #define PHY_PMA_ISO_TX_DATA_LO(n) ((0xcc14 | ((n) << 6)) << 2)
315 #define PHY_PMA_ISO_TX_DATA_HI(n) ((0xcc15 | ((n) << 6)) << 2)
316 #define PHY_PMA_ISO_RX_DATA_LO(n) ((0xcc16 | ((n) << 6)) << 2)
317 #define PHY_PMA_ISO_RX_DATA_HI(n) ((0xcc17 | ((n) << 6)) << 2)
318 #define TX_BIST_CTRL(n) ((0x4140 | ((n) << 9)) << 2)
319 #define TX_BIST_UDDWR(n) ((0x4141 | ((n) << 9)) << 2)
322 * Selects which PLL clock will be driven on the analog high speed
323 * clock 0: PLL 0 div 1
324 * clock 1: PLL 1 div 2
326 #define CLK_PLL_CONFIG 0X30
327 #define CLK_PLL_MASK 0x33
329 #define CMN_READY BIT(0)
331 #define DP_PLL_CLOCK_ENABLE BIT(2)
332 #define DP_PLL_ENABLE BIT(0)
333 #define DP_PLL_DATA_RATE_RBR ((2 << 12) | (4 << 8))
334 #define DP_PLL_DATA_RATE_HBR ((2 << 12) | (4 << 8))
335 #define DP_PLL_DATA_RATE_HBR2 ((1 << 12) | (2 << 8))
337 #define DP_MODE_A0 BIT(4)
338 #define DP_MODE_A2 BIT(6)
339 #define DP_MODE_ENTER_A0 0xc101
340 #define DP_MODE_ENTER_A2 0xc104
342 #define PHY_MODE_SET_TIMEOUT 100000
344 #define PIN_ASSIGN_C_E 0x51d9
345 #define PIN_ASSIGN_D_F 0x5100
347 #define MODE_DISCONNECT 0
348 #define MODE_UFP_USB BIT(0)
349 #define MODE_DFP_USB BIT(1)
350 #define MODE_DFP_DP BIT(2)
359 * struct rockchip_usb3phy_port_cfg: usb3-phy port configuration.
360 * @reg: the base address for usb3-phy config.
361 * @typec_conn_dir: the register of type-c connector direction.
362 * @usb3tousb2_en: the register of type-c force usb2 to usb2 enable.
363 * @external_psm: the register of type-c phy external psm clock.
364 * @pipe_status: the register of type-c phy pipe status.
365 * @usb3_host_disable: the register of type-c usb3 host disable.
366 * @usb3_host_port: the register of type-c usb3 host port.
367 * @uphy_dp_sel: the register of type-c phy DP select control.
369 struct rockchip_usb3phy_port_cfg
{
371 struct usb3phy_reg typec_conn_dir
;
372 struct usb3phy_reg usb3tousb2_en
;
373 struct usb3phy_reg external_psm
;
374 struct usb3phy_reg pipe_status
;
375 struct usb3phy_reg usb3_host_disable
;
376 struct usb3phy_reg usb3_host_port
;
377 struct usb3phy_reg uphy_dp_sel
;
380 struct rockchip_typec_phy
{
383 struct extcon_dev
*extcon
;
384 struct regmap
*grf_regs
;
385 struct clk
*clk_core
;
387 struct reset_control
*uphy_rst
;
388 struct reset_control
*pipe_rst
;
389 struct reset_control
*tcphy_rst
;
390 const struct rockchip_usb3phy_port_cfg
*port_cfgs
;
391 /* mutex to protect access to individual PHYs */
403 struct phy_reg usb3_pll_cfg
[] = {
404 { 0xf0, CMN_PLL0_VCOCAL_INIT
},
405 { 0x18, CMN_PLL0_VCOCAL_ITER
},
406 { 0xd0, CMN_PLL0_INTDIV
},
407 { 0x4a4a, CMN_PLL0_FRACDIV
},
408 { 0x34, CMN_PLL0_HIGH_THR
},
409 { 0x1ee, CMN_PLL0_SS_CTRL1
},
410 { 0x7f03, CMN_PLL0_SS_CTRL2
},
411 { 0x20, CMN_PLL0_DSM_DIAG
},
412 { 0, CMN_DIAG_PLL0_OVRD
},
413 { 0, CMN_DIAG_PLL0_FBH_OVRD
},
414 { 0, CMN_DIAG_PLL0_FBL_OVRD
},
415 { 0x7, CMN_DIAG_PLL0_V2I_TUNE
},
416 { 0x45, CMN_DIAG_PLL0_CP_TUNE
},
417 { 0x8, CMN_DIAG_PLL0_LF_PROG
},
420 struct phy_reg dp_pll_cfg
[] = {
421 { 0xf0, CMN_PLL1_VCOCAL_INIT
},
422 { 0x18, CMN_PLL1_VCOCAL_ITER
},
423 { 0x30b9, CMN_PLL1_VCOCAL_START
},
424 { 0x21c, CMN_PLL1_INTDIV
},
425 { 0, CMN_PLL1_FRACDIV
},
426 { 0x5, CMN_PLL1_HIGH_THR
},
427 { 0x35, CMN_PLL1_SS_CTRL1
},
428 { 0x7f1e, CMN_PLL1_SS_CTRL2
},
429 { 0x20, CMN_PLL1_DSM_DIAG
},
430 { 0, CMN_PLLSM1_USER_DEF_CTRL
},
431 { 0, CMN_DIAG_PLL1_OVRD
},
432 { 0, CMN_DIAG_PLL1_FBH_OVRD
},
433 { 0, CMN_DIAG_PLL1_FBL_OVRD
},
434 { 0x6, CMN_DIAG_PLL1_V2I_TUNE
},
435 { 0x45, CMN_DIAG_PLL1_CP_TUNE
},
436 { 0x8, CMN_DIAG_PLL1_LF_PROG
},
437 { 0x100, CMN_DIAG_PLL1_PTATIS_TUNE1
},
438 { 0x7, CMN_DIAG_PLL1_PTATIS_TUNE2
},
439 { 0x4, CMN_DIAG_PLL1_INCLK_CTRL
},
442 static const struct rockchip_usb3phy_port_cfg rk3399_usb3phy_port_cfgs
[] = {
445 .typec_conn_dir
= { 0xe580, 0, 16 },
446 .usb3tousb2_en
= { 0xe580, 3, 19 },
447 .external_psm
= { 0xe588, 14, 30 },
448 .pipe_status
= { 0xe5c0, 0, 0 },
449 .usb3_host_disable
= { 0x2434, 0, 16 },
450 .usb3_host_port
= { 0x2434, 12, 28 },
451 .uphy_dp_sel
= { 0x6268, 19, 19 },
455 .typec_conn_dir
= { 0xe58c, 0, 16 },
456 .usb3tousb2_en
= { 0xe58c, 3, 19 },
457 .external_psm
= { 0xe594, 14, 30 },
458 .pipe_status
= { 0xe5c0, 16, 16 },
459 .usb3_host_disable
= { 0x2444, 0, 16 },
460 .usb3_host_port
= { 0x2444, 12, 28 },
461 .uphy_dp_sel
= { 0x6268, 3, 19 },
466 static void tcphy_cfg_24m(struct rockchip_typec_phy
*tcphy
)
471 * cmn_ref_clk_sel = 3, select the 24Mhz for clk parent
472 * cmn_psm_clk_dig_div = 2, set the clk division to 2
474 writel(0x830, tcphy
->base
+ PMA_CMN_CTRL1
);
475 for (i
= 0; i
< 4; i
++) {
477 * The following PHY configuration assumes a 24 MHz reference
480 writel(0x90, tcphy
->base
+ XCVR_DIAG_LANE_FCM_EN_MGN(i
));
481 writel(0x960, tcphy
->base
+ TX_RCVDET_EN_TMR(i
));
482 writel(0x30, tcphy
->base
+ TX_RCVDET_ST_TMR(i
));
485 rdata
= readl(tcphy
->base
+ CMN_DIAG_HSCLK_SEL
);
486 rdata
&= ~CLK_PLL_MASK
;
487 rdata
|= CLK_PLL_CONFIG
;
488 writel(rdata
, tcphy
->base
+ CMN_DIAG_HSCLK_SEL
);
491 static void tcphy_cfg_usb3_pll(struct rockchip_typec_phy
*tcphy
)
495 /* load the configuration of PLL0 */
496 for (i
= 0; i
< ARRAY_SIZE(usb3_pll_cfg
); i
++)
497 writel(usb3_pll_cfg
[i
].value
,
498 tcphy
->base
+ usb3_pll_cfg
[i
].addr
);
501 static void tcphy_cfg_dp_pll(struct rockchip_typec_phy
*tcphy
)
505 /* set the default mode to RBR */
506 writel(DP_PLL_CLOCK_ENABLE
| DP_PLL_ENABLE
| DP_PLL_DATA_RATE_RBR
,
507 tcphy
->base
+ DP_CLK_CTL
);
509 /* load the configuration of PLL1 */
510 for (i
= 0; i
< ARRAY_SIZE(dp_pll_cfg
); i
++)
511 writel(dp_pll_cfg
[i
].value
, tcphy
->base
+ dp_pll_cfg
[i
].addr
);
514 static void tcphy_tx_usb3_cfg_lane(struct rockchip_typec_phy
*tcphy
, u32 lane
)
516 writel(0x7799, tcphy
->base
+ TX_PSC_A0(lane
));
517 writel(0x7798, tcphy
->base
+ TX_PSC_A1(lane
));
518 writel(0x5098, tcphy
->base
+ TX_PSC_A2(lane
));
519 writel(0x5098, tcphy
->base
+ TX_PSC_A3(lane
));
520 writel(0, tcphy
->base
+ TX_TXCC_MGNFS_MULT_000(lane
));
521 writel(0xbf, tcphy
->base
+ XCVR_DIAG_BIDI_CTRL(lane
));
524 static void tcphy_rx_usb3_cfg_lane(struct rockchip_typec_phy
*tcphy
, u32 lane
)
526 writel(0xa6fd, tcphy
->base
+ RX_PSC_A0(lane
));
527 writel(0xa6fd, tcphy
->base
+ RX_PSC_A1(lane
));
528 writel(0xa410, tcphy
->base
+ RX_PSC_A2(lane
));
529 writel(0x2410, tcphy
->base
+ RX_PSC_A3(lane
));
530 writel(0x23ff, tcphy
->base
+ RX_PSC_CAL(lane
));
531 writel(0x13, tcphy
->base
+ RX_SIGDET_HL_FILT_TMR(lane
));
532 writel(0x03e7, tcphy
->base
+ RX_REE_CTRL_DATA_MASK(lane
));
533 writel(0x1004, tcphy
->base
+ RX_DIAG_SIGDET_TUNE(lane
));
534 writel(0x2010, tcphy
->base
+ RX_PSC_RDY(lane
));
535 writel(0xfb, tcphy
->base
+ XCVR_DIAG_BIDI_CTRL(lane
));
538 static void tcphy_dp_cfg_lane(struct rockchip_typec_phy
*tcphy
, u32 lane
)
542 writel(0xbefc, tcphy
->base
+ XCVR_PSM_RCTRL(lane
));
543 writel(0x6799, tcphy
->base
+ TX_PSC_A0(lane
));
544 writel(0x6798, tcphy
->base
+ TX_PSC_A1(lane
));
545 writel(0x98, tcphy
->base
+ TX_PSC_A2(lane
));
546 writel(0x98, tcphy
->base
+ TX_PSC_A3(lane
));
548 writel(0, tcphy
->base
+ TX_TXCC_MGNFS_MULT_000(lane
));
549 writel(0, tcphy
->base
+ TX_TXCC_MGNFS_MULT_001(lane
));
550 writel(0, tcphy
->base
+ TX_TXCC_MGNFS_MULT_010(lane
));
551 writel(0, tcphy
->base
+ TX_TXCC_MGNFS_MULT_011(lane
));
552 writel(0, tcphy
->base
+ TX_TXCC_MGNFS_MULT_100(lane
));
553 writel(0, tcphy
->base
+ TX_TXCC_MGNFS_MULT_101(lane
));
554 writel(0, tcphy
->base
+ TX_TXCC_MGNFS_MULT_110(lane
));
555 writel(0, tcphy
->base
+ TX_TXCC_MGNFS_MULT_111(lane
));
556 writel(0, tcphy
->base
+ TX_TXCC_CPOST_MULT_10(lane
));
557 writel(0, tcphy
->base
+ TX_TXCC_CPOST_MULT_01(lane
));
558 writel(0, tcphy
->base
+ TX_TXCC_CPOST_MULT_00(lane
));
559 writel(0, tcphy
->base
+ TX_TXCC_CPOST_MULT_11(lane
));
561 writel(0x128, tcphy
->base
+ TX_TXCC_CAL_SCLR_MULT(lane
));
562 writel(0x400, tcphy
->base
+ TX_DIAG_TX_DRV(lane
));
564 rdata
= readl(tcphy
->base
+ XCVR_DIAG_PLLDRC_CTRL(lane
));
565 rdata
= (rdata
& 0x8fff) | 0x6000;
566 writel(rdata
, tcphy
->base
+ XCVR_DIAG_PLLDRC_CTRL(lane
));
569 static inline int property_enable(struct rockchip_typec_phy
*tcphy
,
570 const struct usb3phy_reg
*reg
, bool en
)
572 u32 mask
= 1 << reg
->write_enable
;
573 u32 val
= en
<< reg
->enable_bit
;
575 return regmap_write(tcphy
->grf_regs
, reg
->offset
, val
| mask
);
578 static void tcphy_dp_aux_set_flip(struct rockchip_typec_phy
*tcphy
)
580 u16 tx_ana_ctrl_reg_1
;
583 * Select the polarity of the xcvr:
584 * 1, Reverses the polarity (If TYPEC, Pulls ups aux_p and pull
586 * 0, Normal polarity (if TYPEC, pulls up aux_m and pulls down
589 tx_ana_ctrl_reg_1
= readl(tcphy
->base
+ TX_ANA_CTRL_REG_1
);
591 tx_ana_ctrl_reg_1
|= AUXDA_POLARITY
;
593 tx_ana_ctrl_reg_1
&= ~AUXDA_POLARITY
;
594 writel(tx_ana_ctrl_reg_1
, tcphy
->base
+ TX_ANA_CTRL_REG_1
);
597 static void tcphy_dp_aux_calibration(struct rockchip_typec_phy
*tcphy
)
600 u16 tx_ana_ctrl_reg_1
;
601 u16 tx_ana_ctrl_reg_2
;
602 s32 pu_calib_code
, pd_calib_code
;
607 * Calculate calibration code as per docs: use an average of the
608 * pull down and pull up. Then add in adjustments.
610 val
= readl(tcphy
->base
+ CMN_TXPUCAL_CTRL
);
611 pu_calib_code
= CMN_CALIB_CODE_POS(val
);
612 val
= readl(tcphy
->base
+ CMN_TXPDCAL_CTRL
);
613 pd_calib_code
= CMN_CALIB_CODE_POS(val
);
614 val
= readl(tcphy
->base
+ CMN_TXPU_ADJ_CTRL
);
615 pu_adj
= CMN_CALIB_CODE(val
);
616 val
= readl(tcphy
->base
+ CMN_TXPD_ADJ_CTRL
);
617 pd_adj
= CMN_CALIB_CODE(val
);
618 calib
= (pu_calib_code
+ pd_calib_code
) / 2 + pu_adj
+ pd_adj
;
620 /* disable txda_cal_latch_en for rewrite the calibration values */
621 tx_ana_ctrl_reg_1
= readl(tcphy
->base
+ TX_ANA_CTRL_REG_1
);
622 tx_ana_ctrl_reg_1
&= ~TXDA_CAL_LATCH_EN
;
623 writel(tx_ana_ctrl_reg_1
, tcphy
->base
+ TX_ANA_CTRL_REG_1
);
625 /* write the calibration, then delay 10 ms as sample in docs */
626 val
= readl(tcphy
->base
+ TX_DIG_CTRL_REG_2
);
627 val
&= ~(TX_RESCAL_CODE_MASK
<< TX_RESCAL_CODE_OFFSET
);
628 val
|= calib
<< TX_RESCAL_CODE_OFFSET
;
629 writel(val
, tcphy
->base
+ TX_DIG_CTRL_REG_2
);
630 usleep_range(10000, 10050);
633 * Enable signal for latch that sample and holds calibration values.
634 * Activate this signal for 1 clock cycle to sample new calibration
637 tx_ana_ctrl_reg_1
|= TXDA_CAL_LATCH_EN
;
638 writel(tx_ana_ctrl_reg_1
, tcphy
->base
+ TX_ANA_CTRL_REG_1
);
639 usleep_range(150, 200);
641 /* set TX Voltage Level and TX Deemphasis to 0 */
642 writel(0, tcphy
->base
+ PHY_DP_TX_CTL
);
644 /* re-enable decap */
645 tx_ana_ctrl_reg_2
= XCVR_DECAP_EN
;
646 writel(tx_ana_ctrl_reg_2
, tcphy
->base
+ TX_ANA_CTRL_REG_2
);
648 tx_ana_ctrl_reg_2
|= XCVR_DECAP_EN_DEL
;
649 writel(tx_ana_ctrl_reg_2
, tcphy
->base
+ TX_ANA_CTRL_REG_2
);
651 writel(0, tcphy
->base
+ TX_ANA_CTRL_REG_3
);
653 tx_ana_ctrl_reg_1
|= TXDA_UPHY_SUPPLY_EN
;
654 writel(tx_ana_ctrl_reg_1
, tcphy
->base
+ TX_ANA_CTRL_REG_1
);
656 tx_ana_ctrl_reg_1
|= TXDA_UPHY_SUPPLY_EN_DEL
;
657 writel(tx_ana_ctrl_reg_1
, tcphy
->base
+ TX_ANA_CTRL_REG_1
);
659 writel(0, tcphy
->base
+ TX_ANA_CTRL_REG_5
);
662 * Programs txda_drv_ldo_prog[15:0], Sets driver LDO
663 * voltage 16'h1001 for DP-AUX-TX and RX
665 writel(0x1001, tcphy
->base
+ TX_ANA_CTRL_REG_4
);
667 /* re-enables Bandgap reference for LDO */
668 tx_ana_ctrl_reg_1
|= TXDA_DRV_LDO_EN
;
669 writel(tx_ana_ctrl_reg_1
, tcphy
->base
+ TX_ANA_CTRL_REG_1
);
671 tx_ana_ctrl_reg_1
|= TXDA_BGREF_EN
;
672 writel(tx_ana_ctrl_reg_1
, tcphy
->base
+ TX_ANA_CTRL_REG_1
);
675 * re-enables the transmitter pre-driver, driver data selection MUX,
676 * and receiver detect circuits.
678 tx_ana_ctrl_reg_2
|= TXDA_DRV_PREDRV_EN
;
679 writel(tx_ana_ctrl_reg_2
, tcphy
->base
+ TX_ANA_CTRL_REG_2
);
681 tx_ana_ctrl_reg_2
|= TXDA_DRV_PREDRV_EN_DEL
;
682 writel(tx_ana_ctrl_reg_2
, tcphy
->base
+ TX_ANA_CTRL_REG_2
);
685 * Do all the undocumented magic:
686 * - Turn on TXDA_DP_AUX_EN, whatever that is, even though sample
687 * never shows this going on.
688 * - Turn on TXDA_DECAP_EN (and TXDA_DECAP_EN_DEL) even though
689 * docs say for aux it's always 0.
690 * - Turn off the LDO and BGREF, which we just spent time turning
693 * Without this magic, things seem worse.
695 tx_ana_ctrl_reg_1
|= TXDA_DP_AUX_EN
;
696 tx_ana_ctrl_reg_1
|= TXDA_DECAP_EN
;
697 tx_ana_ctrl_reg_1
&= ~TXDA_DRV_LDO_EN
;
698 tx_ana_ctrl_reg_1
&= ~TXDA_BGREF_EN
;
699 writel(tx_ana_ctrl_reg_1
, tcphy
->base
+ TX_ANA_CTRL_REG_1
);
701 tx_ana_ctrl_reg_1
|= TXDA_DECAP_EN_DEL
;
702 writel(tx_ana_ctrl_reg_1
, tcphy
->base
+ TX_ANA_CTRL_REG_1
);
705 * Undo the work we did to set the LDO voltage.
706 * This doesn't seem to help nor hurt, but it kinda goes with the
707 * undocumented magic above.
709 writel(0, tcphy
->base
+ TX_ANA_CTRL_REG_4
);
711 /* Don't set voltage swing to 400 mV peak to peak (differential) */
712 writel(0, tcphy
->base
+ TXDA_COEFF_CALC_CTRL
);
714 /* Init TXDA_CYA_AUXDA_CYA for unknown magic reasons */
715 writel(0, tcphy
->base
+ TXDA_CYA_AUXDA_CYA
);
718 * More undocumented magic, presumably the goal of which is to
719 * make the "auxda_source_aux_oen" be ignored and instead to decide
720 * about "high impedance state" based on what software puts in the
721 * register TXDA_COEFF_CALC_CTRL (see TX_HIGH_Z). Since we only
722 * program that register once and we don't set the bit TX_HIGH_Z,
723 * presumably the goal here is that we should never put the analog
724 * driver in high impedance state.
726 val
= readl(tcphy
->base
+ TX_DIG_CTRL_REG_2
);
727 val
|= TX_HIGH_Z_TM_EN
;
728 writel(val
, tcphy
->base
+ TX_DIG_CTRL_REG_2
);
731 static int tcphy_phy_init(struct rockchip_typec_phy
*tcphy
, u8 mode
)
733 const struct rockchip_usb3phy_port_cfg
*cfg
= tcphy
->port_cfgs
;
737 ret
= clk_prepare_enable(tcphy
->clk_core
);
739 dev_err(tcphy
->dev
, "Failed to prepare_enable core clock\n");
743 ret
= clk_prepare_enable(tcphy
->clk_ref
);
745 dev_err(tcphy
->dev
, "Failed to prepare_enable ref clock\n");
749 reset_control_deassert(tcphy
->tcphy_rst
);
751 property_enable(tcphy
, &cfg
->typec_conn_dir
, tcphy
->flip
);
752 tcphy_dp_aux_set_flip(tcphy
);
754 tcphy_cfg_24m(tcphy
);
756 if (mode
== MODE_DFP_DP
) {
757 tcphy_cfg_dp_pll(tcphy
);
758 for (i
= 0; i
< 4; i
++)
759 tcphy_dp_cfg_lane(tcphy
, i
);
761 writel(PIN_ASSIGN_C_E
, tcphy
->base
+ PMA_LANE_CFG
);
763 tcphy_cfg_usb3_pll(tcphy
);
764 tcphy_cfg_dp_pll(tcphy
);
766 tcphy_tx_usb3_cfg_lane(tcphy
, 3);
767 tcphy_rx_usb3_cfg_lane(tcphy
, 2);
768 tcphy_dp_cfg_lane(tcphy
, 0);
769 tcphy_dp_cfg_lane(tcphy
, 1);
771 tcphy_tx_usb3_cfg_lane(tcphy
, 0);
772 tcphy_rx_usb3_cfg_lane(tcphy
, 1);
773 tcphy_dp_cfg_lane(tcphy
, 2);
774 tcphy_dp_cfg_lane(tcphy
, 3);
777 writel(PIN_ASSIGN_D_F
, tcphy
->base
+ PMA_LANE_CFG
);
780 writel(DP_MODE_ENTER_A2
, tcphy
->base
+ DP_MODE_CTL
);
782 reset_control_deassert(tcphy
->uphy_rst
);
784 ret
= readx_poll_timeout(readl
, tcphy
->base
+ PMA_CMN_CTRL1
,
785 val
, val
& CMN_READY
, 10,
786 PHY_MODE_SET_TIMEOUT
);
788 dev_err(tcphy
->dev
, "wait pma ready timeout\n");
793 reset_control_deassert(tcphy
->pipe_rst
);
798 reset_control_assert(tcphy
->uphy_rst
);
799 reset_control_assert(tcphy
->tcphy_rst
);
800 clk_disable_unprepare(tcphy
->clk_ref
);
802 clk_disable_unprepare(tcphy
->clk_core
);
806 static void tcphy_phy_deinit(struct rockchip_typec_phy
*tcphy
)
808 reset_control_assert(tcphy
->tcphy_rst
);
809 reset_control_assert(tcphy
->uphy_rst
);
810 reset_control_assert(tcphy
->pipe_rst
);
811 clk_disable_unprepare(tcphy
->clk_core
);
812 clk_disable_unprepare(tcphy
->clk_ref
);
815 static int tcphy_get_mode(struct rockchip_typec_phy
*tcphy
)
817 struct extcon_dev
*edev
= tcphy
->extcon
;
818 union extcon_property_value property
;
827 ufp
= extcon_get_state(edev
, EXTCON_USB
);
828 dp
= extcon_get_state(edev
, EXTCON_DISP_DP
);
831 id
= EXTCON_USB_HOST
;
840 ret
= extcon_get_property(edev
, id
, EXTCON_PROP_USB_SS
,
843 dev_err(tcphy
->dev
, "get superspeed property failed\n");
848 mode
|= MODE_DFP_USB
;
851 ret
= extcon_get_property(edev
, id
, EXTCON_PROP_USB_TYPEC_POLARITY
,
854 dev_err(tcphy
->dev
, "get polarity property failed\n");
858 tcphy
->flip
= property
.intval
? 1 : 0;
863 static int tcphy_cfg_usb3_to_usb2_only(struct rockchip_typec_phy
*tcphy
,
866 const struct rockchip_usb3phy_port_cfg
*cfg
= tcphy
->port_cfgs
;
868 property_enable(tcphy
, &cfg
->usb3tousb2_en
, value
);
869 property_enable(tcphy
, &cfg
->usb3_host_disable
, value
);
870 property_enable(tcphy
, &cfg
->usb3_host_port
, !value
);
875 static int rockchip_usb3_phy_power_on(struct phy
*phy
)
877 struct rockchip_typec_phy
*tcphy
= phy_get_drvdata(phy
);
878 const struct rockchip_usb3phy_port_cfg
*cfg
= tcphy
->port_cfgs
;
879 const struct usb3phy_reg
*reg
= &cfg
->pipe_status
;
880 int timeout
, new_mode
, ret
= 0;
883 mutex_lock(&tcphy
->lock
);
885 new_mode
= tcphy_get_mode(tcphy
);
891 /* DP-only mode; fall back to USB2 */
892 if (!(new_mode
& (MODE_DFP_USB
| MODE_UFP_USB
))) {
893 tcphy_cfg_usb3_to_usb2_only(tcphy
, true);
897 if (tcphy
->mode
== new_mode
)
900 if (tcphy
->mode
== MODE_DISCONNECT
) {
901 ret
= tcphy_phy_init(tcphy
, new_mode
);
906 /* wait TCPHY for pipe ready */
907 for (timeout
= 0; timeout
< 100; timeout
++) {
908 regmap_read(tcphy
->grf_regs
, reg
->offset
, &val
);
909 if (!(val
& BIT(reg
->enable_bit
))) {
910 tcphy
->mode
|= new_mode
& (MODE_DFP_USB
| MODE_UFP_USB
);
912 /* enable usb3 host */
913 tcphy_cfg_usb3_to_usb2_only(tcphy
, false);
916 usleep_range(10, 20);
919 if (tcphy
->mode
== MODE_DISCONNECT
)
920 tcphy_phy_deinit(tcphy
);
925 mutex_unlock(&tcphy
->lock
);
929 static int rockchip_usb3_phy_power_off(struct phy
*phy
)
931 struct rockchip_typec_phy
*tcphy
= phy_get_drvdata(phy
);
933 mutex_lock(&tcphy
->lock
);
934 tcphy_cfg_usb3_to_usb2_only(tcphy
, false);
936 if (tcphy
->mode
== MODE_DISCONNECT
)
939 tcphy
->mode
&= ~(MODE_UFP_USB
| MODE_DFP_USB
);
940 if (tcphy
->mode
== MODE_DISCONNECT
)
941 tcphy_phy_deinit(tcphy
);
944 mutex_unlock(&tcphy
->lock
);
948 static const struct phy_ops rockchip_usb3_phy_ops
= {
949 .power_on
= rockchip_usb3_phy_power_on
,
950 .power_off
= rockchip_usb3_phy_power_off
,
951 .owner
= THIS_MODULE
,
954 static int rockchip_dp_phy_power_on(struct phy
*phy
)
956 struct rockchip_typec_phy
*tcphy
= phy_get_drvdata(phy
);
957 const struct rockchip_usb3phy_port_cfg
*cfg
= tcphy
->port_cfgs
;
958 int new_mode
, ret
= 0;
961 mutex_lock(&tcphy
->lock
);
963 new_mode
= tcphy_get_mode(tcphy
);
969 if (!(new_mode
& MODE_DFP_DP
)) {
974 if (tcphy
->mode
== new_mode
)
978 * If the PHY has been power on, but the mode is not DP only mode,
979 * re-init the PHY for setting all of 4 lanes to DP.
981 if (new_mode
== MODE_DFP_DP
&& tcphy
->mode
!= MODE_DISCONNECT
) {
982 tcphy_phy_deinit(tcphy
);
983 ret
= tcphy_phy_init(tcphy
, new_mode
);
984 } else if (tcphy
->mode
== MODE_DISCONNECT
) {
985 ret
= tcphy_phy_init(tcphy
, new_mode
);
990 property_enable(tcphy
, &cfg
->uphy_dp_sel
, 1);
992 ret
= readx_poll_timeout(readl
, tcphy
->base
+ DP_MODE_CTL
,
993 val
, val
& DP_MODE_A2
, 1000,
994 PHY_MODE_SET_TIMEOUT
);
996 dev_err(tcphy
->dev
, "failed to wait TCPHY enter A2\n");
997 goto power_on_finish
;
1000 tcphy_dp_aux_calibration(tcphy
);
1002 writel(DP_MODE_ENTER_A0
, tcphy
->base
+ DP_MODE_CTL
);
1004 ret
= readx_poll_timeout(readl
, tcphy
->base
+ DP_MODE_CTL
,
1005 val
, val
& DP_MODE_A0
, 1000,
1006 PHY_MODE_SET_TIMEOUT
);
1008 writel(DP_MODE_ENTER_A2
, tcphy
->base
+ DP_MODE_CTL
);
1009 dev_err(tcphy
->dev
, "failed to wait TCPHY enter A0\n");
1010 goto power_on_finish
;
1013 tcphy
->mode
|= MODE_DFP_DP
;
1016 if (tcphy
->mode
== MODE_DISCONNECT
)
1017 tcphy_phy_deinit(tcphy
);
1019 mutex_unlock(&tcphy
->lock
);
1023 static int rockchip_dp_phy_power_off(struct phy
*phy
)
1025 struct rockchip_typec_phy
*tcphy
= phy_get_drvdata(phy
);
1027 mutex_lock(&tcphy
->lock
);
1029 if (tcphy
->mode
== MODE_DISCONNECT
)
1032 tcphy
->mode
&= ~MODE_DFP_DP
;
1034 writel(DP_MODE_ENTER_A2
, tcphy
->base
+ DP_MODE_CTL
);
1036 if (tcphy
->mode
== MODE_DISCONNECT
)
1037 tcphy_phy_deinit(tcphy
);
1040 mutex_unlock(&tcphy
->lock
);
1044 static const struct phy_ops rockchip_dp_phy_ops
= {
1045 .power_on
= rockchip_dp_phy_power_on
,
1046 .power_off
= rockchip_dp_phy_power_off
,
1047 .owner
= THIS_MODULE
,
1050 static int tcphy_parse_dt(struct rockchip_typec_phy
*tcphy
,
1053 tcphy
->grf_regs
= syscon_regmap_lookup_by_phandle(dev
->of_node
,
1055 if (IS_ERR(tcphy
->grf_regs
)) {
1056 dev_err(dev
, "could not find grf dt node\n");
1057 return PTR_ERR(tcphy
->grf_regs
);
1060 tcphy
->clk_core
= devm_clk_get(dev
, "tcpdcore");
1061 if (IS_ERR(tcphy
->clk_core
)) {
1062 dev_err(dev
, "could not get uphy core clock\n");
1063 return PTR_ERR(tcphy
->clk_core
);
1066 tcphy
->clk_ref
= devm_clk_get(dev
, "tcpdphy-ref");
1067 if (IS_ERR(tcphy
->clk_ref
)) {
1068 dev_err(dev
, "could not get uphy ref clock\n");
1069 return PTR_ERR(tcphy
->clk_ref
);
1072 tcphy
->uphy_rst
= devm_reset_control_get(dev
, "uphy");
1073 if (IS_ERR(tcphy
->uphy_rst
)) {
1074 dev_err(dev
, "no uphy_rst reset control found\n");
1075 return PTR_ERR(tcphy
->uphy_rst
);
1078 tcphy
->pipe_rst
= devm_reset_control_get(dev
, "uphy-pipe");
1079 if (IS_ERR(tcphy
->pipe_rst
)) {
1080 dev_err(dev
, "no pipe_rst reset control found\n");
1081 return PTR_ERR(tcphy
->pipe_rst
);
1084 tcphy
->tcphy_rst
= devm_reset_control_get(dev
, "uphy-tcphy");
1085 if (IS_ERR(tcphy
->tcphy_rst
)) {
1086 dev_err(dev
, "no tcphy_rst reset control found\n");
1087 return PTR_ERR(tcphy
->tcphy_rst
);
1093 static void typec_phy_pre_init(struct rockchip_typec_phy
*tcphy
)
1095 const struct rockchip_usb3phy_port_cfg
*cfg
= tcphy
->port_cfgs
;
1097 reset_control_assert(tcphy
->tcphy_rst
);
1098 reset_control_assert(tcphy
->uphy_rst
);
1099 reset_control_assert(tcphy
->pipe_rst
);
1101 /* select external psm clock */
1102 property_enable(tcphy
, &cfg
->external_psm
, 1);
1103 property_enable(tcphy
, &cfg
->usb3tousb2_en
, 0);
1105 tcphy
->mode
= MODE_DISCONNECT
;
1108 static int rockchip_typec_phy_probe(struct platform_device
*pdev
)
1110 struct device
*dev
= &pdev
->dev
;
1111 struct device_node
*np
= dev
->of_node
;
1112 struct device_node
*child_np
;
1113 struct rockchip_typec_phy
*tcphy
;
1114 struct phy_provider
*phy_provider
;
1115 struct resource
*res
;
1116 const struct rockchip_usb3phy_port_cfg
*phy_cfgs
;
1117 const struct of_device_id
*match
;
1120 tcphy
= devm_kzalloc(dev
, sizeof(*tcphy
), GFP_KERNEL
);
1124 match
= of_match_device(dev
->driver
->of_match_table
, dev
);
1125 if (!match
|| !match
->data
) {
1126 dev_err(dev
, "phy configs are not assigned!\n");
1130 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1131 tcphy
->base
= devm_ioremap_resource(dev
, res
);
1132 if (IS_ERR(tcphy
->base
))
1133 return PTR_ERR(tcphy
->base
);
1135 phy_cfgs
= match
->data
;
1136 /* find out a proper config which can be matched with dt. */
1138 while (phy_cfgs
[index
].reg
) {
1139 if (phy_cfgs
[index
].reg
== res
->start
) {
1140 tcphy
->port_cfgs
= &phy_cfgs
[index
];
1147 if (!tcphy
->port_cfgs
) {
1148 dev_err(dev
, "no phy-config can be matched with %pOFn node\n",
1153 ret
= tcphy_parse_dt(tcphy
, dev
);
1158 platform_set_drvdata(pdev
, tcphy
);
1159 mutex_init(&tcphy
->lock
);
1161 typec_phy_pre_init(tcphy
);
1163 tcphy
->extcon
= extcon_get_edev_by_phandle(dev
, 0);
1164 if (IS_ERR(tcphy
->extcon
)) {
1165 if (PTR_ERR(tcphy
->extcon
) == -ENODEV
) {
1166 tcphy
->extcon
= NULL
;
1168 if (PTR_ERR(tcphy
->extcon
) != -EPROBE_DEFER
)
1169 dev_err(dev
, "Invalid or missing extcon\n");
1170 return PTR_ERR(tcphy
->extcon
);
1174 pm_runtime_enable(dev
);
1176 for_each_available_child_of_node(np
, child_np
) {
1179 if (of_node_name_eq(child_np
, "dp-port"))
1180 phy
= devm_phy_create(dev
, child_np
,
1181 &rockchip_dp_phy_ops
);
1182 else if (of_node_name_eq(child_np
, "usb3-port"))
1183 phy
= devm_phy_create(dev
, child_np
,
1184 &rockchip_usb3_phy_ops
);
1189 dev_err(dev
, "failed to create phy: %pOFn\n",
1191 pm_runtime_disable(dev
);
1192 return PTR_ERR(phy
);
1195 phy_set_drvdata(phy
, tcphy
);
1198 phy_provider
= devm_of_phy_provider_register(dev
, of_phy_simple_xlate
);
1199 if (IS_ERR(phy_provider
)) {
1200 dev_err(dev
, "Failed to register phy provider\n");
1201 pm_runtime_disable(dev
);
1202 return PTR_ERR(phy_provider
);
1208 static int rockchip_typec_phy_remove(struct platform_device
*pdev
)
1210 pm_runtime_disable(&pdev
->dev
);
1215 static const struct of_device_id rockchip_typec_phy_dt_ids
[] = {
1217 .compatible
= "rockchip,rk3399-typec-phy",
1218 .data
= &rk3399_usb3phy_port_cfgs
1223 MODULE_DEVICE_TABLE(of
, rockchip_typec_phy_dt_ids
);
1225 static struct platform_driver rockchip_typec_phy_driver
= {
1226 .probe
= rockchip_typec_phy_probe
,
1227 .remove
= rockchip_typec_phy_remove
,
1229 .name
= "rockchip-typec-phy",
1230 .of_match_table
= rockchip_typec_phy_dt_ids
,
1234 module_platform_driver(rockchip_typec_phy_driver
);
1236 MODULE_AUTHOR("Chris Zhong <zyw@rock-chips.com>");
1237 MODULE_AUTHOR("Kever Yang <kever.yang@rock-chips.com>");
1238 MODULE_DESCRIPTION("Rockchip USB TYPE-C PHY driver");
1239 MODULE_LICENSE("GPL v2");