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Linux 5.1.15
[linux/fpc-iii.git] / drivers / pinctrl / bcm / pinctrl-bcm2835.c
blob183d1ffe6a75de6f6f205c17b88bc15db4fd23a8
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Driver for Broadcom BCM2835 GPIO unit (pinctrl + GPIO)
4 *
5 * Copyright (C) 2012 Chris Boot, Simon Arlott, Stephen Warren
6 *
7 * This driver is inspired by:
8 * pinctrl-nomadik.c, please see original file for copyright information
9 * pinctrl-tegra.c, please see original file for copyright information
10 */
11
12 #include <linux/bitmap.h>
13 #include <linux/bug.h>
14 #include <linux/delay.h>
15 #include <linux/device.h>
16 #include <linux/err.h>
17 #include <linux/gpio/driver.h>
18 #include <linux/io.h>
19 #include <linux/irq.h>
20 #include <linux/irqdesc.h>
21 #include <linux/init.h>
22 #include <linux/of_address.h>
23 #include <linux/of.h>
24 #include <linux/of_irq.h>
25 #include <linux/pinctrl/consumer.h>
26 #include <linux/pinctrl/machine.h>
27 #include <linux/pinctrl/pinconf.h>
28 #include <linux/pinctrl/pinctrl.h>
29 #include <linux/pinctrl/pinmux.h>
30 #include <linux/pinctrl/pinconf-generic.h>
31 #include <linux/platform_device.h>
32 #include <linux/seq_file.h>
33 #include <linux/slab.h>
34 #include <linux/spinlock.h>
35 #include <linux/types.h>
36 #include <dt-bindings/pinctrl/bcm2835.h>
37
38 #define MODULE_NAME "pinctrl-bcm2835"
39 #define BCM2835_NUM_GPIOS 54
40 #define BCM2835_NUM_BANKS 2
41 #define BCM2835_NUM_IRQS 3
42
43 #define BCM2835_PIN_BITMAP_SZ \
44 DIV_ROUND_UP(BCM2835_NUM_GPIOS, sizeof(unsigned long) * 8)
45
46 /* GPIO register offsets */
47 #define GPFSEL0 0x0 /* Function Select */
48 #define GPSET0 0x1c /* Pin Output Set */
49 #define GPCLR0 0x28 /* Pin Output Clear */
50 #define GPLEV0 0x34 /* Pin Level */
51 #define GPEDS0 0x40 /* Pin Event Detect Status */
52 #define GPREN0 0x4c /* Pin Rising Edge Detect Enable */
53 #define GPFEN0 0x58 /* Pin Falling Edge Detect Enable */
54 #define GPHEN0 0x64 /* Pin High Detect Enable */
55 #define GPLEN0 0x70 /* Pin Low Detect Enable */
56 #define GPAREN0 0x7c /* Pin Async Rising Edge Detect */
57 #define GPAFEN0 0x88 /* Pin Async Falling Edge Detect */
58 #define GPPUD 0x94 /* Pin Pull-up/down Enable */
59 #define GPPUDCLK0 0x98 /* Pin Pull-up/down Enable Clock */
60
61 #define FSEL_REG(p) (GPFSEL0 + (((p) / 10) * 4))
62 #define FSEL_SHIFT(p) (((p) % 10) * 3)
63 #define GPIO_REG_OFFSET(p) ((p) / 32)
64 #define GPIO_REG_SHIFT(p) ((p) % 32)
65
66 /* argument: bcm2835_pinconf_pull */
67 #define BCM2835_PINCONF_PARAM_PULL (PIN_CONFIG_END + 1)
68
69 struct bcm2835_pinctrl {
70 struct device *dev;
71 void __iomem *base;
72 int irq[BCM2835_NUM_IRQS];
73
74 /* note: locking assumes each bank will have its own unsigned long */
75 unsigned long enabled_irq_map[BCM2835_NUM_BANKS];
76 unsigned int irq_type[BCM2835_NUM_GPIOS];
77
78 struct pinctrl_dev *pctl_dev;
79 struct gpio_chip gpio_chip;
80 struct pinctrl_gpio_range gpio_range;
81
82 raw_spinlock_t irq_lock[BCM2835_NUM_BANKS];
83 };
84
85 /* pins are just named GPIO0..GPIO53 */
86 #define BCM2835_GPIO_PIN(a) PINCTRL_PIN(a, "gpio" #a)
87 static struct pinctrl_pin_desc bcm2835_gpio_pins[] = {
88 BCM2835_GPIO_PIN(0),
89 BCM2835_GPIO_PIN(1),
90 BCM2835_GPIO_PIN(2),
91 BCM2835_GPIO_PIN(3),
92 BCM2835_GPIO_PIN(4),
93 BCM2835_GPIO_PIN(5),
94 BCM2835_GPIO_PIN(6),
95 BCM2835_GPIO_PIN(7),
96 BCM2835_GPIO_PIN(8),
97 BCM2835_GPIO_PIN(9),
98 BCM2835_GPIO_PIN(10),
99 BCM2835_GPIO_PIN(11),
100 BCM2835_GPIO_PIN(12),
101 BCM2835_GPIO_PIN(13),
102 BCM2835_GPIO_PIN(14),
103 BCM2835_GPIO_PIN(15),
104 BCM2835_GPIO_PIN(16),
105 BCM2835_GPIO_PIN(17),
106 BCM2835_GPIO_PIN(18),
107 BCM2835_GPIO_PIN(19),
108 BCM2835_GPIO_PIN(20),
109 BCM2835_GPIO_PIN(21),
110 BCM2835_GPIO_PIN(22),
111 BCM2835_GPIO_PIN(23),
112 BCM2835_GPIO_PIN(24),
113 BCM2835_GPIO_PIN(25),
114 BCM2835_GPIO_PIN(26),
115 BCM2835_GPIO_PIN(27),
116 BCM2835_GPIO_PIN(28),
117 BCM2835_GPIO_PIN(29),
118 BCM2835_GPIO_PIN(30),
119 BCM2835_GPIO_PIN(31),
120 BCM2835_GPIO_PIN(32),
121 BCM2835_GPIO_PIN(33),
122 BCM2835_GPIO_PIN(34),
123 BCM2835_GPIO_PIN(35),
124 BCM2835_GPIO_PIN(36),
125 BCM2835_GPIO_PIN(37),
126 BCM2835_GPIO_PIN(38),
127 BCM2835_GPIO_PIN(39),
128 BCM2835_GPIO_PIN(40),
129 BCM2835_GPIO_PIN(41),
130 BCM2835_GPIO_PIN(42),
131 BCM2835_GPIO_PIN(43),
132 BCM2835_GPIO_PIN(44),
133 BCM2835_GPIO_PIN(45),
134 BCM2835_GPIO_PIN(46),
135 BCM2835_GPIO_PIN(47),
136 BCM2835_GPIO_PIN(48),
137 BCM2835_GPIO_PIN(49),
138 BCM2835_GPIO_PIN(50),
139 BCM2835_GPIO_PIN(51),
140 BCM2835_GPIO_PIN(52),
141 BCM2835_GPIO_PIN(53),
142 };
143
144 /* one pin per group */
145 static const char * const bcm2835_gpio_groups[] = {
146 "gpio0",
147 "gpio1",
148 "gpio2",
149 "gpio3",
150 "gpio4",
151 "gpio5",
152 "gpio6",
153 "gpio7",
154 "gpio8",
155 "gpio9",
156 "gpio10",
157 "gpio11",
158 "gpio12",
159 "gpio13",
160 "gpio14",
161 "gpio15",
162 "gpio16",
163 "gpio17",
164 "gpio18",
165 "gpio19",
166 "gpio20",
167 "gpio21",
168 "gpio22",
169 "gpio23",
170 "gpio24",
171 "gpio25",
172 "gpio26",
173 "gpio27",
174 "gpio28",
175 "gpio29",
176 "gpio30",
177 "gpio31",
178 "gpio32",
179 "gpio33",
180 "gpio34",
181 "gpio35",
182 "gpio36",
183 "gpio37",
184 "gpio38",
185 "gpio39",
186 "gpio40",
187 "gpio41",
188 "gpio42",
189 "gpio43",
190 "gpio44",
191 "gpio45",
192 "gpio46",
193 "gpio47",
194 "gpio48",
195 "gpio49",
196 "gpio50",
197 "gpio51",
198 "gpio52",
199 "gpio53",
200 };
201
202 enum bcm2835_fsel {
203 BCM2835_FSEL_COUNT = 8,
204 BCM2835_FSEL_MASK = 0x7,
205 };
206
207 static const char * const bcm2835_functions[BCM2835_FSEL_COUNT] = {
208 [BCM2835_FSEL_GPIO_IN] = "gpio_in",
209 [BCM2835_FSEL_GPIO_OUT] = "gpio_out",
210 [BCM2835_FSEL_ALT0] = "alt0",
211 [BCM2835_FSEL_ALT1] = "alt1",
212 [BCM2835_FSEL_ALT2] = "alt2",
213 [BCM2835_FSEL_ALT3] = "alt3",
214 [BCM2835_FSEL_ALT4] = "alt4",
215 [BCM2835_FSEL_ALT5] = "alt5",
216 };
217
218 static const char * const irq_type_names[] = {
219 [IRQ_TYPE_NONE] = "none",
220 [IRQ_TYPE_EDGE_RISING] = "edge-rising",
221 [IRQ_TYPE_EDGE_FALLING] = "edge-falling",
222 [IRQ_TYPE_EDGE_BOTH] = "edge-both",
223 [IRQ_TYPE_LEVEL_HIGH] = "level-high",
224 [IRQ_TYPE_LEVEL_LOW] = "level-low",
225 };
226
227 static inline u32 bcm2835_gpio_rd(struct bcm2835_pinctrl *pc, unsigned reg)
228 {
229 return readl(pc->base + reg);
230 }
231
232 static inline void bcm2835_gpio_wr(struct bcm2835_pinctrl *pc, unsigned reg,
233 u32 val)
234 {
235 writel(val, pc->base + reg);
236 }
237
238 static inline int bcm2835_gpio_get_bit(struct bcm2835_pinctrl *pc, unsigned reg,
239 unsigned bit)
240 {
241 reg += GPIO_REG_OFFSET(bit) * 4;
242 return (bcm2835_gpio_rd(pc, reg) >> GPIO_REG_SHIFT(bit)) & 1;
243 }
244
245 /* note NOT a read/modify/write cycle */
246 static inline void bcm2835_gpio_set_bit(struct bcm2835_pinctrl *pc,
247 unsigned reg, unsigned bit)
248 {
249 reg += GPIO_REG_OFFSET(bit) * 4;
250 bcm2835_gpio_wr(pc, reg, BIT(GPIO_REG_SHIFT(bit)));
251 }
252
253 static inline enum bcm2835_fsel bcm2835_pinctrl_fsel_get(
254 struct bcm2835_pinctrl *pc, unsigned pin)
255 {
256 u32 val = bcm2835_gpio_rd(pc, FSEL_REG(pin));
257 enum bcm2835_fsel status = (val >> FSEL_SHIFT(pin)) & BCM2835_FSEL_MASK;
258
259 dev_dbg(pc->dev, "get %08x (%u => %s)\n", val, pin,
260 bcm2835_functions[status]);
261
262 return status;
263 }
264
265 static inline void bcm2835_pinctrl_fsel_set(
266 struct bcm2835_pinctrl *pc, unsigned pin,
267 enum bcm2835_fsel fsel)
268 {
269 u32 val = bcm2835_gpio_rd(pc, FSEL_REG(pin));
270 enum bcm2835_fsel cur = (val >> FSEL_SHIFT(pin)) & BCM2835_FSEL_MASK;
271
272 dev_dbg(pc->dev, "read %08x (%u => %s)\n", val, pin,
273 bcm2835_functions[cur]);
274
275 if (cur == fsel)
276 return;
277
278 if (cur != BCM2835_FSEL_GPIO_IN && fsel != BCM2835_FSEL_GPIO_IN) {
279 /* always transition through GPIO_IN */
280 val &= ~(BCM2835_FSEL_MASK << FSEL_SHIFT(pin));
281 val |= BCM2835_FSEL_GPIO_IN << FSEL_SHIFT(pin);
282
283 dev_dbg(pc->dev, "trans %08x (%u <= %s)\n", val, pin,
284 bcm2835_functions[BCM2835_FSEL_GPIO_IN]);
285 bcm2835_gpio_wr(pc, FSEL_REG(pin), val);
286 }
287
288 val &= ~(BCM2835_FSEL_MASK << FSEL_SHIFT(pin));
289 val |= fsel << FSEL_SHIFT(pin);
290
291 dev_dbg(pc->dev, "write %08x (%u <= %s)\n", val, pin,
292 bcm2835_functions[fsel]);
293 bcm2835_gpio_wr(pc, FSEL_REG(pin), val);
294 }
295
296 static int bcm2835_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
297 {
298 return pinctrl_gpio_direction_input(chip->base + offset);
299 }
300
301 static int bcm2835_gpio_get(struct gpio_chip *chip, unsigned offset)
302 {
303 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
304
305 return bcm2835_gpio_get_bit(pc, GPLEV0, offset);
306 }
307
308 static int bcm2835_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
309 {
310 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
311 enum bcm2835_fsel fsel = bcm2835_pinctrl_fsel_get(pc, offset);
312
313 /* Alternative function doesn't clearly provide a direction */
314 if (fsel > BCM2835_FSEL_GPIO_OUT)
315 return -EINVAL;
316
317 return (fsel == BCM2835_FSEL_GPIO_IN);
318 }
319
320 static void bcm2835_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
321 {
322 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
323
324 bcm2835_gpio_set_bit(pc, value ? GPSET0 : GPCLR0, offset);
325 }
326
327 static int bcm2835_gpio_direction_output(struct gpio_chip *chip,
328 unsigned offset, int value)
329 {
330 bcm2835_gpio_set(chip, offset, value);
331 return pinctrl_gpio_direction_output(chip->base + offset);
332 }
333
334 static const struct gpio_chip bcm2835_gpio_chip = {
335 .label = MODULE_NAME,
336 .owner = THIS_MODULE,
337 .request = gpiochip_generic_request,
338 .free = gpiochip_generic_free,
339 .direction_input = bcm2835_gpio_direction_input,
340 .direction_output = bcm2835_gpio_direction_output,
341 .get_direction = bcm2835_gpio_get_direction,
342 .get = bcm2835_gpio_get,
343 .set = bcm2835_gpio_set,
344 .set_config = gpiochip_generic_config,
345 .base = -1,
346 .ngpio = BCM2835_NUM_GPIOS,
347 .can_sleep = false,
348 };
349
350 static void bcm2835_gpio_irq_handle_bank(struct bcm2835_pinctrl *pc,
351 unsigned int bank, u32 mask)
352 {
353 unsigned long events;
354 unsigned offset;
355 unsigned gpio;
356
357 events = bcm2835_gpio_rd(pc, GPEDS0 + bank * 4);
358 events &= mask;
359 events &= pc->enabled_irq_map[bank];
360 for_each_set_bit(offset, &events, 32) {
361 gpio = (32 * bank) + offset;
362 generic_handle_irq(irq_linear_revmap(pc->gpio_chip.irq.domain,
363 gpio));
364 }
365 }
366
367 static void bcm2835_gpio_irq_handler(struct irq_desc *desc)
368 {
369 struct gpio_chip *chip = irq_desc_get_handler_data(desc);
370 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
371 struct irq_chip *host_chip = irq_desc_get_chip(desc);
372 int irq = irq_desc_get_irq(desc);
373 int group;
374 int i;
375
376 for (i = 0; i < ARRAY_SIZE(pc->irq); i++) {
377 if (pc->irq[i] == irq) {
378 group = i;
379 break;
380 }
381 }
382 /* This should not happen, every IRQ has a bank */
383 if (i == ARRAY_SIZE(pc->irq))
384 BUG();
385
386 chained_irq_enter(host_chip, desc);
387
388 switch (group) {
389 case 0: /* IRQ0 covers GPIOs 0-27 */
390 bcm2835_gpio_irq_handle_bank(pc, 0, 0x0fffffff);
391 break;
392 case 1: /* IRQ1 covers GPIOs 28-45 */
393 bcm2835_gpio_irq_handle_bank(pc, 0, 0xf0000000);
394 bcm2835_gpio_irq_handle_bank(pc, 1, 0x00003fff);
395 break;
396 case 2: /* IRQ2 covers GPIOs 46-53 */
397 bcm2835_gpio_irq_handle_bank(pc, 1, 0x003fc000);
398 break;
399 }
400
401 chained_irq_exit(host_chip, desc);
402 }
403
404 static inline void __bcm2835_gpio_irq_config(struct bcm2835_pinctrl *pc,
405 unsigned reg, unsigned offset, bool enable)
406 {
407 u32 value;
408 reg += GPIO_REG_OFFSET(offset) * 4;
409 value = bcm2835_gpio_rd(pc, reg);
410 if (enable)
411 value |= BIT(GPIO_REG_SHIFT(offset));
412 else
413 value &= ~(BIT(GPIO_REG_SHIFT(offset)));
414 bcm2835_gpio_wr(pc, reg, value);
415 }
416
417 /* fast path for IRQ handler */
418 static void bcm2835_gpio_irq_config(struct bcm2835_pinctrl *pc,
419 unsigned offset, bool enable)
420 {
421 switch (pc->irq_type[offset]) {
422 case IRQ_TYPE_EDGE_RISING:
423 __bcm2835_gpio_irq_config(pc, GPREN0, offset, enable);
424 break;
425
426 case IRQ_TYPE_EDGE_FALLING:
427 __bcm2835_gpio_irq_config(pc, GPFEN0, offset, enable);
428 break;
429
430 case IRQ_TYPE_EDGE_BOTH:
431 __bcm2835_gpio_irq_config(pc, GPREN0, offset, enable);
432 __bcm2835_gpio_irq_config(pc, GPFEN0, offset, enable);
433 break;
434
435 case IRQ_TYPE_LEVEL_HIGH:
436 __bcm2835_gpio_irq_config(pc, GPHEN0, offset, enable);
437 break;
438
439 case IRQ_TYPE_LEVEL_LOW:
440 __bcm2835_gpio_irq_config(pc, GPLEN0, offset, enable);
441 break;
442 }
443 }
444
445 static void bcm2835_gpio_irq_enable(struct irq_data *data)
446 {
447 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
448 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
449 unsigned gpio = irqd_to_hwirq(data);
450 unsigned offset = GPIO_REG_SHIFT(gpio);
451 unsigned bank = GPIO_REG_OFFSET(gpio);
452 unsigned long flags;
453
454 raw_spin_lock_irqsave(&pc->irq_lock[bank], flags);
455 set_bit(offset, &pc->enabled_irq_map[bank]);
456 bcm2835_gpio_irq_config(pc, gpio, true);
457 raw_spin_unlock_irqrestore(&pc->irq_lock[bank], flags);
458 }
459
460 static void bcm2835_gpio_irq_disable(struct irq_data *data)
461 {
462 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
463 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
464 unsigned gpio = irqd_to_hwirq(data);
465 unsigned offset = GPIO_REG_SHIFT(gpio);
466 unsigned bank = GPIO_REG_OFFSET(gpio);
467 unsigned long flags;
468
469 raw_spin_lock_irqsave(&pc->irq_lock[bank], flags);
470 bcm2835_gpio_irq_config(pc, gpio, false);
471 /* Clear events that were latched prior to clearing event sources */
472 bcm2835_gpio_set_bit(pc, GPEDS0, gpio);
473 clear_bit(offset, &pc->enabled_irq_map[bank]);
474 raw_spin_unlock_irqrestore(&pc->irq_lock[bank], flags);
475 }
476
477 static int __bcm2835_gpio_irq_set_type_disabled(struct bcm2835_pinctrl *pc,
478 unsigned offset, unsigned int type)
479 {
480 switch (type) {
481 case IRQ_TYPE_NONE:
482 case IRQ_TYPE_EDGE_RISING:
483 case IRQ_TYPE_EDGE_FALLING:
484 case IRQ_TYPE_EDGE_BOTH:
485 case IRQ_TYPE_LEVEL_HIGH:
486 case IRQ_TYPE_LEVEL_LOW:
487 pc->irq_type[offset] = type;
488 break;
489
490 default:
491 return -EINVAL;
492 }
493 return 0;
494 }
495
496 /* slower path for reconfiguring IRQ type */
497 static int __bcm2835_gpio_irq_set_type_enabled(struct bcm2835_pinctrl *pc,
498 unsigned offset, unsigned int type)
499 {
500 switch (type) {
501 case IRQ_TYPE_NONE:
502 if (pc->irq_type[offset] != type) {
503 bcm2835_gpio_irq_config(pc, offset, false);
504 pc->irq_type[offset] = type;
505 }
506 break;
507
508 case IRQ_TYPE_EDGE_RISING:
509 if (pc->irq_type[offset] == IRQ_TYPE_EDGE_BOTH) {
510 /* RISING already enabled, disable FALLING */
511 pc->irq_type[offset] = IRQ_TYPE_EDGE_FALLING;
512 bcm2835_gpio_irq_config(pc, offset, false);
513 pc->irq_type[offset] = type;
514 } else if (pc->irq_type[offset] != type) {
515 bcm2835_gpio_irq_config(pc, offset, false);
516 pc->irq_type[offset] = type;
517 bcm2835_gpio_irq_config(pc, offset, true);
518 }
519 break;
520
521 case IRQ_TYPE_EDGE_FALLING:
522 if (pc->irq_type[offset] == IRQ_TYPE_EDGE_BOTH) {
523 /* FALLING already enabled, disable RISING */
524 pc->irq_type[offset] = IRQ_TYPE_EDGE_RISING;
525 bcm2835_gpio_irq_config(pc, offset, false);
526 pc->irq_type[offset] = type;
527 } else if (pc->irq_type[offset] != type) {
528 bcm2835_gpio_irq_config(pc, offset, false);
529 pc->irq_type[offset] = type;
530 bcm2835_gpio_irq_config(pc, offset, true);
531 }
532 break;
533
534 case IRQ_TYPE_EDGE_BOTH:
535 if (pc->irq_type[offset] == IRQ_TYPE_EDGE_RISING) {
536 /* RISING already enabled, enable FALLING too */
537 pc->irq_type[offset] = IRQ_TYPE_EDGE_FALLING;
538 bcm2835_gpio_irq_config(pc, offset, true);
539 pc->irq_type[offset] = type;
540 } else if (pc->irq_type[offset] == IRQ_TYPE_EDGE_FALLING) {
541 /* FALLING already enabled, enable RISING too */
542 pc->irq_type[offset] = IRQ_TYPE_EDGE_RISING;
543 bcm2835_gpio_irq_config(pc, offset, true);
544 pc->irq_type[offset] = type;
545 } else if (pc->irq_type[offset] != type) {
546 bcm2835_gpio_irq_config(pc, offset, false);
547 pc->irq_type[offset] = type;
548 bcm2835_gpio_irq_config(pc, offset, true);
549 }
550 break;
551
552 case IRQ_TYPE_LEVEL_HIGH:
553 case IRQ_TYPE_LEVEL_LOW:
554 if (pc->irq_type[offset] != type) {
555 bcm2835_gpio_irq_config(pc, offset, false);
556 pc->irq_type[offset] = type;
557 bcm2835_gpio_irq_config(pc, offset, true);
558 }
559 break;
560
561 default:
562 return -EINVAL;
563 }
564 return 0;
565 }
566
567 static int bcm2835_gpio_irq_set_type(struct irq_data *data, unsigned int type)
568 {
569 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
570 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
571 unsigned gpio = irqd_to_hwirq(data);
572 unsigned offset = GPIO_REG_SHIFT(gpio);
573 unsigned bank = GPIO_REG_OFFSET(gpio);
574 unsigned long flags;
575 int ret;
576
577 raw_spin_lock_irqsave(&pc->irq_lock[bank], flags);
578
579 if (test_bit(offset, &pc->enabled_irq_map[bank]))
580 ret = __bcm2835_gpio_irq_set_type_enabled(pc, gpio, type);
581 else
582 ret = __bcm2835_gpio_irq_set_type_disabled(pc, gpio, type);
583
584 if (type & IRQ_TYPE_EDGE_BOTH)
585 irq_set_handler_locked(data, handle_edge_irq);
586 else
587 irq_set_handler_locked(data, handle_level_irq);
588
589 raw_spin_unlock_irqrestore(&pc->irq_lock[bank], flags);
590
591 return ret;
592 }
593
594 static void bcm2835_gpio_irq_ack(struct irq_data *data)
595 {
596 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
597 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
598 unsigned gpio = irqd_to_hwirq(data);
599
600 bcm2835_gpio_set_bit(pc, GPEDS0, gpio);
601 }
602
603 static struct irq_chip bcm2835_gpio_irq_chip = {
604 .name = MODULE_NAME,
605 .irq_enable = bcm2835_gpio_irq_enable,
606 .irq_disable = bcm2835_gpio_irq_disable,
607 .irq_set_type = bcm2835_gpio_irq_set_type,
608 .irq_ack = bcm2835_gpio_irq_ack,
609 .irq_mask = bcm2835_gpio_irq_disable,
610 .irq_unmask = bcm2835_gpio_irq_enable,
611 };
612
613 static int bcm2835_pctl_get_groups_count(struct pinctrl_dev *pctldev)
614 {
615 return ARRAY_SIZE(bcm2835_gpio_groups);
616 }
617
618 static const char *bcm2835_pctl_get_group_name(struct pinctrl_dev *pctldev,
619 unsigned selector)
620 {
621 return bcm2835_gpio_groups[selector];
622 }
623
624 static int bcm2835_pctl_get_group_pins(struct pinctrl_dev *pctldev,
625 unsigned selector,
626 const unsigned **pins,
627 unsigned *num_pins)
628 {
629 *pins = &bcm2835_gpio_pins[selector].number;
630 *num_pins = 1;
631
632 return 0;
633 }
634
635 static void bcm2835_pctl_pin_dbg_show(struct pinctrl_dev *pctldev,
636 struct seq_file *s,
637 unsigned offset)
638 {
639 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
640 struct gpio_chip *chip = &pc->gpio_chip;
641 enum bcm2835_fsel fsel = bcm2835_pinctrl_fsel_get(pc, offset);
642 const char *fname = bcm2835_functions[fsel];
643 int value = bcm2835_gpio_get_bit(pc, GPLEV0, offset);
644 int irq = irq_find_mapping(chip->irq.domain, offset);
645
646 seq_printf(s, "function %s in %s; irq %d (%s)",
647 fname, value ? "hi" : "lo",
648 irq, irq_type_names[pc->irq_type[offset]]);
649 }
650
651 static void bcm2835_pctl_dt_free_map(struct pinctrl_dev *pctldev,
652 struct pinctrl_map *maps, unsigned num_maps)
653 {
654 int i;
655
656 for (i = 0; i < num_maps; i++)
657 if (maps[i].type == PIN_MAP_TYPE_CONFIGS_PIN)
658 kfree(maps[i].data.configs.configs);
659
660 kfree(maps);
661 }
662
663 static int bcm2835_pctl_dt_node_to_map_func(struct bcm2835_pinctrl *pc,
664 struct device_node *np, u32 pin, u32 fnum,
665 struct pinctrl_map **maps)
666 {
667 struct pinctrl_map *map = *maps;
668
669 if (fnum >= ARRAY_SIZE(bcm2835_functions)) {
670 dev_err(pc->dev, "%pOF: invalid brcm,function %d\n", np, fnum);
671 return -EINVAL;
672 }
673
674 map->type = PIN_MAP_TYPE_MUX_GROUP;
675 map->data.mux.group = bcm2835_gpio_groups[pin];
676 map->data.mux.function = bcm2835_functions[fnum];
677 (*maps)++;
678
679 return 0;
680 }
681
682 static int bcm2835_pctl_dt_node_to_map_pull(struct bcm2835_pinctrl *pc,
683 struct device_node *np, u32 pin, u32 pull,
684 struct pinctrl_map **maps)
685 {
686 struct pinctrl_map *map = *maps;
687 unsigned long *configs;
688
689 if (pull > 2) {
690 dev_err(pc->dev, "%pOF: invalid brcm,pull %d\n", np, pull);
691 return -EINVAL;
692 }
693
694 configs = kzalloc(sizeof(*configs), GFP_KERNEL);
695 if (!configs)
696 return -ENOMEM;
697 configs[0] = pinconf_to_config_packed(BCM2835_PINCONF_PARAM_PULL, pull);
698
699 map->type = PIN_MAP_TYPE_CONFIGS_PIN;
700 map->data.configs.group_or_pin = bcm2835_gpio_pins[pin].name;
701 map->data.configs.configs = configs;
702 map->data.configs.num_configs = 1;
703 (*maps)++;
704
705 return 0;
706 }
707
708 static int bcm2835_pctl_dt_node_to_map(struct pinctrl_dev *pctldev,
709 struct device_node *np,
710 struct pinctrl_map **map, unsigned int *num_maps)
711 {
712 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
713 struct property *pins, *funcs, *pulls;
714 int num_pins, num_funcs, num_pulls, maps_per_pin;
715 struct pinctrl_map *maps, *cur_map;
716 int i, err;
717 u32 pin, func, pull;
718
719 /* Check for generic binding in this node */
720 err = pinconf_generic_dt_node_to_map_all(pctldev, np, map, num_maps);
721 if (err || *num_maps)
722 return err;
723
724 /* Generic binding did not find anything continue with legacy parse */
725 pins = of_find_property(np, "brcm,pins", NULL);
726 if (!pins) {
727 dev_err(pc->dev, "%pOF: missing brcm,pins property\n", np);
728 return -EINVAL;
729 }
730
731 funcs = of_find_property(np, "brcm,function", NULL);
732 pulls = of_find_property(np, "brcm,pull", NULL);
733
734 if (!funcs && !pulls) {
735 dev_err(pc->dev,
736 "%pOF: neither brcm,function nor brcm,pull specified\n",
737 np);
738 return -EINVAL;
739 }
740
741 num_pins = pins->length / 4;
742 num_funcs = funcs ? (funcs->length / 4) : 0;
743 num_pulls = pulls ? (pulls->length / 4) : 0;
744
745 if (num_funcs > 1 && num_funcs != num_pins) {
746 dev_err(pc->dev,
747 "%pOF: brcm,function must have 1 or %d entries\n",
748 np, num_pins);
749 return -EINVAL;
750 }
751
752 if (num_pulls > 1 && num_pulls != num_pins) {
753 dev_err(pc->dev,
754 "%pOF: brcm,pull must have 1 or %d entries\n",
755 np, num_pins);
756 return -EINVAL;
757 }
758
759 maps_per_pin = 0;
760 if (num_funcs)
761 maps_per_pin++;
762 if (num_pulls)
763 maps_per_pin++;
764 cur_map = maps = kcalloc(num_pins * maps_per_pin, sizeof(*maps),
765 GFP_KERNEL);
766 if (!maps)
767 return -ENOMEM;
768
769 for (i = 0; i < num_pins; i++) {
770 err = of_property_read_u32_index(np, "brcm,pins", i, &pin);
771 if (err)
772 goto out;
773 if (pin >= ARRAY_SIZE(bcm2835_gpio_pins)) {
774 dev_err(pc->dev, "%pOF: invalid brcm,pins value %d\n",
775 np, pin);
776 err = -EINVAL;
777 goto out;
778 }
779
780 if (num_funcs) {
781 err = of_property_read_u32_index(np, "brcm,function",
782 (num_funcs > 1) ? i : 0, &func);
783 if (err)
784 goto out;
785 err = bcm2835_pctl_dt_node_to_map_func(pc, np, pin,
786 func, &cur_map);
787 if (err)
788 goto out;
789 }
790 if (num_pulls) {
791 err = of_property_read_u32_index(np, "brcm,pull",
792 (num_pulls > 1) ? i : 0, &pull);
793 if (err)
794 goto out;
795 err = bcm2835_pctl_dt_node_to_map_pull(pc, np, pin,
796 pull, &cur_map);
797 if (err)
798 goto out;
799 }
800 }
801
802 *map = maps;
803 *num_maps = num_pins * maps_per_pin;
804
805 return 0;
806
807 out:
808 bcm2835_pctl_dt_free_map(pctldev, maps, num_pins * maps_per_pin);
809 return err;
810 }
811
812 static const struct pinctrl_ops bcm2835_pctl_ops = {
813 .get_groups_count = bcm2835_pctl_get_groups_count,
814 .get_group_name = bcm2835_pctl_get_group_name,
815 .get_group_pins = bcm2835_pctl_get_group_pins,
816 .pin_dbg_show = bcm2835_pctl_pin_dbg_show,
817 .dt_node_to_map = bcm2835_pctl_dt_node_to_map,
818 .dt_free_map = bcm2835_pctl_dt_free_map,
819 };
820
821 static int bcm2835_pmx_free(struct pinctrl_dev *pctldev,
822 unsigned offset)
823 {
824 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
825
826 /* disable by setting to GPIO_IN */
827 bcm2835_pinctrl_fsel_set(pc, offset, BCM2835_FSEL_GPIO_IN);
828 return 0;
829 }
830
831 static int bcm2835_pmx_get_functions_count(struct pinctrl_dev *pctldev)
832 {
833 return BCM2835_FSEL_COUNT;
834 }
835
836 static const char *bcm2835_pmx_get_function_name(struct pinctrl_dev *pctldev,
837 unsigned selector)
838 {
839 return bcm2835_functions[selector];
840 }
841
842 static int bcm2835_pmx_get_function_groups(struct pinctrl_dev *pctldev,
843 unsigned selector,
844 const char * const **groups,
845 unsigned * const num_groups)
846 {
847 /* every pin can do every function */
848 *groups = bcm2835_gpio_groups;
849 *num_groups = ARRAY_SIZE(bcm2835_gpio_groups);
850
851 return 0;
852 }
853
854 static int bcm2835_pmx_set(struct pinctrl_dev *pctldev,
855 unsigned func_selector,
856 unsigned group_selector)
857 {
858 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
859
860 bcm2835_pinctrl_fsel_set(pc, group_selector, func_selector);
861
862 return 0;
863 }
864
865 static void bcm2835_pmx_gpio_disable_free(struct pinctrl_dev *pctldev,
866 struct pinctrl_gpio_range *range,
867 unsigned offset)
868 {
869 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
870
871 /* disable by setting to GPIO_IN */
872 bcm2835_pinctrl_fsel_set(pc, offset, BCM2835_FSEL_GPIO_IN);
873 }
874
875 static int bcm2835_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
876 struct pinctrl_gpio_range *range,
877 unsigned offset,
878 bool input)
879 {
880 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
881 enum bcm2835_fsel fsel = input ?
882 BCM2835_FSEL_GPIO_IN : BCM2835_FSEL_GPIO_OUT;
883
884 bcm2835_pinctrl_fsel_set(pc, offset, fsel);
885
886 return 0;
887 }
888
889 static const struct pinmux_ops bcm2835_pmx_ops = {
890 .free = bcm2835_pmx_free,
891 .get_functions_count = bcm2835_pmx_get_functions_count,
892 .get_function_name = bcm2835_pmx_get_function_name,
893 .get_function_groups = bcm2835_pmx_get_function_groups,
894 .set_mux = bcm2835_pmx_set,
895 .gpio_disable_free = bcm2835_pmx_gpio_disable_free,
896 .gpio_set_direction = bcm2835_pmx_gpio_set_direction,
897 };
898
899 static int bcm2835_pinconf_get(struct pinctrl_dev *pctldev,
900 unsigned pin, unsigned long *config)
901 {
902 /* No way to read back config in HW */
903 return -ENOTSUPP;
904 }
905
906 static void bcm2835_pull_config_set(struct bcm2835_pinctrl *pc,
907 unsigned int pin, unsigned int arg)
908 {
909 u32 off, bit;
910
911 off = GPIO_REG_OFFSET(pin);
912 bit = GPIO_REG_SHIFT(pin);
913
914 bcm2835_gpio_wr(pc, GPPUD, arg & 3);
915 /*
916 * BCM2835 datasheet say to wait 150 cycles, but not of what.
917 * But the VideoCore firmware delay for this operation
918 * based nearly on the same amount of VPU cycles and this clock
919 * runs at 250 MHz.
920 */
921 udelay(1);
922 bcm2835_gpio_wr(pc, GPPUDCLK0 + (off * 4), BIT(bit));
923 udelay(1);
924 bcm2835_gpio_wr(pc, GPPUDCLK0 + (off * 4), 0);
925 }
926
927 static int bcm2835_pinconf_set(struct pinctrl_dev *pctldev,
928 unsigned int pin, unsigned long *configs,
929 unsigned int num_configs)
930 {
931 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
932 u32 param, arg;
933 int i;
934
935 for (i = 0; i < num_configs; i++) {
936 param = pinconf_to_config_param(configs[i]);
937 arg = pinconf_to_config_argument(configs[i]);
938
939 switch (param) {
940 /* Set legacy brcm,pull */
941 case BCM2835_PINCONF_PARAM_PULL:
942 bcm2835_pull_config_set(pc, pin, arg);
943 break;
944
945 /* Set pull generic bindings */
946 case PIN_CONFIG_BIAS_DISABLE:
947 bcm2835_pull_config_set(pc, pin, BCM2835_PUD_OFF);
948 break;
949
950 case PIN_CONFIG_BIAS_PULL_DOWN:
951 bcm2835_pull_config_set(pc, pin, BCM2835_PUD_DOWN);
952 break;
953
954 case PIN_CONFIG_BIAS_PULL_UP:
955 bcm2835_pull_config_set(pc, pin, BCM2835_PUD_UP);
956 break;
957
958 /* Set output-high or output-low */
959 case PIN_CONFIG_OUTPUT:
960 bcm2835_gpio_set_bit(pc, arg ? GPSET0 : GPCLR0, pin);
961 break;
962
963 default:
964 return -ENOTSUPP;
965
966 } /* switch param type */
967 } /* for each config */
968
969 return 0;
970 }
971
972 static const struct pinconf_ops bcm2835_pinconf_ops = {
973 .is_generic = true,
974 .pin_config_get = bcm2835_pinconf_get,
975 .pin_config_set = bcm2835_pinconf_set,
976 };
977
978 static struct pinctrl_desc bcm2835_pinctrl_desc = {
979 .name = MODULE_NAME,
980 .pins = bcm2835_gpio_pins,
981 .npins = ARRAY_SIZE(bcm2835_gpio_pins),
982 .pctlops = &bcm2835_pctl_ops,
983 .pmxops = &bcm2835_pmx_ops,
984 .confops = &bcm2835_pinconf_ops,
985 .owner = THIS_MODULE,
986 };
987
988 static struct pinctrl_gpio_range bcm2835_pinctrl_gpio_range = {
989 .name = MODULE_NAME,
990 .npins = BCM2835_NUM_GPIOS,
991 };
992
993 static int bcm2835_pinctrl_probe(struct platform_device *pdev)
994 {
995 struct device *dev = &pdev->dev;
996 struct device_node *np = dev->of_node;
997 struct bcm2835_pinctrl *pc;
998 struct resource iomem;
999 int err, i;
1000 BUILD_BUG_ON(ARRAY_SIZE(bcm2835_gpio_pins) != BCM2835_NUM_GPIOS);
1001 BUILD_BUG_ON(ARRAY_SIZE(bcm2835_gpio_groups) != BCM2835_NUM_GPIOS);
1002
1003 pc = devm_kzalloc(dev, sizeof(*pc), GFP_KERNEL);
1004 if (!pc)
1005 return -ENOMEM;
1006
1007 platform_set_drvdata(pdev, pc);
1008 pc->dev = dev;
1009
1010 err = of_address_to_resource(np, 0, &iomem);
1011 if (err) {
1012 dev_err(dev, "could not get IO memory\n");
1013 return err;
1014 }
1015
1016 pc->base = devm_ioremap_resource(dev, &iomem);
1017 if (IS_ERR(pc->base))
1018 return PTR_ERR(pc->base);
1019
1020 pc->gpio_chip = bcm2835_gpio_chip;
1021 pc->gpio_chip.parent = dev;
1022 pc->gpio_chip.of_node = np;
1023
1024 for (i = 0; i < BCM2835_NUM_BANKS; i++) {
1025 unsigned long events;
1026 unsigned offset;
1027
1028 /* clear event detection flags */
1029 bcm2835_gpio_wr(pc, GPREN0 + i * 4, 0);
1030 bcm2835_gpio_wr(pc, GPFEN0 + i * 4, 0);
1031 bcm2835_gpio_wr(pc, GPHEN0 + i * 4, 0);
1032 bcm2835_gpio_wr(pc, GPLEN0 + i * 4, 0);
1033 bcm2835_gpio_wr(pc, GPAREN0 + i * 4, 0);
1034 bcm2835_gpio_wr(pc, GPAFEN0 + i * 4, 0);
1035
1036 /* clear all the events */
1037 events = bcm2835_gpio_rd(pc, GPEDS0 + i * 4);
1038 for_each_set_bit(offset, &events, 32)
1039 bcm2835_gpio_wr(pc, GPEDS0 + i * 4, BIT(offset));
1040
1041 raw_spin_lock_init(&pc->irq_lock[i]);
1042 }
1043
1044 err = gpiochip_add_data(&pc->gpio_chip, pc);
1045 if (err) {
1046 dev_err(dev, "could not add GPIO chip\n");
1047 return err;
1048 }
1049
1050 err = gpiochip_irqchip_add(&pc->gpio_chip, &bcm2835_gpio_irq_chip,
1051 0, handle_level_irq, IRQ_TYPE_NONE);
1052 if (err) {
1053 dev_info(dev, "could not add irqchip\n");
1054 return err;
1055 }
1056
1057 for (i = 0; i < BCM2835_NUM_IRQS; i++) {
1058 pc->irq[i] = irq_of_parse_and_map(np, i);
1059
1060 if (pc->irq[i] == 0)
1061 continue;
1062
1063 /*
1064 * Use the same handler for all groups: this is necessary
1065 * since we use one gpiochip to cover all lines - the
1066 * irq handler then needs to figure out which group and
1067 * bank that was firing the IRQ and look up the per-group
1068 * and bank data.
1069 */
1070 gpiochip_set_chained_irqchip(&pc->gpio_chip,
1071 &bcm2835_gpio_irq_chip,
1072 pc->irq[i],
1073 bcm2835_gpio_irq_handler);
1074 }
1075
1076 pc->pctl_dev = devm_pinctrl_register(dev, &bcm2835_pinctrl_desc, pc);
1077 if (IS_ERR(pc->pctl_dev)) {
1078 gpiochip_remove(&pc->gpio_chip);
1079 return PTR_ERR(pc->pctl_dev);
1080 }
1081
1082 pc->gpio_range = bcm2835_pinctrl_gpio_range;
1083 pc->gpio_range.base = pc->gpio_chip.base;
1084 pc->gpio_range.gc = &pc->gpio_chip;
1085 pinctrl_add_gpio_range(pc->pctl_dev, &pc->gpio_range);
1086
1087 return 0;
1088 }
1089
1090 static const struct of_device_id bcm2835_pinctrl_match[] = {
1091 { .compatible = "brcm,bcm2835-gpio" },
1092 {}
1093 };
1094
1095 static struct platform_driver bcm2835_pinctrl_driver = {
1096 .probe = bcm2835_pinctrl_probe,
1097 .driver = {
1098 .name = MODULE_NAME,
1099 .of_match_table = bcm2835_pinctrl_match,
1100 .suppress_bind_attrs = true,
1101 },
1102 };
1103 builtin_platform_driver(bcm2835_pinctrl_driver);
Linux with added FPC-III support