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Linux 5.1.15
[linux/fpc-iii.git] / drivers / pinctrl / intel / pinctrl-merrifield.c
blob4b65e1296b8af7542437ec5d9b48bb840a2528b2
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Intel Merrifield SoC pinctrl driver
4 *
5 * Copyright (C) 2016, Intel Corporation
6 * Author: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
7 */
8
9 #include <linux/bits.h>
10 #include <linux/err.h>
11 #include <linux/io.h>
12 #include <linux/module.h>
13 #include <linux/mod_devicetable.h>
14 #include <linux/platform_device.h>
15 #include <linux/pinctrl/pinconf.h>
16 #include <linux/pinctrl/pinconf-generic.h>
17 #include <linux/pinctrl/pinctrl.h>
18 #include <linux/pinctrl/pinmux.h>
19
20 #include "pinctrl-intel.h"
21
22 #define MRFLD_FAMILY_NR 64
23 #define MRFLD_FAMILY_LEN 0x400
24
25 #define SLEW_OFFSET 0x000
26 #define BUFCFG_OFFSET 0x100
27 #define MISC_OFFSET 0x300
28
29 #define BUFCFG_PINMODE_SHIFT 0
30 #define BUFCFG_PINMODE_MASK GENMASK(2, 0)
31 #define BUFCFG_PINMODE_GPIO 0
32 #define BUFCFG_PUPD_VAL_SHIFT 4
33 #define BUFCFG_PUPD_VAL_MASK GENMASK(5, 4)
34 #define BUFCFG_PUPD_VAL_2K 0
35 #define BUFCFG_PUPD_VAL_20K 1
36 #define BUFCFG_PUPD_VAL_50K 2
37 #define BUFCFG_PUPD_VAL_910 3
38 #define BUFCFG_PU_EN BIT(8)
39 #define BUFCFG_PD_EN BIT(9)
40 #define BUFCFG_Px_EN_MASK GENMASK(9, 8)
41 #define BUFCFG_SLEWSEL BIT(10)
42 #define BUFCFG_OVINEN BIT(12)
43 #define BUFCFG_OVINEN_EN BIT(13)
44 #define BUFCFG_OVINEN_MASK GENMASK(13, 12)
45 #define BUFCFG_OVOUTEN BIT(14)
46 #define BUFCFG_OVOUTEN_EN BIT(15)
47 #define BUFCFG_OVOUTEN_MASK GENMASK(15, 14)
48 #define BUFCFG_INDATAOV_VAL BIT(16)
49 #define BUFCFG_INDATAOV_EN BIT(17)
50 #define BUFCFG_INDATAOV_MASK GENMASK(17, 16)
51 #define BUFCFG_OUTDATAOV_VAL BIT(18)
52 #define BUFCFG_OUTDATAOV_EN BIT(19)
53 #define BUFCFG_OUTDATAOV_MASK GENMASK(19, 18)
54 #define BUFCFG_OD_EN BIT(21)
55
56 /**
57 * struct mrfld_family - Intel pin family description
58 * @barno: MMIO BAR number where registers for this family reside
59 * @pin_base: Starting pin of pins in this family
60 * @npins: Number of pins in this family
61 * @protected: True if family is protected by access
62 * @regs: family specific common registers
63 */
64 struct mrfld_family {
65 unsigned int barno;
66 unsigned int pin_base;
67 size_t npins;
68 bool protected;
69 void __iomem *regs;
70 };
71
72 #define MRFLD_FAMILY(b, s, e) \
73 { \
74 .barno = (b), \
75 .pin_base = (s), \
76 .npins = (e) - (s) + 1, \
77 }
78
79 #define MRFLD_FAMILY_PROTECTED(b, s, e) \
80 { \
81 .barno = (b), \
82 .pin_base = (s), \
83 .npins = (e) - (s) + 1, \
84 .protected = true, \
85 }
86
87 static const struct pinctrl_pin_desc mrfld_pins[] = {
88 /* Family 0: OCP2SSC (0 pins) */
89 /* Family 1: ULPI (13 pins) */
90 PINCTRL_PIN(0, "ULPI_CLK"),
91 PINCTRL_PIN(1, "ULPI_D0"),
92 PINCTRL_PIN(2, "ULPI_D1"),
93 PINCTRL_PIN(3, "ULPI_D2"),
94 PINCTRL_PIN(4, "ULPI_D3"),
95 PINCTRL_PIN(5, "ULPI_D4"),
96 PINCTRL_PIN(6, "ULPI_D5"),
97 PINCTRL_PIN(7, "ULPI_D6"),
98 PINCTRL_PIN(8, "ULPI_D7"),
99 PINCTRL_PIN(9, "ULPI_DIR"),
100 PINCTRL_PIN(10, "ULPI_NXT"),
101 PINCTRL_PIN(11, "ULPI_REFCLK"),
102 PINCTRL_PIN(12, "ULPI_STP"),
103 /* Family 2: eMMC (24 pins) */
104 PINCTRL_PIN(13, "EMMC_CLK"),
105 PINCTRL_PIN(14, "EMMC_CMD"),
106 PINCTRL_PIN(15, "EMMC_D0"),
107 PINCTRL_PIN(16, "EMMC_D1"),
108 PINCTRL_PIN(17, "EMMC_D2"),
109 PINCTRL_PIN(18, "EMMC_D3"),
110 PINCTRL_PIN(19, "EMMC_D4"),
111 PINCTRL_PIN(20, "EMMC_D5"),
112 PINCTRL_PIN(21, "EMMC_D6"),
113 PINCTRL_PIN(22, "EMMC_D7"),
114 PINCTRL_PIN(23, "EMMC_RST_N"),
115 PINCTRL_PIN(24, "GP154"),
116 PINCTRL_PIN(25, "GP155"),
117 PINCTRL_PIN(26, "GP156"),
118 PINCTRL_PIN(27, "GP157"),
119 PINCTRL_PIN(28, "GP158"),
120 PINCTRL_PIN(29, "GP159"),
121 PINCTRL_PIN(30, "GP160"),
122 PINCTRL_PIN(31, "GP161"),
123 PINCTRL_PIN(32, "GP162"),
124 PINCTRL_PIN(33, "GP163"),
125 PINCTRL_PIN(34, "GP97"),
126 PINCTRL_PIN(35, "GP14"),
127 PINCTRL_PIN(36, "GP15"),
128 /* Family 3: SDIO (20 pins) */
129 PINCTRL_PIN(37, "GP77_SD_CD"),
130 PINCTRL_PIN(38, "GP78_SD_CLK"),
131 PINCTRL_PIN(39, "GP79_SD_CMD"),
132 PINCTRL_PIN(40, "GP80_SD_D0"),
133 PINCTRL_PIN(41, "GP81_SD_D1"),
134 PINCTRL_PIN(42, "GP82_SD_D2"),
135 PINCTRL_PIN(43, "GP83_SD_D3"),
136 PINCTRL_PIN(44, "GP84_SD_LS_CLK_FB"),
137 PINCTRL_PIN(45, "GP85_SD_LS_CMD_DIR"),
138 PINCTRL_PIN(46, "GP86_SD_LVL_D_DIR"),
139 PINCTRL_PIN(47, "GP88_SD_LS_SEL"),
140 PINCTRL_PIN(48, "GP87_SD_PD"),
141 PINCTRL_PIN(49, "GP89_SD_WP"),
142 PINCTRL_PIN(50, "GP90_SDIO_CLK"),
143 PINCTRL_PIN(51, "GP91_SDIO_CMD"),
144 PINCTRL_PIN(52, "GP92_SDIO_D0"),
145 PINCTRL_PIN(53, "GP93_SDIO_D1"),
146 PINCTRL_PIN(54, "GP94_SDIO_D2"),
147 PINCTRL_PIN(55, "GP95_SDIO_D3"),
148 PINCTRL_PIN(56, "GP96_SDIO_PD"),
149 /* Family 4: HSI (8 pins) */
150 PINCTRL_PIN(57, "HSI_ACDATA"),
151 PINCTRL_PIN(58, "HSI_ACFLAG"),
152 PINCTRL_PIN(59, "HSI_ACREADY"),
153 PINCTRL_PIN(60, "HSI_ACWAKE"),
154 PINCTRL_PIN(61, "HSI_CADATA"),
155 PINCTRL_PIN(62, "HSI_CAFLAG"),
156 PINCTRL_PIN(63, "HSI_CAREADY"),
157 PINCTRL_PIN(64, "HSI_CAWAKE"),
158 /* Family 5: SSP Audio (14 pins) */
159 PINCTRL_PIN(65, "GP70"),
160 PINCTRL_PIN(66, "GP71"),
161 PINCTRL_PIN(67, "GP32_I2S_0_CLK"),
162 PINCTRL_PIN(68, "GP33_I2S_0_FS"),
163 PINCTRL_PIN(69, "GP34_I2S_0_RXD"),
164 PINCTRL_PIN(70, "GP35_I2S_0_TXD"),
165 PINCTRL_PIN(71, "GP36_I2S_1_CLK"),
166 PINCTRL_PIN(72, "GP37_I2S_1_FS"),
167 PINCTRL_PIN(73, "GP38_I2S_1_RXD"),
168 PINCTRL_PIN(74, "GP39_I2S_1_TXD"),
169 PINCTRL_PIN(75, "GP40_I2S_2_CLK"),
170 PINCTRL_PIN(76, "GP41_I2S_2_FS"),
171 PINCTRL_PIN(77, "GP42_I2S_2_RXD"),
172 PINCTRL_PIN(78, "GP43_I2S_2_TXD"),
173 /* Family 6: GP SSP (22 pins) */
174 PINCTRL_PIN(79, "GP120_SPI_3_CLK"),
175 PINCTRL_PIN(80, "GP121_SPI_3_SS"),
176 PINCTRL_PIN(81, "GP122_SPI_3_RXD"),
177 PINCTRL_PIN(82, "GP123_SPI_3_TXD"),
178 PINCTRL_PIN(83, "GP102_SPI_4_CLK"),
179 PINCTRL_PIN(84, "GP103_SPI_4_SS_0"),
180 PINCTRL_PIN(85, "GP104_SPI_4_SS_1"),
181 PINCTRL_PIN(86, "GP105_SPI_4_SS_2"),
182 PINCTRL_PIN(87, "GP106_SPI_4_SS_3"),
183 PINCTRL_PIN(88, "GP107_SPI_4_RXD"),
184 PINCTRL_PIN(89, "GP108_SPI_4_TXD"),
185 PINCTRL_PIN(90, "GP109_SPI_5_CLK"),
186 PINCTRL_PIN(91, "GP110_SPI_5_SS_0"),
187 PINCTRL_PIN(92, "GP111_SPI_5_SS_1"),
188 PINCTRL_PIN(93, "GP112_SPI_5_SS_2"),
189 PINCTRL_PIN(94, "GP113_SPI_5_SS_3"),
190 PINCTRL_PIN(95, "GP114_SPI_5_RXD"),
191 PINCTRL_PIN(96, "GP115_SPI_5_TXD"),
192 PINCTRL_PIN(97, "GP116_SPI_6_CLK"),
193 PINCTRL_PIN(98, "GP117_SPI_6_SS"),
194 PINCTRL_PIN(99, "GP118_SPI_6_RXD"),
195 PINCTRL_PIN(100, "GP119_SPI_6_TXD"),
196 /* Family 7: I2C (14 pins) */
197 PINCTRL_PIN(101, "GP19_I2C_1_SCL"),
198 PINCTRL_PIN(102, "GP20_I2C_1_SDA"),
199 PINCTRL_PIN(103, "GP21_I2C_2_SCL"),
200 PINCTRL_PIN(104, "GP22_I2C_2_SDA"),
201 PINCTRL_PIN(105, "GP17_I2C_3_SCL_HDMI"),
202 PINCTRL_PIN(106, "GP18_I2C_3_SDA_HDMI"),
203 PINCTRL_PIN(107, "GP23_I2C_4_SCL"),
204 PINCTRL_PIN(108, "GP24_I2C_4_SDA"),
205 PINCTRL_PIN(109, "GP25_I2C_5_SCL"),
206 PINCTRL_PIN(110, "GP26_I2C_5_SDA"),
207 PINCTRL_PIN(111, "GP27_I2C_6_SCL"),
208 PINCTRL_PIN(112, "GP28_I2C_6_SDA"),
209 PINCTRL_PIN(113, "GP29_I2C_7_SCL"),
210 PINCTRL_PIN(114, "GP30_I2C_7_SDA"),
211 /* Family 8: UART (12 pins) */
212 PINCTRL_PIN(115, "GP124_UART_0_CTS"),
213 PINCTRL_PIN(116, "GP125_UART_0_RTS"),
214 PINCTRL_PIN(117, "GP126_UART_0_RX"),
215 PINCTRL_PIN(118, "GP127_UART_0_TX"),
216 PINCTRL_PIN(119, "GP128_UART_1_CTS"),
217 PINCTRL_PIN(120, "GP129_UART_1_RTS"),
218 PINCTRL_PIN(121, "GP130_UART_1_RX"),
219 PINCTRL_PIN(122, "GP131_UART_1_TX"),
220 PINCTRL_PIN(123, "GP132_UART_2_CTS"),
221 PINCTRL_PIN(124, "GP133_UART_2_RTS"),
222 PINCTRL_PIN(125, "GP134_UART_2_RX"),
223 PINCTRL_PIN(126, "GP135_UART_2_TX"),
224 /* Family 9: GPIO South (19 pins) */
225 PINCTRL_PIN(127, "GP177"),
226 PINCTRL_PIN(128, "GP178"),
227 PINCTRL_PIN(129, "GP179"),
228 PINCTRL_PIN(130, "GP180"),
229 PINCTRL_PIN(131, "GP181"),
230 PINCTRL_PIN(132, "GP182_PWM2"),
231 PINCTRL_PIN(133, "GP183_PWM3"),
232 PINCTRL_PIN(134, "GP184"),
233 PINCTRL_PIN(135, "GP185"),
234 PINCTRL_PIN(136, "GP186"),
235 PINCTRL_PIN(137, "GP187"),
236 PINCTRL_PIN(138, "GP188"),
237 PINCTRL_PIN(139, "GP189"),
238 PINCTRL_PIN(140, "GP64_FAST_INT0"),
239 PINCTRL_PIN(141, "GP65_FAST_INT1"),
240 PINCTRL_PIN(142, "GP66_FAST_INT2"),
241 PINCTRL_PIN(143, "GP67_FAST_INT3"),
242 PINCTRL_PIN(144, "GP12_PWM0"),
243 PINCTRL_PIN(145, "GP13_PWM1"),
244 /* Family 10: Camera Sideband (12 pins) */
245 PINCTRL_PIN(146, "GP0"),
246 PINCTRL_PIN(147, "GP1"),
247 PINCTRL_PIN(148, "GP2"),
248 PINCTRL_PIN(149, "GP3"),
249 PINCTRL_PIN(150, "GP4"),
250 PINCTRL_PIN(151, "GP5"),
251 PINCTRL_PIN(152, "GP6"),
252 PINCTRL_PIN(153, "GP7"),
253 PINCTRL_PIN(154, "GP8"),
254 PINCTRL_PIN(155, "GP9"),
255 PINCTRL_PIN(156, "GP10"),
256 PINCTRL_PIN(157, "GP11"),
257 /* Family 11: Clock (22 pins) */
258 PINCTRL_PIN(158, "GP137"),
259 PINCTRL_PIN(159, "GP138"),
260 PINCTRL_PIN(160, "GP139"),
261 PINCTRL_PIN(161, "GP140"),
262 PINCTRL_PIN(162, "GP141"),
263 PINCTRL_PIN(163, "GP142"),
264 PINCTRL_PIN(164, "GP16_HDMI_HPD"),
265 PINCTRL_PIN(165, "GP68_DSI_A_TE"),
266 PINCTRL_PIN(166, "GP69_DSI_C_TE"),
267 PINCTRL_PIN(167, "OSC_CLK_CTRL0"),
268 PINCTRL_PIN(168, "OSC_CLK_CTRL1"),
269 PINCTRL_PIN(169, "OSC_CLK0"),
270 PINCTRL_PIN(170, "OSC_CLK1"),
271 PINCTRL_PIN(171, "OSC_CLK2"),
272 PINCTRL_PIN(172, "OSC_CLK3"),
273 PINCTRL_PIN(173, "OSC_CLK4"),
274 PINCTRL_PIN(174, "RESETOUT"),
275 PINCTRL_PIN(175, "PMODE"),
276 PINCTRL_PIN(176, "PRDY"),
277 PINCTRL_PIN(177, "PREQ"),
278 PINCTRL_PIN(178, "GP190"),
279 PINCTRL_PIN(179, "GP191"),
280 /* Family 12: MSIC (15 pins) */
281 PINCTRL_PIN(180, "I2C_0_SCL"),
282 PINCTRL_PIN(181, "I2C_0_SDA"),
283 PINCTRL_PIN(182, "IERR"),
284 PINCTRL_PIN(183, "JTAG_TCK"),
285 PINCTRL_PIN(184, "JTAG_TDI"),
286 PINCTRL_PIN(185, "JTAG_TDO"),
287 PINCTRL_PIN(186, "JTAG_TMS"),
288 PINCTRL_PIN(187, "JTAG_TRST"),
289 PINCTRL_PIN(188, "PROCHOT"),
290 PINCTRL_PIN(189, "RTC_CLK"),
291 PINCTRL_PIN(190, "SVID_ALERT"),
292 PINCTRL_PIN(191, "SVID_CLK"),
293 PINCTRL_PIN(192, "SVID_D"),
294 PINCTRL_PIN(193, "THERMTRIP"),
295 PINCTRL_PIN(194, "STANDBY"),
296 /* Family 13: Keyboard (20 pins) */
297 PINCTRL_PIN(195, "GP44"),
298 PINCTRL_PIN(196, "GP45"),
299 PINCTRL_PIN(197, "GP46"),
300 PINCTRL_PIN(198, "GP47"),
301 PINCTRL_PIN(199, "GP48"),
302 PINCTRL_PIN(200, "GP49"),
303 PINCTRL_PIN(201, "GP50"),
304 PINCTRL_PIN(202, "GP51"),
305 PINCTRL_PIN(203, "GP52"),
306 PINCTRL_PIN(204, "GP53"),
307 PINCTRL_PIN(205, "GP54"),
308 PINCTRL_PIN(206, "GP55"),
309 PINCTRL_PIN(207, "GP56"),
310 PINCTRL_PIN(208, "GP57"),
311 PINCTRL_PIN(209, "GP58"),
312 PINCTRL_PIN(210, "GP59"),
313 PINCTRL_PIN(211, "GP60"),
314 PINCTRL_PIN(212, "GP61"),
315 PINCTRL_PIN(213, "GP62"),
316 PINCTRL_PIN(214, "GP63"),
317 /* Family 14: GPIO North (13 pins) */
318 PINCTRL_PIN(215, "GP164"),
319 PINCTRL_PIN(216, "GP165"),
320 PINCTRL_PIN(217, "GP166"),
321 PINCTRL_PIN(218, "GP167"),
322 PINCTRL_PIN(219, "GP168_MJTAG_TCK"),
323 PINCTRL_PIN(220, "GP169_MJTAG_TDI"),
324 PINCTRL_PIN(221, "GP170_MJTAG_TDO"),
325 PINCTRL_PIN(222, "GP171_MJTAG_TMS"),
326 PINCTRL_PIN(223, "GP172_MJTAG_TRST"),
327 PINCTRL_PIN(224, "GP173"),
328 PINCTRL_PIN(225, "GP174"),
329 PINCTRL_PIN(226, "GP175"),
330 PINCTRL_PIN(227, "GP176"),
331 /* Family 15: PTI (5 pins) */
332 PINCTRL_PIN(228, "GP72_PTI_CLK"),
333 PINCTRL_PIN(229, "GP73_PTI_D0"),
334 PINCTRL_PIN(230, "GP74_PTI_D1"),
335 PINCTRL_PIN(231, "GP75_PTI_D2"),
336 PINCTRL_PIN(232, "GP76_PTI_D3"),
337 /* Family 16: USB3 (0 pins) */
338 /* Family 17: HSIC (0 pins) */
339 /* Family 18: Broadcast (0 pins) */
340 };
341
342 static const unsigned int mrfld_sdio_pins[] = { 50, 51, 52, 53, 54, 55, 56 };
343 static const unsigned int mrfld_spi5_pins[] = { 90, 91, 92, 93, 94, 95, 96 };
344 static const unsigned int mrfld_uart0_pins[] = { 115, 116, 117, 118 };
345 static const unsigned int mrfld_uart1_pins[] = { 119, 120, 121, 122 };
346 static const unsigned int mrfld_uart2_pins[] = { 123, 124, 125, 126 };
347 static const unsigned int mrfld_pwm0_pins[] = { 144 };
348 static const unsigned int mrfld_pwm1_pins[] = { 145 };
349 static const unsigned int mrfld_pwm2_pins[] = { 132 };
350 static const unsigned int mrfld_pwm3_pins[] = { 133 };
351
352 static const struct intel_pingroup mrfld_groups[] = {
353 PIN_GROUP("sdio_grp", mrfld_sdio_pins, 1),
354 PIN_GROUP("spi5_grp", mrfld_spi5_pins, 1),
355 PIN_GROUP("uart0_grp", mrfld_uart0_pins, 1),
356 PIN_GROUP("uart1_grp", mrfld_uart1_pins, 1),
357 PIN_GROUP("uart2_grp", mrfld_uart2_pins, 1),
358 PIN_GROUP("pwm0_grp", mrfld_pwm0_pins, 1),
359 PIN_GROUP("pwm1_grp", mrfld_pwm1_pins, 1),
360 PIN_GROUP("pwm2_grp", mrfld_pwm2_pins, 1),
361 PIN_GROUP("pwm3_grp", mrfld_pwm3_pins, 1),
362 };
363
364 static const char * const mrfld_sdio_groups[] = { "sdio_grp" };
365 static const char * const mrfld_spi5_groups[] = { "spi5_grp" };
366 static const char * const mrfld_uart0_groups[] = { "uart0_grp" };
367 static const char * const mrfld_uart1_groups[] = { "uart1_grp" };
368 static const char * const mrfld_uart2_groups[] = { "uart2_grp" };
369 static const char * const mrfld_pwm0_groups[] = { "pwm0_grp" };
370 static const char * const mrfld_pwm1_groups[] = { "pwm1_grp" };
371 static const char * const mrfld_pwm2_groups[] = { "pwm2_grp" };
372 static const char * const mrfld_pwm3_groups[] = { "pwm3_grp" };
373
374 static const struct intel_function mrfld_functions[] = {
375 FUNCTION("sdio", mrfld_sdio_groups),
376 FUNCTION("spi5", mrfld_spi5_groups),
377 FUNCTION("uart0", mrfld_uart0_groups),
378 FUNCTION("uart1", mrfld_uart1_groups),
379 FUNCTION("uart2", mrfld_uart2_groups),
380 FUNCTION("pwm0", mrfld_pwm0_groups),
381 FUNCTION("pwm1", mrfld_pwm1_groups),
382 FUNCTION("pwm2", mrfld_pwm2_groups),
383 FUNCTION("pwm3", mrfld_pwm3_groups),
384 };
385
386 static const struct mrfld_family mrfld_families[] = {
387 MRFLD_FAMILY(1, 0, 12),
388 MRFLD_FAMILY(2, 13, 36),
389 MRFLD_FAMILY(3, 37, 56),
390 MRFLD_FAMILY(4, 57, 64),
391 MRFLD_FAMILY(5, 65, 78),
392 MRFLD_FAMILY(6, 79, 100),
393 MRFLD_FAMILY_PROTECTED(7, 101, 114),
394 MRFLD_FAMILY(8, 115, 126),
395 MRFLD_FAMILY(9, 127, 145),
396 MRFLD_FAMILY(10, 146, 157),
397 MRFLD_FAMILY(11, 158, 179),
398 MRFLD_FAMILY_PROTECTED(12, 180, 194),
399 MRFLD_FAMILY(13, 195, 214),
400 MRFLD_FAMILY(14, 215, 227),
401 MRFLD_FAMILY(15, 228, 232),
402 };
403
404 /**
405 * struct mrfld_pinctrl - Intel Merrifield pinctrl private structure
406 * @dev: Pointer to the device structure
407 * @lock: Lock to serialize register access
408 * @pctldesc: Pin controller description
409 * @pctldev: Pointer to the pin controller device
410 * @families: Array of families this pinctrl handles
411 * @nfamilies: Number of families in the array
412 * @functions: Array of functions
413 * @nfunctions: Number of functions in the array
414 * @groups: Array of pin groups
415 * @ngroups: Number of groups in the array
416 * @pins: Array of pins this pinctrl controls
417 * @npins: Number of pins in the array
418 */
419 struct mrfld_pinctrl {
420 struct device *dev;
421 raw_spinlock_t lock;
422 struct pinctrl_desc pctldesc;
423 struct pinctrl_dev *pctldev;
424
425 /* Pin controller configuration */
426 const struct mrfld_family *families;
427 size_t nfamilies;
428 const struct intel_function *functions;
429 size_t nfunctions;
430 const struct intel_pingroup *groups;
431 size_t ngroups;
432 const struct pinctrl_pin_desc *pins;
433 size_t npins;
434 };
435
436 #define pin_to_bufno(f, p) ((p) - (f)->pin_base)
437
438 static const struct mrfld_family *mrfld_get_family(struct mrfld_pinctrl *mp,
439 unsigned int pin)
440 {
441 const struct mrfld_family *family;
442 unsigned int i;
443
444 for (i = 0; i < mp->nfamilies; i++) {
445 family = &mp->families[i];
446 if (pin >= family->pin_base &&
447 pin < family->pin_base + family->npins)
448 return family;
449 }
450
451 dev_warn(mp->dev, "failed to find family for pin %u\n", pin);
452 return NULL;
453 }
454
455 static bool mrfld_buf_available(struct mrfld_pinctrl *mp, unsigned int pin)
456 {
457 const struct mrfld_family *family;
458
459 family = mrfld_get_family(mp, pin);
460 if (!family)
461 return false;
462
463 return !family->protected;
464 }
465
466 static void __iomem *mrfld_get_bufcfg(struct mrfld_pinctrl *mp, unsigned int pin)
467 {
468 const struct mrfld_family *family;
469 unsigned int bufno;
470
471 family = mrfld_get_family(mp, pin);
472 if (!family)
473 return NULL;
474
475 bufno = pin_to_bufno(family, pin);
476 return family->regs + BUFCFG_OFFSET + bufno * 4;
477 }
478
479 static int mrfld_read_bufcfg(struct mrfld_pinctrl *mp, unsigned int pin, u32 *value)
480 {
481 void __iomem *bufcfg;
482
483 if (!mrfld_buf_available(mp, pin))
484 return -EBUSY;
485
486 bufcfg = mrfld_get_bufcfg(mp, pin);
487 *value = readl(bufcfg);
488
489 return 0;
490 }
491
492 static void mrfld_update_bufcfg(struct mrfld_pinctrl *mp, unsigned int pin,
493 u32 bits, u32 mask)
494 {
495 void __iomem *bufcfg;
496 u32 value;
497
498 bufcfg = mrfld_get_bufcfg(mp, pin);
499 value = readl(bufcfg);
500
501 value &= ~mask;
502 value |= bits & mask;
503
504 writel(value, bufcfg);
505 }
506
507 static int mrfld_get_groups_count(struct pinctrl_dev *pctldev)
508 {
509 struct mrfld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev);
510
511 return mp->ngroups;
512 }
513
514 static const char *mrfld_get_group_name(struct pinctrl_dev *pctldev,
515 unsigned int group)
516 {
517 struct mrfld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev);
518
519 return mp->groups[group].name;
520 }
521
522 static int mrfld_get_group_pins(struct pinctrl_dev *pctldev, unsigned int group,
523 const unsigned int **pins, unsigned int *npins)
524 {
525 struct mrfld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev);
526
527 *pins = mp->groups[group].pins;
528 *npins = mp->groups[group].npins;
529 return 0;
530 }
531
532 static void mrfld_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
533 unsigned int pin)
534 {
535 struct mrfld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev);
536 u32 value, mode;
537 int ret;
538
539 ret = mrfld_read_bufcfg(mp, pin, &value);
540 if (ret) {
541 seq_puts(s, "not available");
542 return;
543 }
544
545 mode = (value & BUFCFG_PINMODE_MASK) >> BUFCFG_PINMODE_SHIFT;
546 if (!mode)
547 seq_puts(s, "GPIO ");
548 else
549 seq_printf(s, "mode %d ", mode);
550
551 seq_printf(s, "0x%08x", value);
552 }
553
554 static const struct pinctrl_ops mrfld_pinctrl_ops = {
555 .get_groups_count = mrfld_get_groups_count,
556 .get_group_name = mrfld_get_group_name,
557 .get_group_pins = mrfld_get_group_pins,
558 .pin_dbg_show = mrfld_pin_dbg_show,
559 };
560
561 static int mrfld_get_functions_count(struct pinctrl_dev *pctldev)
562 {
563 struct mrfld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev);
564
565 return mp->nfunctions;
566 }
567
568 static const char *mrfld_get_function_name(struct pinctrl_dev *pctldev,
569 unsigned int function)
570 {
571 struct mrfld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev);
572
573 return mp->functions[function].name;
574 }
575
576 static int mrfld_get_function_groups(struct pinctrl_dev *pctldev,
577 unsigned int function,
578 const char * const **groups,
579 unsigned int * const ngroups)
580 {
581 struct mrfld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev);
582
583 *groups = mp->functions[function].groups;
584 *ngroups = mp->functions[function].ngroups;
585 return 0;
586 }
587
588 static int mrfld_pinmux_set_mux(struct pinctrl_dev *pctldev,
589 unsigned int function,
590 unsigned int group)
591 {
592 struct mrfld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev);
593 const struct intel_pingroup *grp = &mp->groups[group];
594 u32 bits = grp->mode << BUFCFG_PINMODE_SHIFT;
595 u32 mask = BUFCFG_PINMODE_MASK;
596 unsigned long flags;
597 unsigned int i;
598
599 /*
600 * All pins in the groups needs to be accessible and writable
601 * before we can enable the mux for this group.
602 */
603 for (i = 0; i < grp->npins; i++) {
604 if (!mrfld_buf_available(mp, grp->pins[i]))
605 return -EBUSY;
606 }
607
608 /* Now enable the mux setting for each pin in the group */
609 raw_spin_lock_irqsave(&mp->lock, flags);
610 for (i = 0; i < grp->npins; i++)
611 mrfld_update_bufcfg(mp, grp->pins[i], bits, mask);
612 raw_spin_unlock_irqrestore(&mp->lock, flags);
613
614 return 0;
615 }
616
617 static int mrfld_gpio_request_enable(struct pinctrl_dev *pctldev,
618 struct pinctrl_gpio_range *range,
619 unsigned int pin)
620 {
621 struct mrfld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev);
622 u32 bits = BUFCFG_PINMODE_GPIO << BUFCFG_PINMODE_SHIFT;
623 u32 mask = BUFCFG_PINMODE_MASK;
624 unsigned long flags;
625
626 if (!mrfld_buf_available(mp, pin))
627 return -EBUSY;
628
629 raw_spin_lock_irqsave(&mp->lock, flags);
630 mrfld_update_bufcfg(mp, pin, bits, mask);
631 raw_spin_unlock_irqrestore(&mp->lock, flags);
632
633 return 0;
634 }
635
636 static const struct pinmux_ops mrfld_pinmux_ops = {
637 .get_functions_count = mrfld_get_functions_count,
638 .get_function_name = mrfld_get_function_name,
639 .get_function_groups = mrfld_get_function_groups,
640 .set_mux = mrfld_pinmux_set_mux,
641 .gpio_request_enable = mrfld_gpio_request_enable,
642 };
643
644 static int mrfld_config_get(struct pinctrl_dev *pctldev, unsigned int pin,
645 unsigned long *config)
646 {
647 struct mrfld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev);
648 enum pin_config_param param = pinconf_to_config_param(*config);
649 u32 value, term;
650 u16 arg = 0;
651 int ret;
652
653 ret = mrfld_read_bufcfg(mp, pin, &value);
654 if (ret)
655 return -ENOTSUPP;
656
657 term = (value & BUFCFG_PUPD_VAL_MASK) >> BUFCFG_PUPD_VAL_SHIFT;
658
659 switch (param) {
660 case PIN_CONFIG_BIAS_DISABLE:
661 if (value & BUFCFG_Px_EN_MASK)
662 return -EINVAL;
663 break;
664
665 case PIN_CONFIG_BIAS_PULL_UP:
666 if ((value & BUFCFG_Px_EN_MASK) != BUFCFG_PU_EN)
667 return -EINVAL;
668
669 switch (term) {
670 case BUFCFG_PUPD_VAL_910:
671 arg = 910;
672 break;
673 case BUFCFG_PUPD_VAL_2K:
674 arg = 2000;
675 break;
676 case BUFCFG_PUPD_VAL_20K:
677 arg = 20000;
678 break;
679 case BUFCFG_PUPD_VAL_50K:
680 arg = 50000;
681 break;
682 }
683
684 break;
685
686 case PIN_CONFIG_BIAS_PULL_DOWN:
687 if ((value & BUFCFG_Px_EN_MASK) != BUFCFG_PD_EN)
688 return -EINVAL;
689
690 switch (term) {
691 case BUFCFG_PUPD_VAL_910:
692 arg = 910;
693 break;
694 case BUFCFG_PUPD_VAL_2K:
695 arg = 2000;
696 break;
697 case BUFCFG_PUPD_VAL_20K:
698 arg = 20000;
699 break;
700 case BUFCFG_PUPD_VAL_50K:
701 arg = 50000;
702 break;
703 }
704
705 break;
706
707 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
708 if (!(value & BUFCFG_OD_EN))
709 return -EINVAL;
710 break;
711
712 case PIN_CONFIG_SLEW_RATE:
713 if (!(value & BUFCFG_SLEWSEL))
714 arg = 0;
715 else
716 arg = 1;
717 break;
718
719 default:
720 return -ENOTSUPP;
721 }
722
723 *config = pinconf_to_config_packed(param, arg);
724 return 0;
725 }
726
727 static int mrfld_config_set_pin(struct mrfld_pinctrl *mp, unsigned int pin,
728 unsigned long config)
729 {
730 unsigned int param = pinconf_to_config_param(config);
731 unsigned int arg = pinconf_to_config_argument(config);
732 u32 bits = 0, mask = 0;
733 unsigned long flags;
734
735 switch (param) {
736 case PIN_CONFIG_BIAS_DISABLE:
737 mask |= BUFCFG_Px_EN_MASK | BUFCFG_PUPD_VAL_MASK;
738 break;
739
740 case PIN_CONFIG_BIAS_PULL_UP:
741 mask |= BUFCFG_Px_EN_MASK | BUFCFG_PUPD_VAL_MASK;
742 bits |= BUFCFG_PU_EN;
743
744 switch (arg) {
745 case 50000:
746 bits |= BUFCFG_PUPD_VAL_50K << BUFCFG_PUPD_VAL_SHIFT;
747 break;
748 case 20000:
749 bits |= BUFCFG_PUPD_VAL_20K << BUFCFG_PUPD_VAL_SHIFT;
750 break;
751 case 2000:
752 bits |= BUFCFG_PUPD_VAL_2K << BUFCFG_PUPD_VAL_SHIFT;
753 break;
754 default:
755 return -EINVAL;
756 }
757
758 break;
759
760 case PIN_CONFIG_BIAS_PULL_DOWN:
761 mask |= BUFCFG_Px_EN_MASK | BUFCFG_PUPD_VAL_MASK;
762 bits |= BUFCFG_PD_EN;
763
764 switch (arg) {
765 case 50000:
766 bits |= BUFCFG_PUPD_VAL_50K << BUFCFG_PUPD_VAL_SHIFT;
767 break;
768 case 20000:
769 bits |= BUFCFG_PUPD_VAL_20K << BUFCFG_PUPD_VAL_SHIFT;
770 break;
771 case 2000:
772 bits |= BUFCFG_PUPD_VAL_2K << BUFCFG_PUPD_VAL_SHIFT;
773 break;
774 default:
775 return -EINVAL;
776 }
777
778 break;
779
780 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
781 mask |= BUFCFG_OD_EN;
782 if (arg)
783 bits |= BUFCFG_OD_EN;
784 break;
785
786 case PIN_CONFIG_SLEW_RATE:
787 mask |= BUFCFG_SLEWSEL;
788 if (arg)
789 bits |= BUFCFG_SLEWSEL;
790 break;
791 }
792
793 raw_spin_lock_irqsave(&mp->lock, flags);
794 mrfld_update_bufcfg(mp, pin, bits, mask);
795 raw_spin_unlock_irqrestore(&mp->lock, flags);
796
797 return 0;
798 }
799
800 static int mrfld_config_set(struct pinctrl_dev *pctldev, unsigned int pin,
801 unsigned long *configs, unsigned int nconfigs)
802 {
803 struct mrfld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev);
804 unsigned int i;
805 int ret;
806
807 if (!mrfld_buf_available(mp, pin))
808 return -ENOTSUPP;
809
810 for (i = 0; i < nconfigs; i++) {
811 switch (pinconf_to_config_param(configs[i])) {
812 case PIN_CONFIG_BIAS_DISABLE:
813 case PIN_CONFIG_BIAS_PULL_UP:
814 case PIN_CONFIG_BIAS_PULL_DOWN:
815 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
816 case PIN_CONFIG_SLEW_RATE:
817 ret = mrfld_config_set_pin(mp, pin, configs[i]);
818 if (ret)
819 return ret;
820 break;
821
822 default:
823 return -ENOTSUPP;
824 }
825 }
826
827 return 0;
828 }
829
830 static int mrfld_config_group_get(struct pinctrl_dev *pctldev,
831 unsigned int group, unsigned long *config)
832 {
833 const unsigned int *pins;
834 unsigned int npins;
835 int ret;
836
837 ret = mrfld_get_group_pins(pctldev, group, &pins, &npins);
838 if (ret)
839 return ret;
840
841 ret = mrfld_config_get(pctldev, pins[0], config);
842 if (ret)
843 return ret;
844
845 return 0;
846 }
847
848 static int mrfld_config_group_set(struct pinctrl_dev *pctldev,
849 unsigned int group, unsigned long *configs,
850 unsigned int num_configs)
851 {
852 const unsigned int *pins;
853 unsigned int npins;
854 int i, ret;
855
856 ret = mrfld_get_group_pins(pctldev, group, &pins, &npins);
857 if (ret)
858 return ret;
859
860 for (i = 0; i < npins; i++) {
861 ret = mrfld_config_set(pctldev, pins[i], configs, num_configs);
862 if (ret)
863 return ret;
864 }
865
866 return 0;
867 }
868
869 static const struct pinconf_ops mrfld_pinconf_ops = {
870 .is_generic = true,
871 .pin_config_get = mrfld_config_get,
872 .pin_config_set = mrfld_config_set,
873 .pin_config_group_get = mrfld_config_group_get,
874 .pin_config_group_set = mrfld_config_group_set,
875 };
876
877 static const struct pinctrl_desc mrfld_pinctrl_desc = {
878 .pctlops = &mrfld_pinctrl_ops,
879 .pmxops = &mrfld_pinmux_ops,
880 .confops = &mrfld_pinconf_ops,
881 .owner = THIS_MODULE,
882 };
883
884 static int mrfld_pinctrl_probe(struct platform_device *pdev)
885 {
886 struct mrfld_family *families;
887 struct mrfld_pinctrl *mp;
888 struct resource *mem;
889 void __iomem *regs;
890 size_t nfamilies;
891 unsigned int i;
892
893 mp = devm_kzalloc(&pdev->dev, sizeof(*mp), GFP_KERNEL);
894 if (!mp)
895 return -ENOMEM;
896
897 mp->dev = &pdev->dev;
898 raw_spin_lock_init(&mp->lock);
899
900 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
901 regs = devm_ioremap_resource(&pdev->dev, mem);
902 if (IS_ERR(regs))
903 return PTR_ERR(regs);
904
905 /*
906 * Make a copy of the families which we can use to hold pointers
907 * to the registers.
908 */
909 nfamilies = ARRAY_SIZE(mrfld_families),
910 families = devm_kmemdup(&pdev->dev, mrfld_families,
911 sizeof(mrfld_families),
912 GFP_KERNEL);
913 if (!families)
914 return -ENOMEM;
915
916 /* Splice memory resource by chunk per family */
917 for (i = 0; i < nfamilies; i++) {
918 struct mrfld_family *family = &families[i];
919
920 family->regs = regs + family->barno * MRFLD_FAMILY_LEN;
921 }
922
923 mp->families = families;
924 mp->nfamilies = nfamilies;
925 mp->functions = mrfld_functions;
926 mp->nfunctions = ARRAY_SIZE(mrfld_functions);
927 mp->groups = mrfld_groups;
928 mp->ngroups = ARRAY_SIZE(mrfld_groups);
929 mp->pctldesc = mrfld_pinctrl_desc;
930 mp->pctldesc.name = dev_name(&pdev->dev);
931 mp->pctldesc.pins = mrfld_pins;
932 mp->pctldesc.npins = ARRAY_SIZE(mrfld_pins);
933
934 mp->pctldev = devm_pinctrl_register(&pdev->dev, &mp->pctldesc, mp);
935 if (IS_ERR(mp->pctldev)) {
936 dev_err(&pdev->dev, "failed to register pinctrl driver\n");
937 return PTR_ERR(mp->pctldev);
938 }
939
940 platform_set_drvdata(pdev, mp);
941 return 0;
942 }
943
944 static const struct acpi_device_id mrfld_acpi_table[] = {
945 { "INTC1002" },
946 { }
947 };
948 MODULE_DEVICE_TABLE(acpi, mrfld_acpi_table);
949
950 static struct platform_driver mrfld_pinctrl_driver = {
951 .probe = mrfld_pinctrl_probe,
952 .driver = {
953 .name = "pinctrl-merrifield",
954 .acpi_match_table = mrfld_acpi_table,
955 },
956 };
957
958 static int __init mrfld_pinctrl_init(void)
959 {
960 return platform_driver_register(&mrfld_pinctrl_driver);
961 }
962 subsys_initcall(mrfld_pinctrl_init);
963
964 static void __exit mrfld_pinctrl_exit(void)
965 {
966 platform_driver_unregister(&mrfld_pinctrl_driver);
967 }
968 module_exit(mrfld_pinctrl_exit);
969
970 MODULE_AUTHOR("Andy Shevchenko <andriy.shevchenko@linux.intel.com>");
971 MODULE_DESCRIPTION("Intel Merrifield SoC pinctrl driver");
972 MODULE_LICENSE("GPL v2");
973 MODULE_ALIAS("platform:pinctrl-merrifield");
Linux with added FPC-III support