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Linux 5.1.15
[linux/fpc-iii.git] / drivers / pinctrl / pinctrl-at91.c
blobcb7c432769a5ece3775c31c70d3f13a387313d7b
1 /*
2 * at91 pinctrl driver based on at91 pinmux core
3 *
4 * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
5 *
6 * Under GPLv2 only
7 */
8
9 #include <linux/clk.h>
10 #include <linux/err.h>
11 #include <linux/init.h>
12 #include <linux/of.h>
13 #include <linux/of_device.h>
14 #include <linux/of_address.h>
15 #include <linux/of_irq.h>
16 #include <linux/slab.h>
17 #include <linux/interrupt.h>
18 #include <linux/io.h>
19 #include <linux/gpio/driver.h>
20 #include <linux/pinctrl/machine.h>
21 #include <linux/pinctrl/pinconf.h>
22 #include <linux/pinctrl/pinctrl.h>
23 #include <linux/pinctrl/pinmux.h>
24 /* Since we request GPIOs from ourself */
25 #include <linux/pinctrl/consumer.h>
26
27 #include "pinctrl-at91.h"
28 #include "core.h"
29
30 #define MAX_GPIO_BANKS 5
31 #define MAX_NB_GPIO_PER_BANK 32
32
33 struct at91_pinctrl_mux_ops;
34
35 struct at91_gpio_chip {
36 struct gpio_chip chip;
37 struct pinctrl_gpio_range range;
38 struct at91_gpio_chip *next; /* Bank sharing same clock */
39 int pioc_hwirq; /* PIO bank interrupt identifier on AIC */
40 int pioc_virq; /* PIO bank Linux virtual interrupt */
41 int pioc_idx; /* PIO bank index */
42 void __iomem *regbase; /* PIO bank virtual address */
43 struct clk *clock; /* associated clock */
44 struct at91_pinctrl_mux_ops *ops; /* ops */
45 };
46
47 static struct at91_gpio_chip *gpio_chips[MAX_GPIO_BANKS];
48
49 static int gpio_banks;
50
51 #define PULL_UP (1 << 0)
52 #define MULTI_DRIVE (1 << 1)
53 #define DEGLITCH (1 << 2)
54 #define PULL_DOWN (1 << 3)
55 #define DIS_SCHMIT (1 << 4)
56 #define DRIVE_STRENGTH_SHIFT 5
57 #define DRIVE_STRENGTH_MASK 0x3
58 #define DRIVE_STRENGTH (DRIVE_STRENGTH_MASK << DRIVE_STRENGTH_SHIFT)
59 #define OUTPUT (1 << 7)
60 #define OUTPUT_VAL_SHIFT 8
61 #define OUTPUT_VAL (0x1 << OUTPUT_VAL_SHIFT)
62 #define SLEWRATE_SHIFT 9
63 #define SLEWRATE_MASK 0x1
64 #define SLEWRATE (SLEWRATE_MASK << SLEWRATE_SHIFT)
65 #define DEBOUNCE (1 << 16)
66 #define DEBOUNCE_VAL_SHIFT 17
67 #define DEBOUNCE_VAL (0x3fff << DEBOUNCE_VAL_SHIFT)
68
69 /**
70 * These defines will translated the dt binding settings to our internal
71 * settings. They are not necessarily the same value as the register setting.
72 * The actual drive strength current of low, medium and high must be looked up
73 * from the corresponding device datasheet. This value is different for pins
74 * that are even in the same banks. It is also dependent on VCC.
75 * DRIVE_STRENGTH_DEFAULT is just a placeholder to avoid changing the drive
76 * strength when there is no dt config for it.
77 */
78 enum drive_strength_bit {
79 DRIVE_STRENGTH_BIT_DEF,
80 DRIVE_STRENGTH_BIT_LOW,
81 DRIVE_STRENGTH_BIT_MED,
82 DRIVE_STRENGTH_BIT_HI,
83 };
84
85 #define DRIVE_STRENGTH_BIT_MSK(name) (DRIVE_STRENGTH_BIT_##name << \
86 DRIVE_STRENGTH_SHIFT)
87
88 enum slewrate_bit {
89 SLEWRATE_BIT_DIS,
90 SLEWRATE_BIT_ENA,
91 };
92
93 #define SLEWRATE_BIT_MSK(name) (SLEWRATE_BIT_##name << SLEWRATE_SHIFT)
94
95 /**
96 * struct at91_pmx_func - describes AT91 pinmux functions
97 * @name: the name of this specific function
98 * @groups: corresponding pin groups
99 * @ngroups: the number of groups
100 */
101 struct at91_pmx_func {
102 const char *name;
103 const char **groups;
104 unsigned ngroups;
105 };
106
107 enum at91_mux {
108 AT91_MUX_GPIO = 0,
109 AT91_MUX_PERIPH_A = 1,
110 AT91_MUX_PERIPH_B = 2,
111 AT91_MUX_PERIPH_C = 3,
112 AT91_MUX_PERIPH_D = 4,
113 };
114
115 /**
116 * struct at91_pmx_pin - describes an At91 pin mux
117 * @bank: the bank of the pin
118 * @pin: the pin number in the @bank
119 * @mux: the mux mode : gpio or periph_x of the pin i.e. alternate function.
120 * @conf: the configuration of the pin: PULL_UP, MULTIDRIVE etc...
121 */
122 struct at91_pmx_pin {
123 uint32_t bank;
124 uint32_t pin;
125 enum at91_mux mux;
126 unsigned long conf;
127 };
128
129 /**
130 * struct at91_pin_group - describes an At91 pin group
131 * @name: the name of this specific pin group
132 * @pins_conf: the mux mode for each pin in this group. The size of this
133 * array is the same as pins.
134 * @pins: an array of discrete physical pins used in this group, taken
135 * from the driver-local pin enumeration space
136 * @npins: the number of pins in this group array, i.e. the number of
137 * elements in .pins so we can iterate over that array
138 */
139 struct at91_pin_group {
140 const char *name;
141 struct at91_pmx_pin *pins_conf;
142 unsigned int *pins;
143 unsigned npins;
144 };
145
146 /**
147 * struct at91_pinctrl_mux_ops - describes an AT91 mux ops group
148 * on new IP with support for periph C and D the way to mux in
149 * periph A and B has changed
150 * So provide the right call back
151 * if not present means the IP does not support it
152 * @get_periph: return the periph mode configured
153 * @mux_A_periph: mux as periph A
154 * @mux_B_periph: mux as periph B
155 * @mux_C_periph: mux as periph C
156 * @mux_D_periph: mux as periph D
157 * @get_deglitch: get deglitch status
158 * @set_deglitch: enable/disable deglitch
159 * @get_debounce: get debounce status
160 * @set_debounce: enable/disable debounce
161 * @get_pulldown: get pulldown status
162 * @set_pulldown: enable/disable pulldown
163 * @get_schmitt_trig: get schmitt trigger status
164 * @disable_schmitt_trig: disable schmitt trigger
165 * @irq_type: return irq type
166 */
167 struct at91_pinctrl_mux_ops {
168 enum at91_mux (*get_periph)(void __iomem *pio, unsigned mask);
169 void (*mux_A_periph)(void __iomem *pio, unsigned mask);
170 void (*mux_B_periph)(void __iomem *pio, unsigned mask);
171 void (*mux_C_periph)(void __iomem *pio, unsigned mask);
172 void (*mux_D_periph)(void __iomem *pio, unsigned mask);
173 bool (*get_deglitch)(void __iomem *pio, unsigned pin);
174 void (*set_deglitch)(void __iomem *pio, unsigned mask, bool is_on);
175 bool (*get_debounce)(void __iomem *pio, unsigned pin, u32 *div);
176 void (*set_debounce)(void __iomem *pio, unsigned mask, bool is_on, u32 div);
177 bool (*get_pulldown)(void __iomem *pio, unsigned pin);
178 void (*set_pulldown)(void __iomem *pio, unsigned mask, bool is_on);
179 bool (*get_schmitt_trig)(void __iomem *pio, unsigned pin);
180 void (*disable_schmitt_trig)(void __iomem *pio, unsigned mask);
181 unsigned (*get_drivestrength)(void __iomem *pio, unsigned pin);
182 void (*set_drivestrength)(void __iomem *pio, unsigned pin,
183 u32 strength);
184 unsigned (*get_slewrate)(void __iomem *pio, unsigned pin);
185 void (*set_slewrate)(void __iomem *pio, unsigned pin, u32 slewrate);
186 /* irq */
187 int (*irq_type)(struct irq_data *d, unsigned type);
188 };
189
190 static int gpio_irq_type(struct irq_data *d, unsigned type);
191 static int alt_gpio_irq_type(struct irq_data *d, unsigned type);
192
193 struct at91_pinctrl {
194 struct device *dev;
195 struct pinctrl_dev *pctl;
196
197 int nactive_banks;
198
199 uint32_t *mux_mask;
200 int nmux;
201
202 struct at91_pmx_func *functions;
203 int nfunctions;
204
205 struct at91_pin_group *groups;
206 int ngroups;
207
208 struct at91_pinctrl_mux_ops *ops;
209 };
210
211 static inline const struct at91_pin_group *at91_pinctrl_find_group_by_name(
212 const struct at91_pinctrl *info,
213 const char *name)
214 {
215 const struct at91_pin_group *grp = NULL;
216 int i;
217
218 for (i = 0; i < info->ngroups; i++) {
219 if (strcmp(info->groups[i].name, name))
220 continue;
221
222 grp = &info->groups[i];
223 dev_dbg(info->dev, "%s: %d 0:%d\n", name, grp->npins, grp->pins[0]);
224 break;
225 }
226
227 return grp;
228 }
229
230 static int at91_get_groups_count(struct pinctrl_dev *pctldev)
231 {
232 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
233
234 return info->ngroups;
235 }
236
237 static const char *at91_get_group_name(struct pinctrl_dev *pctldev,
238 unsigned selector)
239 {
240 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
241
242 return info->groups[selector].name;
243 }
244
245 static int at91_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
246 const unsigned **pins,
247 unsigned *npins)
248 {
249 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
250
251 if (selector >= info->ngroups)
252 return -EINVAL;
253
254 *pins = info->groups[selector].pins;
255 *npins = info->groups[selector].npins;
256
257 return 0;
258 }
259
260 static void at91_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
261 unsigned offset)
262 {
263 seq_printf(s, "%s", dev_name(pctldev->dev));
264 }
265
266 static int at91_dt_node_to_map(struct pinctrl_dev *pctldev,
267 struct device_node *np,
268 struct pinctrl_map **map, unsigned *num_maps)
269 {
270 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
271 const struct at91_pin_group *grp;
272 struct pinctrl_map *new_map;
273 struct device_node *parent;
274 int map_num = 1;
275 int i;
276
277 /*
278 * first find the group of this node and check if we need to create
279 * config maps for pins
280 */
281 grp = at91_pinctrl_find_group_by_name(info, np->name);
282 if (!grp) {
283 dev_err(info->dev, "unable to find group for node %pOFn\n",
284 np);
285 return -EINVAL;
286 }
287
288 map_num += grp->npins;
289 new_map = devm_kcalloc(pctldev->dev, map_num, sizeof(*new_map),
290 GFP_KERNEL);
291 if (!new_map)
292 return -ENOMEM;
293
294 *map = new_map;
295 *num_maps = map_num;
296
297 /* create mux map */
298 parent = of_get_parent(np);
299 if (!parent) {
300 devm_kfree(pctldev->dev, new_map);
301 return -EINVAL;
302 }
303 new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
304 new_map[0].data.mux.function = parent->name;
305 new_map[0].data.mux.group = np->name;
306 of_node_put(parent);
307
308 /* create config map */
309 new_map++;
310 for (i = 0; i < grp->npins; i++) {
311 new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN;
312 new_map[i].data.configs.group_or_pin =
313 pin_get_name(pctldev, grp->pins[i]);
314 new_map[i].data.configs.configs = &grp->pins_conf[i].conf;
315 new_map[i].data.configs.num_configs = 1;
316 }
317
318 dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n",
319 (*map)->data.mux.function, (*map)->data.mux.group, map_num);
320
321 return 0;
322 }
323
324 static void at91_dt_free_map(struct pinctrl_dev *pctldev,
325 struct pinctrl_map *map, unsigned num_maps)
326 {
327 }
328
329 static const struct pinctrl_ops at91_pctrl_ops = {
330 .get_groups_count = at91_get_groups_count,
331 .get_group_name = at91_get_group_name,
332 .get_group_pins = at91_get_group_pins,
333 .pin_dbg_show = at91_pin_dbg_show,
334 .dt_node_to_map = at91_dt_node_to_map,
335 .dt_free_map = at91_dt_free_map,
336 };
337
338 static void __iomem *pin_to_controller(struct at91_pinctrl *info,
339 unsigned int bank)
340 {
341 if (!gpio_chips[bank])
342 return NULL;
343
344 return gpio_chips[bank]->regbase;
345 }
346
347 static inline int pin_to_bank(unsigned pin)
348 {
349 return pin /= MAX_NB_GPIO_PER_BANK;
350 }
351
352 static unsigned pin_to_mask(unsigned int pin)
353 {
354 return 1 << pin;
355 }
356
357 static unsigned two_bit_pin_value_shift_amount(unsigned int pin)
358 {
359 /* return the shift value for a pin for "two bit" per pin registers,
360 * i.e. drive strength */
361 return 2*((pin >= MAX_NB_GPIO_PER_BANK/2)
362 ? pin - MAX_NB_GPIO_PER_BANK/2 : pin);
363 }
364
365 static unsigned sama5d3_get_drive_register(unsigned int pin)
366 {
367 /* drive strength is split between two registers
368 * with two bits per pin */
369 return (pin >= MAX_NB_GPIO_PER_BANK/2)
370 ? SAMA5D3_PIO_DRIVER2 : SAMA5D3_PIO_DRIVER1;
371 }
372
373 static unsigned at91sam9x5_get_drive_register(unsigned int pin)
374 {
375 /* drive strength is split between two registers
376 * with two bits per pin */
377 return (pin >= MAX_NB_GPIO_PER_BANK/2)
378 ? AT91SAM9X5_PIO_DRIVER2 : AT91SAM9X5_PIO_DRIVER1;
379 }
380
381 static void at91_mux_disable_interrupt(void __iomem *pio, unsigned mask)
382 {
383 writel_relaxed(mask, pio + PIO_IDR);
384 }
385
386 static unsigned at91_mux_get_pullup(void __iomem *pio, unsigned pin)
387 {
388 return !((readl_relaxed(pio + PIO_PUSR) >> pin) & 0x1);
389 }
390
391 static void at91_mux_set_pullup(void __iomem *pio, unsigned mask, bool on)
392 {
393 if (on)
394 writel_relaxed(mask, pio + PIO_PPDDR);
395
396 writel_relaxed(mask, pio + (on ? PIO_PUER : PIO_PUDR));
397 }
398
399 static bool at91_mux_get_output(void __iomem *pio, unsigned int pin, bool *val)
400 {
401 *val = (readl_relaxed(pio + PIO_ODSR) >> pin) & 0x1;
402 return (readl_relaxed(pio + PIO_OSR) >> pin) & 0x1;
403 }
404
405 static void at91_mux_set_output(void __iomem *pio, unsigned int mask,
406 bool is_on, bool val)
407 {
408 writel_relaxed(mask, pio + (val ? PIO_SODR : PIO_CODR));
409 writel_relaxed(mask, pio + (is_on ? PIO_OER : PIO_ODR));
410 }
411
412 static unsigned at91_mux_get_multidrive(void __iomem *pio, unsigned pin)
413 {
414 return (readl_relaxed(pio + PIO_MDSR) >> pin) & 0x1;
415 }
416
417 static void at91_mux_set_multidrive(void __iomem *pio, unsigned mask, bool on)
418 {
419 writel_relaxed(mask, pio + (on ? PIO_MDER : PIO_MDDR));
420 }
421
422 static void at91_mux_set_A_periph(void __iomem *pio, unsigned mask)
423 {
424 writel_relaxed(mask, pio + PIO_ASR);
425 }
426
427 static void at91_mux_set_B_periph(void __iomem *pio, unsigned mask)
428 {
429 writel_relaxed(mask, pio + PIO_BSR);
430 }
431
432 static void at91_mux_pio3_set_A_periph(void __iomem *pio, unsigned mask)
433 {
434
435 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) & ~mask,
436 pio + PIO_ABCDSR1);
437 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) & ~mask,
438 pio + PIO_ABCDSR2);
439 }
440
441 static void at91_mux_pio3_set_B_periph(void __iomem *pio, unsigned mask)
442 {
443 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) | mask,
444 pio + PIO_ABCDSR1);
445 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) & ~mask,
446 pio + PIO_ABCDSR2);
447 }
448
449 static void at91_mux_pio3_set_C_periph(void __iomem *pio, unsigned mask)
450 {
451 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) & ~mask, pio + PIO_ABCDSR1);
452 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) | mask, pio + PIO_ABCDSR2);
453 }
454
455 static void at91_mux_pio3_set_D_periph(void __iomem *pio, unsigned mask)
456 {
457 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) | mask, pio + PIO_ABCDSR1);
458 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) | mask, pio + PIO_ABCDSR2);
459 }
460
461 static enum at91_mux at91_mux_pio3_get_periph(void __iomem *pio, unsigned mask)
462 {
463 unsigned select;
464
465 if (readl_relaxed(pio + PIO_PSR) & mask)
466 return AT91_MUX_GPIO;
467
468 select = !!(readl_relaxed(pio + PIO_ABCDSR1) & mask);
469 select |= (!!(readl_relaxed(pio + PIO_ABCDSR2) & mask) << 1);
470
471 return select + 1;
472 }
473
474 static enum at91_mux at91_mux_get_periph(void __iomem *pio, unsigned mask)
475 {
476 unsigned select;
477
478 if (readl_relaxed(pio + PIO_PSR) & mask)
479 return AT91_MUX_GPIO;
480
481 select = readl_relaxed(pio + PIO_ABSR) & mask;
482
483 return select + 1;
484 }
485
486 static bool at91_mux_get_deglitch(void __iomem *pio, unsigned pin)
487 {
488 return (readl_relaxed(pio + PIO_IFSR) >> pin) & 0x1;
489 }
490
491 static void at91_mux_set_deglitch(void __iomem *pio, unsigned mask, bool is_on)
492 {
493 writel_relaxed(mask, pio + (is_on ? PIO_IFER : PIO_IFDR));
494 }
495
496 static bool at91_mux_pio3_get_deglitch(void __iomem *pio, unsigned pin)
497 {
498 if ((readl_relaxed(pio + PIO_IFSR) >> pin) & 0x1)
499 return !((readl_relaxed(pio + PIO_IFSCSR) >> pin) & 0x1);
500
501 return false;
502 }
503
504 static void at91_mux_pio3_set_deglitch(void __iomem *pio, unsigned mask, bool is_on)
505 {
506 if (is_on)
507 writel_relaxed(mask, pio + PIO_IFSCDR);
508 at91_mux_set_deglitch(pio, mask, is_on);
509 }
510
511 static bool at91_mux_pio3_get_debounce(void __iomem *pio, unsigned pin, u32 *div)
512 {
513 *div = readl_relaxed(pio + PIO_SCDR);
514
515 return ((readl_relaxed(pio + PIO_IFSR) >> pin) & 0x1) &&
516 ((readl_relaxed(pio + PIO_IFSCSR) >> pin) & 0x1);
517 }
518
519 static void at91_mux_pio3_set_debounce(void __iomem *pio, unsigned mask,
520 bool is_on, u32 div)
521 {
522 if (is_on) {
523 writel_relaxed(mask, pio + PIO_IFSCER);
524 writel_relaxed(div & PIO_SCDR_DIV, pio + PIO_SCDR);
525 writel_relaxed(mask, pio + PIO_IFER);
526 } else
527 writel_relaxed(mask, pio + PIO_IFSCDR);
528 }
529
530 static bool at91_mux_pio3_get_pulldown(void __iomem *pio, unsigned pin)
531 {
532 return !((readl_relaxed(pio + PIO_PPDSR) >> pin) & 0x1);
533 }
534
535 static void at91_mux_pio3_set_pulldown(void __iomem *pio, unsigned mask, bool is_on)
536 {
537 if (is_on)
538 writel_relaxed(mask, pio + PIO_PUDR);
539
540 writel_relaxed(mask, pio + (is_on ? PIO_PPDER : PIO_PPDDR));
541 }
542
543 static void at91_mux_pio3_disable_schmitt_trig(void __iomem *pio, unsigned mask)
544 {
545 writel_relaxed(readl_relaxed(pio + PIO_SCHMITT) | mask, pio + PIO_SCHMITT);
546 }
547
548 static bool at91_mux_pio3_get_schmitt_trig(void __iomem *pio, unsigned pin)
549 {
550 return (readl_relaxed(pio + PIO_SCHMITT) >> pin) & 0x1;
551 }
552
553 static inline u32 read_drive_strength(void __iomem *reg, unsigned pin)
554 {
555 unsigned tmp = readl_relaxed(reg);
556
557 tmp = tmp >> two_bit_pin_value_shift_amount(pin);
558
559 return tmp & DRIVE_STRENGTH_MASK;
560 }
561
562 static unsigned at91_mux_sama5d3_get_drivestrength(void __iomem *pio,
563 unsigned pin)
564 {
565 unsigned tmp = read_drive_strength(pio +
566 sama5d3_get_drive_register(pin), pin);
567
568 /* SAMA5 strength is 1:1 with our defines,
569 * except 0 is equivalent to low per datasheet */
570 if (!tmp)
571 tmp = DRIVE_STRENGTH_BIT_MSK(LOW);
572
573 return tmp;
574 }
575
576 static unsigned at91_mux_sam9x5_get_drivestrength(void __iomem *pio,
577 unsigned pin)
578 {
579 unsigned tmp = read_drive_strength(pio +
580 at91sam9x5_get_drive_register(pin), pin);
581
582 /* strength is inverse in SAM9x5s hardware with the pinctrl defines
583 * hardware: 0 = hi, 1 = med, 2 = low, 3 = rsvd */
584 tmp = DRIVE_STRENGTH_BIT_MSK(HI) - tmp;
585
586 return tmp;
587 }
588
589 static unsigned at91_mux_sam9x60_get_drivestrength(void __iomem *pio,
590 unsigned pin)
591 {
592 unsigned tmp = readl_relaxed(pio + SAM9X60_PIO_DRIVER1);
593
594 if (tmp & BIT(pin))
595 return DRIVE_STRENGTH_BIT_HI;
596
597 return DRIVE_STRENGTH_BIT_LOW;
598 }
599
600 static unsigned at91_mux_sam9x60_get_slewrate(void __iomem *pio, unsigned pin)
601 {
602 unsigned tmp = readl_relaxed(pio + SAM9X60_PIO_SLEWR);
603
604 if ((tmp & BIT(pin)))
605 return SLEWRATE_BIT_ENA;
606
607 return SLEWRATE_BIT_DIS;
608 }
609
610 static void set_drive_strength(void __iomem *reg, unsigned pin, u32 strength)
611 {
612 unsigned tmp = readl_relaxed(reg);
613 unsigned shift = two_bit_pin_value_shift_amount(pin);
614
615 tmp &= ~(DRIVE_STRENGTH_MASK << shift);
616 tmp |= strength << shift;
617
618 writel_relaxed(tmp, reg);
619 }
620
621 static void at91_mux_sama5d3_set_drivestrength(void __iomem *pio, unsigned pin,
622 u32 setting)
623 {
624 /* do nothing if setting is zero */
625 if (!setting)
626 return;
627
628 /* strength is 1 to 1 with setting for SAMA5 */
629 set_drive_strength(pio + sama5d3_get_drive_register(pin), pin, setting);
630 }
631
632 static void at91_mux_sam9x5_set_drivestrength(void __iomem *pio, unsigned pin,
633 u32 setting)
634 {
635 /* do nothing if setting is zero */
636 if (!setting)
637 return;
638
639 /* strength is inverse on SAM9x5s with our defines
640 * 0 = hi, 1 = med, 2 = low, 3 = rsvd */
641 setting = DRIVE_STRENGTH_BIT_MSK(HI) - setting;
642
643 set_drive_strength(pio + at91sam9x5_get_drive_register(pin), pin,
644 setting);
645 }
646
647 static void at91_mux_sam9x60_set_drivestrength(void __iomem *pio, unsigned pin,
648 u32 setting)
649 {
650 unsigned int tmp;
651
652 if (setting <= DRIVE_STRENGTH_BIT_DEF ||
653 setting == DRIVE_STRENGTH_BIT_MED ||
654 setting > DRIVE_STRENGTH_BIT_HI)
655 return;
656
657 tmp = readl_relaxed(pio + SAM9X60_PIO_DRIVER1);
658
659 /* Strength is 0: low, 1: hi */
660 if (setting == DRIVE_STRENGTH_BIT_LOW)
661 tmp &= ~BIT(pin);
662 else
663 tmp |= BIT(pin);
664
665 writel_relaxed(tmp, pio + SAM9X60_PIO_DRIVER1);
666 }
667
668 static void at91_mux_sam9x60_set_slewrate(void __iomem *pio, unsigned pin,
669 u32 setting)
670 {
671 unsigned int tmp;
672
673 if (setting < SLEWRATE_BIT_DIS || setting > SLEWRATE_BIT_ENA)
674 return;
675
676 tmp = readl_relaxed(pio + SAM9X60_PIO_SLEWR);
677
678 if (setting == SLEWRATE_BIT_DIS)
679 tmp &= ~BIT(pin);
680 else
681 tmp |= BIT(pin);
682
683 writel_relaxed(tmp, pio + SAM9X60_PIO_SLEWR);
684 }
685
686 static struct at91_pinctrl_mux_ops at91rm9200_ops = {
687 .get_periph = at91_mux_get_periph,
688 .mux_A_periph = at91_mux_set_A_periph,
689 .mux_B_periph = at91_mux_set_B_periph,
690 .get_deglitch = at91_mux_get_deglitch,
691 .set_deglitch = at91_mux_set_deglitch,
692 .irq_type = gpio_irq_type,
693 };
694
695 static struct at91_pinctrl_mux_ops at91sam9x5_ops = {
696 .get_periph = at91_mux_pio3_get_periph,
697 .mux_A_periph = at91_mux_pio3_set_A_periph,
698 .mux_B_periph = at91_mux_pio3_set_B_periph,
699 .mux_C_periph = at91_mux_pio3_set_C_periph,
700 .mux_D_periph = at91_mux_pio3_set_D_periph,
701 .get_deglitch = at91_mux_pio3_get_deglitch,
702 .set_deglitch = at91_mux_pio3_set_deglitch,
703 .get_debounce = at91_mux_pio3_get_debounce,
704 .set_debounce = at91_mux_pio3_set_debounce,
705 .get_pulldown = at91_mux_pio3_get_pulldown,
706 .set_pulldown = at91_mux_pio3_set_pulldown,
707 .get_schmitt_trig = at91_mux_pio3_get_schmitt_trig,
708 .disable_schmitt_trig = at91_mux_pio3_disable_schmitt_trig,
709 .get_drivestrength = at91_mux_sam9x5_get_drivestrength,
710 .set_drivestrength = at91_mux_sam9x5_set_drivestrength,
711 .irq_type = alt_gpio_irq_type,
712 };
713
714 static const struct at91_pinctrl_mux_ops sam9x60_ops = {
715 .get_periph = at91_mux_pio3_get_periph,
716 .mux_A_periph = at91_mux_pio3_set_A_periph,
717 .mux_B_periph = at91_mux_pio3_set_B_periph,
718 .mux_C_periph = at91_mux_pio3_set_C_periph,
719 .mux_D_periph = at91_mux_pio3_set_D_periph,
720 .get_deglitch = at91_mux_pio3_get_deglitch,
721 .set_deglitch = at91_mux_pio3_set_deglitch,
722 .get_debounce = at91_mux_pio3_get_debounce,
723 .set_debounce = at91_mux_pio3_set_debounce,
724 .get_pulldown = at91_mux_pio3_get_pulldown,
725 .set_pulldown = at91_mux_pio3_set_pulldown,
726 .get_schmitt_trig = at91_mux_pio3_get_schmitt_trig,
727 .disable_schmitt_trig = at91_mux_pio3_disable_schmitt_trig,
728 .get_drivestrength = at91_mux_sam9x60_get_drivestrength,
729 .set_drivestrength = at91_mux_sam9x60_set_drivestrength,
730 .get_slewrate = at91_mux_sam9x60_get_slewrate,
731 .set_slewrate = at91_mux_sam9x60_set_slewrate,
732 .irq_type = alt_gpio_irq_type,
733
734 };
735
736 static struct at91_pinctrl_mux_ops sama5d3_ops = {
737 .get_periph = at91_mux_pio3_get_periph,
738 .mux_A_periph = at91_mux_pio3_set_A_periph,
739 .mux_B_periph = at91_mux_pio3_set_B_periph,
740 .mux_C_periph = at91_mux_pio3_set_C_periph,
741 .mux_D_periph = at91_mux_pio3_set_D_periph,
742 .get_deglitch = at91_mux_pio3_get_deglitch,
743 .set_deglitch = at91_mux_pio3_set_deglitch,
744 .get_debounce = at91_mux_pio3_get_debounce,
745 .set_debounce = at91_mux_pio3_set_debounce,
746 .get_pulldown = at91_mux_pio3_get_pulldown,
747 .set_pulldown = at91_mux_pio3_set_pulldown,
748 .get_schmitt_trig = at91_mux_pio3_get_schmitt_trig,
749 .disable_schmitt_trig = at91_mux_pio3_disable_schmitt_trig,
750 .get_drivestrength = at91_mux_sama5d3_get_drivestrength,
751 .set_drivestrength = at91_mux_sama5d3_set_drivestrength,
752 .irq_type = alt_gpio_irq_type,
753 };
754
755 static void at91_pin_dbg(const struct device *dev, const struct at91_pmx_pin *pin)
756 {
757 if (pin->mux) {
758 dev_dbg(dev, "pio%c%d configured as periph%c with conf = 0x%lx\n",
759 pin->bank + 'A', pin->pin, pin->mux - 1 + 'A', pin->conf);
760 } else {
761 dev_dbg(dev, "pio%c%d configured as gpio with conf = 0x%lx\n",
762 pin->bank + 'A', pin->pin, pin->conf);
763 }
764 }
765
766 static int pin_check_config(struct at91_pinctrl *info, const char *name,
767 int index, const struct at91_pmx_pin *pin)
768 {
769 int mux;
770
771 /* check if it's a valid config */
772 if (pin->bank >= gpio_banks) {
773 dev_err(info->dev, "%s: pin conf %d bank_id %d >= nbanks %d\n",
774 name, index, pin->bank, gpio_banks);
775 return -EINVAL;
776 }
777
778 if (!gpio_chips[pin->bank]) {
779 dev_err(info->dev, "%s: pin conf %d bank_id %d not enabled\n",
780 name, index, pin->bank);
781 return -ENXIO;
782 }
783
784 if (pin->pin >= MAX_NB_GPIO_PER_BANK) {
785 dev_err(info->dev, "%s: pin conf %d pin_bank_id %d >= %d\n",
786 name, index, pin->pin, MAX_NB_GPIO_PER_BANK);
787 return -EINVAL;
788 }
789
790 if (!pin->mux)
791 return 0;
792
793 mux = pin->mux - 1;
794
795 if (mux >= info->nmux) {
796 dev_err(info->dev, "%s: pin conf %d mux_id %d >= nmux %d\n",
797 name, index, mux, info->nmux);
798 return -EINVAL;
799 }
800
801 if (!(info->mux_mask[pin->bank * info->nmux + mux] & 1 << pin->pin)) {
802 dev_err(info->dev, "%s: pin conf %d mux_id %d not supported for pio%c%d\n",
803 name, index, mux, pin->bank + 'A', pin->pin);
804 return -EINVAL;
805 }
806
807 return 0;
808 }
809
810 static void at91_mux_gpio_disable(void __iomem *pio, unsigned mask)
811 {
812 writel_relaxed(mask, pio + PIO_PDR);
813 }
814
815 static void at91_mux_gpio_enable(void __iomem *pio, unsigned mask, bool input)
816 {
817 writel_relaxed(mask, pio + PIO_PER);
818 writel_relaxed(mask, pio + (input ? PIO_ODR : PIO_OER));
819 }
820
821 static int at91_pmx_set(struct pinctrl_dev *pctldev, unsigned selector,
822 unsigned group)
823 {
824 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
825 const struct at91_pmx_pin *pins_conf = info->groups[group].pins_conf;
826 const struct at91_pmx_pin *pin;
827 uint32_t npins = info->groups[group].npins;
828 int i, ret;
829 unsigned mask;
830 void __iomem *pio;
831
832 dev_dbg(info->dev, "enable function %s group %s\n",
833 info->functions[selector].name, info->groups[group].name);
834
835 /* first check that all the pins of the group are valid with a valid
836 * parameter */
837 for (i = 0; i < npins; i++) {
838 pin = &pins_conf[i];
839 ret = pin_check_config(info, info->groups[group].name, i, pin);
840 if (ret)
841 return ret;
842 }
843
844 for (i = 0; i < npins; i++) {
845 pin = &pins_conf[i];
846 at91_pin_dbg(info->dev, pin);
847 pio = pin_to_controller(info, pin->bank);
848
849 if (!pio)
850 continue;
851
852 mask = pin_to_mask(pin->pin);
853 at91_mux_disable_interrupt(pio, mask);
854 switch (pin->mux) {
855 case AT91_MUX_GPIO:
856 at91_mux_gpio_enable(pio, mask, 1);
857 break;
858 case AT91_MUX_PERIPH_A:
859 info->ops->mux_A_periph(pio, mask);
860 break;
861 case AT91_MUX_PERIPH_B:
862 info->ops->mux_B_periph(pio, mask);
863 break;
864 case AT91_MUX_PERIPH_C:
865 if (!info->ops->mux_C_periph)
866 return -EINVAL;
867 info->ops->mux_C_periph(pio, mask);
868 break;
869 case AT91_MUX_PERIPH_D:
870 if (!info->ops->mux_D_periph)
871 return -EINVAL;
872 info->ops->mux_D_periph(pio, mask);
873 break;
874 }
875 if (pin->mux)
876 at91_mux_gpio_disable(pio, mask);
877 }
878
879 return 0;
880 }
881
882 static int at91_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
883 {
884 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
885
886 return info->nfunctions;
887 }
888
889 static const char *at91_pmx_get_func_name(struct pinctrl_dev *pctldev,
890 unsigned selector)
891 {
892 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
893
894 return info->functions[selector].name;
895 }
896
897 static int at91_pmx_get_groups(struct pinctrl_dev *pctldev, unsigned selector,
898 const char * const **groups,
899 unsigned * const num_groups)
900 {
901 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
902
903 *groups = info->functions[selector].groups;
904 *num_groups = info->functions[selector].ngroups;
905
906 return 0;
907 }
908
909 static int at91_gpio_request_enable(struct pinctrl_dev *pctldev,
910 struct pinctrl_gpio_range *range,
911 unsigned offset)
912 {
913 struct at91_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
914 struct at91_gpio_chip *at91_chip;
915 struct gpio_chip *chip;
916 unsigned mask;
917
918 if (!range) {
919 dev_err(npct->dev, "invalid range\n");
920 return -EINVAL;
921 }
922 if (!range->gc) {
923 dev_err(npct->dev, "missing GPIO chip in range\n");
924 return -EINVAL;
925 }
926 chip = range->gc;
927 at91_chip = gpiochip_get_data(chip);
928
929 dev_dbg(npct->dev, "enable pin %u as GPIO\n", offset);
930
931 mask = 1 << (offset - chip->base);
932
933 dev_dbg(npct->dev, "enable pin %u as PIO%c%d 0x%x\n",
934 offset, 'A' + range->id, offset - chip->base, mask);
935
936 writel_relaxed(mask, at91_chip->regbase + PIO_PER);
937
938 return 0;
939 }
940
941 static void at91_gpio_disable_free(struct pinctrl_dev *pctldev,
942 struct pinctrl_gpio_range *range,
943 unsigned offset)
944 {
945 struct at91_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
946
947 dev_dbg(npct->dev, "disable pin %u as GPIO\n", offset);
948 /* Set the pin to some default state, GPIO is usually default */
949 }
950
951 static const struct pinmux_ops at91_pmx_ops = {
952 .get_functions_count = at91_pmx_get_funcs_count,
953 .get_function_name = at91_pmx_get_func_name,
954 .get_function_groups = at91_pmx_get_groups,
955 .set_mux = at91_pmx_set,
956 .gpio_request_enable = at91_gpio_request_enable,
957 .gpio_disable_free = at91_gpio_disable_free,
958 };
959
960 static int at91_pinconf_get(struct pinctrl_dev *pctldev,
961 unsigned pin_id, unsigned long *config)
962 {
963 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
964 void __iomem *pio;
965 unsigned pin;
966 int div;
967 bool out;
968
969 *config = 0;
970 dev_dbg(info->dev, "%s:%d, pin_id=%d", __func__, __LINE__, pin_id);
971 pio = pin_to_controller(info, pin_to_bank(pin_id));
972
973 if (!pio)
974 return -EINVAL;
975
976 pin = pin_id % MAX_NB_GPIO_PER_BANK;
977
978 if (at91_mux_get_multidrive(pio, pin))
979 *config |= MULTI_DRIVE;
980
981 if (at91_mux_get_pullup(pio, pin))
982 *config |= PULL_UP;
983
984 if (info->ops->get_deglitch && info->ops->get_deglitch(pio, pin))
985 *config |= DEGLITCH;
986 if (info->ops->get_debounce && info->ops->get_debounce(pio, pin, &div))
987 *config |= DEBOUNCE | (div << DEBOUNCE_VAL_SHIFT);
988 if (info->ops->get_pulldown && info->ops->get_pulldown(pio, pin))
989 *config |= PULL_DOWN;
990 if (info->ops->get_schmitt_trig && info->ops->get_schmitt_trig(pio, pin))
991 *config |= DIS_SCHMIT;
992 if (info->ops->get_drivestrength)
993 *config |= (info->ops->get_drivestrength(pio, pin)
994 << DRIVE_STRENGTH_SHIFT);
995 if (info->ops->get_slewrate)
996 *config |= (info->ops->get_slewrate(pio, pin) << SLEWRATE_SHIFT);
997 if (at91_mux_get_output(pio, pin, &out))
998 *config |= OUTPUT | (out << OUTPUT_VAL_SHIFT);
999
1000 return 0;
1001 }
1002
1003 static int at91_pinconf_set(struct pinctrl_dev *pctldev,
1004 unsigned pin_id, unsigned long *configs,
1005 unsigned num_configs)
1006 {
1007 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
1008 unsigned mask;
1009 void __iomem *pio;
1010 int i;
1011 unsigned long config;
1012 unsigned pin;
1013
1014 for (i = 0; i < num_configs; i++) {
1015 config = configs[i];
1016
1017 dev_dbg(info->dev,
1018 "%s:%d, pin_id=%d, config=0x%lx",
1019 __func__, __LINE__, pin_id, config);
1020 pio = pin_to_controller(info, pin_to_bank(pin_id));
1021
1022 if (!pio)
1023 return -EINVAL;
1024
1025 pin = pin_id % MAX_NB_GPIO_PER_BANK;
1026 mask = pin_to_mask(pin);
1027
1028 if (config & PULL_UP && config & PULL_DOWN)
1029 return -EINVAL;
1030
1031 at91_mux_set_output(pio, mask, config & OUTPUT,
1032 (config & OUTPUT_VAL) >> OUTPUT_VAL_SHIFT);
1033 at91_mux_set_pullup(pio, mask, config & PULL_UP);
1034 at91_mux_set_multidrive(pio, mask, config & MULTI_DRIVE);
1035 if (info->ops->set_deglitch)
1036 info->ops->set_deglitch(pio, mask, config & DEGLITCH);
1037 if (info->ops->set_debounce)
1038 info->ops->set_debounce(pio, mask, config & DEBOUNCE,
1039 (config & DEBOUNCE_VAL) >> DEBOUNCE_VAL_SHIFT);
1040 if (info->ops->set_pulldown)
1041 info->ops->set_pulldown(pio, mask, config & PULL_DOWN);
1042 if (info->ops->disable_schmitt_trig && config & DIS_SCHMIT)
1043 info->ops->disable_schmitt_trig(pio, mask);
1044 if (info->ops->set_drivestrength)
1045 info->ops->set_drivestrength(pio, pin,
1046 (config & DRIVE_STRENGTH)
1047 >> DRIVE_STRENGTH_SHIFT);
1048 if (info->ops->set_slewrate)
1049 info->ops->set_slewrate(pio, pin,
1050 (config & SLEWRATE) >> SLEWRATE_SHIFT);
1051
1052 } /* for each config */
1053
1054 return 0;
1055 }
1056
1057 #define DBG_SHOW_FLAG(flag) do { \
1058 if (config & flag) { \
1059 if (num_conf) \
1060 seq_puts(s, "|"); \
1061 seq_puts(s, #flag); \
1062 num_conf++; \
1063 } \
1064 } while (0)
1065
1066 #define DBG_SHOW_FLAG_MASKED(mask, flag, name) do { \
1067 if ((config & mask) == flag) { \
1068 if (num_conf) \
1069 seq_puts(s, "|"); \
1070 seq_puts(s, #name); \
1071 num_conf++; \
1072 } \
1073 } while (0)
1074
1075 static void at91_pinconf_dbg_show(struct pinctrl_dev *pctldev,
1076 struct seq_file *s, unsigned pin_id)
1077 {
1078 unsigned long config;
1079 int val, num_conf = 0;
1080
1081 at91_pinconf_get(pctldev, pin_id, &config);
1082
1083 DBG_SHOW_FLAG(MULTI_DRIVE);
1084 DBG_SHOW_FLAG(PULL_UP);
1085 DBG_SHOW_FLAG(PULL_DOWN);
1086 DBG_SHOW_FLAG(DIS_SCHMIT);
1087 DBG_SHOW_FLAG(DEGLITCH);
1088 DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_BIT_MSK(LOW),
1089 DRIVE_STRENGTH_LOW);
1090 DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_BIT_MSK(MED),
1091 DRIVE_STRENGTH_MED);
1092 DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_BIT_MSK(HI),
1093 DRIVE_STRENGTH_HI);
1094 DBG_SHOW_FLAG(SLEWRATE);
1095 DBG_SHOW_FLAG(DEBOUNCE);
1096 if (config & DEBOUNCE) {
1097 val = config >> DEBOUNCE_VAL_SHIFT;
1098 seq_printf(s, "(%d)", val);
1099 }
1100
1101 return;
1102 }
1103
1104 static void at91_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
1105 struct seq_file *s, unsigned group)
1106 {
1107 }
1108
1109 static const struct pinconf_ops at91_pinconf_ops = {
1110 .pin_config_get = at91_pinconf_get,
1111 .pin_config_set = at91_pinconf_set,
1112 .pin_config_dbg_show = at91_pinconf_dbg_show,
1113 .pin_config_group_dbg_show = at91_pinconf_group_dbg_show,
1114 };
1115
1116 static struct pinctrl_desc at91_pinctrl_desc = {
1117 .pctlops = &at91_pctrl_ops,
1118 .pmxops = &at91_pmx_ops,
1119 .confops = &at91_pinconf_ops,
1120 .owner = THIS_MODULE,
1121 };
1122
1123 static const char *gpio_compat = "atmel,at91rm9200-gpio";
1124
1125 static void at91_pinctrl_child_count(struct at91_pinctrl *info,
1126 struct device_node *np)
1127 {
1128 struct device_node *child;
1129
1130 for_each_child_of_node(np, child) {
1131 if (of_device_is_compatible(child, gpio_compat)) {
1132 if (of_device_is_available(child))
1133 info->nactive_banks++;
1134 } else {
1135 info->nfunctions++;
1136 info->ngroups += of_get_child_count(child);
1137 }
1138 }
1139 }
1140
1141 static int at91_pinctrl_mux_mask(struct at91_pinctrl *info,
1142 struct device_node *np)
1143 {
1144 int ret = 0;
1145 int size;
1146 const __be32 *list;
1147
1148 list = of_get_property(np, "atmel,mux-mask", &size);
1149 if (!list) {
1150 dev_err(info->dev, "can not read the mux-mask of %d\n", size);
1151 return -EINVAL;
1152 }
1153
1154 size /= sizeof(*list);
1155 if (!size || size % gpio_banks) {
1156 dev_err(info->dev, "wrong mux mask array should be by %d\n", gpio_banks);
1157 return -EINVAL;
1158 }
1159 info->nmux = size / gpio_banks;
1160
1161 info->mux_mask = devm_kcalloc(info->dev, size, sizeof(u32),
1162 GFP_KERNEL);
1163 if (!info->mux_mask)
1164 return -ENOMEM;
1165
1166 ret = of_property_read_u32_array(np, "atmel,mux-mask",
1167 info->mux_mask, size);
1168 if (ret)
1169 dev_err(info->dev, "can not read the mux-mask of %d\n", size);
1170 return ret;
1171 }
1172
1173 static int at91_pinctrl_parse_groups(struct device_node *np,
1174 struct at91_pin_group *grp,
1175 struct at91_pinctrl *info, u32 index)
1176 {
1177 struct at91_pmx_pin *pin;
1178 int size;
1179 const __be32 *list;
1180 int i, j;
1181
1182 dev_dbg(info->dev, "group(%d): %pOFn\n", index, np);
1183
1184 /* Initialise group */
1185 grp->name = np->name;
1186
1187 /*
1188 * the binding format is atmel,pins = <bank pin mux CONFIG ...>,
1189 * do sanity check and calculate pins number
1190 */
1191 list = of_get_property(np, "atmel,pins", &size);
1192 /* we do not check return since it's safe node passed down */
1193 size /= sizeof(*list);
1194 if (!size || size % 4) {
1195 dev_err(info->dev, "wrong pins number or pins and configs should be by 4\n");
1196 return -EINVAL;
1197 }
1198
1199 grp->npins = size / 4;
1200 pin = grp->pins_conf = devm_kcalloc(info->dev,
1201 grp->npins,
1202 sizeof(struct at91_pmx_pin),
1203 GFP_KERNEL);
1204 grp->pins = devm_kcalloc(info->dev, grp->npins, sizeof(unsigned int),
1205 GFP_KERNEL);
1206 if (!grp->pins_conf || !grp->pins)
1207 return -ENOMEM;
1208
1209 for (i = 0, j = 0; i < size; i += 4, j++) {
1210 pin->bank = be32_to_cpu(*list++);
1211 pin->pin = be32_to_cpu(*list++);
1212 grp->pins[j] = pin->bank * MAX_NB_GPIO_PER_BANK + pin->pin;
1213 pin->mux = be32_to_cpu(*list++);
1214 pin->conf = be32_to_cpu(*list++);
1215
1216 at91_pin_dbg(info->dev, pin);
1217 pin++;
1218 }
1219
1220 return 0;
1221 }
1222
1223 static int at91_pinctrl_parse_functions(struct device_node *np,
1224 struct at91_pinctrl *info, u32 index)
1225 {
1226 struct device_node *child;
1227 struct at91_pmx_func *func;
1228 struct at91_pin_group *grp;
1229 int ret;
1230 static u32 grp_index;
1231 u32 i = 0;
1232
1233 dev_dbg(info->dev, "parse function(%d): %pOFn\n", index, np);
1234
1235 func = &info->functions[index];
1236
1237 /* Initialise function */
1238 func->name = np->name;
1239 func->ngroups = of_get_child_count(np);
1240 if (func->ngroups == 0) {
1241 dev_err(info->dev, "no groups defined\n");
1242 return -EINVAL;
1243 }
1244 func->groups = devm_kcalloc(info->dev,
1245 func->ngroups, sizeof(char *), GFP_KERNEL);
1246 if (!func->groups)
1247 return -ENOMEM;
1248
1249 for_each_child_of_node(np, child) {
1250 func->groups[i] = child->name;
1251 grp = &info->groups[grp_index++];
1252 ret = at91_pinctrl_parse_groups(child, grp, info, i++);
1253 if (ret) {
1254 of_node_put(child);
1255 return ret;
1256 }
1257 }
1258
1259 return 0;
1260 }
1261
1262 static const struct of_device_id at91_pinctrl_of_match[] = {
1263 { .compatible = "atmel,sama5d3-pinctrl", .data = &sama5d3_ops },
1264 { .compatible = "atmel,at91sam9x5-pinctrl", .data = &at91sam9x5_ops },
1265 { .compatible = "atmel,at91rm9200-pinctrl", .data = &at91rm9200_ops },
1266 { .compatible = "microchip,sam9x60-pinctrl", .data = &sam9x60_ops },
1267 { /* sentinel */ }
1268 };
1269
1270 static int at91_pinctrl_probe_dt(struct platform_device *pdev,
1271 struct at91_pinctrl *info)
1272 {
1273 int ret = 0;
1274 int i, j;
1275 uint32_t *tmp;
1276 struct device_node *np = pdev->dev.of_node;
1277 struct device_node *child;
1278
1279 if (!np)
1280 return -ENODEV;
1281
1282 info->dev = &pdev->dev;
1283 info->ops = (struct at91_pinctrl_mux_ops *)
1284 of_match_device(at91_pinctrl_of_match, &pdev->dev)->data;
1285 at91_pinctrl_child_count(info, np);
1286
1287 if (gpio_banks < 1) {
1288 dev_err(&pdev->dev, "you need to specify at least one gpio-controller\n");
1289 return -EINVAL;
1290 }
1291
1292 ret = at91_pinctrl_mux_mask(info, np);
1293 if (ret)
1294 return ret;
1295
1296 dev_dbg(&pdev->dev, "nmux = %d\n", info->nmux);
1297
1298 dev_dbg(&pdev->dev, "mux-mask\n");
1299 tmp = info->mux_mask;
1300 for (i = 0; i < gpio_banks; i++) {
1301 for (j = 0; j < info->nmux; j++, tmp++) {
1302 dev_dbg(&pdev->dev, "%d:%d\t0x%x\n", i, j, tmp[0]);
1303 }
1304 }
1305
1306 dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions);
1307 dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups);
1308 info->functions = devm_kcalloc(&pdev->dev,
1309 info->nfunctions,
1310 sizeof(struct at91_pmx_func),
1311 GFP_KERNEL);
1312 if (!info->functions)
1313 return -ENOMEM;
1314
1315 info->groups = devm_kcalloc(&pdev->dev,
1316 info->ngroups,
1317 sizeof(struct at91_pin_group),
1318 GFP_KERNEL);
1319 if (!info->groups)
1320 return -ENOMEM;
1321
1322 dev_dbg(&pdev->dev, "nbanks = %d\n", gpio_banks);
1323 dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions);
1324 dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups);
1325
1326 i = 0;
1327
1328 for_each_child_of_node(np, child) {
1329 if (of_device_is_compatible(child, gpio_compat))
1330 continue;
1331 ret = at91_pinctrl_parse_functions(child, info, i++);
1332 if (ret) {
1333 dev_err(&pdev->dev, "failed to parse function\n");
1334 of_node_put(child);
1335 return ret;
1336 }
1337 }
1338
1339 return 0;
1340 }
1341
1342 static int at91_pinctrl_probe(struct platform_device *pdev)
1343 {
1344 struct at91_pinctrl *info;
1345 struct pinctrl_pin_desc *pdesc;
1346 int ret, i, j, k, ngpio_chips_enabled = 0;
1347
1348 info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL);
1349 if (!info)
1350 return -ENOMEM;
1351
1352 ret = at91_pinctrl_probe_dt(pdev, info);
1353 if (ret)
1354 return ret;
1355
1356 /*
1357 * We need all the GPIO drivers to probe FIRST, or we will not be able
1358 * to obtain references to the struct gpio_chip * for them, and we
1359 * need this to proceed.
1360 */
1361 for (i = 0; i < gpio_banks; i++)
1362 if (gpio_chips[i])
1363 ngpio_chips_enabled++;
1364
1365 if (ngpio_chips_enabled < info->nactive_banks) {
1366 dev_warn(&pdev->dev,
1367 "All GPIO chips are not registered yet (%d/%d)\n",
1368 ngpio_chips_enabled, info->nactive_banks);
1369 devm_kfree(&pdev->dev, info);
1370 return -EPROBE_DEFER;
1371 }
1372
1373 at91_pinctrl_desc.name = dev_name(&pdev->dev);
1374 at91_pinctrl_desc.npins = gpio_banks * MAX_NB_GPIO_PER_BANK;
1375 at91_pinctrl_desc.pins = pdesc =
1376 devm_kcalloc(&pdev->dev,
1377 at91_pinctrl_desc.npins, sizeof(*pdesc),
1378 GFP_KERNEL);
1379
1380 if (!at91_pinctrl_desc.pins)
1381 return -ENOMEM;
1382
1383 for (i = 0, k = 0; i < gpio_banks; i++) {
1384 for (j = 0; j < MAX_NB_GPIO_PER_BANK; j++, k++) {
1385 pdesc->number = k;
1386 pdesc->name = kasprintf(GFP_KERNEL, "pio%c%d", i + 'A', j);
1387 pdesc++;
1388 }
1389 }
1390
1391 platform_set_drvdata(pdev, info);
1392 info->pctl = devm_pinctrl_register(&pdev->dev, &at91_pinctrl_desc,
1393 info);
1394
1395 if (IS_ERR(info->pctl)) {
1396 dev_err(&pdev->dev, "could not register AT91 pinctrl driver\n");
1397 return PTR_ERR(info->pctl);
1398 }
1399
1400 /* We will handle a range of GPIO pins */
1401 for (i = 0; i < gpio_banks; i++)
1402 if (gpio_chips[i])
1403 pinctrl_add_gpio_range(info->pctl, &gpio_chips[i]->range);
1404
1405 dev_info(&pdev->dev, "initialized AT91 pinctrl driver\n");
1406
1407 return 0;
1408 }
1409
1410 static int at91_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
1411 {
1412 struct at91_gpio_chip *at91_gpio = gpiochip_get_data(chip);
1413 void __iomem *pio = at91_gpio->regbase;
1414 unsigned mask = 1 << offset;
1415 u32 osr;
1416
1417 osr = readl_relaxed(pio + PIO_OSR);
1418 return !(osr & mask);
1419 }
1420
1421 static int at91_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
1422 {
1423 struct at91_gpio_chip *at91_gpio = gpiochip_get_data(chip);
1424 void __iomem *pio = at91_gpio->regbase;
1425 unsigned mask = 1 << offset;
1426
1427 writel_relaxed(mask, pio + PIO_ODR);
1428 return 0;
1429 }
1430
1431 static int at91_gpio_get(struct gpio_chip *chip, unsigned offset)
1432 {
1433 struct at91_gpio_chip *at91_gpio = gpiochip_get_data(chip);
1434 void __iomem *pio = at91_gpio->regbase;
1435 unsigned mask = 1 << offset;
1436 u32 pdsr;
1437
1438 pdsr = readl_relaxed(pio + PIO_PDSR);
1439 return (pdsr & mask) != 0;
1440 }
1441
1442 static void at91_gpio_set(struct gpio_chip *chip, unsigned offset,
1443 int val)
1444 {
1445 struct at91_gpio_chip *at91_gpio = gpiochip_get_data(chip);
1446 void __iomem *pio = at91_gpio->regbase;
1447 unsigned mask = 1 << offset;
1448
1449 writel_relaxed(mask, pio + (val ? PIO_SODR : PIO_CODR));
1450 }
1451
1452 static void at91_gpio_set_multiple(struct gpio_chip *chip,
1453 unsigned long *mask, unsigned long *bits)
1454 {
1455 struct at91_gpio_chip *at91_gpio = gpiochip_get_data(chip);
1456 void __iomem *pio = at91_gpio->regbase;
1457
1458 #define BITS_MASK(bits) (((bits) == 32) ? ~0U : (BIT(bits) - 1))
1459 /* Mask additionally to ngpio as not all GPIO controllers have 32 pins */
1460 uint32_t set_mask = (*mask & *bits) & BITS_MASK(chip->ngpio);
1461 uint32_t clear_mask = (*mask & ~(*bits)) & BITS_MASK(chip->ngpio);
1462
1463 writel_relaxed(set_mask, pio + PIO_SODR);
1464 writel_relaxed(clear_mask, pio + PIO_CODR);
1465 }
1466
1467 static int at91_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
1468 int val)
1469 {
1470 struct at91_gpio_chip *at91_gpio = gpiochip_get_data(chip);
1471 void __iomem *pio = at91_gpio->regbase;
1472 unsigned mask = 1 << offset;
1473
1474 writel_relaxed(mask, pio + (val ? PIO_SODR : PIO_CODR));
1475 writel_relaxed(mask, pio + PIO_OER);
1476
1477 return 0;
1478 }
1479
1480 #ifdef CONFIG_DEBUG_FS
1481 static void at91_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
1482 {
1483 enum at91_mux mode;
1484 int i;
1485 struct at91_gpio_chip *at91_gpio = gpiochip_get_data(chip);
1486 void __iomem *pio = at91_gpio->regbase;
1487
1488 for (i = 0; i < chip->ngpio; i++) {
1489 unsigned mask = pin_to_mask(i);
1490 const char *gpio_label;
1491
1492 gpio_label = gpiochip_is_requested(chip, i);
1493 if (!gpio_label)
1494 continue;
1495 mode = at91_gpio->ops->get_periph(pio, mask);
1496 seq_printf(s, "[%s] GPIO%s%d: ",
1497 gpio_label, chip->label, i);
1498 if (mode == AT91_MUX_GPIO) {
1499 seq_printf(s, "[gpio] ");
1500 seq_printf(s, "%s ",
1501 readl_relaxed(pio + PIO_OSR) & mask ?
1502 "output" : "input");
1503 seq_printf(s, "%s\n",
1504 readl_relaxed(pio + PIO_PDSR) & mask ?
1505 "set" : "clear");
1506 } else {
1507 seq_printf(s, "[periph %c]\n",
1508 mode + 'A' - 1);
1509 }
1510 }
1511 }
1512 #else
1513 #define at91_gpio_dbg_show NULL
1514 #endif
1515
1516 /* Several AIC controller irqs are dispatched through this GPIO handler.
1517 * To use any AT91_PIN_* as an externally triggered IRQ, first call
1518 * at91_set_gpio_input() then maybe enable its glitch filter.
1519 * Then just request_irq() with the pin ID; it works like any ARM IRQ
1520 * handler.
1521 * First implementation always triggers on rising and falling edges
1522 * whereas the newer PIO3 can be additionally configured to trigger on
1523 * level, edge with any polarity.
1524 *
1525 * Alternatively, certain pins may be used directly as IRQ0..IRQ6 after
1526 * configuring them with at91_set_a_periph() or at91_set_b_periph().
1527 * IRQ0..IRQ6 should be configurable, e.g. level vs edge triggering.
1528 */
1529
1530 static void gpio_irq_mask(struct irq_data *d)
1531 {
1532 struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
1533 void __iomem *pio = at91_gpio->regbase;
1534 unsigned mask = 1 << d->hwirq;
1535
1536 if (pio)
1537 writel_relaxed(mask, pio + PIO_IDR);
1538 }
1539
1540 static void gpio_irq_unmask(struct irq_data *d)
1541 {
1542 struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
1543 void __iomem *pio = at91_gpio->regbase;
1544 unsigned mask = 1 << d->hwirq;
1545
1546 if (pio)
1547 writel_relaxed(mask, pio + PIO_IER);
1548 }
1549
1550 static int gpio_irq_type(struct irq_data *d, unsigned type)
1551 {
1552 switch (type) {
1553 case IRQ_TYPE_NONE:
1554 case IRQ_TYPE_EDGE_BOTH:
1555 return 0;
1556 default:
1557 return -EINVAL;
1558 }
1559 }
1560
1561 /* Alternate irq type for PIO3 support */
1562 static int alt_gpio_irq_type(struct irq_data *d, unsigned type)
1563 {
1564 struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
1565 void __iomem *pio = at91_gpio->regbase;
1566 unsigned mask = 1 << d->hwirq;
1567
1568 switch (type) {
1569 case IRQ_TYPE_EDGE_RISING:
1570 irq_set_handler_locked(d, handle_simple_irq);
1571 writel_relaxed(mask, pio + PIO_ESR);
1572 writel_relaxed(mask, pio + PIO_REHLSR);
1573 break;
1574 case IRQ_TYPE_EDGE_FALLING:
1575 irq_set_handler_locked(d, handle_simple_irq);
1576 writel_relaxed(mask, pio + PIO_ESR);
1577 writel_relaxed(mask, pio + PIO_FELLSR);
1578 break;
1579 case IRQ_TYPE_LEVEL_LOW:
1580 irq_set_handler_locked(d, handle_level_irq);
1581 writel_relaxed(mask, pio + PIO_LSR);
1582 writel_relaxed(mask, pio + PIO_FELLSR);
1583 break;
1584 case IRQ_TYPE_LEVEL_HIGH:
1585 irq_set_handler_locked(d, handle_level_irq);
1586 writel_relaxed(mask, pio + PIO_LSR);
1587 writel_relaxed(mask, pio + PIO_REHLSR);
1588 break;
1589 case IRQ_TYPE_EDGE_BOTH:
1590 /*
1591 * disable additional interrupt modes:
1592 * fall back to default behavior
1593 */
1594 irq_set_handler_locked(d, handle_simple_irq);
1595 writel_relaxed(mask, pio + PIO_AIMDR);
1596 return 0;
1597 case IRQ_TYPE_NONE:
1598 default:
1599 pr_warn("AT91: No type for GPIO irq offset %d\n", d->irq);
1600 return -EINVAL;
1601 }
1602
1603 /* enable additional interrupt modes */
1604 writel_relaxed(mask, pio + PIO_AIMER);
1605
1606 return 0;
1607 }
1608
1609 static void gpio_irq_ack(struct irq_data *d)
1610 {
1611 /* the interrupt is already cleared before by reading ISR */
1612 }
1613
1614 #ifdef CONFIG_PM
1615
1616 static u32 wakeups[MAX_GPIO_BANKS];
1617 static u32 backups[MAX_GPIO_BANKS];
1618
1619 static int gpio_irq_set_wake(struct irq_data *d, unsigned state)
1620 {
1621 struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
1622 unsigned bank = at91_gpio->pioc_idx;
1623 unsigned mask = 1 << d->hwirq;
1624
1625 if (unlikely(bank >= MAX_GPIO_BANKS))
1626 return -EINVAL;
1627
1628 if (state)
1629 wakeups[bank] |= mask;
1630 else
1631 wakeups[bank] &= ~mask;
1632
1633 irq_set_irq_wake(at91_gpio->pioc_virq, state);
1634
1635 return 0;
1636 }
1637
1638 void at91_pinctrl_gpio_suspend(void)
1639 {
1640 int i;
1641
1642 for (i = 0; i < gpio_banks; i++) {
1643 void __iomem *pio;
1644
1645 if (!gpio_chips[i])
1646 continue;
1647
1648 pio = gpio_chips[i]->regbase;
1649
1650 backups[i] = readl_relaxed(pio + PIO_IMR);
1651 writel_relaxed(backups[i], pio + PIO_IDR);
1652 writel_relaxed(wakeups[i], pio + PIO_IER);
1653
1654 if (!wakeups[i])
1655 clk_disable_unprepare(gpio_chips[i]->clock);
1656 else
1657 printk(KERN_DEBUG "GPIO-%c may wake for %08x\n",
1658 'A'+i, wakeups[i]);
1659 }
1660 }
1661
1662 void at91_pinctrl_gpio_resume(void)
1663 {
1664 int i;
1665
1666 for (i = 0; i < gpio_banks; i++) {
1667 void __iomem *pio;
1668
1669 if (!gpio_chips[i])
1670 continue;
1671
1672 pio = gpio_chips[i]->regbase;
1673
1674 if (!wakeups[i])
1675 clk_prepare_enable(gpio_chips[i]->clock);
1676
1677 writel_relaxed(wakeups[i], pio + PIO_IDR);
1678 writel_relaxed(backups[i], pio + PIO_IER);
1679 }
1680 }
1681
1682 #else
1683 #define gpio_irq_set_wake NULL
1684 #endif /* CONFIG_PM */
1685
1686 static void gpio_irq_handler(struct irq_desc *desc)
1687 {
1688 struct irq_chip *chip = irq_desc_get_chip(desc);
1689 struct gpio_chip *gpio_chip = irq_desc_get_handler_data(desc);
1690 struct at91_gpio_chip *at91_gpio = gpiochip_get_data(gpio_chip);
1691 void __iomem *pio = at91_gpio->regbase;
1692 unsigned long isr;
1693 int n;
1694
1695 chained_irq_enter(chip, desc);
1696 for (;;) {
1697 /* Reading ISR acks pending (edge triggered) GPIO interrupts.
1698 * When there are none pending, we're finished unless we need
1699 * to process multiple banks (like ID_PIOCDE on sam9263).
1700 */
1701 isr = readl_relaxed(pio + PIO_ISR) & readl_relaxed(pio + PIO_IMR);
1702 if (!isr) {
1703 if (!at91_gpio->next)
1704 break;
1705 at91_gpio = at91_gpio->next;
1706 pio = at91_gpio->regbase;
1707 gpio_chip = &at91_gpio->chip;
1708 continue;
1709 }
1710
1711 for_each_set_bit(n, &isr, BITS_PER_LONG) {
1712 generic_handle_irq(irq_find_mapping(
1713 gpio_chip->irq.domain, n));
1714 }
1715 }
1716 chained_irq_exit(chip, desc);
1717 /* now it may re-trigger */
1718 }
1719
1720 static int at91_gpio_of_irq_setup(struct platform_device *pdev,
1721 struct at91_gpio_chip *at91_gpio)
1722 {
1723 struct gpio_chip *gpiochip_prev = NULL;
1724 struct at91_gpio_chip *prev = NULL;
1725 struct irq_data *d = irq_get_irq_data(at91_gpio->pioc_virq);
1726 struct irq_chip *gpio_irqchip;
1727 int ret, i;
1728
1729 gpio_irqchip = devm_kzalloc(&pdev->dev, sizeof(*gpio_irqchip), GFP_KERNEL);
1730 if (!gpio_irqchip)
1731 return -ENOMEM;
1732
1733 at91_gpio->pioc_hwirq = irqd_to_hwirq(d);
1734
1735 gpio_irqchip->name = "GPIO";
1736 gpio_irqchip->irq_ack = gpio_irq_ack;
1737 gpio_irqchip->irq_disable = gpio_irq_mask;
1738 gpio_irqchip->irq_mask = gpio_irq_mask;
1739 gpio_irqchip->irq_unmask = gpio_irq_unmask;
1740 gpio_irqchip->irq_set_wake = gpio_irq_set_wake,
1741 gpio_irqchip->irq_set_type = at91_gpio->ops->irq_type;
1742
1743 /* Disable irqs of this PIO controller */
1744 writel_relaxed(~0, at91_gpio->regbase + PIO_IDR);
1745
1746 /*
1747 * Let the generic code handle this edge IRQ, the the chained
1748 * handler will perform the actual work of handling the parent
1749 * interrupt.
1750 */
1751 ret = gpiochip_irqchip_add(&at91_gpio->chip,
1752 gpio_irqchip,
1753 0,
1754 handle_edge_irq,
1755 IRQ_TYPE_NONE);
1756 if (ret) {
1757 dev_err(&pdev->dev, "at91_gpio.%d: Couldn't add irqchip to gpiochip.\n",
1758 at91_gpio->pioc_idx);
1759 return ret;
1760 }
1761
1762 /* The top level handler handles one bank of GPIOs, except
1763 * on some SoC it can handle up to three...
1764 * We only set up the handler for the first of the list.
1765 */
1766 gpiochip_prev = irq_get_handler_data(at91_gpio->pioc_virq);
1767 if (!gpiochip_prev) {
1768 /* Then register the chain on the parent IRQ */
1769 gpiochip_set_chained_irqchip(&at91_gpio->chip,
1770 gpio_irqchip,
1771 at91_gpio->pioc_virq,
1772 gpio_irq_handler);
1773 return 0;
1774 }
1775
1776 prev = gpiochip_get_data(gpiochip_prev);
1777
1778 /* we can only have 2 banks before */
1779 for (i = 0; i < 2; i++) {
1780 if (prev->next) {
1781 prev = prev->next;
1782 } else {
1783 prev->next = at91_gpio;
1784 return 0;
1785 }
1786 }
1787
1788 return -EINVAL;
1789 }
1790
1791 /* This structure is replicated for each GPIO block allocated at probe time */
1792 static const struct gpio_chip at91_gpio_template = {
1793 .request = gpiochip_generic_request,
1794 .free = gpiochip_generic_free,
1795 .get_direction = at91_gpio_get_direction,
1796 .direction_input = at91_gpio_direction_input,
1797 .get = at91_gpio_get,
1798 .direction_output = at91_gpio_direction_output,
1799 .set = at91_gpio_set,
1800 .set_multiple = at91_gpio_set_multiple,
1801 .dbg_show = at91_gpio_dbg_show,
1802 .can_sleep = false,
1803 .ngpio = MAX_NB_GPIO_PER_BANK,
1804 };
1805
1806 static const struct of_device_id at91_gpio_of_match[] = {
1807 { .compatible = "atmel,at91sam9x5-gpio", .data = &at91sam9x5_ops, },
1808 { .compatible = "atmel,at91rm9200-gpio", .data = &at91rm9200_ops },
1809 { .compatible = "microchip,sam9x60-gpio", .data = &sam9x60_ops },
1810 { /* sentinel */ }
1811 };
1812
1813 static int at91_gpio_probe(struct platform_device *pdev)
1814 {
1815 struct device_node *np = pdev->dev.of_node;
1816 struct resource *res;
1817 struct at91_gpio_chip *at91_chip = NULL;
1818 struct gpio_chip *chip;
1819 struct pinctrl_gpio_range *range;
1820 int ret = 0;
1821 int irq, i;
1822 int alias_idx = of_alias_get_id(np, "gpio");
1823 uint32_t ngpio;
1824 char **names;
1825
1826 BUG_ON(alias_idx >= ARRAY_SIZE(gpio_chips));
1827 if (gpio_chips[alias_idx]) {
1828 ret = -EBUSY;
1829 goto err;
1830 }
1831
1832 irq = platform_get_irq(pdev, 0);
1833 if (irq < 0) {
1834 ret = irq;
1835 goto err;
1836 }
1837
1838 at91_chip = devm_kzalloc(&pdev->dev, sizeof(*at91_chip), GFP_KERNEL);
1839 if (!at91_chip) {
1840 ret = -ENOMEM;
1841 goto err;
1842 }
1843
1844 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1845 at91_chip->regbase = devm_ioremap_resource(&pdev->dev, res);
1846 if (IS_ERR(at91_chip->regbase)) {
1847 ret = PTR_ERR(at91_chip->regbase);
1848 goto err;
1849 }
1850
1851 at91_chip->ops = (struct at91_pinctrl_mux_ops *)
1852 of_match_device(at91_gpio_of_match, &pdev->dev)->data;
1853 at91_chip->pioc_virq = irq;
1854 at91_chip->pioc_idx = alias_idx;
1855
1856 at91_chip->clock = devm_clk_get(&pdev->dev, NULL);
1857 if (IS_ERR(at91_chip->clock)) {
1858 dev_err(&pdev->dev, "failed to get clock, ignoring.\n");
1859 ret = PTR_ERR(at91_chip->clock);
1860 goto err;
1861 }
1862
1863 ret = clk_prepare_enable(at91_chip->clock);
1864 if (ret) {
1865 dev_err(&pdev->dev, "failed to prepare and enable clock, ignoring.\n");
1866 goto clk_enable_err;
1867 }
1868
1869 at91_chip->chip = at91_gpio_template;
1870
1871 chip = &at91_chip->chip;
1872 chip->of_node = np;
1873 chip->label = dev_name(&pdev->dev);
1874 chip->parent = &pdev->dev;
1875 chip->owner = THIS_MODULE;
1876 chip->base = alias_idx * MAX_NB_GPIO_PER_BANK;
1877
1878 if (!of_property_read_u32(np, "#gpio-lines", &ngpio)) {
1879 if (ngpio >= MAX_NB_GPIO_PER_BANK)
1880 pr_err("at91_gpio.%d, gpio-nb >= %d failback to %d\n",
1881 alias_idx, MAX_NB_GPIO_PER_BANK, MAX_NB_GPIO_PER_BANK);
1882 else
1883 chip->ngpio = ngpio;
1884 }
1885
1886 names = devm_kcalloc(&pdev->dev, chip->ngpio, sizeof(char *),
1887 GFP_KERNEL);
1888
1889 if (!names) {
1890 ret = -ENOMEM;
1891 goto clk_enable_err;
1892 }
1893
1894 for (i = 0; i < chip->ngpio; i++)
1895 names[i] = kasprintf(GFP_KERNEL, "pio%c%d", alias_idx + 'A', i);
1896
1897 chip->names = (const char *const *)names;
1898
1899 range = &at91_chip->range;
1900 range->name = chip->label;
1901 range->id = alias_idx;
1902 range->pin_base = range->base = range->id * MAX_NB_GPIO_PER_BANK;
1903
1904 range->npins = chip->ngpio;
1905 range->gc = chip;
1906
1907 ret = gpiochip_add_data(chip, at91_chip);
1908 if (ret)
1909 goto gpiochip_add_err;
1910
1911 gpio_chips[alias_idx] = at91_chip;
1912 gpio_banks = max(gpio_banks, alias_idx + 1);
1913
1914 ret = at91_gpio_of_irq_setup(pdev, at91_chip);
1915 if (ret)
1916 goto irq_setup_err;
1917
1918 dev_info(&pdev->dev, "at address %p\n", at91_chip->regbase);
1919
1920 return 0;
1921
1922 irq_setup_err:
1923 gpiochip_remove(chip);
1924 gpiochip_add_err:
1925 clk_enable_err:
1926 clk_disable_unprepare(at91_chip->clock);
1927 err:
1928 dev_err(&pdev->dev, "Failure %i for GPIO %i\n", ret, alias_idx);
1929
1930 return ret;
1931 }
1932
1933 static struct platform_driver at91_gpio_driver = {
1934 .driver = {
1935 .name = "gpio-at91",
1936 .of_match_table = at91_gpio_of_match,
1937 },
1938 .probe = at91_gpio_probe,
1939 };
1940
1941 static struct platform_driver at91_pinctrl_driver = {
1942 .driver = {
1943 .name = "pinctrl-at91",
1944 .of_match_table = at91_pinctrl_of_match,
1945 },
1946 .probe = at91_pinctrl_probe,
1947 };
1948
1949 static struct platform_driver * const drivers[] = {
1950 &at91_gpio_driver,
1951 &at91_pinctrl_driver,
1952 };
1953
1954 static int __init at91_pinctrl_init(void)
1955 {
1956 return platform_register_drivers(drivers, ARRAY_SIZE(drivers));
1957 }
1958 arch_initcall(at91_pinctrl_init);
Linux with added FPC-III support