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Linux 5.1.15
[linux/fpc-iii.git] / drivers / pinctrl / pinctrl-zynq.c
blob90fd37e8207bfbabd39b53e45379719c311bad8a
1 /*
2 * Zynq pin controller
3 *
4 * Copyright (C) 2014 Xilinx
5 *
6 * Sören Brinkmann <soren.brinkmann@xilinx.com>
7 *
8 * This program is free software: you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation, either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program. If not, see <http://www.gnu.org/licenses/>.
20 */
21 #include <linux/io.h>
22 #include <linux/mfd/syscon.h>
23 #include <linux/init.h>
24 #include <linux/of.h>
25 #include <linux/platform_device.h>
26 #include <linux/pinctrl/pinctrl.h>
27 #include <linux/pinctrl/pinmux.h>
28 #include <linux/pinctrl/pinconf.h>
29 #include <linux/pinctrl/pinconf-generic.h>
30 #include <linux/regmap.h>
31 #include "pinctrl-utils.h"
32 #include "core.h"
33
34 #define ZYNQ_NUM_MIOS 54
35
36 #define ZYNQ_PCTRL_MIO_MST_TRI0 0x10c
37 #define ZYNQ_PCTRL_MIO_MST_TRI1 0x110
38
39 #define ZYNQ_PINMUX_MUX_SHIFT 1
40 #define ZYNQ_PINMUX_MUX_MASK (0x7f << ZYNQ_PINMUX_MUX_SHIFT)
41
42 /**
43 * struct zynq_pinctrl - driver data
44 * @pctrl: Pinctrl device
45 * @syscon: Syscon regmap
46 * @pctrl_offset: Offset for pinctrl into the @syscon space
47 * @groups: Pingroups
48 * @ngroups: Number of @groups
49 * @funcs: Pinmux functions
50 * @nfuncs: Number of @funcs
51 */
52 struct zynq_pinctrl {
53 struct pinctrl_dev *pctrl;
54 struct regmap *syscon;
55 u32 pctrl_offset;
56 const struct zynq_pctrl_group *groups;
57 unsigned int ngroups;
58 const struct zynq_pinmux_function *funcs;
59 unsigned int nfuncs;
60 };
61
62 struct zynq_pctrl_group {
63 const char *name;
64 const unsigned int *pins;
65 const unsigned int npins;
66 };
67
68 /**
69 * struct zynq_pinmux_function - a pinmux function
70 * @name: Name of the pinmux function.
71 * @groups: List of pingroups for this function.
72 * @ngroups: Number of entries in @groups.
73 * @mux_val: Selector for this function
74 * @mux: Offset of function specific mux
75 * @mux_mask: Mask for function specific selector
76 * @mux_shift: Shift for function specific selector
77 */
78 struct zynq_pinmux_function {
79 const char *name;
80 const char * const *groups;
81 unsigned int ngroups;
82 unsigned int mux_val;
83 u32 mux;
84 u32 mux_mask;
85 u8 mux_shift;
86 };
87
88 enum zynq_pinmux_functions {
89 ZYNQ_PMUX_can0,
90 ZYNQ_PMUX_can1,
91 ZYNQ_PMUX_ethernet0,
92 ZYNQ_PMUX_ethernet1,
93 ZYNQ_PMUX_gpio0,
94 ZYNQ_PMUX_i2c0,
95 ZYNQ_PMUX_i2c1,
96 ZYNQ_PMUX_mdio0,
97 ZYNQ_PMUX_mdio1,
98 ZYNQ_PMUX_qspi0,
99 ZYNQ_PMUX_qspi1,
100 ZYNQ_PMUX_qspi_fbclk,
101 ZYNQ_PMUX_qspi_cs1,
102 ZYNQ_PMUX_spi0,
103 ZYNQ_PMUX_spi1,
104 ZYNQ_PMUX_spi0_ss,
105 ZYNQ_PMUX_spi1_ss,
106 ZYNQ_PMUX_sdio0,
107 ZYNQ_PMUX_sdio0_pc,
108 ZYNQ_PMUX_sdio0_cd,
109 ZYNQ_PMUX_sdio0_wp,
110 ZYNQ_PMUX_sdio1,
111 ZYNQ_PMUX_sdio1_pc,
112 ZYNQ_PMUX_sdio1_cd,
113 ZYNQ_PMUX_sdio1_wp,
114 ZYNQ_PMUX_smc0_nor,
115 ZYNQ_PMUX_smc0_nor_cs1,
116 ZYNQ_PMUX_smc0_nor_addr25,
117 ZYNQ_PMUX_smc0_nand,
118 ZYNQ_PMUX_ttc0,
119 ZYNQ_PMUX_ttc1,
120 ZYNQ_PMUX_uart0,
121 ZYNQ_PMUX_uart1,
122 ZYNQ_PMUX_usb0,
123 ZYNQ_PMUX_usb1,
124 ZYNQ_PMUX_swdt0,
125 ZYNQ_PMUX_MAX_FUNC
126 };
127
128 static const struct pinctrl_pin_desc zynq_pins[] = {
129 PINCTRL_PIN(0, "MIO0"),
130 PINCTRL_PIN(1, "MIO1"),
131 PINCTRL_PIN(2, "MIO2"),
132 PINCTRL_PIN(3, "MIO3"),
133 PINCTRL_PIN(4, "MIO4"),
134 PINCTRL_PIN(5, "MIO5"),
135 PINCTRL_PIN(6, "MIO6"),
136 PINCTRL_PIN(7, "MIO7"),
137 PINCTRL_PIN(8, "MIO8"),
138 PINCTRL_PIN(9, "MIO9"),
139 PINCTRL_PIN(10, "MIO10"),
140 PINCTRL_PIN(11, "MIO11"),
141 PINCTRL_PIN(12, "MIO12"),
142 PINCTRL_PIN(13, "MIO13"),
143 PINCTRL_PIN(14, "MIO14"),
144 PINCTRL_PIN(15, "MIO15"),
145 PINCTRL_PIN(16, "MIO16"),
146 PINCTRL_PIN(17, "MIO17"),
147 PINCTRL_PIN(18, "MIO18"),
148 PINCTRL_PIN(19, "MIO19"),
149 PINCTRL_PIN(20, "MIO20"),
150 PINCTRL_PIN(21, "MIO21"),
151 PINCTRL_PIN(22, "MIO22"),
152 PINCTRL_PIN(23, "MIO23"),
153 PINCTRL_PIN(24, "MIO24"),
154 PINCTRL_PIN(25, "MIO25"),
155 PINCTRL_PIN(26, "MIO26"),
156 PINCTRL_PIN(27, "MIO27"),
157 PINCTRL_PIN(28, "MIO28"),
158 PINCTRL_PIN(29, "MIO29"),
159 PINCTRL_PIN(30, "MIO30"),
160 PINCTRL_PIN(31, "MIO31"),
161 PINCTRL_PIN(32, "MIO32"),
162 PINCTRL_PIN(33, "MIO33"),
163 PINCTRL_PIN(34, "MIO34"),
164 PINCTRL_PIN(35, "MIO35"),
165 PINCTRL_PIN(36, "MIO36"),
166 PINCTRL_PIN(37, "MIO37"),
167 PINCTRL_PIN(38, "MIO38"),
168 PINCTRL_PIN(39, "MIO39"),
169 PINCTRL_PIN(40, "MIO40"),
170 PINCTRL_PIN(41, "MIO41"),
171 PINCTRL_PIN(42, "MIO42"),
172 PINCTRL_PIN(43, "MIO43"),
173 PINCTRL_PIN(44, "MIO44"),
174 PINCTRL_PIN(45, "MIO45"),
175 PINCTRL_PIN(46, "MIO46"),
176 PINCTRL_PIN(47, "MIO47"),
177 PINCTRL_PIN(48, "MIO48"),
178 PINCTRL_PIN(49, "MIO49"),
179 PINCTRL_PIN(50, "MIO50"),
180 PINCTRL_PIN(51, "MIO51"),
181 PINCTRL_PIN(52, "MIO52"),
182 PINCTRL_PIN(53, "MIO53"),
183 PINCTRL_PIN(54, "EMIO_SD0_WP"),
184 PINCTRL_PIN(55, "EMIO_SD0_CD"),
185 PINCTRL_PIN(56, "EMIO_SD1_WP"),
186 PINCTRL_PIN(57, "EMIO_SD1_CD"),
187 };
188
189 /* pin groups */
190 static const unsigned int ethernet0_0_pins[] = {16, 17, 18, 19, 20, 21, 22, 23,
191 24, 25, 26, 27};
192 static const unsigned int ethernet1_0_pins[] = {28, 29, 30, 31, 32, 33, 34, 35,
193 36, 37, 38, 39};
194 static const unsigned int mdio0_0_pins[] = {52, 53};
195 static const unsigned int mdio1_0_pins[] = {52, 53};
196 static const unsigned int qspi0_0_pins[] = {1, 2, 3, 4, 5, 6};
197
198 static const unsigned int qspi1_0_pins[] = {9, 10, 11, 12, 13};
199 static const unsigned int qspi_cs1_pins[] = {0};
200 static const unsigned int qspi_fbclk_pins[] = {8};
201 static const unsigned int spi0_0_pins[] = {16, 17, 21};
202 static const unsigned int spi0_0_ss0_pins[] = {18};
203 static const unsigned int spi0_0_ss1_pins[] = {19};
204 static const unsigned int spi0_0_ss2_pins[] = {20,};
205 static const unsigned int spi0_1_pins[] = {28, 29, 33};
206 static const unsigned int spi0_1_ss0_pins[] = {30};
207 static const unsigned int spi0_1_ss1_pins[] = {31};
208 static const unsigned int spi0_1_ss2_pins[] = {32};
209 static const unsigned int spi0_2_pins[] = {40, 41, 45};
210 static const unsigned int spi0_2_ss0_pins[] = {42};
211 static const unsigned int spi0_2_ss1_pins[] = {43};
212 static const unsigned int spi0_2_ss2_pins[] = {44};
213 static const unsigned int spi1_0_pins[] = {10, 11, 12};
214 static const unsigned int spi1_0_ss0_pins[] = {13};
215 static const unsigned int spi1_0_ss1_pins[] = {14};
216 static const unsigned int spi1_0_ss2_pins[] = {15};
217 static const unsigned int spi1_1_pins[] = {22, 23, 24};
218 static const unsigned int spi1_1_ss0_pins[] = {25};
219 static const unsigned int spi1_1_ss1_pins[] = {26};
220 static const unsigned int spi1_1_ss2_pins[] = {27};
221 static const unsigned int spi1_2_pins[] = {34, 35, 36};
222 static const unsigned int spi1_2_ss0_pins[] = {37};
223 static const unsigned int spi1_2_ss1_pins[] = {38};
224 static const unsigned int spi1_2_ss2_pins[] = {39};
225 static const unsigned int spi1_3_pins[] = {46, 47, 48, 49};
226 static const unsigned int spi1_3_ss0_pins[] = {49};
227 static const unsigned int spi1_3_ss1_pins[] = {50};
228 static const unsigned int spi1_3_ss2_pins[] = {51};
229
230 static const unsigned int sdio0_0_pins[] = {16, 17, 18, 19, 20, 21};
231 static const unsigned int sdio0_1_pins[] = {28, 29, 30, 31, 32, 33};
232 static const unsigned int sdio0_2_pins[] = {40, 41, 42, 43, 44, 45};
233 static const unsigned int sdio1_0_pins[] = {10, 11, 12, 13, 14, 15};
234 static const unsigned int sdio1_1_pins[] = {22, 23, 24, 25, 26, 27};
235 static const unsigned int sdio1_2_pins[] = {34, 35, 36, 37, 38, 39};
236 static const unsigned int sdio1_3_pins[] = {46, 47, 48, 49, 50, 51};
237 static const unsigned int sdio0_emio_wp_pins[] = {54};
238 static const unsigned int sdio0_emio_cd_pins[] = {55};
239 static const unsigned int sdio1_emio_wp_pins[] = {56};
240 static const unsigned int sdio1_emio_cd_pins[] = {57};
241 static const unsigned int smc0_nor_pins[] = {0, 3, 4, 5, 6, 7, 8, 9, 10, 11, 13,
242 15, 16, 17, 18, 19, 20, 21, 22, 23,
243 24, 25, 26, 27, 28, 29, 30, 31, 32,
244 33, 34, 35, 36, 37, 38, 39};
245 static const unsigned int smc0_nor_cs1_pins[] = {1};
246 static const unsigned int smc0_nor_addr25_pins[] = {1};
247 static const unsigned int smc0_nand_pins[] = {0, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11,
248 12, 13, 14, 16, 17, 18, 19, 20,
249 21, 22, 23};
250 static const unsigned int smc0_nand8_pins[] = {0, 2, 3, 4, 5, 6, 7,
251 8, 9, 10, 11, 12, 13, 14};
252 /* Note: CAN MIO clock inputs are modeled in the clock framework */
253 static const unsigned int can0_0_pins[] = {10, 11};
254 static const unsigned int can0_1_pins[] = {14, 15};
255 static const unsigned int can0_2_pins[] = {18, 19};
256 static const unsigned int can0_3_pins[] = {22, 23};
257 static const unsigned int can0_4_pins[] = {26, 27};
258 static const unsigned int can0_5_pins[] = {30, 31};
259 static const unsigned int can0_6_pins[] = {34, 35};
260 static const unsigned int can0_7_pins[] = {38, 39};
261 static const unsigned int can0_8_pins[] = {42, 43};
262 static const unsigned int can0_9_pins[] = {46, 47};
263 static const unsigned int can0_10_pins[] = {50, 51};
264 static const unsigned int can1_0_pins[] = {8, 9};
265 static const unsigned int can1_1_pins[] = {12, 13};
266 static const unsigned int can1_2_pins[] = {16, 17};
267 static const unsigned int can1_3_pins[] = {20, 21};
268 static const unsigned int can1_4_pins[] = {24, 25};
269 static const unsigned int can1_5_pins[] = {28, 29};
270 static const unsigned int can1_6_pins[] = {32, 33};
271 static const unsigned int can1_7_pins[] = {36, 37};
272 static const unsigned int can1_8_pins[] = {40, 41};
273 static const unsigned int can1_9_pins[] = {44, 45};
274 static const unsigned int can1_10_pins[] = {48, 49};
275 static const unsigned int can1_11_pins[] = {52, 53};
276 static const unsigned int uart0_0_pins[] = {10, 11};
277 static const unsigned int uart0_1_pins[] = {14, 15};
278 static const unsigned int uart0_2_pins[] = {18, 19};
279 static const unsigned int uart0_3_pins[] = {22, 23};
280 static const unsigned int uart0_4_pins[] = {26, 27};
281 static const unsigned int uart0_5_pins[] = {30, 31};
282 static const unsigned int uart0_6_pins[] = {34, 35};
283 static const unsigned int uart0_7_pins[] = {38, 39};
284 static const unsigned int uart0_8_pins[] = {42, 43};
285 static const unsigned int uart0_9_pins[] = {46, 47};
286 static const unsigned int uart0_10_pins[] = {50, 51};
287 static const unsigned int uart1_0_pins[] = {8, 9};
288 static const unsigned int uart1_1_pins[] = {12, 13};
289 static const unsigned int uart1_2_pins[] = {16, 17};
290 static const unsigned int uart1_3_pins[] = {20, 21};
291 static const unsigned int uart1_4_pins[] = {24, 25};
292 static const unsigned int uart1_5_pins[] = {28, 29};
293 static const unsigned int uart1_6_pins[] = {32, 33};
294 static const unsigned int uart1_7_pins[] = {36, 37};
295 static const unsigned int uart1_8_pins[] = {40, 41};
296 static const unsigned int uart1_9_pins[] = {44, 45};
297 static const unsigned int uart1_10_pins[] = {48, 49};
298 static const unsigned int uart1_11_pins[] = {52, 53};
299 static const unsigned int i2c0_0_pins[] = {10, 11};
300 static const unsigned int i2c0_1_pins[] = {14, 15};
301 static const unsigned int i2c0_2_pins[] = {18, 19};
302 static const unsigned int i2c0_3_pins[] = {22, 23};
303 static const unsigned int i2c0_4_pins[] = {26, 27};
304 static const unsigned int i2c0_5_pins[] = {30, 31};
305 static const unsigned int i2c0_6_pins[] = {34, 35};
306 static const unsigned int i2c0_7_pins[] = {38, 39};
307 static const unsigned int i2c0_8_pins[] = {42, 43};
308 static const unsigned int i2c0_9_pins[] = {46, 47};
309 static const unsigned int i2c0_10_pins[] = {50, 51};
310 static const unsigned int i2c1_0_pins[] = {12, 13};
311 static const unsigned int i2c1_1_pins[] = {16, 17};
312 static const unsigned int i2c1_2_pins[] = {20, 21};
313 static const unsigned int i2c1_3_pins[] = {24, 25};
314 static const unsigned int i2c1_4_pins[] = {28, 29};
315 static const unsigned int i2c1_5_pins[] = {32, 33};
316 static const unsigned int i2c1_6_pins[] = {36, 37};
317 static const unsigned int i2c1_7_pins[] = {40, 41};
318 static const unsigned int i2c1_8_pins[] = {44, 45};
319 static const unsigned int i2c1_9_pins[] = {48, 49};
320 static const unsigned int i2c1_10_pins[] = {52, 53};
321 static const unsigned int ttc0_0_pins[] = {18, 19};
322 static const unsigned int ttc0_1_pins[] = {30, 31};
323 static const unsigned int ttc0_2_pins[] = {42, 43};
324 static const unsigned int ttc1_0_pins[] = {16, 17};
325 static const unsigned int ttc1_1_pins[] = {28, 29};
326 static const unsigned int ttc1_2_pins[] = {40, 41};
327 static const unsigned int swdt0_0_pins[] = {14, 15};
328 static const unsigned int swdt0_1_pins[] = {26, 27};
329 static const unsigned int swdt0_2_pins[] = {38, 39};
330 static const unsigned int swdt0_3_pins[] = {50, 51};
331 static const unsigned int swdt0_4_pins[] = {52, 53};
332 static const unsigned int gpio0_0_pins[] = {0};
333 static const unsigned int gpio0_1_pins[] = {1};
334 static const unsigned int gpio0_2_pins[] = {2};
335 static const unsigned int gpio0_3_pins[] = {3};
336 static const unsigned int gpio0_4_pins[] = {4};
337 static const unsigned int gpio0_5_pins[] = {5};
338 static const unsigned int gpio0_6_pins[] = {6};
339 static const unsigned int gpio0_7_pins[] = {7};
340 static const unsigned int gpio0_8_pins[] = {8};
341 static const unsigned int gpio0_9_pins[] = {9};
342 static const unsigned int gpio0_10_pins[] = {10};
343 static const unsigned int gpio0_11_pins[] = {11};
344 static const unsigned int gpio0_12_pins[] = {12};
345 static const unsigned int gpio0_13_pins[] = {13};
346 static const unsigned int gpio0_14_pins[] = {14};
347 static const unsigned int gpio0_15_pins[] = {15};
348 static const unsigned int gpio0_16_pins[] = {16};
349 static const unsigned int gpio0_17_pins[] = {17};
350 static const unsigned int gpio0_18_pins[] = {18};
351 static const unsigned int gpio0_19_pins[] = {19};
352 static const unsigned int gpio0_20_pins[] = {20};
353 static const unsigned int gpio0_21_pins[] = {21};
354 static const unsigned int gpio0_22_pins[] = {22};
355 static const unsigned int gpio0_23_pins[] = {23};
356 static const unsigned int gpio0_24_pins[] = {24};
357 static const unsigned int gpio0_25_pins[] = {25};
358 static const unsigned int gpio0_26_pins[] = {26};
359 static const unsigned int gpio0_27_pins[] = {27};
360 static const unsigned int gpio0_28_pins[] = {28};
361 static const unsigned int gpio0_29_pins[] = {29};
362 static const unsigned int gpio0_30_pins[] = {30};
363 static const unsigned int gpio0_31_pins[] = {31};
364 static const unsigned int gpio0_32_pins[] = {32};
365 static const unsigned int gpio0_33_pins[] = {33};
366 static const unsigned int gpio0_34_pins[] = {34};
367 static const unsigned int gpio0_35_pins[] = {35};
368 static const unsigned int gpio0_36_pins[] = {36};
369 static const unsigned int gpio0_37_pins[] = {37};
370 static const unsigned int gpio0_38_pins[] = {38};
371 static const unsigned int gpio0_39_pins[] = {39};
372 static const unsigned int gpio0_40_pins[] = {40};
373 static const unsigned int gpio0_41_pins[] = {41};
374 static const unsigned int gpio0_42_pins[] = {42};
375 static const unsigned int gpio0_43_pins[] = {43};
376 static const unsigned int gpio0_44_pins[] = {44};
377 static const unsigned int gpio0_45_pins[] = {45};
378 static const unsigned int gpio0_46_pins[] = {46};
379 static const unsigned int gpio0_47_pins[] = {47};
380 static const unsigned int gpio0_48_pins[] = {48};
381 static const unsigned int gpio0_49_pins[] = {49};
382 static const unsigned int gpio0_50_pins[] = {50};
383 static const unsigned int gpio0_51_pins[] = {51};
384 static const unsigned int gpio0_52_pins[] = {52};
385 static const unsigned int gpio0_53_pins[] = {53};
386 static const unsigned int usb0_0_pins[] = {28, 29, 30, 31, 32, 33, 34, 35, 36,
387 37, 38, 39};
388 static const unsigned int usb1_0_pins[] = {40, 41, 42, 43, 44, 45, 46, 47, 48,
389 49, 50, 51};
390
391 #define DEFINE_ZYNQ_PINCTRL_GRP(nm) \
392 { \
393 .name = #nm "_grp", \
394 .pins = nm ## _pins, \
395 .npins = ARRAY_SIZE(nm ## _pins), \
396 }
397
398 static const struct zynq_pctrl_group zynq_pctrl_groups[] = {
399 DEFINE_ZYNQ_PINCTRL_GRP(ethernet0_0),
400 DEFINE_ZYNQ_PINCTRL_GRP(ethernet1_0),
401 DEFINE_ZYNQ_PINCTRL_GRP(mdio0_0),
402 DEFINE_ZYNQ_PINCTRL_GRP(mdio1_0),
403 DEFINE_ZYNQ_PINCTRL_GRP(qspi0_0),
404 DEFINE_ZYNQ_PINCTRL_GRP(qspi1_0),
405 DEFINE_ZYNQ_PINCTRL_GRP(qspi_fbclk),
406 DEFINE_ZYNQ_PINCTRL_GRP(qspi_cs1),
407 DEFINE_ZYNQ_PINCTRL_GRP(spi0_0),
408 DEFINE_ZYNQ_PINCTRL_GRP(spi0_0_ss0),
409 DEFINE_ZYNQ_PINCTRL_GRP(spi0_0_ss1),
410 DEFINE_ZYNQ_PINCTRL_GRP(spi0_0_ss2),
411 DEFINE_ZYNQ_PINCTRL_GRP(spi0_1),
412 DEFINE_ZYNQ_PINCTRL_GRP(spi0_1_ss0),
413 DEFINE_ZYNQ_PINCTRL_GRP(spi0_1_ss1),
414 DEFINE_ZYNQ_PINCTRL_GRP(spi0_1_ss2),
415 DEFINE_ZYNQ_PINCTRL_GRP(spi0_2),
416 DEFINE_ZYNQ_PINCTRL_GRP(spi0_2_ss0),
417 DEFINE_ZYNQ_PINCTRL_GRP(spi0_2_ss1),
418 DEFINE_ZYNQ_PINCTRL_GRP(spi0_2_ss2),
419 DEFINE_ZYNQ_PINCTRL_GRP(spi1_0),
420 DEFINE_ZYNQ_PINCTRL_GRP(spi1_0_ss0),
421 DEFINE_ZYNQ_PINCTRL_GRP(spi1_0_ss1),
422 DEFINE_ZYNQ_PINCTRL_GRP(spi1_0_ss2),
423 DEFINE_ZYNQ_PINCTRL_GRP(spi1_1),
424 DEFINE_ZYNQ_PINCTRL_GRP(spi1_1_ss0),
425 DEFINE_ZYNQ_PINCTRL_GRP(spi1_1_ss1),
426 DEFINE_ZYNQ_PINCTRL_GRP(spi1_1_ss2),
427 DEFINE_ZYNQ_PINCTRL_GRP(spi1_2),
428 DEFINE_ZYNQ_PINCTRL_GRP(spi1_2_ss0),
429 DEFINE_ZYNQ_PINCTRL_GRP(spi1_2_ss1),
430 DEFINE_ZYNQ_PINCTRL_GRP(spi1_2_ss2),
431 DEFINE_ZYNQ_PINCTRL_GRP(spi1_3),
432 DEFINE_ZYNQ_PINCTRL_GRP(spi1_3_ss0),
433 DEFINE_ZYNQ_PINCTRL_GRP(spi1_3_ss1),
434 DEFINE_ZYNQ_PINCTRL_GRP(spi1_3_ss2),
435 DEFINE_ZYNQ_PINCTRL_GRP(sdio0_0),
436 DEFINE_ZYNQ_PINCTRL_GRP(sdio0_1),
437 DEFINE_ZYNQ_PINCTRL_GRP(sdio0_2),
438 DEFINE_ZYNQ_PINCTRL_GRP(sdio1_0),
439 DEFINE_ZYNQ_PINCTRL_GRP(sdio1_1),
440 DEFINE_ZYNQ_PINCTRL_GRP(sdio1_2),
441 DEFINE_ZYNQ_PINCTRL_GRP(sdio1_3),
442 DEFINE_ZYNQ_PINCTRL_GRP(sdio0_emio_wp),
443 DEFINE_ZYNQ_PINCTRL_GRP(sdio0_emio_cd),
444 DEFINE_ZYNQ_PINCTRL_GRP(sdio1_emio_wp),
445 DEFINE_ZYNQ_PINCTRL_GRP(sdio1_emio_cd),
446 DEFINE_ZYNQ_PINCTRL_GRP(smc0_nor),
447 DEFINE_ZYNQ_PINCTRL_GRP(smc0_nor_cs1),
448 DEFINE_ZYNQ_PINCTRL_GRP(smc0_nor_addr25),
449 DEFINE_ZYNQ_PINCTRL_GRP(smc0_nand),
450 DEFINE_ZYNQ_PINCTRL_GRP(smc0_nand8),
451 DEFINE_ZYNQ_PINCTRL_GRP(can0_0),
452 DEFINE_ZYNQ_PINCTRL_GRP(can0_1),
453 DEFINE_ZYNQ_PINCTRL_GRP(can0_2),
454 DEFINE_ZYNQ_PINCTRL_GRP(can0_3),
455 DEFINE_ZYNQ_PINCTRL_GRP(can0_4),
456 DEFINE_ZYNQ_PINCTRL_GRP(can0_5),
457 DEFINE_ZYNQ_PINCTRL_GRP(can0_6),
458 DEFINE_ZYNQ_PINCTRL_GRP(can0_7),
459 DEFINE_ZYNQ_PINCTRL_GRP(can0_8),
460 DEFINE_ZYNQ_PINCTRL_GRP(can0_9),
461 DEFINE_ZYNQ_PINCTRL_GRP(can0_10),
462 DEFINE_ZYNQ_PINCTRL_GRP(can1_0),
463 DEFINE_ZYNQ_PINCTRL_GRP(can1_1),
464 DEFINE_ZYNQ_PINCTRL_GRP(can1_2),
465 DEFINE_ZYNQ_PINCTRL_GRP(can1_3),
466 DEFINE_ZYNQ_PINCTRL_GRP(can1_4),
467 DEFINE_ZYNQ_PINCTRL_GRP(can1_5),
468 DEFINE_ZYNQ_PINCTRL_GRP(can1_6),
469 DEFINE_ZYNQ_PINCTRL_GRP(can1_7),
470 DEFINE_ZYNQ_PINCTRL_GRP(can1_8),
471 DEFINE_ZYNQ_PINCTRL_GRP(can1_9),
472 DEFINE_ZYNQ_PINCTRL_GRP(can1_10),
473 DEFINE_ZYNQ_PINCTRL_GRP(can1_11),
474 DEFINE_ZYNQ_PINCTRL_GRP(uart0_0),
475 DEFINE_ZYNQ_PINCTRL_GRP(uart0_1),
476 DEFINE_ZYNQ_PINCTRL_GRP(uart0_2),
477 DEFINE_ZYNQ_PINCTRL_GRP(uart0_3),
478 DEFINE_ZYNQ_PINCTRL_GRP(uart0_4),
479 DEFINE_ZYNQ_PINCTRL_GRP(uart0_5),
480 DEFINE_ZYNQ_PINCTRL_GRP(uart0_6),
481 DEFINE_ZYNQ_PINCTRL_GRP(uart0_7),
482 DEFINE_ZYNQ_PINCTRL_GRP(uart0_8),
483 DEFINE_ZYNQ_PINCTRL_GRP(uart0_9),
484 DEFINE_ZYNQ_PINCTRL_GRP(uart0_10),
485 DEFINE_ZYNQ_PINCTRL_GRP(uart1_0),
486 DEFINE_ZYNQ_PINCTRL_GRP(uart1_1),
487 DEFINE_ZYNQ_PINCTRL_GRP(uart1_2),
488 DEFINE_ZYNQ_PINCTRL_GRP(uart1_3),
489 DEFINE_ZYNQ_PINCTRL_GRP(uart1_4),
490 DEFINE_ZYNQ_PINCTRL_GRP(uart1_5),
491 DEFINE_ZYNQ_PINCTRL_GRP(uart1_6),
492 DEFINE_ZYNQ_PINCTRL_GRP(uart1_7),
493 DEFINE_ZYNQ_PINCTRL_GRP(uart1_8),
494 DEFINE_ZYNQ_PINCTRL_GRP(uart1_9),
495 DEFINE_ZYNQ_PINCTRL_GRP(uart1_10),
496 DEFINE_ZYNQ_PINCTRL_GRP(uart1_11),
497 DEFINE_ZYNQ_PINCTRL_GRP(i2c0_0),
498 DEFINE_ZYNQ_PINCTRL_GRP(i2c0_1),
499 DEFINE_ZYNQ_PINCTRL_GRP(i2c0_2),
500 DEFINE_ZYNQ_PINCTRL_GRP(i2c0_3),
501 DEFINE_ZYNQ_PINCTRL_GRP(i2c0_4),
502 DEFINE_ZYNQ_PINCTRL_GRP(i2c0_5),
503 DEFINE_ZYNQ_PINCTRL_GRP(i2c0_6),
504 DEFINE_ZYNQ_PINCTRL_GRP(i2c0_7),
505 DEFINE_ZYNQ_PINCTRL_GRP(i2c0_8),
506 DEFINE_ZYNQ_PINCTRL_GRP(i2c0_9),
507 DEFINE_ZYNQ_PINCTRL_GRP(i2c0_10),
508 DEFINE_ZYNQ_PINCTRL_GRP(i2c1_0),
509 DEFINE_ZYNQ_PINCTRL_GRP(i2c1_1),
510 DEFINE_ZYNQ_PINCTRL_GRP(i2c1_2),
511 DEFINE_ZYNQ_PINCTRL_GRP(i2c1_3),
512 DEFINE_ZYNQ_PINCTRL_GRP(i2c1_4),
513 DEFINE_ZYNQ_PINCTRL_GRP(i2c1_5),
514 DEFINE_ZYNQ_PINCTRL_GRP(i2c1_6),
515 DEFINE_ZYNQ_PINCTRL_GRP(i2c1_7),
516 DEFINE_ZYNQ_PINCTRL_GRP(i2c1_8),
517 DEFINE_ZYNQ_PINCTRL_GRP(i2c1_9),
518 DEFINE_ZYNQ_PINCTRL_GRP(i2c1_10),
519 DEFINE_ZYNQ_PINCTRL_GRP(ttc0_0),
520 DEFINE_ZYNQ_PINCTRL_GRP(ttc0_1),
521 DEFINE_ZYNQ_PINCTRL_GRP(ttc0_2),
522 DEFINE_ZYNQ_PINCTRL_GRP(ttc1_0),
523 DEFINE_ZYNQ_PINCTRL_GRP(ttc1_1),
524 DEFINE_ZYNQ_PINCTRL_GRP(ttc1_2),
525 DEFINE_ZYNQ_PINCTRL_GRP(swdt0_0),
526 DEFINE_ZYNQ_PINCTRL_GRP(swdt0_1),
527 DEFINE_ZYNQ_PINCTRL_GRP(swdt0_2),
528 DEFINE_ZYNQ_PINCTRL_GRP(swdt0_3),
529 DEFINE_ZYNQ_PINCTRL_GRP(swdt0_4),
530 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_0),
531 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_1),
532 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_2),
533 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_3),
534 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_4),
535 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_5),
536 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_6),
537 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_7),
538 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_8),
539 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_9),
540 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_10),
541 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_11),
542 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_12),
543 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_13),
544 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_14),
545 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_15),
546 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_16),
547 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_17),
548 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_18),
549 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_19),
550 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_20),
551 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_21),
552 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_22),
553 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_23),
554 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_24),
555 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_25),
556 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_26),
557 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_27),
558 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_28),
559 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_29),
560 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_30),
561 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_31),
562 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_32),
563 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_33),
564 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_34),
565 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_35),
566 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_36),
567 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_37),
568 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_38),
569 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_39),
570 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_40),
571 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_41),
572 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_42),
573 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_43),
574 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_44),
575 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_45),
576 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_46),
577 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_47),
578 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_48),
579 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_49),
580 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_50),
581 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_51),
582 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_52),
583 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_53),
584 DEFINE_ZYNQ_PINCTRL_GRP(usb0_0),
585 DEFINE_ZYNQ_PINCTRL_GRP(usb1_0),
586 };
587
588 /* function groups */
589 static const char * const ethernet0_groups[] = {"ethernet0_0_grp"};
590 static const char * const ethernet1_groups[] = {"ethernet1_0_grp"};
591 static const char * const usb0_groups[] = {"usb0_0_grp"};
592 static const char * const usb1_groups[] = {"usb1_0_grp"};
593 static const char * const mdio0_groups[] = {"mdio0_0_grp"};
594 static const char * const mdio1_groups[] = {"mdio1_0_grp"};
595 static const char * const qspi0_groups[] = {"qspi0_0_grp"};
596 static const char * const qspi1_groups[] = {"qspi1_0_grp"};
597 static const char * const qspi_fbclk_groups[] = {"qspi_fbclk_grp"};
598 static const char * const qspi_cs1_groups[] = {"qspi_cs1_grp"};
599 static const char * const spi0_groups[] = {"spi0_0_grp", "spi0_1_grp",
600 "spi0_2_grp"};
601 static const char * const spi1_groups[] = {"spi1_0_grp", "spi1_1_grp",
602 "spi1_2_grp", "spi1_3_grp"};
603 static const char * const spi0_ss_groups[] = {"spi0_0_ss0_grp",
604 "spi0_0_ss1_grp", "spi0_0_ss2_grp", "spi0_1_ss0_grp",
605 "spi0_1_ss1_grp", "spi0_1_ss2_grp", "spi0_2_ss0_grp",
606 "spi0_2_ss1_grp", "spi0_2_ss2_grp"};
607 static const char * const spi1_ss_groups[] = {"spi1_0_ss0_grp",
608 "spi1_0_ss1_grp", "spi1_0_ss2_grp", "spi1_1_ss0_grp",
609 "spi1_1_ss1_grp", "spi1_1_ss2_grp", "spi1_2_ss0_grp",
610 "spi1_2_ss1_grp", "spi1_2_ss2_grp", "spi1_3_ss0_grp",
611 "spi1_3_ss1_grp", "spi1_3_ss2_grp"};
612 static const char * const sdio0_groups[] = {"sdio0_0_grp", "sdio0_1_grp",
613 "sdio0_2_grp"};
614 static const char * const sdio1_groups[] = {"sdio1_0_grp", "sdio1_1_grp",
615 "sdio1_2_grp", "sdio1_3_grp"};
616 static const char * const sdio0_pc_groups[] = {"gpio0_0_grp",
617 "gpio0_2_grp", "gpio0_4_grp", "gpio0_6_grp",
618 "gpio0_8_grp", "gpio0_10_grp", "gpio0_12_grp",
619 "gpio0_14_grp", "gpio0_16_grp", "gpio0_18_grp",
620 "gpio0_20_grp", "gpio0_22_grp", "gpio0_24_grp",
621 "gpio0_26_grp", "gpio0_28_grp", "gpio0_30_grp",
622 "gpio0_32_grp", "gpio0_34_grp", "gpio0_36_grp",
623 "gpio0_38_grp", "gpio0_40_grp", "gpio0_42_grp",
624 "gpio0_44_grp", "gpio0_46_grp", "gpio0_48_grp",
625 "gpio0_50_grp", "gpio0_52_grp"};
626 static const char * const sdio1_pc_groups[] = {"gpio0_1_grp",
627 "gpio0_3_grp", "gpio0_5_grp", "gpio0_7_grp",
628 "gpio0_9_grp", "gpio0_11_grp", "gpio0_13_grp",
629 "gpio0_15_grp", "gpio0_17_grp", "gpio0_19_grp",
630 "gpio0_21_grp", "gpio0_23_grp", "gpio0_25_grp",
631 "gpio0_27_grp", "gpio0_29_grp", "gpio0_31_grp",
632 "gpio0_33_grp", "gpio0_35_grp", "gpio0_37_grp",
633 "gpio0_39_grp", "gpio0_41_grp", "gpio0_43_grp",
634 "gpio0_45_grp", "gpio0_47_grp", "gpio0_49_grp",
635 "gpio0_51_grp", "gpio0_53_grp"};
636 static const char * const sdio0_cd_groups[] = {"gpio0_0_grp",
637 "gpio0_2_grp", "gpio0_4_grp", "gpio0_6_grp",
638 "gpio0_10_grp", "gpio0_12_grp",
639 "gpio0_14_grp", "gpio0_16_grp", "gpio0_18_grp",
640 "gpio0_20_grp", "gpio0_22_grp", "gpio0_24_grp",
641 "gpio0_26_grp", "gpio0_28_grp", "gpio0_30_grp",
642 "gpio0_32_grp", "gpio0_34_grp", "gpio0_36_grp",
643 "gpio0_38_grp", "gpio0_40_grp", "gpio0_42_grp",
644 "gpio0_44_grp", "gpio0_46_grp", "gpio0_48_grp",
645 "gpio0_50_grp", "gpio0_52_grp", "gpio0_1_grp",
646 "gpio0_3_grp", "gpio0_5_grp",
647 "gpio0_9_grp", "gpio0_11_grp", "gpio0_13_grp",
648 "gpio0_15_grp", "gpio0_17_grp", "gpio0_19_grp",
649 "gpio0_21_grp", "gpio0_23_grp", "gpio0_25_grp",
650 "gpio0_27_grp", "gpio0_29_grp", "gpio0_31_grp",
651 "gpio0_33_grp", "gpio0_35_grp", "gpio0_37_grp",
652 "gpio0_39_grp", "gpio0_41_grp", "gpio0_43_grp",
653 "gpio0_45_grp", "gpio0_47_grp", "gpio0_49_grp",
654 "gpio0_51_grp", "gpio0_53_grp", "sdio0_emio_cd_grp"};
655 static const char * const sdio0_wp_groups[] = {"gpio0_0_grp",
656 "gpio0_2_grp", "gpio0_4_grp", "gpio0_6_grp",
657 "gpio0_10_grp", "gpio0_12_grp",
658 "gpio0_14_grp", "gpio0_16_grp", "gpio0_18_grp",
659 "gpio0_20_grp", "gpio0_22_grp", "gpio0_24_grp",
660 "gpio0_26_grp", "gpio0_28_grp", "gpio0_30_grp",
661 "gpio0_32_grp", "gpio0_34_grp", "gpio0_36_grp",
662 "gpio0_38_grp", "gpio0_40_grp", "gpio0_42_grp",
663 "gpio0_44_grp", "gpio0_46_grp", "gpio0_48_grp",
664 "gpio0_50_grp", "gpio0_52_grp", "gpio0_1_grp",
665 "gpio0_3_grp", "gpio0_5_grp",
666 "gpio0_9_grp", "gpio0_11_grp", "gpio0_13_grp",
667 "gpio0_15_grp", "gpio0_17_grp", "gpio0_19_grp",
668 "gpio0_21_grp", "gpio0_23_grp", "gpio0_25_grp",
669 "gpio0_27_grp", "gpio0_29_grp", "gpio0_31_grp",
670 "gpio0_33_grp", "gpio0_35_grp", "gpio0_37_grp",
671 "gpio0_39_grp", "gpio0_41_grp", "gpio0_43_grp",
672 "gpio0_45_grp", "gpio0_47_grp", "gpio0_49_grp",
673 "gpio0_51_grp", "gpio0_53_grp", "sdio0_emio_wp_grp"};
674 static const char * const sdio1_cd_groups[] = {"gpio0_0_grp",
675 "gpio0_2_grp", "gpio0_4_grp", "gpio0_6_grp",
676 "gpio0_10_grp", "gpio0_12_grp",
677 "gpio0_14_grp", "gpio0_16_grp", "gpio0_18_grp",
678 "gpio0_20_grp", "gpio0_22_grp", "gpio0_24_grp",
679 "gpio0_26_grp", "gpio0_28_grp", "gpio0_30_grp",
680 "gpio0_32_grp", "gpio0_34_grp", "gpio0_36_grp",
681 "gpio0_38_grp", "gpio0_40_grp", "gpio0_42_grp",
682 "gpio0_44_grp", "gpio0_46_grp", "gpio0_48_grp",
683 "gpio0_50_grp", "gpio0_52_grp", "gpio0_1_grp",
684 "gpio0_3_grp", "gpio0_5_grp",
685 "gpio0_9_grp", "gpio0_11_grp", "gpio0_13_grp",
686 "gpio0_15_grp", "gpio0_17_grp", "gpio0_19_grp",
687 "gpio0_21_grp", "gpio0_23_grp", "gpio0_25_grp",
688 "gpio0_27_grp", "gpio0_29_grp", "gpio0_31_grp",
689 "gpio0_33_grp", "gpio0_35_grp", "gpio0_37_grp",
690 "gpio0_39_grp", "gpio0_41_grp", "gpio0_43_grp",
691 "gpio0_45_grp", "gpio0_47_grp", "gpio0_49_grp",
692 "gpio0_51_grp", "gpio0_53_grp", "sdio1_emio_cd_grp"};
693 static const char * const sdio1_wp_groups[] = {"gpio0_0_grp",
694 "gpio0_2_grp", "gpio0_4_grp", "gpio0_6_grp",
695 "gpio0_10_grp", "gpio0_12_grp",
696 "gpio0_14_grp", "gpio0_16_grp", "gpio0_18_grp",
697 "gpio0_20_grp", "gpio0_22_grp", "gpio0_24_grp",
698 "gpio0_26_grp", "gpio0_28_grp", "gpio0_30_grp",
699 "gpio0_32_grp", "gpio0_34_grp", "gpio0_36_grp",
700 "gpio0_38_grp", "gpio0_40_grp", "gpio0_42_grp",
701 "gpio0_44_grp", "gpio0_46_grp", "gpio0_48_grp",
702 "gpio0_50_grp", "gpio0_52_grp", "gpio0_1_grp",
703 "gpio0_3_grp", "gpio0_5_grp",
704 "gpio0_9_grp", "gpio0_11_grp", "gpio0_13_grp",
705 "gpio0_15_grp", "gpio0_17_grp", "gpio0_19_grp",
706 "gpio0_21_grp", "gpio0_23_grp", "gpio0_25_grp",
707 "gpio0_27_grp", "gpio0_29_grp", "gpio0_31_grp",
708 "gpio0_33_grp", "gpio0_35_grp", "gpio0_37_grp",
709 "gpio0_39_grp", "gpio0_41_grp", "gpio0_43_grp",
710 "gpio0_45_grp", "gpio0_47_grp", "gpio0_49_grp",
711 "gpio0_51_grp", "gpio0_53_grp", "sdio1_emio_wp_grp"};
712 static const char * const smc0_nor_groups[] = {"smc0_nor_grp"};
713 static const char * const smc0_nor_cs1_groups[] = {"smc0_nor_cs1_grp"};
714 static const char * const smc0_nor_addr25_groups[] = {"smc0_nor_addr25_grp"};
715 static const char * const smc0_nand_groups[] = {"smc0_nand_grp",
716 "smc0_nand8_grp"};
717 static const char * const can0_groups[] = {"can0_0_grp", "can0_1_grp",
718 "can0_2_grp", "can0_3_grp", "can0_4_grp", "can0_5_grp",
719 "can0_6_grp", "can0_7_grp", "can0_8_grp", "can0_9_grp",
720 "can0_10_grp"};
721 static const char * const can1_groups[] = {"can1_0_grp", "can1_1_grp",
722 "can1_2_grp", "can1_3_grp", "can1_4_grp", "can1_5_grp",
723 "can1_6_grp", "can1_7_grp", "can1_8_grp", "can1_9_grp",
724 "can1_10_grp", "can1_11_grp"};
725 static const char * const uart0_groups[] = {"uart0_0_grp", "uart0_1_grp",
726 "uart0_2_grp", "uart0_3_grp", "uart0_4_grp", "uart0_5_grp",
727 "uart0_6_grp", "uart0_7_grp", "uart0_8_grp", "uart0_9_grp",
728 "uart0_10_grp"};
729 static const char * const uart1_groups[] = {"uart1_0_grp", "uart1_1_grp",
730 "uart1_2_grp", "uart1_3_grp", "uart1_4_grp", "uart1_5_grp",
731 "uart1_6_grp", "uart1_7_grp", "uart1_8_grp", "uart1_9_grp",
732 "uart1_10_grp", "uart1_11_grp"};
733 static const char * const i2c0_groups[] = {"i2c0_0_grp", "i2c0_1_grp",
734 "i2c0_2_grp", "i2c0_3_grp", "i2c0_4_grp", "i2c0_5_grp",
735 "i2c0_6_grp", "i2c0_7_grp", "i2c0_8_grp", "i2c0_9_grp",
736 "i2c0_10_grp"};
737 static const char * const i2c1_groups[] = {"i2c1_0_grp", "i2c1_1_grp",
738 "i2c1_2_grp", "i2c1_3_grp", "i2c1_4_grp", "i2c1_5_grp",
739 "i2c1_6_grp", "i2c1_7_grp", "i2c1_8_grp", "i2c1_9_grp",
740 "i2c1_10_grp"};
741 static const char * const ttc0_groups[] = {"ttc0_0_grp", "ttc0_1_grp",
742 "ttc0_2_grp"};
743 static const char * const ttc1_groups[] = {"ttc1_0_grp", "ttc1_1_grp",
744 "ttc1_2_grp"};
745 static const char * const swdt0_groups[] = {"swdt0_0_grp", "swdt0_1_grp",
746 "swdt0_2_grp", "swdt0_3_grp", "swdt0_4_grp"};
747 static const char * const gpio0_groups[] = {"gpio0_0_grp",
748 "gpio0_2_grp", "gpio0_4_grp", "gpio0_6_grp",
749 "gpio0_8_grp", "gpio0_10_grp", "gpio0_12_grp",
750 "gpio0_14_grp", "gpio0_16_grp", "gpio0_18_grp",
751 "gpio0_20_grp", "gpio0_22_grp", "gpio0_24_grp",
752 "gpio0_26_grp", "gpio0_28_grp", "gpio0_30_grp",
753 "gpio0_32_grp", "gpio0_34_grp", "gpio0_36_grp",
754 "gpio0_38_grp", "gpio0_40_grp", "gpio0_42_grp",
755 "gpio0_44_grp", "gpio0_46_grp", "gpio0_48_grp",
756 "gpio0_50_grp", "gpio0_52_grp", "gpio0_1_grp",
757 "gpio0_3_grp", "gpio0_5_grp", "gpio0_7_grp",
758 "gpio0_9_grp", "gpio0_11_grp", "gpio0_13_grp",
759 "gpio0_15_grp", "gpio0_17_grp", "gpio0_19_grp",
760 "gpio0_21_grp", "gpio0_23_grp", "gpio0_25_grp",
761 "gpio0_27_grp", "gpio0_29_grp", "gpio0_31_grp",
762 "gpio0_33_grp", "gpio0_35_grp", "gpio0_37_grp",
763 "gpio0_39_grp", "gpio0_41_grp", "gpio0_43_grp",
764 "gpio0_45_grp", "gpio0_47_grp", "gpio0_49_grp",
765 "gpio0_51_grp", "gpio0_53_grp"};
766
767 #define DEFINE_ZYNQ_PINMUX_FUNCTION(fname, mval) \
768 [ZYNQ_PMUX_##fname] = { \
769 .name = #fname, \
770 .groups = fname##_groups, \
771 .ngroups = ARRAY_SIZE(fname##_groups), \
772 .mux_val = mval, \
773 }
774
775 #define DEFINE_ZYNQ_PINMUX_FUNCTION_MUX(fname, mval, offset, mask, shift)\
776 [ZYNQ_PMUX_##fname] = { \
777 .name = #fname, \
778 .groups = fname##_groups, \
779 .ngroups = ARRAY_SIZE(fname##_groups), \
780 .mux_val = mval, \
781 .mux = offset, \
782 .mux_mask = mask, \
783 .mux_shift = shift, \
784 }
785
786 #define ZYNQ_SDIO_WP_SHIFT 0
787 #define ZYNQ_SDIO_WP_MASK (0x3f << ZYNQ_SDIO_WP_SHIFT)
788 #define ZYNQ_SDIO_CD_SHIFT 16
789 #define ZYNQ_SDIO_CD_MASK (0x3f << ZYNQ_SDIO_CD_SHIFT)
790
791 static const struct zynq_pinmux_function zynq_pmux_functions[] = {
792 DEFINE_ZYNQ_PINMUX_FUNCTION(ethernet0, 1),
793 DEFINE_ZYNQ_PINMUX_FUNCTION(ethernet1, 1),
794 DEFINE_ZYNQ_PINMUX_FUNCTION(usb0, 2),
795 DEFINE_ZYNQ_PINMUX_FUNCTION(usb1, 2),
796 DEFINE_ZYNQ_PINMUX_FUNCTION(mdio0, 0x40),
797 DEFINE_ZYNQ_PINMUX_FUNCTION(mdio1, 0x50),
798 DEFINE_ZYNQ_PINMUX_FUNCTION(qspi0, 1),
799 DEFINE_ZYNQ_PINMUX_FUNCTION(qspi1, 1),
800 DEFINE_ZYNQ_PINMUX_FUNCTION(qspi_fbclk, 1),
801 DEFINE_ZYNQ_PINMUX_FUNCTION(qspi_cs1, 1),
802 DEFINE_ZYNQ_PINMUX_FUNCTION(spi0, 0x50),
803 DEFINE_ZYNQ_PINMUX_FUNCTION(spi1, 0x50),
804 DEFINE_ZYNQ_PINMUX_FUNCTION(spi0_ss, 0x50),
805 DEFINE_ZYNQ_PINMUX_FUNCTION(spi1_ss, 0x50),
806 DEFINE_ZYNQ_PINMUX_FUNCTION(sdio0, 0x40),
807 DEFINE_ZYNQ_PINMUX_FUNCTION(sdio0_pc, 0xc),
808 DEFINE_ZYNQ_PINMUX_FUNCTION_MUX(sdio0_wp, 0, 0x130, ZYNQ_SDIO_WP_MASK,
809 ZYNQ_SDIO_WP_SHIFT),
810 DEFINE_ZYNQ_PINMUX_FUNCTION_MUX(sdio0_cd, 0, 0x130, ZYNQ_SDIO_CD_MASK,
811 ZYNQ_SDIO_CD_SHIFT),
812 DEFINE_ZYNQ_PINMUX_FUNCTION(sdio1, 0x40),
813 DEFINE_ZYNQ_PINMUX_FUNCTION(sdio1_pc, 0xc),
814 DEFINE_ZYNQ_PINMUX_FUNCTION_MUX(sdio1_wp, 0, 0x134, ZYNQ_SDIO_WP_MASK,
815 ZYNQ_SDIO_WP_SHIFT),
816 DEFINE_ZYNQ_PINMUX_FUNCTION_MUX(sdio1_cd, 0, 0x134, ZYNQ_SDIO_CD_MASK,
817 ZYNQ_SDIO_CD_SHIFT),
818 DEFINE_ZYNQ_PINMUX_FUNCTION(smc0_nor, 4),
819 DEFINE_ZYNQ_PINMUX_FUNCTION(smc0_nor_cs1, 8),
820 DEFINE_ZYNQ_PINMUX_FUNCTION(smc0_nor_addr25, 4),
821 DEFINE_ZYNQ_PINMUX_FUNCTION(smc0_nand, 8),
822 DEFINE_ZYNQ_PINMUX_FUNCTION(can0, 0x10),
823 DEFINE_ZYNQ_PINMUX_FUNCTION(can1, 0x10),
824 DEFINE_ZYNQ_PINMUX_FUNCTION(uart0, 0x70),
825 DEFINE_ZYNQ_PINMUX_FUNCTION(uart1, 0x70),
826 DEFINE_ZYNQ_PINMUX_FUNCTION(i2c0, 0x20),
827 DEFINE_ZYNQ_PINMUX_FUNCTION(i2c1, 0x20),
828 DEFINE_ZYNQ_PINMUX_FUNCTION(ttc0, 0x60),
829 DEFINE_ZYNQ_PINMUX_FUNCTION(ttc1, 0x60),
830 DEFINE_ZYNQ_PINMUX_FUNCTION(swdt0, 0x30),
831 DEFINE_ZYNQ_PINMUX_FUNCTION(gpio0, 0),
832 };
833
834
835 /* pinctrl */
836 static int zynq_pctrl_get_groups_count(struct pinctrl_dev *pctldev)
837 {
838 struct zynq_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
839
840 return pctrl->ngroups;
841 }
842
843 static const char *zynq_pctrl_get_group_name(struct pinctrl_dev *pctldev,
844 unsigned int selector)
845 {
846 struct zynq_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
847
848 return pctrl->groups[selector].name;
849 }
850
851 static int zynq_pctrl_get_group_pins(struct pinctrl_dev *pctldev,
852 unsigned int selector,
853 const unsigned int **pins,
854 unsigned int *num_pins)
855 {
856 struct zynq_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
857
858 *pins = pctrl->groups[selector].pins;
859 *num_pins = pctrl->groups[selector].npins;
860
861 return 0;
862 }
863
864 static const struct pinctrl_ops zynq_pctrl_ops = {
865 .get_groups_count = zynq_pctrl_get_groups_count,
866 .get_group_name = zynq_pctrl_get_group_name,
867 .get_group_pins = zynq_pctrl_get_group_pins,
868 .dt_node_to_map = pinconf_generic_dt_node_to_map_all,
869 .dt_free_map = pinctrl_utils_free_map,
870 };
871
872 /* pinmux */
873 static int zynq_pmux_get_functions_count(struct pinctrl_dev *pctldev)
874 {
875 struct zynq_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
876
877 return pctrl->nfuncs;
878 }
879
880 static const char *zynq_pmux_get_function_name(struct pinctrl_dev *pctldev,
881 unsigned int selector)
882 {
883 struct zynq_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
884
885 return pctrl->funcs[selector].name;
886 }
887
888 static int zynq_pmux_get_function_groups(struct pinctrl_dev *pctldev,
889 unsigned int selector,
890 const char * const **groups,
891 unsigned * const num_groups)
892 {
893 struct zynq_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
894
895 *groups = pctrl->funcs[selector].groups;
896 *num_groups = pctrl->funcs[selector].ngroups;
897 return 0;
898 }
899
900 static int zynq_pinmux_set_mux(struct pinctrl_dev *pctldev,
901 unsigned int function,
902 unsigned int group)
903 {
904 int i, ret;
905 struct zynq_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
906 const struct zynq_pctrl_group *pgrp = &pctrl->groups[group];
907 const struct zynq_pinmux_function *func = &pctrl->funcs[function];
908
909 /*
910 * SD WP & CD are special. They have dedicated registers
911 * to mux them in
912 */
913 if (function == ZYNQ_PMUX_sdio0_cd || function == ZYNQ_PMUX_sdio0_wp ||
914 function == ZYNQ_PMUX_sdio1_cd ||
915 function == ZYNQ_PMUX_sdio1_wp) {
916 u32 reg;
917
918 ret = regmap_read(pctrl->syscon,
919 pctrl->pctrl_offset + func->mux, &reg);
920 if (ret)
921 return ret;
922
923 reg &= ~func->mux_mask;
924 reg |= pgrp->pins[0] << func->mux_shift;
925 ret = regmap_write(pctrl->syscon,
926 pctrl->pctrl_offset + func->mux, reg);
927 if (ret)
928 return ret;
929 } else {
930 for (i = 0; i < pgrp->npins; i++) {
931 unsigned int pin = pgrp->pins[i];
932 u32 reg, addr = pctrl->pctrl_offset + (4 * pin);
933
934 ret = regmap_read(pctrl->syscon, addr, &reg);
935 if (ret)
936 return ret;
937
938 reg &= ~ZYNQ_PINMUX_MUX_MASK;
939 reg |= func->mux_val << ZYNQ_PINMUX_MUX_SHIFT;
940 ret = regmap_write(pctrl->syscon, addr, reg);
941 if (ret)
942 return ret;
943 }
944 }
945
946 return 0;
947 }
948
949 static const struct pinmux_ops zynq_pinmux_ops = {
950 .get_functions_count = zynq_pmux_get_functions_count,
951 .get_function_name = zynq_pmux_get_function_name,
952 .get_function_groups = zynq_pmux_get_function_groups,
953 .set_mux = zynq_pinmux_set_mux,
954 };
955
956 /* pinconfig */
957 #define ZYNQ_PINCONF_TRISTATE BIT(0)
958 #define ZYNQ_PINCONF_SPEED BIT(8)
959 #define ZYNQ_PINCONF_PULLUP BIT(12)
960 #define ZYNQ_PINCONF_DISABLE_RECVR BIT(13)
961
962 #define ZYNQ_PINCONF_IOTYPE_SHIFT 9
963 #define ZYNQ_PINCONF_IOTYPE_MASK (7 << ZYNQ_PINCONF_IOTYPE_SHIFT)
964
965 enum zynq_io_standards {
966 zynq_iostd_min,
967 zynq_iostd_lvcmos18,
968 zynq_iostd_lvcmos25,
969 zynq_iostd_lvcmos33,
970 zynq_iostd_hstl,
971 zynq_iostd_max
972 };
973
974 /*
975 * PIN_CONFIG_IOSTANDARD: if the pin can select an IO standard, the argument to
976 * this parameter (on a custom format) tells the driver which alternative
977 * IO standard to use.
978 */
979 #define PIN_CONFIG_IOSTANDARD (PIN_CONFIG_END + 1)
980
981 static const struct pinconf_generic_params zynq_dt_params[] = {
982 {"io-standard", PIN_CONFIG_IOSTANDARD, zynq_iostd_lvcmos18},
983 };
984
985 #ifdef CONFIG_DEBUG_FS
986 static const struct pin_config_item zynq_conf_items[ARRAY_SIZE(zynq_dt_params)]
987 = { PCONFDUMP(PIN_CONFIG_IOSTANDARD, "IO-standard", NULL, true),
988 };
989 #endif
990
991 static unsigned int zynq_pinconf_iostd_get(u32 reg)
992 {
993 return (reg & ZYNQ_PINCONF_IOTYPE_MASK) >> ZYNQ_PINCONF_IOTYPE_SHIFT;
994 }
995
996 static int zynq_pinconf_cfg_get(struct pinctrl_dev *pctldev,
997 unsigned int pin,
998 unsigned long *config)
999 {
1000 u32 reg;
1001 int ret;
1002 unsigned int arg = 0;
1003 unsigned int param = pinconf_to_config_param(*config);
1004 struct zynq_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
1005
1006 if (pin >= ZYNQ_NUM_MIOS)
1007 return -ENOTSUPP;
1008
1009 ret = regmap_read(pctrl->syscon, pctrl->pctrl_offset + (4 * pin), &reg);
1010 if (ret)
1011 return -EIO;
1012
1013 switch (param) {
1014 case PIN_CONFIG_BIAS_PULL_UP:
1015 if (!(reg & ZYNQ_PINCONF_PULLUP))
1016 return -EINVAL;
1017 arg = 1;
1018 break;
1019 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
1020 if (!(reg & ZYNQ_PINCONF_TRISTATE))
1021 return -EINVAL;
1022 arg = 1;
1023 break;
1024 case PIN_CONFIG_BIAS_DISABLE:
1025 if (reg & ZYNQ_PINCONF_PULLUP || reg & ZYNQ_PINCONF_TRISTATE)
1026 return -EINVAL;
1027 break;
1028 case PIN_CONFIG_SLEW_RATE:
1029 arg = !!(reg & ZYNQ_PINCONF_SPEED);
1030 break;
1031 case PIN_CONFIG_LOW_POWER_MODE:
1032 {
1033 enum zynq_io_standards iostd = zynq_pinconf_iostd_get(reg);
1034
1035 if (iostd != zynq_iostd_hstl)
1036 return -EINVAL;
1037 if (!(reg & ZYNQ_PINCONF_DISABLE_RECVR))
1038 return -EINVAL;
1039 arg = !!(reg & ZYNQ_PINCONF_DISABLE_RECVR);
1040 break;
1041 }
1042 case PIN_CONFIG_IOSTANDARD:
1043 arg = zynq_pinconf_iostd_get(reg);
1044 break;
1045 default:
1046 return -ENOTSUPP;
1047 }
1048
1049 *config = pinconf_to_config_packed(param, arg);
1050 return 0;
1051 }
1052
1053 static int zynq_pinconf_cfg_set(struct pinctrl_dev *pctldev,
1054 unsigned int pin,
1055 unsigned long *configs,
1056 unsigned int num_configs)
1057 {
1058 int i, ret;
1059 u32 reg;
1060 u32 pullup = 0;
1061 u32 tristate = 0;
1062 struct zynq_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
1063
1064 if (pin >= ZYNQ_NUM_MIOS)
1065 return -ENOTSUPP;
1066
1067 ret = regmap_read(pctrl->syscon, pctrl->pctrl_offset + (4 * pin), &reg);
1068 if (ret)
1069 return -EIO;
1070
1071 for (i = 0; i < num_configs; i++) {
1072 unsigned int param = pinconf_to_config_param(configs[i]);
1073 unsigned int arg = pinconf_to_config_argument(configs[i]);
1074
1075 switch (param) {
1076 case PIN_CONFIG_BIAS_PULL_UP:
1077 pullup = ZYNQ_PINCONF_PULLUP;
1078 break;
1079 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
1080 tristate = ZYNQ_PINCONF_TRISTATE;
1081 break;
1082 case PIN_CONFIG_BIAS_DISABLE:
1083 reg &= ~(ZYNQ_PINCONF_PULLUP | ZYNQ_PINCONF_TRISTATE);
1084 break;
1085 case PIN_CONFIG_SLEW_RATE:
1086 if (arg)
1087 reg |= ZYNQ_PINCONF_SPEED;
1088 else
1089 reg &= ~ZYNQ_PINCONF_SPEED;
1090
1091 break;
1092 case PIN_CONFIG_IOSTANDARD:
1093 if (arg <= zynq_iostd_min || arg >= zynq_iostd_max) {
1094 dev_warn(pctldev->dev,
1095 "unsupported IO standard '%u'\n",
1096 param);
1097 break;
1098 }
1099 reg &= ~ZYNQ_PINCONF_IOTYPE_MASK;
1100 reg |= arg << ZYNQ_PINCONF_IOTYPE_SHIFT;
1101 break;
1102 case PIN_CONFIG_LOW_POWER_MODE:
1103 if (arg)
1104 reg |= ZYNQ_PINCONF_DISABLE_RECVR;
1105 else
1106 reg &= ~ZYNQ_PINCONF_DISABLE_RECVR;
1107
1108 break;
1109 default:
1110 dev_warn(pctldev->dev,
1111 "unsupported configuration parameter '%u'\n",
1112 param);
1113 continue;
1114 }
1115 }
1116
1117 if (tristate || pullup) {
1118 reg &= ~(ZYNQ_PINCONF_PULLUP | ZYNQ_PINCONF_TRISTATE);
1119 reg |= tristate | pullup;
1120 }
1121
1122 ret = regmap_write(pctrl->syscon, pctrl->pctrl_offset + (4 * pin), reg);
1123 if (ret)
1124 return -EIO;
1125
1126 return 0;
1127 }
1128
1129 static int zynq_pinconf_group_set(struct pinctrl_dev *pctldev,
1130 unsigned int selector,
1131 unsigned long *configs,
1132 unsigned int num_configs)
1133 {
1134 int i, ret;
1135 struct zynq_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
1136 const struct zynq_pctrl_group *pgrp = &pctrl->groups[selector];
1137
1138 for (i = 0; i < pgrp->npins; i++) {
1139 ret = zynq_pinconf_cfg_set(pctldev, pgrp->pins[i], configs,
1140 num_configs);
1141 if (ret)
1142 return ret;
1143 }
1144
1145 return 0;
1146 }
1147
1148 static const struct pinconf_ops zynq_pinconf_ops = {
1149 .is_generic = true,
1150 .pin_config_get = zynq_pinconf_cfg_get,
1151 .pin_config_set = zynq_pinconf_cfg_set,
1152 .pin_config_group_set = zynq_pinconf_group_set,
1153 };
1154
1155 static struct pinctrl_desc zynq_desc = {
1156 .name = "zynq_pinctrl",
1157 .pins = zynq_pins,
1158 .npins = ARRAY_SIZE(zynq_pins),
1159 .pctlops = &zynq_pctrl_ops,
1160 .pmxops = &zynq_pinmux_ops,
1161 .confops = &zynq_pinconf_ops,
1162 .num_custom_params = ARRAY_SIZE(zynq_dt_params),
1163 .custom_params = zynq_dt_params,
1164 #ifdef CONFIG_DEBUG_FS
1165 .custom_conf_items = zynq_conf_items,
1166 #endif
1167 .owner = THIS_MODULE,
1168 };
1169
1170 static int zynq_pinctrl_probe(struct platform_device *pdev)
1171
1172 {
1173 struct resource *res;
1174 struct zynq_pinctrl *pctrl;
1175
1176 pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);
1177 if (!pctrl)
1178 return -ENOMEM;
1179
1180 pctrl->syscon = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
1181 "syscon");
1182 if (IS_ERR(pctrl->syscon)) {
1183 dev_err(&pdev->dev, "unable to get syscon\n");
1184 return PTR_ERR(pctrl->syscon);
1185 }
1186
1187 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1188 if (!res) {
1189 dev_err(&pdev->dev, "missing IO resource\n");
1190 return -ENODEV;
1191 }
1192 pctrl->pctrl_offset = res->start;
1193
1194 pctrl->groups = zynq_pctrl_groups;
1195 pctrl->ngroups = ARRAY_SIZE(zynq_pctrl_groups);
1196 pctrl->funcs = zynq_pmux_functions;
1197 pctrl->nfuncs = ARRAY_SIZE(zynq_pmux_functions);
1198
1199 pctrl->pctrl = devm_pinctrl_register(&pdev->dev, &zynq_desc, pctrl);
1200 if (IS_ERR(pctrl->pctrl))
1201 return PTR_ERR(pctrl->pctrl);
1202
1203 platform_set_drvdata(pdev, pctrl);
1204
1205 dev_info(&pdev->dev, "zynq pinctrl initialized\n");
1206
1207 return 0;
1208 }
1209
1210 static const struct of_device_id zynq_pinctrl_of_match[] = {
1211 { .compatible = "xlnx,pinctrl-zynq" },
1212 { }
1213 };
1214
1215 static struct platform_driver zynq_pinctrl_driver = {
1216 .driver = {
1217 .name = "zynq-pinctrl",
1218 .of_match_table = zynq_pinctrl_of_match,
1219 },
1220 .probe = zynq_pinctrl_probe,
1221 };
1222
1223 static int __init zynq_pinctrl_init(void)
1224 {
1225 return platform_driver_register(&zynq_pinctrl_driver);
1226 }
1227 arch_initcall(zynq_pinctrl_init);
Linux with added FPC-III support