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Linux 5.1.15
[linux/fpc-iii.git] / drivers / pinctrl / qcom / pinctrl-msm8998.c
blob00d7b94bc3f18aaca93805bafa18f36096ee0e92
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
4 */
5
6 #include <linux/module.h>
7 #include <linux/of.h>
8 #include <linux/platform_device.h>
9 #include <linux/pinctrl/pinctrl.h>
10
11 #include "pinctrl-msm.h"
12
13 #define NORTH 0x500000
14 #define WEST 0x100000
15 #define EAST 0x900000
16
17 #define FUNCTION(fname) \
18 [msm_mux_##fname] = { \
19 .name = #fname, \
20 .groups = fname##_groups, \
21 .ngroups = ARRAY_SIZE(fname##_groups), \
22 }
23
24 #define PINGROUP(id, base, f1, f2, f3, f4, f5, f6, f7, f8, f9) \
25 { \
26 .name = "gpio" #id, \
27 .pins = gpio##id##_pins, \
28 .npins = ARRAY_SIZE(gpio##id##_pins), \
29 .funcs = (int[]){ \
30 msm_mux_gpio, /* gpio mode */ \
31 msm_mux_##f1, \
32 msm_mux_##f2, \
33 msm_mux_##f3, \
34 msm_mux_##f4, \
35 msm_mux_##f5, \
36 msm_mux_##f6, \
37 msm_mux_##f7, \
38 msm_mux_##f8, \
39 msm_mux_##f9 \
40 }, \
41 .nfuncs = 10, \
42 .ctl_reg = base + 0x1000 * id, \
43 .io_reg = base + 0x4 + 0x1000 * id, \
44 .intr_cfg_reg = base + 0x8 + 0x1000 * id, \
45 .intr_status_reg = base + 0xc + 0x1000 * id, \
46 .intr_target_reg = base + 0x8 + 0x1000 * id, \
47 .mux_bit = 2, \
48 .pull_bit = 0, \
49 .drv_bit = 6, \
50 .oe_bit = 9, \
51 .in_bit = 0, \
52 .out_bit = 1, \
53 .intr_enable_bit = 0, \
54 .intr_status_bit = 0, \
55 .intr_target_bit = 5, \
56 .intr_target_kpss_val = 3, \
57 .intr_raw_status_bit = 4, \
58 .intr_polarity_bit = 1, \
59 .intr_detection_bit = 2, \
60 .intr_detection_width = 2, \
61 }
62
63 #define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv) \
64 { \
65 .name = #pg_name, \
66 .pins = pg_name##_pins, \
67 .npins = ARRAY_SIZE(pg_name##_pins), \
68 .ctl_reg = ctl, \
69 .io_reg = 0, \
70 .intr_cfg_reg = 0, \
71 .intr_status_reg = 0, \
72 .intr_target_reg = 0, \
73 .mux_bit = -1, \
74 .pull_bit = pull, \
75 .drv_bit = drv, \
76 .oe_bit = -1, \
77 .in_bit = -1, \
78 .out_bit = -1, \
79 .intr_enable_bit = -1, \
80 .intr_status_bit = -1, \
81 .intr_target_bit = -1, \
82 .intr_raw_status_bit = -1, \
83 .intr_polarity_bit = -1, \
84 .intr_detection_bit = -1, \
85 .intr_detection_width = -1, \
86 }
87
88 #define UFS_RESET(pg_name, offset) \
89 { \
90 .name = #pg_name, \
91 .pins = pg_name##_pins, \
92 .npins = ARRAY_SIZE(pg_name##_pins), \
93 .ctl_reg = offset, \
94 .io_reg = offset + 0x4, \
95 .intr_cfg_reg = 0, \
96 .intr_status_reg = 0, \
97 .intr_target_reg = 0, \
98 .mux_bit = -1, \
99 .pull_bit = 3, \
100 .drv_bit = 0, \
101 .oe_bit = -1, \
102 .in_bit = -1, \
103 .out_bit = 0, \
104 .intr_enable_bit = -1, \
105 .intr_status_bit = -1, \
106 .intr_target_bit = -1, \
107 .intr_raw_status_bit = -1, \
108 .intr_polarity_bit = -1, \
109 .intr_detection_bit = -1, \
110 .intr_detection_width = -1, \
111 }
112
113 static const struct pinctrl_pin_desc msm8998_pins[] = {
114 PINCTRL_PIN(0, "GPIO_0"),
115 PINCTRL_PIN(1, "GPIO_1"),
116 PINCTRL_PIN(2, "GPIO_2"),
117 PINCTRL_PIN(3, "GPIO_3"),
118 PINCTRL_PIN(4, "GPIO_4"),
119 PINCTRL_PIN(5, "GPIO_5"),
120 PINCTRL_PIN(6, "GPIO_6"),
121 PINCTRL_PIN(7, "GPIO_7"),
122 PINCTRL_PIN(8, "GPIO_8"),
123 PINCTRL_PIN(9, "GPIO_9"),
124 PINCTRL_PIN(10, "GPIO_10"),
125 PINCTRL_PIN(11, "GPIO_11"),
126 PINCTRL_PIN(12, "GPIO_12"),
127 PINCTRL_PIN(13, "GPIO_13"),
128 PINCTRL_PIN(14, "GPIO_14"),
129 PINCTRL_PIN(15, "GPIO_15"),
130 PINCTRL_PIN(16, "GPIO_16"),
131 PINCTRL_PIN(17, "GPIO_17"),
132 PINCTRL_PIN(18, "GPIO_18"),
133 PINCTRL_PIN(19, "GPIO_19"),
134 PINCTRL_PIN(20, "GPIO_20"),
135 PINCTRL_PIN(21, "GPIO_21"),
136 PINCTRL_PIN(22, "GPIO_22"),
137 PINCTRL_PIN(23, "GPIO_23"),
138 PINCTRL_PIN(24, "GPIO_24"),
139 PINCTRL_PIN(25, "GPIO_25"),
140 PINCTRL_PIN(26, "GPIO_26"),
141 PINCTRL_PIN(27, "GPIO_27"),
142 PINCTRL_PIN(28, "GPIO_28"),
143 PINCTRL_PIN(29, "GPIO_29"),
144 PINCTRL_PIN(30, "GPIO_30"),
145 PINCTRL_PIN(31, "GPIO_31"),
146 PINCTRL_PIN(32, "GPIO_32"),
147 PINCTRL_PIN(33, "GPIO_33"),
148 PINCTRL_PIN(34, "GPIO_34"),
149 PINCTRL_PIN(35, "GPIO_35"),
150 PINCTRL_PIN(36, "GPIO_36"),
151 PINCTRL_PIN(37, "GPIO_37"),
152 PINCTRL_PIN(38, "GPIO_38"),
153 PINCTRL_PIN(39, "GPIO_39"),
154 PINCTRL_PIN(40, "GPIO_40"),
155 PINCTRL_PIN(41, "GPIO_41"),
156 PINCTRL_PIN(42, "GPIO_42"),
157 PINCTRL_PIN(43, "GPIO_43"),
158 PINCTRL_PIN(44, "GPIO_44"),
159 PINCTRL_PIN(45, "GPIO_45"),
160 PINCTRL_PIN(46, "GPIO_46"),
161 PINCTRL_PIN(47, "GPIO_47"),
162 PINCTRL_PIN(48, "GPIO_48"),
163 PINCTRL_PIN(49, "GPIO_49"),
164 PINCTRL_PIN(50, "GPIO_50"),
165 PINCTRL_PIN(51, "GPIO_51"),
166 PINCTRL_PIN(52, "GPIO_52"),
167 PINCTRL_PIN(53, "GPIO_53"),
168 PINCTRL_PIN(54, "GPIO_54"),
169 PINCTRL_PIN(55, "GPIO_55"),
170 PINCTRL_PIN(56, "GPIO_56"),
171 PINCTRL_PIN(57, "GPIO_57"),
172 PINCTRL_PIN(58, "GPIO_58"),
173 PINCTRL_PIN(59, "GPIO_59"),
174 PINCTRL_PIN(60, "GPIO_60"),
175 PINCTRL_PIN(61, "GPIO_61"),
176 PINCTRL_PIN(62, "GPIO_62"),
177 PINCTRL_PIN(63, "GPIO_63"),
178 PINCTRL_PIN(64, "GPIO_64"),
179 PINCTRL_PIN(65, "GPIO_65"),
180 PINCTRL_PIN(66, "GPIO_66"),
181 PINCTRL_PIN(67, "GPIO_67"),
182 PINCTRL_PIN(68, "GPIO_68"),
183 PINCTRL_PIN(69, "GPIO_69"),
184 PINCTRL_PIN(70, "GPIO_70"),
185 PINCTRL_PIN(71, "GPIO_71"),
186 PINCTRL_PIN(72, "GPIO_72"),
187 PINCTRL_PIN(73, "GPIO_73"),
188 PINCTRL_PIN(74, "GPIO_74"),
189 PINCTRL_PIN(75, "GPIO_75"),
190 PINCTRL_PIN(76, "GPIO_76"),
191 PINCTRL_PIN(77, "GPIO_77"),
192 PINCTRL_PIN(78, "GPIO_78"),
193 PINCTRL_PIN(79, "GPIO_79"),
194 PINCTRL_PIN(80, "GPIO_80"),
195 PINCTRL_PIN(81, "GPIO_81"),
196 PINCTRL_PIN(82, "GPIO_82"),
197 PINCTRL_PIN(83, "GPIO_83"),
198 PINCTRL_PIN(84, "GPIO_84"),
199 PINCTRL_PIN(85, "GPIO_85"),
200 PINCTRL_PIN(86, "GPIO_86"),
201 PINCTRL_PIN(87, "GPIO_87"),
202 PINCTRL_PIN(88, "GPIO_88"),
203 PINCTRL_PIN(89, "GPIO_89"),
204 PINCTRL_PIN(90, "GPIO_90"),
205 PINCTRL_PIN(91, "GPIO_91"),
206 PINCTRL_PIN(92, "GPIO_92"),
207 PINCTRL_PIN(93, "GPIO_93"),
208 PINCTRL_PIN(94, "GPIO_94"),
209 PINCTRL_PIN(95, "GPIO_95"),
210 PINCTRL_PIN(96, "GPIO_96"),
211 PINCTRL_PIN(97, "GPIO_97"),
212 PINCTRL_PIN(98, "GPIO_98"),
213 PINCTRL_PIN(99, "GPIO_99"),
214 PINCTRL_PIN(100, "GPIO_100"),
215 PINCTRL_PIN(101, "GPIO_101"),
216 PINCTRL_PIN(102, "GPIO_102"),
217 PINCTRL_PIN(103, "GPIO_103"),
218 PINCTRL_PIN(104, "GPIO_104"),
219 PINCTRL_PIN(105, "GPIO_105"),
220 PINCTRL_PIN(106, "GPIO_106"),
221 PINCTRL_PIN(107, "GPIO_107"),
222 PINCTRL_PIN(108, "GPIO_108"),
223 PINCTRL_PIN(109, "GPIO_109"),
224 PINCTRL_PIN(110, "GPIO_110"),
225 PINCTRL_PIN(111, "GPIO_111"),
226 PINCTRL_PIN(112, "GPIO_112"),
227 PINCTRL_PIN(113, "GPIO_113"),
228 PINCTRL_PIN(114, "GPIO_114"),
229 PINCTRL_PIN(115, "GPIO_115"),
230 PINCTRL_PIN(116, "GPIO_116"),
231 PINCTRL_PIN(117, "GPIO_117"),
232 PINCTRL_PIN(118, "GPIO_118"),
233 PINCTRL_PIN(119, "GPIO_119"),
234 PINCTRL_PIN(120, "GPIO_120"),
235 PINCTRL_PIN(121, "GPIO_121"),
236 PINCTRL_PIN(122, "GPIO_122"),
237 PINCTRL_PIN(123, "GPIO_123"),
238 PINCTRL_PIN(124, "GPIO_124"),
239 PINCTRL_PIN(125, "GPIO_125"),
240 PINCTRL_PIN(126, "GPIO_126"),
241 PINCTRL_PIN(127, "GPIO_127"),
242 PINCTRL_PIN(128, "GPIO_128"),
243 PINCTRL_PIN(129, "GPIO_129"),
244 PINCTRL_PIN(130, "GPIO_130"),
245 PINCTRL_PIN(131, "GPIO_131"),
246 PINCTRL_PIN(132, "GPIO_132"),
247 PINCTRL_PIN(133, "GPIO_133"),
248 PINCTRL_PIN(134, "GPIO_134"),
249 PINCTRL_PIN(135, "GPIO_135"),
250 PINCTRL_PIN(136, "GPIO_136"),
251 PINCTRL_PIN(137, "GPIO_137"),
252 PINCTRL_PIN(138, "GPIO_138"),
253 PINCTRL_PIN(139, "GPIO_139"),
254 PINCTRL_PIN(140, "GPIO_140"),
255 PINCTRL_PIN(141, "GPIO_141"),
256 PINCTRL_PIN(142, "GPIO_142"),
257 PINCTRL_PIN(143, "GPIO_143"),
258 PINCTRL_PIN(144, "GPIO_144"),
259 PINCTRL_PIN(145, "GPIO_145"),
260 PINCTRL_PIN(146, "GPIO_146"),
261 PINCTRL_PIN(147, "GPIO_147"),
262 PINCTRL_PIN(148, "GPIO_148"),
263 PINCTRL_PIN(149, "GPIO_149"),
264 PINCTRL_PIN(150, "SDC2_CLK"),
265 PINCTRL_PIN(151, "SDC2_CMD"),
266 PINCTRL_PIN(152, "SDC2_DATA"),
267 PINCTRL_PIN(153, "UFS_RESET"),
268 };
269
270 #define DECLARE_MSM_GPIO_PINS(pin) \
271 static const unsigned int gpio##pin##_pins[] = { pin }
272 DECLARE_MSM_GPIO_PINS(0);
273 DECLARE_MSM_GPIO_PINS(1);
274 DECLARE_MSM_GPIO_PINS(2);
275 DECLARE_MSM_GPIO_PINS(3);
276 DECLARE_MSM_GPIO_PINS(4);
277 DECLARE_MSM_GPIO_PINS(5);
278 DECLARE_MSM_GPIO_PINS(6);
279 DECLARE_MSM_GPIO_PINS(7);
280 DECLARE_MSM_GPIO_PINS(8);
281 DECLARE_MSM_GPIO_PINS(9);
282 DECLARE_MSM_GPIO_PINS(10);
283 DECLARE_MSM_GPIO_PINS(11);
284 DECLARE_MSM_GPIO_PINS(12);
285 DECLARE_MSM_GPIO_PINS(13);
286 DECLARE_MSM_GPIO_PINS(14);
287 DECLARE_MSM_GPIO_PINS(15);
288 DECLARE_MSM_GPIO_PINS(16);
289 DECLARE_MSM_GPIO_PINS(17);
290 DECLARE_MSM_GPIO_PINS(18);
291 DECLARE_MSM_GPIO_PINS(19);
292 DECLARE_MSM_GPIO_PINS(20);
293 DECLARE_MSM_GPIO_PINS(21);
294 DECLARE_MSM_GPIO_PINS(22);
295 DECLARE_MSM_GPIO_PINS(23);
296 DECLARE_MSM_GPIO_PINS(24);
297 DECLARE_MSM_GPIO_PINS(25);
298 DECLARE_MSM_GPIO_PINS(26);
299 DECLARE_MSM_GPIO_PINS(27);
300 DECLARE_MSM_GPIO_PINS(28);
301 DECLARE_MSM_GPIO_PINS(29);
302 DECLARE_MSM_GPIO_PINS(30);
303 DECLARE_MSM_GPIO_PINS(31);
304 DECLARE_MSM_GPIO_PINS(32);
305 DECLARE_MSM_GPIO_PINS(33);
306 DECLARE_MSM_GPIO_PINS(34);
307 DECLARE_MSM_GPIO_PINS(35);
308 DECLARE_MSM_GPIO_PINS(36);
309 DECLARE_MSM_GPIO_PINS(37);
310 DECLARE_MSM_GPIO_PINS(38);
311 DECLARE_MSM_GPIO_PINS(39);
312 DECLARE_MSM_GPIO_PINS(40);
313 DECLARE_MSM_GPIO_PINS(41);
314 DECLARE_MSM_GPIO_PINS(42);
315 DECLARE_MSM_GPIO_PINS(43);
316 DECLARE_MSM_GPIO_PINS(44);
317 DECLARE_MSM_GPIO_PINS(45);
318 DECLARE_MSM_GPIO_PINS(46);
319 DECLARE_MSM_GPIO_PINS(47);
320 DECLARE_MSM_GPIO_PINS(48);
321 DECLARE_MSM_GPIO_PINS(49);
322 DECLARE_MSM_GPIO_PINS(50);
323 DECLARE_MSM_GPIO_PINS(51);
324 DECLARE_MSM_GPIO_PINS(52);
325 DECLARE_MSM_GPIO_PINS(53);
326 DECLARE_MSM_GPIO_PINS(54);
327 DECLARE_MSM_GPIO_PINS(55);
328 DECLARE_MSM_GPIO_PINS(56);
329 DECLARE_MSM_GPIO_PINS(57);
330 DECLARE_MSM_GPIO_PINS(58);
331 DECLARE_MSM_GPIO_PINS(59);
332 DECLARE_MSM_GPIO_PINS(60);
333 DECLARE_MSM_GPIO_PINS(61);
334 DECLARE_MSM_GPIO_PINS(62);
335 DECLARE_MSM_GPIO_PINS(63);
336 DECLARE_MSM_GPIO_PINS(64);
337 DECLARE_MSM_GPIO_PINS(65);
338 DECLARE_MSM_GPIO_PINS(66);
339 DECLARE_MSM_GPIO_PINS(67);
340 DECLARE_MSM_GPIO_PINS(68);
341 DECLARE_MSM_GPIO_PINS(69);
342 DECLARE_MSM_GPIO_PINS(70);
343 DECLARE_MSM_GPIO_PINS(71);
344 DECLARE_MSM_GPIO_PINS(72);
345 DECLARE_MSM_GPIO_PINS(73);
346 DECLARE_MSM_GPIO_PINS(74);
347 DECLARE_MSM_GPIO_PINS(75);
348 DECLARE_MSM_GPIO_PINS(76);
349 DECLARE_MSM_GPIO_PINS(77);
350 DECLARE_MSM_GPIO_PINS(78);
351 DECLARE_MSM_GPIO_PINS(79);
352 DECLARE_MSM_GPIO_PINS(80);
353 DECLARE_MSM_GPIO_PINS(81);
354 DECLARE_MSM_GPIO_PINS(82);
355 DECLARE_MSM_GPIO_PINS(83);
356 DECLARE_MSM_GPIO_PINS(84);
357 DECLARE_MSM_GPIO_PINS(85);
358 DECLARE_MSM_GPIO_PINS(86);
359 DECLARE_MSM_GPIO_PINS(87);
360 DECLARE_MSM_GPIO_PINS(88);
361 DECLARE_MSM_GPIO_PINS(89);
362 DECLARE_MSM_GPIO_PINS(90);
363 DECLARE_MSM_GPIO_PINS(91);
364 DECLARE_MSM_GPIO_PINS(92);
365 DECLARE_MSM_GPIO_PINS(93);
366 DECLARE_MSM_GPIO_PINS(94);
367 DECLARE_MSM_GPIO_PINS(95);
368 DECLARE_MSM_GPIO_PINS(96);
369 DECLARE_MSM_GPIO_PINS(97);
370 DECLARE_MSM_GPIO_PINS(98);
371 DECLARE_MSM_GPIO_PINS(99);
372 DECLARE_MSM_GPIO_PINS(100);
373 DECLARE_MSM_GPIO_PINS(101);
374 DECLARE_MSM_GPIO_PINS(102);
375 DECLARE_MSM_GPIO_PINS(103);
376 DECLARE_MSM_GPIO_PINS(104);
377 DECLARE_MSM_GPIO_PINS(105);
378 DECLARE_MSM_GPIO_PINS(106);
379 DECLARE_MSM_GPIO_PINS(107);
380 DECLARE_MSM_GPIO_PINS(108);
381 DECLARE_MSM_GPIO_PINS(109);
382 DECLARE_MSM_GPIO_PINS(110);
383 DECLARE_MSM_GPIO_PINS(111);
384 DECLARE_MSM_GPIO_PINS(112);
385 DECLARE_MSM_GPIO_PINS(113);
386 DECLARE_MSM_GPIO_PINS(114);
387 DECLARE_MSM_GPIO_PINS(115);
388 DECLARE_MSM_GPIO_PINS(116);
389 DECLARE_MSM_GPIO_PINS(117);
390 DECLARE_MSM_GPIO_PINS(118);
391 DECLARE_MSM_GPIO_PINS(119);
392 DECLARE_MSM_GPIO_PINS(120);
393 DECLARE_MSM_GPIO_PINS(121);
394 DECLARE_MSM_GPIO_PINS(122);
395 DECLARE_MSM_GPIO_PINS(123);
396 DECLARE_MSM_GPIO_PINS(124);
397 DECLARE_MSM_GPIO_PINS(125);
398 DECLARE_MSM_GPIO_PINS(126);
399 DECLARE_MSM_GPIO_PINS(127);
400 DECLARE_MSM_GPIO_PINS(128);
401 DECLARE_MSM_GPIO_PINS(129);
402 DECLARE_MSM_GPIO_PINS(130);
403 DECLARE_MSM_GPIO_PINS(131);
404 DECLARE_MSM_GPIO_PINS(132);
405 DECLARE_MSM_GPIO_PINS(133);
406 DECLARE_MSM_GPIO_PINS(134);
407 DECLARE_MSM_GPIO_PINS(135);
408 DECLARE_MSM_GPIO_PINS(136);
409 DECLARE_MSM_GPIO_PINS(137);
410 DECLARE_MSM_GPIO_PINS(138);
411 DECLARE_MSM_GPIO_PINS(139);
412 DECLARE_MSM_GPIO_PINS(140);
413 DECLARE_MSM_GPIO_PINS(141);
414 DECLARE_MSM_GPIO_PINS(142);
415 DECLARE_MSM_GPIO_PINS(143);
416 DECLARE_MSM_GPIO_PINS(144);
417 DECLARE_MSM_GPIO_PINS(145);
418 DECLARE_MSM_GPIO_PINS(146);
419 DECLARE_MSM_GPIO_PINS(147);
420 DECLARE_MSM_GPIO_PINS(148);
421 DECLARE_MSM_GPIO_PINS(149);
422
423 static const unsigned int sdc2_clk_pins[] = { 150 };
424 static const unsigned int sdc2_cmd_pins[] = { 151 };
425 static const unsigned int sdc2_data_pins[] = { 152 };
426 static const unsigned int ufs_reset_pins[] = { 153 };
427
428 enum msm8998_functions {
429 msm_mux_adsp_ext,
430 msm_mux_agera_pll,
431 msm_mux_atest_char,
432 msm_mux_atest_gpsadc0,
433 msm_mux_atest_gpsadc1,
434 msm_mux_atest_tsens,
435 msm_mux_atest_tsens2,
436 msm_mux_atest_usb1,
437 msm_mux_atest_usb10,
438 msm_mux_atest_usb11,
439 msm_mux_atest_usb12,
440 msm_mux_atest_usb13,
441 msm_mux_audio_ref,
442 msm_mux_bimc_dte0,
443 msm_mux_bimc_dte1,
444 msm_mux_blsp10_spi,
445 msm_mux_blsp10_spi_a,
446 msm_mux_blsp10_spi_b,
447 msm_mux_blsp11_i2c,
448 msm_mux_blsp1_spi,
449 msm_mux_blsp1_spi_a,
450 msm_mux_blsp1_spi_b,
451 msm_mux_blsp2_spi,
452 msm_mux_blsp9_spi,
453 msm_mux_blsp_i2c1,
454 msm_mux_blsp_i2c10,
455 msm_mux_blsp_i2c11,
456 msm_mux_blsp_i2c12,
457 msm_mux_blsp_i2c2,
458 msm_mux_blsp_i2c3,
459 msm_mux_blsp_i2c4,
460 msm_mux_blsp_i2c5,
461 msm_mux_blsp_i2c6,
462 msm_mux_blsp_i2c7,
463 msm_mux_blsp_i2c8,
464 msm_mux_blsp_i2c9,
465 msm_mux_blsp_spi1,
466 msm_mux_blsp_spi10,
467 msm_mux_blsp_spi11,
468 msm_mux_blsp_spi12,
469 msm_mux_blsp_spi2,
470 msm_mux_blsp_spi3,
471 msm_mux_blsp_spi4,
472 msm_mux_blsp_spi5,
473 msm_mux_blsp_spi6,
474 msm_mux_blsp_spi7,
475 msm_mux_blsp_spi8,
476 msm_mux_blsp_spi9,
477 msm_mux_blsp_uart1_a,
478 msm_mux_blsp_uart1_b,
479 msm_mux_blsp_uart2_a,
480 msm_mux_blsp_uart2_b,
481 msm_mux_blsp_uart3_a,
482 msm_mux_blsp_uart3_b,
483 msm_mux_blsp_uart7_a,
484 msm_mux_blsp_uart7_b,
485 msm_mux_blsp_uart8,
486 msm_mux_blsp_uart8_a,
487 msm_mux_blsp_uart8_b,
488 msm_mux_blsp_uart9_a,
489 msm_mux_blsp_uart9_b,
490 msm_mux_blsp_uim1_a,
491 msm_mux_blsp_uim1_b,
492 msm_mux_blsp_uim2_a,
493 msm_mux_blsp_uim2_b,
494 msm_mux_blsp_uim3_a,
495 msm_mux_blsp_uim3_b,
496 msm_mux_blsp_uim7_a,
497 msm_mux_blsp_uim7_b,
498 msm_mux_blsp_uim8_a,
499 msm_mux_blsp_uim8_b,
500 msm_mux_blsp_uim9_a,
501 msm_mux_blsp_uim9_b,
502 msm_mux_bt_reset,
503 msm_mux_btfm_slimbus,
504 msm_mux_cam_mclk,
505 msm_mux_cci_async,
506 msm_mux_cci_i2c,
507 msm_mux_cci_timer0,
508 msm_mux_cci_timer1,
509 msm_mux_cci_timer2,
510 msm_mux_cci_timer3,
511 msm_mux_cci_timer4,
512 msm_mux_cri_trng,
513 msm_mux_cri_trng0,
514 msm_mux_cri_trng1,
515 msm_mux_dbg_out,
516 msm_mux_ddr_bist,
517 msm_mux_edp_hot,
518 msm_mux_edp_lcd,
519 msm_mux_gcc_gp1_a,
520 msm_mux_gcc_gp1_b,
521 msm_mux_gcc_gp2_a,
522 msm_mux_gcc_gp2_b,
523 msm_mux_gcc_gp3_a,
524 msm_mux_gcc_gp3_b,
525 msm_mux_gpio,
526 msm_mux_hdmi_cec,
527 msm_mux_hdmi_ddc,
528 msm_mux_hdmi_hot,
529 msm_mux_hdmi_rcv,
530 msm_mux_isense_dbg,
531 msm_mux_jitter_bist,
532 msm_mux_ldo_en,
533 msm_mux_ldo_update,
534 msm_mux_lpass_slimbus,
535 msm_mux_m_voc,
536 msm_mux_mdp_vsync,
537 msm_mux_mdp_vsync0,
538 msm_mux_mdp_vsync1,
539 msm_mux_mdp_vsync2,
540 msm_mux_mdp_vsync3,
541 msm_mux_mdp_vsync_a,
542 msm_mux_mdp_vsync_b,
543 msm_mux_modem_tsync,
544 msm_mux_mss_lte,
545 msm_mux_nav_dr,
546 msm_mux_nav_pps,
547 msm_mux_pa_indicator,
548 msm_mux_pci_e0,
549 msm_mux_phase_flag,
550 msm_mux_pll_bypassnl,
551 msm_mux_pll_reset,
552 msm_mux_pri_mi2s,
553 msm_mux_pri_mi2s_ws,
554 msm_mux_prng_rosc,
555 msm_mux_pwr_crypto,
556 msm_mux_pwr_modem,
557 msm_mux_pwr_nav,
558 msm_mux_qdss_cti0_a,
559 msm_mux_qdss_cti0_b,
560 msm_mux_qdss_cti1_a,
561 msm_mux_qdss_cti1_b,
562 msm_mux_qdss,
563 msm_mux_qlink_enable,
564 msm_mux_qlink_request,
565 msm_mux_qua_mi2s,
566 msm_mux_sd_card,
567 msm_mux_sd_write,
568 msm_mux_sdc40,
569 msm_mux_sdc41,
570 msm_mux_sdc42,
571 msm_mux_sdc43,
572 msm_mux_sdc4_clk,
573 msm_mux_sdc4_cmd,
574 msm_mux_sec_mi2s,
575 msm_mux_sp_cmu,
576 msm_mux_spkr_i2s,
577 msm_mux_ssbi1,
578 msm_mux_ssc_irq,
579 msm_mux_ter_mi2s,
580 msm_mux_tgu_ch0,
581 msm_mux_tgu_ch1,
582 msm_mux_tsense_pwm1,
583 msm_mux_tsense_pwm2,
584 msm_mux_tsif1_clk,
585 msm_mux_tsif1_data,
586 msm_mux_tsif1_en,
587 msm_mux_tsif1_error,
588 msm_mux_tsif1_sync,
589 msm_mux_tsif2_clk,
590 msm_mux_tsif2_data,
591 msm_mux_tsif2_en,
592 msm_mux_tsif2_error,
593 msm_mux_tsif2_sync,
594 msm_mux_uim1_clk,
595 msm_mux_uim1_data,
596 msm_mux_uim1_present,
597 msm_mux_uim1_reset,
598 msm_mux_uim2_clk,
599 msm_mux_uim2_data,
600 msm_mux_uim2_present,
601 msm_mux_uim2_reset,
602 msm_mux_uim_batt,
603 msm_mux_usb_phy,
604 msm_mux_vfr_1,
605 msm_mux_vsense_clkout,
606 msm_mux_vsense_data0,
607 msm_mux_vsense_data1,
608 msm_mux_vsense_mode,
609 msm_mux_wlan1_adc0,
610 msm_mux_wlan1_adc1,
611 msm_mux_wlan2_adc0,
612 msm_mux_wlan2_adc1,
613 msm_mux__,
614 };
615
616 static const char * const gpio_groups[] = {
617 "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7",
618 "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14",
619 "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21",
620 "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28",
621 "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35",
622 "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42",
623 "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49",
624 "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56",
625 "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63",
626 "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69", "gpio70",
627 "gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77",
628 "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84",
629 "gpio85", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", "gpio91",
630 "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", "gpio98",
631 "gpio99", "gpio100", "gpio101", "gpio102", "gpio103", "gpio104",
632 "gpio105", "gpio106", "gpio107", "gpio108", "gpio109", "gpio110",
633 "gpio111", "gpio112", "gpio113", "gpio114", "gpio115", "gpio116",
634 "gpio117", "gpio118", "gpio119", "gpio120", "gpio121", "gpio122",
635 "gpio123", "gpio124", "gpio125", "gpio126", "gpio127", "gpio128",
636 "gpio129", "gpio130", "gpio131", "gpio132", "gpio133", "gpio134",
637 "gpio135", "gpio136", "gpio137", "gpio138", "gpio139", "gpio140",
638 "gpio141", "gpio142", "gpio143", "gpio144", "gpio145", "gpio146",
639 "gpio147", "gpio148", "gpio149",
640 };
641 static const char * const blsp_spi1_groups[] = {
642 "gpio0", "gpio1", "gpio2", "gpio3",
643 };
644 static const char * const blsp_uim1_a_groups[] = {
645 "gpio0", "gpio1",
646 };
647 static const char * const blsp_uart1_a_groups[] = {
648 "gpio0", "gpio1", "gpio2", "gpio3",
649 };
650 static const char * const blsp_i2c1_groups[] = {
651 "gpio2", "gpio3",
652 };
653 static const char * const blsp_spi8_groups[] = {
654 "gpio4", "gpio5", "gpio6", "gpio7",
655 };
656 static const char * const blsp_uart8_a_groups[] = {
657 "gpio4", "gpio5", "gpio6", "gpio7",
658 };
659 static const char * const blsp_uim8_a_groups[] = {
660 "gpio4", "gpio5",
661 };
662 static const char * const qdss_cti0_b_groups[] = {
663 "gpio4", "gpio5",
664 };
665 static const char * const blsp_i2c8_groups[] = {
666 "gpio6", "gpio7",
667 };
668 static const char * const ddr_bist_groups[] = {
669 "gpio7", "gpio8", "gpio9", "gpio10",
670 };
671 static const char * const atest_tsens2_groups[] = {
672 "gpio7",
673 };
674 static const char * const atest_usb1_groups[] = {
675 "gpio7",
676 };
677 static const char * const blsp_spi4_groups[] = {
678 "gpio8", "gpio9", "gpio10", "gpio11",
679 };
680 static const char * const blsp_uart1_b_groups[] = {
681 "gpio8", "gpio9", "gpio10", "gpio11",
682 };
683 static const char * const blsp_uim1_b_groups[] = {
684 "gpio8", "gpio9",
685 };
686 static const char * const wlan1_adc1_groups[] = {
687 "gpio8",
688 };
689 static const char * const atest_usb13_groups[] = {
690 "gpio8",
691 };
692 static const char * const bimc_dte1_groups[] = {
693 "gpio8", "gpio10",
694 };
695 static const char * const tsif1_sync_groups[] = {
696 "gpio9",
697 };
698 static const char * const wlan1_adc0_groups[] = {
699 "gpio9",
700 };
701 static const char * const atest_usb12_groups[] = {
702 "gpio9",
703 };
704 static const char * const bimc_dte0_groups[] = {
705 "gpio9", "gpio11",
706 };
707 static const char * const mdp_vsync_a_groups[] = {
708 "gpio10", "gpio11",
709 };
710 static const char * const blsp_i2c4_groups[] = {
711 "gpio10", "gpio11",
712 };
713 static const char * const atest_gpsadc1_groups[] = {
714 "gpio10",
715 };
716 static const char * const wlan2_adc1_groups[] = {
717 "gpio10",
718 };
719 static const char * const atest_usb11_groups[] = {
720 "gpio10",
721 };
722 static const char * const edp_lcd_groups[] = {
723 "gpio11",
724 };
725 static const char * const dbg_out_groups[] = {
726 "gpio11",
727 };
728 static const char * const atest_gpsadc0_groups[] = {
729 "gpio11",
730 };
731 static const char * const wlan2_adc0_groups[] = {
732 "gpio11",
733 };
734 static const char * const atest_usb10_groups[] = {
735 "gpio11",
736 };
737 static const char * const mdp_vsync_groups[] = {
738 "gpio12",
739 };
740 static const char * const m_voc_groups[] = {
741 "gpio12",
742 };
743 static const char * const cam_mclk_groups[] = {
744 "gpio13", "gpio14", "gpio15", "gpio16",
745 };
746 static const char * const pll_bypassnl_groups[] = {
747 "gpio13",
748 };
749 static const char * const qdss_groups[] = {
750 "gpio13", "gpio14", "gpio15", "gpio16", "gpio17", "gpio18", "gpio19",
751 "gpio20", "gpio21", "gpio22", "gpio23", "gpio24", "gpio25", "gpio26",
752 "gpio27", "gpio28", "gpio29", "gpio30", "gpio41", "gpio42", "gpio43",
753 "gpio44", "gpio75", "gpio76", "gpio77", "gpio79", "gpio80", "gpio93",
754 "gpio117", "gpio118", "gpio119", "gpio120", "gpio121", "gpio122",
755 "gpio123", "gpio124",
756 };
757 static const char * const pll_reset_groups[] = {
758 "gpio14",
759 };
760 static const char * const cci_i2c_groups[] = {
761 "gpio17", "gpio18", "gpio19", "gpio20",
762 };
763 static const char * const phase_flag_groups[] = {
764 "gpio18", "gpio19", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77",
765 "gpio89", "gpio91", "gpio92", "gpio96", "gpio114", "gpio115",
766 "gpio116", "gpio117", "gpio118", "gpio119", "gpio120", "gpio121",
767 "gpio122", "gpio123", "gpio124", "gpio125", "gpio126", "gpio128",
768 "gpio129", "gpio130", "gpio131", "gpio132", "gpio133", "gpio134",
769 };
770 static const char * const cci_timer4_groups[] = {
771 "gpio25",
772 };
773 static const char * const blsp2_spi_groups[] = {
774 "gpio25", "gpio29", "gpio30",
775 };
776 static const char * const cci_timer0_groups[] = {
777 "gpio21",
778 };
779 static const char * const vsense_data0_groups[] = {
780 "gpio21",
781 };
782 static const char * const cci_timer1_groups[] = {
783 "gpio22",
784 };
785 static const char * const vsense_data1_groups[] = {
786 "gpio22",
787 };
788 static const char * const cci_timer2_groups[] = {
789 "gpio23",
790 };
791 static const char * const blsp1_spi_b_groups[] = {
792 "gpio23", "gpio28",
793 };
794 static const char * const vsense_mode_groups[] = {
795 "gpio23",
796 };
797 static const char * const cci_timer3_groups[] = {
798 "gpio24",
799 };
800 static const char * const cci_async_groups[] = {
801 "gpio24", "gpio25", "gpio26",
802 };
803 static const char * const blsp1_spi_a_groups[] = {
804 "gpio24", "gpio27",
805 };
806 static const char * const vsense_clkout_groups[] = {
807 "gpio24",
808 };
809 static const char * const hdmi_rcv_groups[] = {
810 "gpio30",
811 };
812 static const char * const hdmi_cec_groups[] = {
813 "gpio31",
814 };
815 static const char * const blsp_spi2_groups[] = {
816 "gpio31", "gpio32", "gpio33", "gpio34",
817 };
818 static const char * const blsp_uart2_a_groups[] = {
819 "gpio31", "gpio32", "gpio33", "gpio34",
820 };
821 static const char * const blsp_uim2_a_groups[] = {
822 "gpio31", "gpio34",
823 };
824 static const char * const pwr_modem_groups[] = {
825 "gpio31",
826 };
827 static const char * const hdmi_ddc_groups[] = {
828 "gpio32", "gpio33",
829 };
830 static const char * const blsp_i2c2_groups[] = {
831 "gpio32", "gpio33",
832 };
833 static const char * const pwr_nav_groups[] = {
834 "gpio32",
835 };
836 static const char * const pwr_crypto_groups[] = {
837 "gpio33",
838 };
839 static const char * const hdmi_hot_groups[] = {
840 "gpio34",
841 };
842 static const char * const edp_hot_groups[] = {
843 "gpio34",
844 };
845 static const char * const pci_e0_groups[] = {
846 "gpio35", "gpio36", "gpio37",
847 };
848 static const char * const jitter_bist_groups[] = {
849 "gpio35",
850 };
851 static const char * const agera_pll_groups[] = {
852 "gpio36", "gpio37",
853 };
854 static const char * const atest_tsens_groups[] = {
855 "gpio36",
856 };
857 static const char * const usb_phy_groups[] = {
858 "gpio38",
859 };
860 static const char * const lpass_slimbus_groups[] = {
861 "gpio39", "gpio70", "gpio71", "gpio72",
862 };
863 static const char * const sd_write_groups[] = {
864 "gpio40",
865 };
866 static const char * const tsif1_error_groups[] = {
867 "gpio40",
868 };
869 static const char * const blsp_spi6_groups[] = {
870 "gpio41", "gpio42", "gpio43", "gpio44",
871 };
872 static const char * const blsp_uart3_b_groups[] = {
873 "gpio41", "gpio42", "gpio43", "gpio44",
874 };
875 static const char * const blsp_uim3_b_groups[] = {
876 "gpio41", "gpio42",
877 };
878 static const char * const blsp_i2c6_groups[] = {
879 "gpio43", "gpio44",
880 };
881 static const char * const bt_reset_groups[] = {
882 "gpio45",
883 };
884 static const char * const blsp_spi3_groups[] = {
885 "gpio45", "gpio46", "gpio47", "gpio48",
886 };
887 static const char * const blsp_uart3_a_groups[] = {
888 "gpio45", "gpio46", "gpio47", "gpio48",
889 };
890 static const char * const blsp_uim3_a_groups[] = {
891 "gpio45", "gpio46",
892 };
893 static const char * const blsp_i2c3_groups[] = {
894 "gpio47", "gpio48",
895 };
896 static const char * const blsp_spi9_groups[] = {
897 "gpio49", "gpio50", "gpio51", "gpio52",
898 };
899 static const char * const blsp_uart9_a_groups[] = {
900 "gpio49", "gpio50", "gpio51", "gpio52",
901 };
902 static const char * const blsp_uim9_a_groups[] = {
903 "gpio49", "gpio50",
904 };
905 static const char * const blsp10_spi_b_groups[] = {
906 "gpio49", "gpio50",
907 };
908 static const char * const qdss_cti0_a_groups[] = {
909 "gpio49", "gpio50",
910 };
911 static const char * const blsp_i2c9_groups[] = {
912 "gpio51", "gpio52",
913 };
914 static const char * const blsp10_spi_a_groups[] = {
915 "gpio51", "gpio52",
916 };
917 static const char * const blsp_spi7_groups[] = {
918 "gpio53", "gpio54", "gpio55", "gpio56",
919 };
920 static const char * const blsp_uart7_a_groups[] = {
921 "gpio53", "gpio54", "gpio55", "gpio56",
922 };
923 static const char * const blsp_uim7_a_groups[] = {
924 "gpio53", "gpio54",
925 };
926 static const char * const blsp_i2c7_groups[] = {
927 "gpio55", "gpio56",
928 };
929 static const char * const qua_mi2s_groups[] = {
930 "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63",
931 };
932 static const char * const blsp10_spi_groups[] = {
933 "gpio57",
934 };
935 static const char * const gcc_gp1_a_groups[] = {
936 "gpio57",
937 };
938 static const char * const ssc_irq_groups[] = {
939 "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63", "gpio78",
940 "gpio79", "gpio80", "gpio117", "gpio118", "gpio119", "gpio120",
941 "gpio121", "gpio122", "gpio123", "gpio124", "gpio125",
942 };
943 static const char * const blsp_spi11_groups[] = {
944 "gpio58", "gpio59", "gpio60", "gpio61",
945 };
946 static const char * const blsp_uart8_b_groups[] = {
947 "gpio58", "gpio59", "gpio60", "gpio61",
948 };
949 static const char * const blsp_uim8_b_groups[] = {
950 "gpio58", "gpio59",
951 };
952 static const char * const gcc_gp2_a_groups[] = {
953 "gpio58",
954 };
955 static const char * const qdss_cti1_a_groups[] = {
956 "gpio58", "gpio59",
957 };
958 static const char * const gcc_gp3_a_groups[] = {
959 "gpio59",
960 };
961 static const char * const blsp_i2c11_groups[] = {
962 "gpio60", "gpio61",
963 };
964 static const char * const cri_trng0_groups[] = {
965 "gpio60",
966 };
967 static const char * const cri_trng1_groups[] = {
968 "gpio61",
969 };
970 static const char * const cri_trng_groups[] = {
971 "gpio62",
972 };
973 static const char * const pri_mi2s_groups[] = {
974 "gpio64", "gpio65", "gpio67", "gpio68",
975 };
976 static const char * const sp_cmu_groups[] = {
977 "gpio64",
978 };
979 static const char * const blsp_spi10_groups[] = {
980 "gpio65", "gpio66", "gpio67", "gpio68",
981 };
982 static const char * const blsp_uart7_b_groups[] = {
983 "gpio65", "gpio66", "gpio67", "gpio68",
984 };
985 static const char * const blsp_uim7_b_groups[] = {
986 "gpio65", "gpio66",
987 };
988 static const char * const pri_mi2s_ws_groups[] = {
989 "gpio66",
990 };
991 static const char * const blsp_i2c10_groups[] = {
992 "gpio67", "gpio68",
993 };
994 static const char * const spkr_i2s_groups[] = {
995 "gpio69", "gpio70", "gpio71", "gpio72",
996 };
997 static const char * const audio_ref_groups[] = {
998 "gpio69",
999 };
1000 static const char * const blsp9_spi_groups[] = {
1001 "gpio70", "gpio71", "gpio72",
1002 };
1003 static const char * const tsense_pwm1_groups[] = {
1004 "gpio71",
1005 };
1006 static const char * const tsense_pwm2_groups[] = {
1007 "gpio71",
1008 };
1009 static const char * const btfm_slimbus_groups[] = {
1010 "gpio73", "gpio74",
1011 };
1012 static const char * const ter_mi2s_groups[] = {
1013 "gpio74", "gpio75", "gpio76", "gpio77", "gpio78",
1014 };
1015 static const char * const gcc_gp1_b_groups[] = {
1016 "gpio78",
1017 };
1018 static const char * const sec_mi2s_groups[] = {
1019 "gpio79", "gpio80", "gpio81", "gpio82", "gpio83",
1020 };
1021 static const char * const blsp_spi12_groups[] = {
1022 "gpio81", "gpio82", "gpio83", "gpio84",
1023 };
1024 static const char * const blsp_uart9_b_groups[] = {
1025 "gpio81", "gpio82", "gpio83", "gpio84",
1026 };
1027 static const char * const blsp_uim9_b_groups[] = {
1028 "gpio81", "gpio82",
1029 };
1030 static const char * const gcc_gp2_b_groups[] = {
1031 "gpio81",
1032 };
1033 static const char * const gcc_gp3_b_groups[] = {
1034 "gpio82",
1035 };
1036 static const char * const blsp_i2c12_groups[] = {
1037 "gpio83", "gpio84",
1038 };
1039 static const char * const blsp_spi5_groups[] = {
1040 "gpio85", "gpio86", "gpio87", "gpio88",
1041 };
1042 static const char * const blsp_uart2_b_groups[] = {
1043 "gpio85", "gpio86", "gpio87", "gpio88",
1044 };
1045 static const char * const blsp_uim2_b_groups[] = {
1046 "gpio85", "gpio86",
1047 };
1048 static const char * const blsp_i2c5_groups[] = {
1049 "gpio87", "gpio88",
1050 };
1051 static const char * const tsif1_clk_groups[] = {
1052 "gpio89",
1053 };
1054 static const char * const tsif1_en_groups[] = {
1055 "gpio90",
1056 };
1057 static const char * const mdp_vsync0_groups[] = {
1058 "gpio90",
1059 };
1060 static const char * const mdp_vsync1_groups[] = {
1061 "gpio90",
1062 };
1063 static const char * const mdp_vsync2_groups[] = {
1064 "gpio90",
1065 };
1066 static const char * const mdp_vsync3_groups[] = {
1067 "gpio90",
1068 };
1069 static const char * const blsp1_spi_groups[] = {
1070 "gpio90",
1071 };
1072 static const char * const tgu_ch0_groups[] = {
1073 "gpio90",
1074 };
1075 static const char * const qdss_cti1_b_groups[] = {
1076 "gpio90", "gpio91",
1077 };
1078 static const char * const tsif1_data_groups[] = {
1079 "gpio91",
1080 };
1081 static const char * const sdc4_cmd_groups[] = {
1082 "gpio91",
1083 };
1084 static const char * const tgu_ch1_groups[] = {
1085 "gpio91",
1086 };
1087 static const char * const tsif2_error_groups[] = {
1088 "gpio92",
1089 };
1090 static const char * const sdc43_groups[] = {
1091 "gpio92",
1092 };
1093 static const char * const vfr_1_groups[] = {
1094 "gpio92",
1095 };
1096 static const char * const tsif2_clk_groups[] = {
1097 "gpio93",
1098 };
1099 static const char * const sdc4_clk_groups[] = {
1100 "gpio93",
1101 };
1102 static const char * const tsif2_en_groups[] = {
1103 "gpio94",
1104 };
1105 static const char * const sdc42_groups[] = {
1106 "gpio94",
1107 };
1108 static const char * const sd_card_groups[] = {
1109 "gpio95",
1110 };
1111 static const char * const tsif2_data_groups[] = {
1112 "gpio95",
1113 };
1114 static const char * const sdc41_groups[] = {
1115 "gpio95",
1116 };
1117 static const char * const tsif2_sync_groups[] = {
1118 "gpio96",
1119 };
1120 static const char * const sdc40_groups[] = {
1121 "gpio96",
1122 };
1123 static const char * const mdp_vsync_b_groups[] = {
1124 "gpio97", "gpio98",
1125 };
1126 static const char * const ldo_en_groups[] = {
1127 "gpio97",
1128 };
1129 static const char * const ldo_update_groups[] = {
1130 "gpio98",
1131 };
1132 static const char * const blsp_uart8_groups[] = {
1133 "gpio100", "gpio101",
1134 };
1135 static const char * const blsp11_i2c_groups[] = {
1136 "gpio102", "gpio103",
1137 };
1138 static const char * const prng_rosc_groups[] = {
1139 "gpio102",
1140 };
1141 static const char * const uim2_data_groups[] = {
1142 "gpio105",
1143 };
1144 static const char * const uim2_clk_groups[] = {
1145 "gpio106",
1146 };
1147 static const char * const uim2_reset_groups[] = {
1148 "gpio107",
1149 };
1150 static const char * const uim2_present_groups[] = {
1151 "gpio108",
1152 };
1153 static const char * const uim1_data_groups[] = {
1154 "gpio109",
1155 };
1156 static const char * const uim1_clk_groups[] = {
1157 "gpio110",
1158 };
1159 static const char * const uim1_reset_groups[] = {
1160 "gpio111",
1161 };
1162 static const char * const uim1_present_groups[] = {
1163 "gpio112",
1164 };
1165 static const char * const uim_batt_groups[] = {
1166 "gpio113",
1167 };
1168 static const char * const nav_dr_groups[] = {
1169 "gpio115",
1170 };
1171 static const char * const atest_char_groups[] = {
1172 "gpio117", "gpio118", "gpio119", "gpio120", "gpio121",
1173 };
1174 static const char * const adsp_ext_groups[] = {
1175 "gpio118",
1176 };
1177 static const char * const modem_tsync_groups[] = {
1178 "gpio128",
1179 };
1180 static const char * const nav_pps_groups[] = {
1181 "gpio128",
1182 };
1183 static const char * const qlink_request_groups[] = {
1184 "gpio130",
1185 };
1186 static const char * const qlink_enable_groups[] = {
1187 "gpio131",
1188 };
1189 static const char * const pa_indicator_groups[] = {
1190 "gpio135",
1191 };
1192 static const char * const ssbi1_groups[] = {
1193 "gpio142",
1194 };
1195 static const char * const isense_dbg_groups[] = {
1196 "gpio143",
1197 };
1198 static const char * const mss_lte_groups[] = {
1199 "gpio144", "gpio145",
1200 };
1201
1202 static const struct msm_function msm8998_functions[] = {
1203 FUNCTION(gpio),
1204 FUNCTION(adsp_ext),
1205 FUNCTION(agera_pll),
1206 FUNCTION(atest_char),
1207 FUNCTION(atest_gpsadc0),
1208 FUNCTION(atest_gpsadc1),
1209 FUNCTION(atest_tsens),
1210 FUNCTION(atest_tsens2),
1211 FUNCTION(atest_usb1),
1212 FUNCTION(atest_usb10),
1213 FUNCTION(atest_usb11),
1214 FUNCTION(atest_usb12),
1215 FUNCTION(atest_usb13),
1216 FUNCTION(audio_ref),
1217 FUNCTION(bimc_dte0),
1218 FUNCTION(bimc_dte1),
1219 FUNCTION(blsp10_spi),
1220 FUNCTION(blsp10_spi_a),
1221 FUNCTION(blsp10_spi_b),
1222 FUNCTION(blsp11_i2c),
1223 FUNCTION(blsp1_spi),
1224 FUNCTION(blsp1_spi_a),
1225 FUNCTION(blsp1_spi_b),
1226 FUNCTION(blsp2_spi),
1227 FUNCTION(blsp9_spi),
1228 FUNCTION(blsp_i2c1),
1229 FUNCTION(blsp_i2c2),
1230 FUNCTION(blsp_i2c3),
1231 FUNCTION(blsp_i2c4),
1232 FUNCTION(blsp_i2c5),
1233 FUNCTION(blsp_i2c6),
1234 FUNCTION(blsp_i2c7),
1235 FUNCTION(blsp_i2c8),
1236 FUNCTION(blsp_i2c9),
1237 FUNCTION(blsp_i2c10),
1238 FUNCTION(blsp_i2c11),
1239 FUNCTION(blsp_i2c12),
1240 FUNCTION(blsp_spi1),
1241 FUNCTION(blsp_spi2),
1242 FUNCTION(blsp_spi3),
1243 FUNCTION(blsp_spi4),
1244 FUNCTION(blsp_spi5),
1245 FUNCTION(blsp_spi6),
1246 FUNCTION(blsp_spi7),
1247 FUNCTION(blsp_spi8),
1248 FUNCTION(blsp_spi9),
1249 FUNCTION(blsp_spi10),
1250 FUNCTION(blsp_spi11),
1251 FUNCTION(blsp_spi12),
1252 FUNCTION(blsp_uart1_a),
1253 FUNCTION(blsp_uart1_b),
1254 FUNCTION(blsp_uart2_a),
1255 FUNCTION(blsp_uart2_b),
1256 FUNCTION(blsp_uart3_a),
1257 FUNCTION(blsp_uart3_b),
1258 FUNCTION(blsp_uart7_a),
1259 FUNCTION(blsp_uart7_b),
1260 FUNCTION(blsp_uart8),
1261 FUNCTION(blsp_uart8_a),
1262 FUNCTION(blsp_uart8_b),
1263 FUNCTION(blsp_uart9_a),
1264 FUNCTION(blsp_uart9_b),
1265 FUNCTION(blsp_uim1_a),
1266 FUNCTION(blsp_uim1_b),
1267 FUNCTION(blsp_uim2_a),
1268 FUNCTION(blsp_uim2_b),
1269 FUNCTION(blsp_uim3_a),
1270 FUNCTION(blsp_uim3_b),
1271 FUNCTION(blsp_uim7_a),
1272 FUNCTION(blsp_uim7_b),
1273 FUNCTION(blsp_uim8_a),
1274 FUNCTION(blsp_uim8_b),
1275 FUNCTION(blsp_uim9_a),
1276 FUNCTION(blsp_uim9_b),
1277 FUNCTION(bt_reset),
1278 FUNCTION(btfm_slimbus),
1279 FUNCTION(cam_mclk),
1280 FUNCTION(cci_async),
1281 FUNCTION(cci_i2c),
1282 FUNCTION(cci_timer0),
1283 FUNCTION(cci_timer1),
1284 FUNCTION(cci_timer2),
1285 FUNCTION(cci_timer3),
1286 FUNCTION(cci_timer4),
1287 FUNCTION(cri_trng),
1288 FUNCTION(cri_trng0),
1289 FUNCTION(cri_trng1),
1290 FUNCTION(dbg_out),
1291 FUNCTION(ddr_bist),
1292 FUNCTION(edp_hot),
1293 FUNCTION(edp_lcd),
1294 FUNCTION(gcc_gp1_a),
1295 FUNCTION(gcc_gp1_b),
1296 FUNCTION(gcc_gp2_a),
1297 FUNCTION(gcc_gp2_b),
1298 FUNCTION(gcc_gp3_a),
1299 FUNCTION(gcc_gp3_b),
1300 FUNCTION(hdmi_cec),
1301 FUNCTION(hdmi_ddc),
1302 FUNCTION(hdmi_hot),
1303 FUNCTION(hdmi_rcv),
1304 FUNCTION(isense_dbg),
1305 FUNCTION(jitter_bist),
1306 FUNCTION(ldo_en),
1307 FUNCTION(ldo_update),
1308 FUNCTION(lpass_slimbus),
1309 FUNCTION(m_voc),
1310 FUNCTION(mdp_vsync),
1311 FUNCTION(mdp_vsync0),
1312 FUNCTION(mdp_vsync1),
1313 FUNCTION(mdp_vsync2),
1314 FUNCTION(mdp_vsync3),
1315 FUNCTION(mdp_vsync_a),
1316 FUNCTION(mdp_vsync_b),
1317 FUNCTION(modem_tsync),
1318 FUNCTION(mss_lte),
1319 FUNCTION(nav_dr),
1320 FUNCTION(nav_pps),
1321 FUNCTION(pa_indicator),
1322 FUNCTION(pci_e0),
1323 FUNCTION(phase_flag),
1324 FUNCTION(pll_bypassnl),
1325 FUNCTION(pll_reset),
1326 FUNCTION(pri_mi2s),
1327 FUNCTION(pri_mi2s_ws),
1328 FUNCTION(prng_rosc),
1329 FUNCTION(pwr_crypto),
1330 FUNCTION(pwr_modem),
1331 FUNCTION(pwr_nav),
1332 FUNCTION(qdss_cti0_a),
1333 FUNCTION(qdss_cti0_b),
1334 FUNCTION(qdss_cti1_a),
1335 FUNCTION(qdss_cti1_b),
1336 FUNCTION(qdss),
1337 FUNCTION(qlink_enable),
1338 FUNCTION(qlink_request),
1339 FUNCTION(qua_mi2s),
1340 FUNCTION(sd_card),
1341 FUNCTION(sd_write),
1342 FUNCTION(sdc40),
1343 FUNCTION(sdc41),
1344 FUNCTION(sdc42),
1345 FUNCTION(sdc43),
1346 FUNCTION(sdc4_clk),
1347 FUNCTION(sdc4_cmd),
1348 FUNCTION(sec_mi2s),
1349 FUNCTION(sp_cmu),
1350 FUNCTION(spkr_i2s),
1351 FUNCTION(ssbi1),
1352 FUNCTION(ssc_irq),
1353 FUNCTION(ter_mi2s),
1354 FUNCTION(tgu_ch0),
1355 FUNCTION(tgu_ch1),
1356 FUNCTION(tsense_pwm1),
1357 FUNCTION(tsense_pwm2),
1358 FUNCTION(tsif1_clk),
1359 FUNCTION(tsif1_data),
1360 FUNCTION(tsif1_en),
1361 FUNCTION(tsif1_error),
1362 FUNCTION(tsif1_sync),
1363 FUNCTION(tsif2_clk),
1364 FUNCTION(tsif2_data),
1365 FUNCTION(tsif2_en),
1366 FUNCTION(tsif2_error),
1367 FUNCTION(tsif2_sync),
1368 FUNCTION(uim1_clk),
1369 FUNCTION(uim1_data),
1370 FUNCTION(uim1_present),
1371 FUNCTION(uim1_reset),
1372 FUNCTION(uim2_clk),
1373 FUNCTION(uim2_data),
1374 FUNCTION(uim2_present),
1375 FUNCTION(uim2_reset),
1376 FUNCTION(uim_batt),
1377 FUNCTION(usb_phy),
1378 FUNCTION(vfr_1),
1379 FUNCTION(vsense_clkout),
1380 FUNCTION(vsense_data0),
1381 FUNCTION(vsense_data1),
1382 FUNCTION(vsense_mode),
1383 FUNCTION(wlan1_adc0),
1384 FUNCTION(wlan1_adc1),
1385 FUNCTION(wlan2_adc0),
1386 FUNCTION(wlan2_adc1),
1387 };
1388
1389 static const struct msm_pingroup msm8998_groups[] = {
1390 PINGROUP(0, EAST, blsp_spi1, blsp_uart1_a, blsp_uim1_a, _, _, _, _, _, _),
1391 PINGROUP(1, EAST, blsp_spi1, blsp_uart1_a, blsp_uim1_a, _, _, _, _, _, _),
1392 PINGROUP(2, EAST, blsp_spi1, blsp_uart1_a, blsp_i2c1, _, _, _, _, _, _),
1393 PINGROUP(3, EAST, blsp_spi1, blsp_uart1_a, blsp_i2c1, _, _, _, _, _, _),
1394 PINGROUP(4, WEST, blsp_spi8, blsp_uart8_a, blsp_uim8_a, _, qdss_cti0_b, _, _, _, _),
1395 PINGROUP(5, WEST, blsp_spi8, blsp_uart8_a, blsp_uim8_a, _, qdss_cti0_b, _, _, _, _),
1396 PINGROUP(6, WEST, blsp_spi8, blsp_uart8_a, blsp_i2c8, _, _, _, _, _, _),
1397 PINGROUP(7, WEST, blsp_spi8, blsp_uart8_a, blsp_i2c8, ddr_bist, _, atest_tsens2, atest_usb1, _, _),
1398 PINGROUP(8, EAST, blsp_spi4, blsp_uart1_b, blsp_uim1_b, _, ddr_bist, _, wlan1_adc1, atest_usb13, bimc_dte1),
1399 PINGROUP(9, EAST, blsp_spi4, blsp_uart1_b, blsp_uim1_b, tsif1_sync, ddr_bist, _, wlan1_adc0, atest_usb12, bimc_dte0),
1400 PINGROUP(10, EAST, mdp_vsync_a, blsp_spi4, blsp_uart1_b, blsp_i2c4, ddr_bist, atest_gpsadc1, wlan2_adc1, atest_usb11, bimc_dte1),
1401 PINGROUP(11, EAST, mdp_vsync_a, edp_lcd, blsp_spi4, blsp_uart1_b, blsp_i2c4, dbg_out, atest_gpsadc0, wlan2_adc0, atest_usb10),
1402 PINGROUP(12, EAST, mdp_vsync, m_voc, _, _, _, _, _, _, _),
1403 PINGROUP(13, EAST, cam_mclk, pll_bypassnl, qdss, _, _, _, _, _, _),
1404 PINGROUP(14, EAST, cam_mclk, pll_reset, qdss, _, _, _, _, _, _),
1405 PINGROUP(15, EAST, cam_mclk, qdss, _, _, _, _, _, _, _),
1406 PINGROUP(16, EAST, cam_mclk, qdss, _, _, _, _, _, _, _),
1407 PINGROUP(17, EAST, cci_i2c, qdss, _, _, _, _, _, _, _),
1408 PINGROUP(18, EAST, cci_i2c, phase_flag, qdss, _, _, _, _, _, _),
1409 PINGROUP(19, EAST, cci_i2c, phase_flag, qdss, _, _, _, _, _, _),
1410 PINGROUP(20, EAST, cci_i2c, qdss, _, _, _, _, _, _, _),
1411 PINGROUP(21, EAST, cci_timer0, _, qdss, vsense_data0, _, _, _, _, _),
1412 PINGROUP(22, EAST, cci_timer1, _, qdss, vsense_data1, _, _, _, _, _),
1413 PINGROUP(23, EAST, cci_timer2, blsp1_spi_b, qdss, vsense_mode, _, _, _, _, _),
1414 PINGROUP(24, EAST, cci_timer3, cci_async, blsp1_spi_a, _, qdss, vsense_clkout, _, _, _),
1415 PINGROUP(25, EAST, cci_timer4, cci_async, blsp2_spi, _, qdss, _, _, _, _),
1416 PINGROUP(26, EAST, cci_async, qdss, _, _, _, _, _, _, _),
1417 PINGROUP(27, EAST, blsp1_spi_a, qdss, _, _, _, _, _, _, _),
1418 PINGROUP(28, EAST, blsp1_spi_b, qdss, _, _, _, _, _, _, _),
1419 PINGROUP(29, EAST, blsp2_spi, _, qdss, _, _, _, _, _, _),
1420 PINGROUP(30, EAST, hdmi_rcv, blsp2_spi, qdss, _, _, _, _, _, _),
1421 PINGROUP(31, EAST, hdmi_cec, blsp_spi2, blsp_uart2_a, blsp_uim2_a, pwr_modem, _, _, _, _),
1422 PINGROUP(32, EAST, hdmi_ddc, blsp_spi2, blsp_uart2_a, blsp_i2c2, pwr_nav, _, _, _, _),
1423 PINGROUP(33, EAST, hdmi_ddc, blsp_spi2, blsp_uart2_a, blsp_i2c2, pwr_crypto, _, _, _, _),
1424 PINGROUP(34, EAST, hdmi_hot, edp_hot, blsp_spi2, blsp_uart2_a, blsp_uim2_a, _, _, _, _),
1425 PINGROUP(35, NORTH, pci_e0, jitter_bist, _, _, _, _, _, _, _),
1426 PINGROUP(36, NORTH, pci_e0, agera_pll, _, atest_tsens, _, _, _, _, _),
1427 PINGROUP(37, NORTH, agera_pll, _, _, _, _, _, _, _, _),
1428 PINGROUP(38, WEST, usb_phy, _, _, _, _, _, _, _, _),
1429 PINGROUP(39, WEST, lpass_slimbus, _, _, _, _, _, _, _, _),
1430 PINGROUP(40, EAST, sd_write, tsif1_error, _, _, _, _, _, _, _),
1431 PINGROUP(41, EAST, blsp_spi6, blsp_uart3_b, blsp_uim3_b, _, qdss, _, _, _, _),
1432 PINGROUP(42, EAST, blsp_spi6, blsp_uart3_b, blsp_uim3_b, _, qdss, _, _, _, _),
1433 PINGROUP(43, EAST, blsp_spi6, blsp_uart3_b, blsp_i2c6, _, qdss, _, _, _, _),
1434 PINGROUP(44, EAST, blsp_spi6, blsp_uart3_b, blsp_i2c6, _, qdss, _, _, _, _),
1435 PINGROUP(45, EAST, blsp_spi3, blsp_uart3_a, blsp_uim3_a, _, _, _, _, _, _),
1436 PINGROUP(46, EAST, blsp_spi3, blsp_uart3_a, blsp_uim3_a, _, _, _, _, _, _),
1437 PINGROUP(47, EAST, blsp_spi3, blsp_uart3_a, blsp_i2c3, _, _, _, _, _, _),
1438 PINGROUP(48, EAST, blsp_spi3, blsp_uart3_a, blsp_i2c3, _, _, _, _, _, _),
1439 PINGROUP(49, NORTH, blsp_spi9, blsp_uart9_a, blsp_uim9_a, blsp10_spi_b, qdss_cti0_a, _, _, _, _),
1440 PINGROUP(50, NORTH, blsp_spi9, blsp_uart9_a, blsp_uim9_a, blsp10_spi_b, qdss_cti0_a, _, _, _, _),
1441 PINGROUP(51, NORTH, blsp_spi9, blsp_uart9_a, blsp_i2c9, blsp10_spi_a, _, _, _, _, _),
1442 PINGROUP(52, NORTH, blsp_spi9, blsp_uart9_a, blsp_i2c9, blsp10_spi_a, _, _, _, _, _),
1443 PINGROUP(53, WEST, blsp_spi7, blsp_uart7_a, blsp_uim7_a, _, _, _, _, _, _),
1444 PINGROUP(54, WEST, blsp_spi7, blsp_uart7_a, blsp_uim7_a, _, _, _, _, _, _),
1445 PINGROUP(55, WEST, blsp_spi7, blsp_uart7_a, blsp_i2c7, _, _, _, _, _, _),
1446 PINGROUP(56, WEST, blsp_spi7, blsp_uart7_a, blsp_i2c7, _, _, _, _, _, _),
1447 PINGROUP(57, WEST, qua_mi2s, blsp10_spi, gcc_gp1_a, _, _, _, _, _, _),
1448 PINGROUP(58, WEST, qua_mi2s, blsp_spi11, blsp_uart8_b, blsp_uim8_b, gcc_gp2_a, _, qdss_cti1_a, _, _),
1449 PINGROUP(59, WEST, qua_mi2s, blsp_spi11, blsp_uart8_b, blsp_uim8_b, gcc_gp3_a, _, qdss_cti1_a, _, _),
1450 PINGROUP(60, WEST, qua_mi2s, blsp_spi11, blsp_uart8_b, blsp_i2c11, cri_trng0, _, _, _, _),
1451 PINGROUP(61, WEST, qua_mi2s, blsp_spi11, blsp_uart8_b, blsp_i2c11, cri_trng1, _, _, _, _),
1452 PINGROUP(62, WEST, qua_mi2s, cri_trng, _, _, _, _, _, _, _),
1453 PINGROUP(63, WEST, qua_mi2s, _, _, _, _, _, _, _, _),
1454 PINGROUP(64, WEST, pri_mi2s, sp_cmu, _, _, _, _, _, _, _),
1455 PINGROUP(65, WEST, pri_mi2s, blsp_spi10, blsp_uart7_b, blsp_uim7_b, _, _, _, _, _),
1456 PINGROUP(66, WEST, pri_mi2s_ws, blsp_spi10, blsp_uart7_b, blsp_uim7_b, _, _, _, _, _),
1457 PINGROUP(67, WEST, pri_mi2s, blsp_spi10, blsp_uart7_b, blsp_i2c10, _, _, _, _, _),
1458 PINGROUP(68, WEST, pri_mi2s, blsp_spi10, blsp_uart7_b, blsp_i2c10, _, _, _, _, _),
1459 PINGROUP(69, WEST, spkr_i2s, audio_ref, _, _, _, _, _, _, _),
1460 PINGROUP(70, WEST, lpass_slimbus, spkr_i2s, blsp9_spi, _, _, _, _, _, _),
1461 PINGROUP(71, WEST, lpass_slimbus, spkr_i2s, blsp9_spi, tsense_pwm1, tsense_pwm2, _, _, _, _),
1462 PINGROUP(72, WEST, lpass_slimbus, spkr_i2s, blsp9_spi, _, _, _, _, _, _),
1463 PINGROUP(73, WEST, btfm_slimbus, phase_flag, _, _, _, _, _, _, _),
1464 PINGROUP(74, WEST, btfm_slimbus, ter_mi2s, phase_flag, _, _, _, _, _, _),
1465 PINGROUP(75, WEST, ter_mi2s, phase_flag, qdss, _, _, _, _, _, _),
1466 PINGROUP(76, WEST, ter_mi2s, phase_flag, qdss, _, _, _, _, _, _),
1467 PINGROUP(77, WEST, ter_mi2s, phase_flag, qdss, _, _, _, _, _, _),
1468 PINGROUP(78, WEST, ter_mi2s, gcc_gp1_b, _, _, _, _, _, _, _),
1469 PINGROUP(79, WEST, sec_mi2s, _, qdss, _, _, _, _, _, _),
1470 PINGROUP(80, WEST, sec_mi2s, _, qdss, _, _, _, _, _, _),
1471 PINGROUP(81, WEST, sec_mi2s, blsp_spi12, blsp_uart9_b, blsp_uim9_b, gcc_gp2_b, _, _, _, _),
1472 PINGROUP(82, WEST, sec_mi2s, blsp_spi12, blsp_uart9_b, blsp_uim9_b, gcc_gp3_b, _, _, _, _),
1473 PINGROUP(83, WEST, sec_mi2s, blsp_spi12, blsp_uart9_b, blsp_i2c12, _, _, _, _, _),
1474 PINGROUP(84, WEST, blsp_spi12, blsp_uart9_b, blsp_i2c12, _, _, _, _, _, _),
1475 PINGROUP(85, EAST, blsp_spi5, blsp_uart2_b, blsp_uim2_b, _, _, _, _, _, _),
1476 PINGROUP(86, EAST, blsp_spi5, blsp_uart2_b, blsp_uim2_b, _, _, _, _, _, _),
1477 PINGROUP(87, EAST, blsp_spi5, blsp_uart2_b, blsp_i2c5, _, _, _, _, _, _),
1478 PINGROUP(88, EAST, blsp_spi5, blsp_uart2_b, blsp_i2c5, _, _, _, _, _, _),
1479 PINGROUP(89, EAST, tsif1_clk, phase_flag, _, _, _, _, _, _, _),
1480 PINGROUP(90, EAST, tsif1_en, mdp_vsync0, mdp_vsync1, mdp_vsync2, mdp_vsync3, blsp1_spi, tgu_ch0, qdss_cti1_b, _),
1481 PINGROUP(91, EAST, tsif1_data, sdc4_cmd, tgu_ch1, phase_flag, qdss_cti1_b, _, _, _, _),
1482 PINGROUP(92, EAST, tsif2_error, sdc43, vfr_1, phase_flag, _, _, _, _, _),
1483 PINGROUP(93, EAST, tsif2_clk, sdc4_clk, _, qdss, _, _, _, _, _),
1484 PINGROUP(94, EAST, tsif2_en, sdc42, _, _, _, _, _, _, _),
1485 PINGROUP(95, EAST, tsif2_data, sdc41, _, _, _, _, _, _, _),
1486 PINGROUP(96, EAST, tsif2_sync, sdc40, phase_flag, _, _, _, _, _, _),
1487 PINGROUP(97, WEST, _, mdp_vsync_b, ldo_en, _, _, _, _, _, _),
1488 PINGROUP(98, WEST, _, mdp_vsync_b, ldo_update, _, _, _, _, _, _),
1489 PINGROUP(99, WEST, _, _, _, _, _, _, _, _, _),
1490 PINGROUP(100, WEST, _, _, blsp_uart8, _, _, _, _, _, _),
1491 PINGROUP(101, WEST, _, blsp_uart8, _, _, _, _, _, _, _),
1492 PINGROUP(102, WEST, _, blsp11_i2c, prng_rosc, _, _, _, _, _, _),
1493 PINGROUP(103, WEST, _, blsp11_i2c, phase_flag, _, _, _, _, _, _),
1494 PINGROUP(104, WEST, _, _, _, _, _, _, _, _, _),
1495 PINGROUP(105, NORTH, uim2_data, _, _, _, _, _, _, _, _),
1496 PINGROUP(106, NORTH, uim2_clk, _, _, _, _, _, _, _, _),
1497 PINGROUP(107, NORTH, uim2_reset, _, _, _, _, _, _, _, _),
1498 PINGROUP(108, NORTH, uim2_present, _, _, _, _, _, _, _, _),
1499 PINGROUP(109, NORTH, uim1_data, _, _, _, _, _, _, _, _),
1500 PINGROUP(110, NORTH, uim1_clk, _, _, _, _, _, _, _, _),
1501 PINGROUP(111, NORTH, uim1_reset, _, _, _, _, _, _, _, _),
1502 PINGROUP(112, NORTH, uim1_present, _, _, _, _, _, _, _, _),
1503 PINGROUP(113, NORTH, uim_batt, _, _, _, _, _, _, _, _),
1504 PINGROUP(114, WEST, _, _, phase_flag, _, _, _, _, _, _),
1505 PINGROUP(115, WEST, _, nav_dr, phase_flag, _, _, _, _, _, _),
1506 PINGROUP(116, WEST, phase_flag, _, _, _, _, _, _, _, _),
1507 PINGROUP(117, EAST, phase_flag, qdss, atest_char, _, _, _, _, _, _),
1508 PINGROUP(118, EAST, adsp_ext, phase_flag, qdss, atest_char, _, _, _, _, _),
1509 PINGROUP(119, EAST, phase_flag, qdss, atest_char, _, _, _, _, _, _),
1510 PINGROUP(120, EAST, phase_flag, qdss, atest_char, _, _, _, _, _, _),
1511 PINGROUP(121, EAST, phase_flag, qdss, atest_char, _, _, _, _, _, _),
1512 PINGROUP(122, EAST, phase_flag, qdss, _, _, _, _, _, _, _),
1513 PINGROUP(123, EAST, phase_flag, qdss, _, _, _, _, _, _, _),
1514 PINGROUP(124, EAST, phase_flag, qdss, _, _, _, _, _, _, _),
1515 PINGROUP(125, EAST, phase_flag, _, _, _, _, _, _, _, _),
1516 PINGROUP(126, EAST, phase_flag, _, _, _, _, _, _, _, _),
1517 PINGROUP(127, WEST, _, _, _, _, _, _, _, _, _),
1518 PINGROUP(128, WEST, modem_tsync, nav_pps, phase_flag, _, _, _, _, _, _),
1519 PINGROUP(129, WEST, phase_flag, _, _, _, _, _, _, _, _),
1520 PINGROUP(130, NORTH, qlink_request, phase_flag, _, _, _, _, _, _, _),
1521 PINGROUP(131, NORTH, qlink_enable, phase_flag, _, _, _, _, _, _, _),
1522 PINGROUP(132, WEST, _, phase_flag, _, _, _, _, _, _, _),
1523 PINGROUP(133, WEST, phase_flag, _, _, _, _, _, _, _, _),
1524 PINGROUP(134, WEST, phase_flag, _, _, _, _, _, _, _, _),
1525 PINGROUP(135, WEST, _, pa_indicator, _, _, _, _, _, _, _),
1526 PINGROUP(136, WEST, _, _, _, _, _, _, _, _, _),
1527 PINGROUP(137, WEST, _, _, _, _, _, _, _, _, _),
1528 PINGROUP(138, WEST, _, _, _, _, _, _, _, _, _),
1529 PINGROUP(139, WEST, _, _, _, _, _, _, _, _, _),
1530 PINGROUP(140, WEST, _, _, _, _, _, _, _, _, _),
1531 PINGROUP(141, WEST, _, _, _, _, _, _, _, _, _),
1532 PINGROUP(142, WEST, _, ssbi1, _, _, _, _, _, _, _),
1533 PINGROUP(143, WEST, isense_dbg, _, _, _, _, _, _, _, _),
1534 PINGROUP(144, WEST, mss_lte, _, _, _, _, _, _, _, _),
1535 PINGROUP(145, WEST, mss_lte, _, _, _, _, _, _, _, _),
1536 PINGROUP(146, WEST, _, _, _, _, _, _, _, _, _),
1537 PINGROUP(147, WEST, _, _, _, _, _, _, _, _, _),
1538 PINGROUP(148, WEST, _, _, _, _, _, _, _, _, _),
1539 PINGROUP(149, WEST, _, _, _, _, _, _, _, _, _),
1540 SDC_QDSD_PINGROUP(sdc2_clk, 0x999000, 14, 6),
1541 SDC_QDSD_PINGROUP(sdc2_cmd, 0x999000, 11, 3),
1542 SDC_QDSD_PINGROUP(sdc2_data, 0x999000, 9, 0),
1543 UFS_RESET(ufs_reset, 0x19d000),
1544 };
1545
1546 static const struct msm_pinctrl_soc_data msm8998_pinctrl = {
1547 .pins = msm8998_pins,
1548 .npins = ARRAY_SIZE(msm8998_pins),
1549 .functions = msm8998_functions,
1550 .nfunctions = ARRAY_SIZE(msm8998_functions),
1551 .groups = msm8998_groups,
1552 .ngroups = ARRAY_SIZE(msm8998_groups),
1553 .ngpios = 150,
1554 };
1555
1556 static int msm8998_pinctrl_probe(struct platform_device *pdev)
1557 {
1558 return msm_pinctrl_probe(pdev, &msm8998_pinctrl);
1559 }
1560
1561 static const struct of_device_id msm8998_pinctrl_of_match[] = {
1562 { .compatible = "qcom,msm8998-pinctrl", },
1563 { },
1564 };
1565
1566 static struct platform_driver msm8998_pinctrl_driver = {
1567 .driver = {
1568 .name = "msm8998-pinctrl",
1569 .of_match_table = msm8998_pinctrl_of_match,
1570 },
1571 .probe = msm8998_pinctrl_probe,
1572 .remove = msm_pinctrl_remove,
1573 };
1574
1575 static int __init msm8998_pinctrl_init(void)
1576 {
1577 return platform_driver_register(&msm8998_pinctrl_driver);
1578 }
1579 arch_initcall(msm8998_pinctrl_init);
1580
1581 static void __exit msm8998_pinctrl_exit(void)
1582 {
1583 platform_driver_unregister(&msm8998_pinctrl_driver);
1584 }
1585 module_exit(msm8998_pinctrl_exit);
1586
1587 MODULE_DESCRIPTION("QTI msm8998 pinctrl driver");
1588 MODULE_LICENSE("GPL v2");
1589 MODULE_DEVICE_TABLE(of, msm8998_pinctrl_of_match);
Linux with added FPC-III support