| blob | 72348a4f2ece13b6bec5149a8f82fe4c79e61b4f |
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * R8A7796 processor support - PFC hardware block.
4 *
5 * Copyright (C) 2016-2017 Renesas Electronics Corp.
6 *
7 * This file is based on the drivers/pinctrl/sh-pfc/pfc-r8a7795.c
8 *
9 * R-Car Gen3 processor support - PFC hardware block.
10 *
11 * Copyright (C) 2015 Renesas Electronics Corporation
12 */
14 #include <linux/kernel.h>
19 #define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | \
20 SH_PFC_PIN_CFG_PULL_UP | \
21 SH_PFC_PIN_CFG_PULL_DOWN)
23 #define CPU_ALL_PORT(fn, sfx) \
24 PORT_GP_CFG_16(0, fn, sfx, CFG_FLAGS), \
25 PORT_GP_CFG_29(1, fn, sfx, CFG_FLAGS), \
26 PORT_GP_CFG_15(2, fn, sfx, CFG_FLAGS), \
27 PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
28 PORT_GP_CFG_1(3, 12, fn, sfx, CFG_FLAGS), \
29 PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS), \
30 PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS), \
31 PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS), \
32 PORT_GP_CFG_18(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
33 PORT_GP_CFG_26(5, fn, sfx, CFG_FLAGS), \
34 PORT_GP_CFG_32(6, fn, sfx, CFG_FLAGS), \
35 PORT_GP_CFG_4(7, fn, sfx, CFG_FLAGS)
36 /*
37 * F_() : just information
38 * FM() : macro for FN_xxx / xxx_MARK
39 */
41 /* GPSR0 */
42 #define GPSR0_15 F_(D15, IP7_11_8)
43 #define GPSR0_14 F_(D14, IP7_7_4)
44 #define GPSR0_13 F_(D13, IP7_3_0)
45 #define GPSR0_12 F_(D12, IP6_31_28)
46 #define GPSR0_11 F_(D11, IP6_27_24)
47 #define GPSR0_10 F_(D10, IP6_23_20)
48 #define GPSR0_9 F_(D9, IP6_19_16)
49 #define GPSR0_8 F_(D8, IP6_15_12)
50 #define GPSR0_7 F_(D7, IP6_11_8)
51 #define GPSR0_6 F_(D6, IP6_7_4)
52 #define GPSR0_5 F_(D5, IP6_3_0)
53 #define GPSR0_4 F_(D4, IP5_31_28)
54 #define GPSR0_3 F_(D3, IP5_27_24)
55 #define GPSR0_2 F_(D2, IP5_23_20)
56 #define GPSR0_1 F_(D1, IP5_19_16)
57 #define GPSR0_0 F_(D0, IP5_15_12)
59 /* GPSR1 */
60 #define GPSR1_28 FM(CLKOUT)
61 #define GPSR1_27 F_(EX_WAIT0_A, IP5_11_8)
62 #define GPSR1_26 F_(WE1_N, IP5_7_4)
63 #define GPSR1_25 F_(WE0_N, IP5_3_0)
64 #define GPSR1_24 F_(RD_WR_N, IP4_31_28)
65 #define GPSR1_23 F_(RD_N, IP4_27_24)
66 #define GPSR1_22 F_(BS_N, IP4_23_20)
67 #define GPSR1_21 F_(CS1_N, IP4_19_16)
68 #define GPSR1_20 F_(CS0_N, IP4_15_12)
69 #define GPSR1_19 F_(A19, IP4_11_8)
70 #define GPSR1_18 F_(A18, IP4_7_4)
71 #define GPSR1_17 F_(A17, IP4_3_0)
72 #define GPSR1_16 F_(A16, IP3_31_28)
73 #define GPSR1_15 F_(A15, IP3_27_24)
74 #define GPSR1_14 F_(A14, IP3_23_20)
75 #define GPSR1_13 F_(A13, IP3_19_16)
76 #define GPSR1_12 F_(A12, IP3_15_12)
77 #define GPSR1_11 F_(A11, IP3_11_8)
78 #define GPSR1_10 F_(A10, IP3_7_4)
79 #define GPSR1_9 F_(A9, IP3_3_0)
80 #define GPSR1_8 F_(A8, IP2_31_28)
81 #define GPSR1_7 F_(A7, IP2_27_24)
82 #define GPSR1_6 F_(A6, IP2_23_20)
83 #define GPSR1_5 F_(A5, IP2_19_16)
84 #define GPSR1_4 F_(A4, IP2_15_12)
85 #define GPSR1_3 F_(A3, IP2_11_8)
86 #define GPSR1_2 F_(A2, IP2_7_4)
87 #define GPSR1_1 F_(A1, IP2_3_0)
88 #define GPSR1_0 F_(A0, IP1_31_28)
90 /* GPSR2 */
91 #define GPSR2_14 F_(AVB_AVTP_CAPTURE_A, IP0_23_20)
92 #define GPSR2_13 F_(AVB_AVTP_MATCH_A, IP0_19_16)
93 #define GPSR2_12 F_(AVB_LINK, IP0_15_12)
94 #define GPSR2_11 F_(AVB_PHY_INT, IP0_11_8)
95 #define GPSR2_10 F_(AVB_MAGIC, IP0_7_4)
96 #define GPSR2_9 F_(AVB_MDC, IP0_3_0)
97 #define GPSR2_8 F_(PWM2_A, IP1_27_24)
98 #define GPSR2_7 F_(PWM1_A, IP1_23_20)
99 #define GPSR2_6 F_(PWM0, IP1_19_16)
100 #define GPSR2_5 F_(IRQ5, IP1_15_12)
101 #define GPSR2_4 F_(IRQ4, IP1_11_8)
102 #define GPSR2_3 F_(IRQ3, IP1_7_4)
103 #define GPSR2_2 F_(IRQ2, IP1_3_0)
104 #define GPSR2_1 F_(IRQ1, IP0_31_28)
105 #define GPSR2_0 F_(IRQ0, IP0_27_24)
107 /* GPSR3 */
108 #define GPSR3_15 F_(SD1_WP, IP11_23_20)
109 #define GPSR3_14 F_(SD1_CD, IP11_19_16)
110 #define GPSR3_13 F_(SD0_WP, IP11_15_12)
111 #define GPSR3_12 F_(SD0_CD, IP11_11_8)
112 #define GPSR3_11 F_(SD1_DAT3, IP8_31_28)
113 #define GPSR3_10 F_(SD1_DAT2, IP8_27_24)
114 #define GPSR3_9 F_(SD1_DAT1, IP8_23_20)
115 #define GPSR3_8 F_(SD1_DAT0, IP8_19_16)
116 #define GPSR3_7 F_(SD1_CMD, IP8_15_12)
117 #define GPSR3_6 F_(SD1_CLK, IP8_11_8)
118 #define GPSR3_5 F_(SD0_DAT3, IP8_7_4)
119 #define GPSR3_4 F_(SD0_DAT2, IP8_3_0)
120 #define GPSR3_3 F_(SD0_DAT1, IP7_31_28)
121 #define GPSR3_2 F_(SD0_DAT0, IP7_27_24)
122 #define GPSR3_1 F_(SD0_CMD, IP7_23_20)
123 #define GPSR3_0 F_(SD0_CLK, IP7_19_16)
125 /* GPSR4 */
126 #define GPSR4_17 F_(SD3_DS, IP11_7_4)
127 #define GPSR4_16 F_(SD3_DAT7, IP11_3_0)
128 #define GPSR4_15 F_(SD3_DAT6, IP10_31_28)
129 #define GPSR4_14 F_(SD3_DAT5, IP10_27_24)
130 #define GPSR4_13 F_(SD3_DAT4, IP10_23_20)
131 #define GPSR4_12 F_(SD3_DAT3, IP10_19_16)
132 #define GPSR4_11 F_(SD3_DAT2, IP10_15_12)
133 #define GPSR4_10 F_(SD3_DAT1, IP10_11_8)
134 #define GPSR4_9 F_(SD3_DAT0, IP10_7_4)
135 #define GPSR4_8 F_(SD3_CMD, IP10_3_0)
136 #define GPSR4_7 F_(SD3_CLK, IP9_31_28)
137 #define GPSR4_6 F_(SD2_DS, IP9_27_24)
138 #define GPSR4_5 F_(SD2_DAT3, IP9_23_20)
139 #define GPSR4_4 F_(SD2_DAT2, IP9_19_16)
140 #define GPSR4_3 F_(SD2_DAT1, IP9_15_12)
141 #define GPSR4_2 F_(SD2_DAT0, IP9_11_8)
142 #define GPSR4_1 F_(SD2_CMD, IP9_7_4)
143 #define GPSR4_0 F_(SD2_CLK, IP9_3_0)
145 /* GPSR5 */
146 #define GPSR5_25 F_(MLB_DAT, IP14_19_16)
147 #define GPSR5_24 F_(MLB_SIG, IP14_15_12)
148 #define GPSR5_23 F_(MLB_CLK, IP14_11_8)
149 #define GPSR5_22 FM(MSIOF0_RXD)
150 #define GPSR5_21 F_(MSIOF0_SS2, IP14_7_4)
151 #define GPSR5_20 FM(MSIOF0_TXD)
152 #define GPSR5_19 F_(MSIOF0_SS1, IP14_3_0)
153 #define GPSR5_18 F_(MSIOF0_SYNC, IP13_31_28)
154 #define GPSR5_17 FM(MSIOF0_SCK)
155 #define GPSR5_16 F_(HRTS0_N, IP13_27_24)
156 #define GPSR5_15 F_(HCTS0_N, IP13_23_20)
157 #define GPSR5_14 F_(HTX0, IP13_19_16)
158 #define GPSR5_13 F_(HRX0, IP13_15_12)
159 #define GPSR5_12 F_(HSCK0, IP13_11_8)
160 #define GPSR5_11 F_(RX2_A, IP13_7_4)
161 #define GPSR5_10 F_(TX2_A, IP13_3_0)
162 #define GPSR5_9 F_(SCK2, IP12_31_28)
163 #define GPSR5_8 F_(RTS1_N, IP12_27_24)
164 #define GPSR5_7 F_(CTS1_N, IP12_23_20)
165 #define GPSR5_6 F_(TX1_A, IP12_19_16)
166 #define GPSR5_5 F_(RX1_A, IP12_15_12)
167 #define GPSR5_4 F_(RTS0_N, IP12_11_8)
168 #define GPSR5_3 F_(CTS0_N, IP12_7_4)
169 #define GPSR5_2 F_(TX0, IP12_3_0)
170 #define GPSR5_1 F_(RX0, IP11_31_28)
171 #define GPSR5_0 F_(SCK0, IP11_27_24)
173 /* GPSR6 */
174 #define GPSR6_31 F_(GP6_31, IP18_7_4)
175 #define GPSR6_30 F_(GP6_30, IP18_3_0)
176 #define GPSR6_29 F_(USB30_OVC, IP17_31_28)
177 #define GPSR6_28 F_(USB30_PWEN, IP17_27_24)
178 #define GPSR6_27 F_(USB1_OVC, IP17_23_20)
179 #define GPSR6_26 F_(USB1_PWEN, IP17_19_16)
180 #define GPSR6_25 F_(USB0_OVC, IP17_15_12)
181 #define GPSR6_24 F_(USB0_PWEN, IP17_11_8)
182 #define GPSR6_23 F_(AUDIO_CLKB_B, IP17_7_4)
183 #define GPSR6_22 F_(AUDIO_CLKA_A, IP17_3_0)
184 #define GPSR6_21 F_(SSI_SDATA9_A, IP16_31_28)
185 #define GPSR6_20 F_(SSI_SDATA8, IP16_27_24)
186 #define GPSR6_19 F_(SSI_SDATA7, IP16_23_20)
187 #define GPSR6_18 F_(SSI_WS78, IP16_19_16)
188 #define GPSR6_17 F_(SSI_SCK78, IP16_15_12)
189 #define GPSR6_16 F_(SSI_SDATA6, IP16_11_8)
190 #define GPSR6_15 F_(SSI_WS6, IP16_7_4)
191 #define GPSR6_14 F_(SSI_SCK6, IP16_3_0)
192 #define GPSR6_13 FM(SSI_SDATA5)
193 #define GPSR6_12 FM(SSI_WS5)
194 #define GPSR6_11 FM(SSI_SCK5)
195 #define GPSR6_10 F_(SSI_SDATA4, IP15_31_28)
196 #define GPSR6_9 F_(SSI_WS4, IP15_27_24)
197 #define GPSR6_8 F_(SSI_SCK4, IP15_23_20)
198 #define GPSR6_7 F_(SSI_SDATA3, IP15_19_16)
199 #define GPSR6_6 F_(SSI_WS349, IP15_15_12)
200 #define GPSR6_5 F_(SSI_SCK349, IP15_11_8)
201 #define GPSR6_4 F_(SSI_SDATA2_A, IP15_7_4)
202 #define GPSR6_3 F_(SSI_SDATA1_A, IP15_3_0)
203 #define GPSR6_2 F_(SSI_SDATA0, IP14_31_28)
204 #define GPSR6_1 F_(SSI_WS01239, IP14_27_24)
205 #define GPSR6_0 F_(SSI_SCK01239, IP14_23_20)
207 /* GPSR7 */
208 #define GPSR7_3 FM(GP7_03)
209 #define GPSR7_2 FM(HDMI0_CEC)
210 #define GPSR7_1 FM(AVS2)
211 #define GPSR7_0 FM(AVS1)
214 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
215 #define IP0_3_0 FM(AVB_MDC) F_(0, 0) FM(MSIOF2_SS2_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
216 #define IP0_7_4 FM(AVB_MAGIC) F_(0, 0) FM(MSIOF2_SS1_C) FM(SCK4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
217 #define IP0_11_8 FM(AVB_PHY_INT) F_(0, 0) FM(MSIOF2_SYNC_C) FM(RX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
218 #define IP0_15_12 FM(AVB_LINK) F_(0, 0) FM(MSIOF2_SCK_C) FM(TX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
219 #define IP0_19_16 FM(AVB_AVTP_MATCH_A) F_(0, 0) FM(MSIOF2_RXD_C) FM(CTS4_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
220 #define IP0_23_20 FM(AVB_AVTP_CAPTURE_A) F_(0, 0) FM(MSIOF2_TXD_C) FM(RTS4_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
221 #define IP0_27_24 FM(IRQ0) FM(QPOLB) F_(0, 0) FM(DU_CDE) FM(VI4_DATA0_B) FM(CAN0_TX_B) FM(CANFD0_TX_B) FM(MSIOF3_SS2_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
222 #define IP0_31_28 FM(IRQ1) FM(QPOLA) F_(0, 0) FM(DU_DISP) FM(VI4_DATA1_B) FM(CAN0_RX_B) FM(CANFD0_RX_B) FM(MSIOF3_SS1_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
223 #define IP1_3_0 FM(IRQ2) FM(QCPV_QDE) F_(0, 0) FM(DU_EXODDF_DU_ODDF_DISP_CDE) FM(VI4_DATA2_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SYNC_E) F_(0, 0) FM(PWM3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
224 #define IP1_7_4 FM(IRQ3) FM(QSTVB_QVE) F_(0, 0) FM(DU_DOTCLKOUT1) FM(VI4_DATA3_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SCK_E) F_(0, 0) FM(PWM4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
225 #define IP1_11_8 FM(IRQ4) FM(QSTH_QHS) F_(0, 0) FM(DU_EXHSYNC_DU_HSYNC) FM(VI4_DATA4_B) F_(0, 0) F_(0, 0) FM(MSIOF3_RXD_E) F_(0, 0) FM(PWM5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
226 #define IP1_15_12 FM(IRQ5) FM(QSTB_QHE) F_(0, 0) FM(DU_EXVSYNC_DU_VSYNC) FM(VI4_DATA5_B) F_(0, 0) F_(0, 0) FM(MSIOF3_TXD_E) F_(0, 0) FM(PWM6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
227 #define IP1_19_16 FM(PWM0) FM(AVB_AVTP_PPS)F_(0, 0) F_(0, 0) FM(VI4_DATA6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IECLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
228 #define IP1_23_20 FM(PWM1_A) F_(0, 0) F_(0, 0) FM(HRX3_D) FM(VI4_DATA7_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IERX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
229 #define IP1_27_24 FM(PWM2_A) F_(0, 0) F_(0, 0) FM(HTX3_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IETX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
230 #define IP1_31_28 FM(A0) FM(LCDOUT16) FM(MSIOF3_SYNC_B) F_(0, 0) FM(VI4_DATA8) F_(0, 0) FM(DU_DB0) F_(0, 0) F_(0, 0) FM(PWM3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
231 #define IP2_3_0 FM(A1) FM(LCDOUT17) FM(MSIOF3_TXD_B) F_(0, 0) FM(VI4_DATA9) F_(0, 0) FM(DU_DB1) F_(0, 0) F_(0, 0) FM(PWM4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
232 #define IP2_7_4 FM(A2) FM(LCDOUT18) FM(MSIOF3_SCK_B) F_(0, 0) FM(VI4_DATA10) F_(0, 0) FM(DU_DB2) F_(0, 0) F_(0, 0) FM(PWM5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
233 #define IP2_11_8 FM(A3) FM(LCDOUT19) FM(MSIOF3_RXD_B) F_(0, 0) FM(VI4_DATA11) F_(0, 0) FM(DU_DB3) F_(0, 0) F_(0, 0) FM(PWM6_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
234 #define IP2_15_12 FM(A4) FM(LCDOUT20) FM(MSIOF3_SS1_B) F_(0, 0) FM(VI4_DATA12) FM(VI5_DATA12) FM(DU_DB4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
235 #define IP2_19_16 FM(A5) FM(LCDOUT21) FM(MSIOF3_SS2_B) FM(SCK4_B) FM(VI4_DATA13) FM(VI5_DATA13) FM(DU_DB5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
236 #define IP2_23_20 FM(A6) FM(LCDOUT22) FM(MSIOF2_SS1_A) FM(RX4_B) FM(VI4_DATA14) FM(VI5_DATA14) FM(DU_DB6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
237 #define IP2_27_24 FM(A7) FM(LCDOUT23) FM(MSIOF2_SS2_A) FM(TX4_B) FM(VI4_DATA15) FM(VI5_DATA15) FM(DU_DB7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
238 #define IP2_31_28 FM(A8) FM(RX3_B) FM(MSIOF2_SYNC_A) FM(HRX4_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(SDA6_A) FM(AVB_AVTP_MATCH_B) FM(PWM1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
239 #define IP3_3_0 FM(A9) F_(0, 0) FM(MSIOF2_SCK_A) FM(CTS4_N_B) F_(0, 0) FM(VI5_VSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
240 #define IP3_7_4 FM(A10) F_(0, 0) FM(MSIOF2_RXD_A) FM(RTS4_N_B) F_(0, 0) FM(VI5_HSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
241 #define IP3_11_8 FM(A11) FM(TX3_B) FM(MSIOF2_TXD_A) FM(HTX4_B) FM(HSCK4) FM(VI5_FIELD) F_(0, 0) FM(SCL6_A) FM(AVB_AVTP_CAPTURE_B) FM(PWM2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
243 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
244 #define IP3_15_12 FM(A12) FM(LCDOUT12) FM(MSIOF3_SCK_C) F_(0, 0) FM(HRX4_A) FM(VI5_DATA8) FM(DU_DG4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
245 #define IP3_19_16 FM(A13) FM(LCDOUT13) FM(MSIOF3_SYNC_C) F_(0, 0) FM(HTX4_A) FM(VI5_DATA9) FM(DU_DG5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
246 #define IP3_23_20 FM(A14) FM(LCDOUT14) FM(MSIOF3_RXD_C) F_(0, 0) FM(HCTS4_N) FM(VI5_DATA10) FM(DU_DG6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
247 #define IP3_27_24 FM(A15) FM(LCDOUT15) FM(MSIOF3_TXD_C) F_(0, 0) FM(HRTS4_N) FM(VI5_DATA11) FM(DU_DG7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
248 #define IP3_31_28 FM(A16) FM(LCDOUT8) F_(0, 0) F_(0, 0) FM(VI4_FIELD) F_(0, 0) FM(DU_DG0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
249 #define IP4_3_0 FM(A17) FM(LCDOUT9) F_(0, 0) F_(0, 0) FM(VI4_VSYNC_N) F_(0, 0) FM(DU_DG1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
250 #define IP4_7_4 FM(A18) FM(LCDOUT10) F_(0, 0) F_(0, 0) FM(VI4_HSYNC_N) F_(0, 0) FM(DU_DG2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
251 #define IP4_11_8 FM(A19) FM(LCDOUT11) F_(0, 0) F_(0, 0) FM(VI4_CLKENB) F_(0, 0) FM(DU_DG3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
252 #define IP4_15_12 FM(CS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLKENB) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
253 #define IP4_19_16 FM(CS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLK) F_(0, 0) FM(EX_WAIT0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
254 #define IP4_23_20 FM(BS_N) FM(QSTVA_QVS) FM(MSIOF3_SCK_D) FM(SCK3) FM(HSCK3) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN1_TX) FM(CANFD1_TX) FM(IETX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
255 #define IP4_27_24 FM(RD_N) F_(0, 0) FM(MSIOF3_SYNC_D) FM(RX3_A) FM(HRX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_TX_A) FM(CANFD0_TX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
256 #define IP4_31_28 FM(RD_WR_N) F_(0, 0) FM(MSIOF3_RXD_D) FM(TX3_A) FM(HTX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_RX_A) FM(CANFD0_RX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
257 #define IP5_3_0 FM(WE0_N) F_(0, 0) FM(MSIOF3_TXD_D) FM(CTS3_N) FM(HCTS3_N) F_(0, 0) F_(0, 0) FM(SCL6_B) FM(CAN_CLK) F_(0, 0) FM(IECLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
258 #define IP5_7_4 FM(WE1_N) F_(0, 0) FM(MSIOF3_SS1_D) FM(RTS3_N) FM(HRTS3_N) F_(0, 0) F_(0, 0) FM(SDA6_B) FM(CAN1_RX) FM(CANFD1_RX) FM(IERX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
259 #define IP5_11_8 FM(EX_WAIT0_A) FM(QCLK) F_(0, 0) F_(0, 0) FM(VI4_CLK) F_(0, 0) FM(DU_DOTCLKOUT0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
260 #define IP5_15_12 FM(D0) FM(MSIOF2_SS1_B)FM(MSIOF3_SCK_A) F_(0, 0) FM(VI4_DATA16) FM(VI5_DATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
261 #define IP5_19_16 FM(D1) FM(MSIOF2_SS2_B)FM(MSIOF3_SYNC_A) F_(0, 0) FM(VI4_DATA17) FM(VI5_DATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
262 #define IP5_23_20 FM(D2) F_(0, 0) FM(MSIOF3_RXD_A) F_(0, 0) FM(VI4_DATA18) FM(VI5_DATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
263 #define IP5_27_24 FM(D3) F_(0, 0) FM(MSIOF3_TXD_A) F_(0, 0) FM(VI4_DATA19) FM(VI5_DATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
264 #define IP5_31_28 FM(D4) FM(MSIOF2_SCK_B)F_(0, 0) F_(0, 0) FM(VI4_DATA20) FM(VI5_DATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
265 #define IP6_3_0 FM(D5) FM(MSIOF2_SYNC_B)F_(0, 0) F_(0, 0) FM(VI4_DATA21) FM(VI5_DATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
266 #define IP6_7_4 FM(D6) FM(MSIOF2_RXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA22) FM(VI5_DATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
267 #define IP6_11_8 FM(D7) FM(MSIOF2_TXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA23) FM(VI5_DATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
268 #define IP6_15_12 FM(D8) FM(LCDOUT0) FM(MSIOF2_SCK_D) FM(SCK4_C) FM(VI4_DATA0_A) F_(0, 0) FM(DU_DR0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
269 #define IP6_19_16 FM(D9) FM(LCDOUT1) FM(MSIOF2_SYNC_D) F_(0, 0) FM(VI4_DATA1_A) F_(0, 0) FM(DU_DR1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
270 #define IP6_23_20 FM(D10) FM(LCDOUT2) FM(MSIOF2_RXD_D) FM(HRX3_B) FM(VI4_DATA2_A) FM(CTS4_N_C) FM(DU_DR2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
271 #define IP6_27_24 FM(D11) FM(LCDOUT3) FM(MSIOF2_TXD_D) FM(HTX3_B) FM(VI4_DATA3_A) FM(RTS4_N_C) FM(DU_DR3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
272 #define IP6_31_28 FM(D12) FM(LCDOUT4) FM(MSIOF2_SS1_D) FM(RX4_C) FM(VI4_DATA4_A) F_(0, 0) FM(DU_DR4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
274 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
275 #define IP7_3_0 FM(D13) FM(LCDOUT5) FM(MSIOF2_SS2_D) FM(TX4_C) FM(VI4_DATA5_A) F_(0, 0) FM(DU_DR5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
276 #define IP7_7_4 FM(D14) FM(LCDOUT6) FM(MSIOF3_SS1_A) FM(HRX3_C) FM(VI4_DATA6_A) F_(0, 0) FM(DU_DR6) FM(SCL6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
277 #define IP7_11_8 FM(D15) FM(LCDOUT7) FM(MSIOF3_SS2_A) FM(HTX3_C) FM(VI4_DATA7_A) F_(0, 0) FM(DU_DR7) FM(SDA6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
278 #define IP7_19_16 FM(SD0_CLK) F_(0, 0) FM(MSIOF1_SCK_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
279 #define IP7_23_20 FM(SD0_CMD) F_(0, 0) FM(MSIOF1_SYNC_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
280 #define IP7_27_24 FM(SD0_DAT0) F_(0, 0) FM(MSIOF1_RXD_E) F_(0, 0) F_(0, 0) FM(TS_SCK0_B) FM(STP_ISCLK_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
281 #define IP7_31_28 FM(SD0_DAT1) F_(0, 0) FM(MSIOF1_TXD_E) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_B)FM(STP_ISSYNC_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
282 #define IP8_3_0 FM(SD0_DAT2) F_(0, 0) FM(MSIOF1_SS1_E) F_(0, 0) F_(0, 0) FM(TS_SDAT0_B) FM(STP_ISD_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
283 #define IP8_7_4 FM(SD0_DAT3) F_(0, 0) FM(MSIOF1_SS2_E) F_(0, 0) F_(0, 0) FM(TS_SDEN0_B) FM(STP_ISEN_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
284 #define IP8_11_8 FM(SD1_CLK) F_(0, 0) FM(MSIOF1_SCK_G) F_(0, 0) F_(0, 0) FM(SIM0_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
285 #define IP8_15_12 FM(SD1_CMD) F_(0, 0) FM(MSIOF1_SYNC_G) FM(NFCE_N_B) F_(0, 0) FM(SIM0_D_A) FM(STP_IVCXO27_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
286 #define IP8_19_16 FM(SD1_DAT0) FM(SD2_DAT4) FM(MSIOF1_RXD_G) FM(NFWP_N_B) F_(0, 0) FM(TS_SCK1_B) FM(STP_ISCLK_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
287 #define IP8_23_20 FM(SD1_DAT1) FM(SD2_DAT5) FM(MSIOF1_TXD_G) FM(NFDATA14_B) F_(0, 0) FM(TS_SPSYNC1_B)FM(STP_ISSYNC_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
288 #define IP8_27_24 FM(SD1_DAT2) FM(SD2_DAT6) FM(MSIOF1_SS1_G) FM(NFDATA15_B) F_(0, 0) FM(TS_SDAT1_B) FM(STP_ISD_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
289 #define IP8_31_28 FM(SD1_DAT3) FM(SD2_DAT7) FM(MSIOF1_SS2_G) FM(NFRB_N_B) F_(0, 0) FM(TS_SDEN1_B) FM(STP_ISEN_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
290 #define IP9_3_0 FM(SD2_CLK) F_(0, 0) FM(NFDATA8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
291 #define IP9_7_4 FM(SD2_CMD) F_(0, 0) FM(NFDATA9) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
292 #define IP9_11_8 FM(SD2_DAT0) F_(0, 0) FM(NFDATA10) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
293 #define IP9_15_12 FM(SD2_DAT1) F_(0, 0) FM(NFDATA11) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
294 #define IP9_19_16 FM(SD2_DAT2) F_(0, 0) FM(NFDATA12) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
295 #define IP9_23_20 FM(SD2_DAT3) F_(0, 0) FM(NFDATA13) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
296 #define IP9_27_24 FM(SD2_DS) F_(0, 0) FM(NFALE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
297 #define IP9_31_28 FM(SD3_CLK) F_(0, 0) FM(NFWE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
298 #define IP10_3_0 FM(SD3_CMD) F_(0, 0) FM(NFRE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
299 #define IP10_7_4 FM(SD3_DAT0) F_(0, 0) FM(NFDATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
300 #define IP10_11_8 FM(SD3_DAT1) F_(0, 0) FM(NFDATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
301 #define IP10_15_12 FM(SD3_DAT2) F_(0, 0) FM(NFDATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
302 #define IP10_19_16 FM(SD3_DAT3) F_(0, 0) FM(NFDATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
303 #define IP10_23_20 FM(SD3_DAT4) FM(SD2_CD_A) FM(NFDATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
304 #define IP10_27_24 FM(SD3_DAT5) FM(SD2_WP_A) FM(NFDATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
305 #define IP10_31_28 FM(SD3_DAT6) FM(SD3_CD) FM(NFDATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
306 #define IP11_3_0 FM(SD3_DAT7) FM(SD3_WP) FM(NFDATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
307 #define IP11_7_4 FM(SD3_DS) F_(0, 0) FM(NFCLE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
308 #define IP11_11_8 FM(SD0_CD) F_(0, 0) FM(NFDATA14_A) F_(0, 0) FM(SCL2_B) FM(SIM0_RST_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
310 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
311 #define IP11_15_12 FM(SD0_WP) F_(0, 0) FM(NFDATA15_A) F_(0, 0) FM(SDA2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
312 #define IP11_19_16 FM(SD1_CD) F_(0, 0) FM(NFRB_N_A) F_(0, 0) F_(0, 0) FM(SIM0_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
313 #define IP11_23_20 FM(SD1_WP) F_(0, 0) FM(NFCE_N_A) F_(0, 0) F_(0, 0) FM(SIM0_D_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
314 #define IP11_27_24 FM(SCK0) FM(HSCK1_B) FM(MSIOF1_SS2_B) FM(AUDIO_CLKC_B) FM(SDA2_A) FM(SIM0_RST_B) FM(STP_OPWM_0_C) FM(RIF0_CLK_B) F_(0, 0) FM(ADICHS2) FM(SCK5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
315 #define IP11_31_28 FM(RX0) FM(HRX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SCK0_C) FM(STP_ISCLK_0_C) FM(RIF0_D0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
316 #define IP12_3_0 FM(TX0) FM(HTX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_C)FM(STP_ISSYNC_0_C) FM(RIF0_D1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
317 #define IP12_7_4 FM(CTS0_N) FM(HCTS1_N_B) FM(MSIOF1_SYNC_B) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_C)FM(STP_ISSYNC_1_C) FM(RIF1_SYNC_B) FM(AUDIO_CLKOUT_C) FM(ADICS_SAMP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
318 #define IP12_11_8 FM(RTS0_N) FM(HRTS1_N_B) FM(MSIOF1_SS1_B) FM(AUDIO_CLKA_B) FM(SCL2_A) F_(0, 0) FM(STP_IVCXO27_1_C) FM(RIF0_SYNC_B) F_(0, 0) FM(ADICHS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
319 #define IP12_15_12 FM(RX1_A) FM(HRX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDAT0_C) FM(STP_ISD_0_C) FM(RIF1_CLK_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
320 #define IP12_19_16 FM(TX1_A) FM(HTX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDEN0_C) FM(STP_ISEN_0_C) FM(RIF1_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
321 #define IP12_23_20 FM(CTS1_N) FM(HCTS1_N_A) FM(MSIOF1_RXD_B) F_(0, 0) F_(0, 0) FM(TS_SDEN1_C) FM(STP_ISEN_1_C) FM(RIF1_D0_B) F_(0, 0) FM(ADIDATA) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
322 #define IP12_27_24 FM(RTS1_N) FM(HRTS1_N_A) FM(MSIOF1_TXD_B) F_(0, 0) F_(0, 0) FM(TS_SDAT1_C) FM(STP_ISD_1_C) FM(RIF1_D1_B) F_(0, 0) FM(ADICHS0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
323 #define IP12_31_28 FM(SCK2) FM(SCIF_CLK_B) FM(MSIOF1_SCK_B) F_(0, 0) F_(0, 0) FM(TS_SCK1_C) FM(STP_ISCLK_1_C) FM(RIF1_CLK_B) F_(0, 0) FM(ADICLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
324 #define IP13_3_0 FM(TX2_A) F_(0, 0) F_(0, 0) FM(SD2_CD_B) FM(SCL1_A) F_(0, 0) FM(FMCLK_A) FM(RIF1_D1_C) F_(0, 0) FM(FSO_CFE_0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
325 #define IP13_7_4 FM(RX2_A) F_(0, 0) F_(0, 0) FM(SD2_WP_B) FM(SDA1_A) F_(0, 0) FM(FMIN_A) FM(RIF1_SYNC_C) F_(0, 0) FM(FSO_CFE_1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
326 #define IP13_11_8 FM(HSCK0) F_(0, 0) FM(MSIOF1_SCK_D) FM(AUDIO_CLKB_A) FM(SSI_SDATA1_B)FM(TS_SCK0_D) FM(STP_ISCLK_0_D) FM(RIF0_CLK_C) F_(0, 0) F_(0, 0) FM(RX5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
327 #define IP13_15_12 FM(HRX0) F_(0, 0) FM(MSIOF1_RXD_D) F_(0, 0) FM(SSI_SDATA2_B)FM(TS_SDEN0_D) FM(STP_ISEN_0_D) FM(RIF0_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
328 #define IP13_19_16 FM(HTX0) F_(0, 0) FM(MSIOF1_TXD_D) F_(0, 0) FM(SSI_SDATA9_B)FM(TS_SDAT0_D) FM(STP_ISD_0_D) FM(RIF0_D1_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
329 #define IP13_23_20 FM(HCTS0_N) FM(RX2_B) FM(MSIOF1_SYNC_D) F_(0, 0) FM(SSI_SCK9_A) FM(TS_SPSYNC0_D)FM(STP_ISSYNC_0_D) FM(RIF0_SYNC_C) FM(AUDIO_CLKOUT1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
330 #define IP13_27_24 FM(HRTS0_N) FM(TX2_B) FM(MSIOF1_SS1_D) F_(0, 0) FM(SSI_WS9_A) F_(0, 0) FM(STP_IVCXO27_0_D) FM(BPFCLK_A) FM(AUDIO_CLKOUT2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
331 #define IP13_31_28 FM(MSIOF0_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_A) F_(0, 0) FM(TX5_B) F_(0, 0) F_(0, 0) FM(BPFCLK_D) F_(0, 0) F_(0, 0)
332 #define IP14_3_0 FM(MSIOF0_SS1) FM(RX5_A) FM(NFWP_N_A) FM(AUDIO_CLKA_C) FM(SSI_SCK2_A) F_(0, 0) FM(STP_IVCXO27_0_C) F_(0, 0) FM(AUDIO_CLKOUT3_A) F_(0, 0) FM(TCLK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
333 #define IP14_7_4 FM(MSIOF0_SS2) FM(TX5_A) FM(MSIOF1_SS2_D) FM(AUDIO_CLKC_A) FM(SSI_WS2_A) F_(0, 0) FM(STP_OPWM_0_D) F_(0, 0) FM(AUDIO_CLKOUT_D) F_(0, 0) FM(SPEEDIN_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
334 #define IP14_11_8 FM(MLB_CLK) F_(0, 0) FM(MSIOF1_SCK_F) F_(0, 0) FM(SCL1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
335 #define IP14_15_12 FM(MLB_SIG) FM(RX1_B) FM(MSIOF1_SYNC_F) F_(0, 0) FM(SDA1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
336 #define IP14_19_16 FM(MLB_DAT) FM(TX1_B) FM(MSIOF1_RXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
337 #define IP14_23_20 FM(SSI_SCK01239) F_(0, 0) FM(MSIOF1_TXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
338 #define IP14_27_24 FM(SSI_WS01239) F_(0, 0) FM(MSIOF1_SS1_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
340 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
341 #define IP14_31_28 FM(SSI_SDATA0) F_(0, 0) FM(MSIOF1_SS2_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
342 #define IP15_3_0 FM(SSI_SDATA1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
343 #define IP15_7_4 FM(SSI_SDATA2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(SSI_SCK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
344 #define IP15_11_8 FM(SSI_SCK349) F_(0, 0) FM(MSIOF1_SS1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
345 #define IP15_15_12 FM(SSI_WS349) FM(HCTS2_N_A) FM(MSIOF1_SS2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
346 #define IP15_19_16 FM(SSI_SDATA3) FM(HRTS2_N_A) FM(MSIOF1_TXD_A) F_(0, 0) F_(0, 0) FM(TS_SCK0_A) FM(STP_ISCLK_0_A) FM(RIF0_D1_A) FM(RIF2_D0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
347 #define IP15_23_20 FM(SSI_SCK4) FM(HRX2_A) FM(MSIOF1_SCK_A) F_(0, 0) F_(0, 0) FM(TS_SDAT0_A) FM(STP_ISD_0_A) FM(RIF0_CLK_A) FM(RIF2_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
348 #define IP15_27_24 FM(SSI_WS4) FM(HTX2_A) FM(MSIOF1_SYNC_A) F_(0, 0) F_(0, 0) FM(TS_SDEN0_A) FM(STP_ISEN_0_A) FM(RIF0_SYNC_A) FM(RIF2_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
349 #define IP15_31_28 FM(SSI_SDATA4) FM(HSCK2_A) FM(MSIOF1_RXD_A) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_A)FM(STP_ISSYNC_0_A) FM(RIF0_D0_A) FM(RIF2_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
350 #define IP16_3_0 FM(SSI_SCK6) F_(0, 0) F_(0, 0) FM(SIM0_RST_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
351 #define IP16_7_4 FM(SSI_WS6) F_(0, 0) F_(0, 0) FM(SIM0_D_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
352 #define IP16_11_8 FM(SSI_SDATA6) F_(0, 0) F_(0, 0) FM(SIM0_CLK_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
353 #define IP16_15_12 FM(SSI_SCK78) FM(HRX2_B) FM(MSIOF1_SCK_C) F_(0, 0) F_(0, 0) FM(TS_SCK1_A) FM(STP_ISCLK_1_A) FM(RIF1_CLK_A) FM(RIF3_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
354 #define IP16_19_16 FM(SSI_WS78) FM(HTX2_B) FM(MSIOF1_SYNC_C) F_(0, 0) F_(0, 0) FM(TS_SDAT1_A) FM(STP_ISD_1_A) FM(RIF1_SYNC_A) FM(RIF3_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
355 #define IP16_23_20 FM(SSI_SDATA7) FM(HCTS2_N_B) FM(MSIOF1_RXD_C) F_(0, 0) F_(0, 0) FM(TS_SDEN1_A) FM(STP_ISEN_1_A) FM(RIF1_D0_A) FM(RIF3_D0_A) F_(0, 0) FM(TCLK2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
356 #define IP16_27_24 FM(SSI_SDATA8) FM(HRTS2_N_B) FM(MSIOF1_TXD_C) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_A)FM(STP_ISSYNC_1_A) FM(RIF1_D1_A) FM(RIF3_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
357 #define IP16_31_28 FM(SSI_SDATA9_A) FM(HSCK2_B) FM(MSIOF1_SS1_C) FM(HSCK1_A) FM(SSI_WS1_B) FM(SCK1) FM(STP_IVCXO27_1_A) FM(SCK5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
358 #define IP17_3_0 FM(AUDIO_CLKA_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(CC5_OSCOUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
359 #define IP17_7_4 FM(AUDIO_CLKB_B) FM(SCIF_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_1_D) FM(REMOCON_A) F_(0, 0) F_(0, 0) FM(TCLK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
360 #define IP17_11_8 FM(USB0_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_RST_C) F_(0, 0) FM(TS_SCK1_D) FM(STP_ISCLK_1_D) FM(BPFCLK_B) FM(RIF3_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HSCK2_C) F_(0, 0) F_(0, 0)
361 #define IP17_15_12 FM(USB0_OVC) F_(0, 0) F_(0, 0) FM(SIM0_D_C) F_(0, 0) FM(TS_SDAT1_D) FM(STP_ISD_1_D) F_(0, 0) FM(RIF3_SYNC_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HRX2_C) F_(0, 0) F_(0, 0)
362 #define IP17_19_16 FM(USB1_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_CLK_C) FM(SSI_SCK1_A) FM(TS_SCK0_E) FM(STP_ISCLK_0_E) FM(FMCLK_B) FM(RIF2_CLK_B) F_(0, 0) FM(SPEEDIN_A) F_(0, 0) F_(0, 0) FM(HTX2_C) F_(0, 0) F_(0, 0)
363 #define IP17_23_20 FM(USB1_OVC) F_(0, 0) FM(MSIOF1_SS2_C) F_(0, 0) FM(SSI_WS1_A) FM(TS_SDAT0_E) FM(STP_ISD_0_E) FM(FMIN_B) FM(RIF2_SYNC_B) F_(0, 0) FM(REMOCON_B) F_(0, 0) F_(0, 0) FM(HCTS2_N_C) F_(0, 0) F_(0, 0)
364 #define IP17_27_24 FM(USB30_PWEN) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_B) FM(SSI_SCK2_B) FM(TS_SDEN1_D) FM(STP_ISEN_1_D) FM(STP_OPWM_0_E)FM(RIF3_D0_B) F_(0, 0) FM(TCLK2_B) FM(TPU0TO0) FM(BPFCLK_C) FM(HRTS2_N_C) F_(0, 0) F_(0, 0)
365 #define IP17_31_28 FM(USB30_OVC) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT1_B) FM(SSI_WS2_B) FM(TS_SPSYNC1_D)FM(STP_ISSYNC_1_D) FM(STP_IVCXO27_0_E)FM(RIF3_D1_B) F_(0, 0) FM(FSO_TOE_N) FM(TPU0TO1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
366 #define IP18_3_0 FM(GP6_30) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT2_B) FM(SSI_SCK9_B) FM(TS_SDEN0_E) FM(STP_ISEN_0_E) F_(0, 0) FM(RIF2_D0_B) F_(0, 0) F_(0, 0) FM(TPU0TO2) FM(FMCLK_C) FM(FMCLK_D) F_(0, 0) F_(0, 0)
367 #define IP18_7_4 FM(GP6_31) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT3_B) FM(SSI_WS9_B) FM(TS_SPSYNC0_E)FM(STP_ISSYNC_0_E) F_(0, 0) FM(RIF2_D1_B) F_(0, 0) F_(0, 0) FM(TPU0TO3) FM(FMIN_C) FM(FMIN_D) F_(0, 0) F_(0, 0)
369 #define PINMUX_GPSR \
370 \
371 GPSR6_31 \
372 GPSR6_30 \
373 GPSR6_29 \
374 GPSR1_28 GPSR6_28 \
375 GPSR1_27 GPSR6_27 \
376 GPSR1_26 GPSR6_26 \
377 GPSR1_25 GPSR5_25 GPSR6_25 \
378 GPSR1_24 GPSR5_24 GPSR6_24 \
379 GPSR1_23 GPSR5_23 GPSR6_23 \
380 GPSR1_22 GPSR5_22 GPSR6_22 \
381 GPSR1_21 GPSR5_21 GPSR6_21 \
382 GPSR1_20 GPSR5_20 GPSR6_20 \
383 GPSR1_19 GPSR5_19 GPSR6_19 \
384 GPSR1_18 GPSR5_18 GPSR6_18 \
385 GPSR1_17 GPSR4_17 GPSR5_17 GPSR6_17 \
386 GPSR1_16 GPSR4_16 GPSR5_16 GPSR6_16 \
387 GPSR0_15 GPSR1_15 GPSR3_15 GPSR4_15 GPSR5_15 GPSR6_15 \
388 GPSR0_14 GPSR1_14 GPSR2_14 GPSR3_14 GPSR4_14 GPSR5_14 GPSR6_14 \
389 GPSR0_13 GPSR1_13 GPSR2_13 GPSR3_13 GPSR4_13 GPSR5_13 GPSR6_13 \
390 GPSR0_12 GPSR1_12 GPSR2_12 GPSR3_12 GPSR4_12 GPSR5_12 GPSR6_12 \
391 GPSR0_11 GPSR1_11 GPSR2_11 GPSR3_11 GPSR4_11 GPSR5_11 GPSR6_11 \
392 GPSR0_10 GPSR1_10 GPSR2_10 GPSR3_10 GPSR4_10 GPSR5_10 GPSR6_10 \
393 GPSR0_9 GPSR1_9 GPSR2_9 GPSR3_9 GPSR4_9 GPSR5_9 GPSR6_9 \
394 GPSR0_8 GPSR1_8 GPSR2_8 GPSR3_8 GPSR4_8 GPSR5_8 GPSR6_8 \
395 GPSR0_7 GPSR1_7 GPSR2_7 GPSR3_7 GPSR4_7 GPSR5_7 GPSR6_7 \
396 GPSR0_6 GPSR1_6 GPSR2_6 GPSR3_6 GPSR4_6 GPSR5_6 GPSR6_6 \
397 GPSR0_5 GPSR1_5 GPSR2_5 GPSR3_5 GPSR4_5 GPSR5_5 GPSR6_5 \
398 GPSR0_4 GPSR1_4 GPSR2_4 GPSR3_4 GPSR4_4 GPSR5_4 GPSR6_4 \
399 GPSR0_3 GPSR1_3 GPSR2_3 GPSR3_3 GPSR4_3 GPSR5_3 GPSR6_3 GPSR7_3 \
400 GPSR0_2 GPSR1_2 GPSR2_2 GPSR3_2 GPSR4_2 GPSR5_2 GPSR6_2 GPSR7_2 \
401 GPSR0_1 GPSR1_1 GPSR2_1 GPSR3_1 GPSR4_1 GPSR5_1 GPSR6_1 GPSR7_1 \
402 GPSR0_0 GPSR1_0 GPSR2_0 GPSR3_0 GPSR4_0 GPSR5_0 GPSR6_0 GPSR7_0
404 #define PINMUX_IPSR \
405 \
406 FM(IP0_3_0) IP0_3_0 FM(IP1_3_0) IP1_3_0 FM(IP2_3_0) IP2_3_0 FM(IP3_3_0) IP3_3_0 \
407 FM(IP0_7_4) IP0_7_4 FM(IP1_7_4) IP1_7_4 FM(IP2_7_4) IP2_7_4 FM(IP3_7_4) IP3_7_4 \
408 FM(IP0_11_8) IP0_11_8 FM(IP1_11_8) IP1_11_8 FM(IP2_11_8) IP2_11_8 FM(IP3_11_8) IP3_11_8 \
409 FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \
410 FM(IP0_19_16) IP0_19_16 FM(IP1_19_16) IP1_19_16 FM(IP2_19_16) IP2_19_16 FM(IP3_19_16) IP3_19_16 \
411 FM(IP0_23_20) IP0_23_20 FM(IP1_23_20) IP1_23_20 FM(IP2_23_20) IP2_23_20 FM(IP3_23_20) IP3_23_20 \
412 FM(IP0_27_24) IP0_27_24 FM(IP1_27_24) IP1_27_24 FM(IP2_27_24) IP2_27_24 FM(IP3_27_24) IP3_27_24 \
413 FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \
414 \
415 FM(IP4_3_0) IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) IP6_3_0 FM(IP7_3_0) IP7_3_0 \
416 FM(IP4_7_4) IP4_7_4 FM(IP5_7_4) IP5_7_4 FM(IP6_7_4) IP6_7_4 FM(IP7_7_4) IP7_7_4 \
417 FM(IP4_11_8) IP4_11_8 FM(IP5_11_8) IP5_11_8 FM(IP6_11_8) IP6_11_8 FM(IP7_11_8) IP7_11_8 \
418 FM(IP4_15_12) IP4_15_12 FM(IP5_15_12) IP5_15_12 FM(IP6_15_12) IP6_15_12 \
419 FM(IP4_19_16) IP4_19_16 FM(IP5_19_16) IP5_19_16 FM(IP6_19_16) IP6_19_16 FM(IP7_19_16) IP7_19_16 \
420 FM(IP4_23_20) IP4_23_20 FM(IP5_23_20) IP5_23_20 FM(IP6_23_20) IP6_23_20 FM(IP7_23_20) IP7_23_20 \
421 FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \
422 FM(IP4_31_28) IP4_31_28 FM(IP5_31_28) IP5_31_28 FM(IP6_31_28) IP6_31_28 FM(IP7_31_28) IP7_31_28 \
423 \
424 FM(IP8_3_0) IP8_3_0 FM(IP9_3_0) IP9_3_0 FM(IP10_3_0) IP10_3_0 FM(IP11_3_0) IP11_3_0 \
425 FM(IP8_7_4) IP8_7_4 FM(IP9_7_4) IP9_7_4 FM(IP10_7_4) IP10_7_4 FM(IP11_7_4) IP11_7_4 \
426 FM(IP8_11_8) IP8_11_8 FM(IP9_11_8) IP9_11_8 FM(IP10_11_8) IP10_11_8 FM(IP11_11_8) IP11_11_8 \
427 FM(IP8_15_12) IP8_15_12 FM(IP9_15_12) IP9_15_12 FM(IP10_15_12) IP10_15_12 FM(IP11_15_12) IP11_15_12 \
428 FM(IP8_19_16) IP8_19_16 FM(IP9_19_16) IP9_19_16 FM(IP10_19_16) IP10_19_16 FM(IP11_19_16) IP11_19_16 \
429 FM(IP8_23_20) IP8_23_20 FM(IP9_23_20) IP9_23_20 FM(IP10_23_20) IP10_23_20 FM(IP11_23_20) IP11_23_20 \
430 FM(IP8_27_24) IP8_27_24 FM(IP9_27_24) IP9_27_24 FM(IP10_27_24) IP10_27_24 FM(IP11_27_24) IP11_27_24 \
431 FM(IP8_31_28) IP8_31_28 FM(IP9_31_28) IP9_31_28 FM(IP10_31_28) IP10_31_28 FM(IP11_31_28) IP11_31_28 \
432 \
433 FM(IP12_3_0) IP12_3_0 FM(IP13_3_0) IP13_3_0 FM(IP14_3_0) IP14_3_0 FM(IP15_3_0) IP15_3_0 \
434 FM(IP12_7_4) IP12_7_4 FM(IP13_7_4) IP13_7_4 FM(IP14_7_4) IP14_7_4 FM(IP15_7_4) IP15_7_4 \
435 FM(IP12_11_8) IP12_11_8 FM(IP13_11_8) IP13_11_8 FM(IP14_11_8) IP14_11_8 FM(IP15_11_8) IP15_11_8 \
436 FM(IP12_15_12) IP12_15_12 FM(IP13_15_12) IP13_15_12 FM(IP14_15_12) IP14_15_12 FM(IP15_15_12) IP15_15_12 \
437 FM(IP12_19_16) IP12_19_16 FM(IP13_19_16) IP13_19_16 FM(IP14_19_16) IP14_19_16 FM(IP15_19_16) IP15_19_16 \
438 FM(IP12_23_20) IP12_23_20 FM(IP13_23_20) IP13_23_20 FM(IP14_23_20) IP14_23_20 FM(IP15_23_20) IP15_23_20 \
439 FM(IP12_27_24) IP12_27_24 FM(IP13_27_24) IP13_27_24 FM(IP14_27_24) IP14_27_24 FM(IP15_27_24) IP15_27_24 \
440 FM(IP12_31_28) IP12_31_28 FM(IP13_31_28) IP13_31_28 FM(IP14_31_28) IP14_31_28 FM(IP15_31_28) IP15_31_28 \
441 \
442 FM(IP16_3_0) IP16_3_0 FM(IP17_3_0) IP17_3_0 FM(IP18_3_0) IP18_3_0 \
443 FM(IP16_7_4) IP16_7_4 FM(IP17_7_4) IP17_7_4 FM(IP18_7_4) IP18_7_4 \
444 FM(IP16_11_8) IP16_11_8 FM(IP17_11_8) IP17_11_8 \
445 FM(IP16_15_12) IP16_15_12 FM(IP17_15_12) IP17_15_12 \
446 FM(IP16_19_16) IP16_19_16 FM(IP17_19_16) IP17_19_16 \
447 FM(IP16_23_20) IP16_23_20 FM(IP17_23_20) IP17_23_20 \
448 FM(IP16_27_24) IP16_27_24 FM(IP17_27_24) IP17_27_24 \
449 FM(IP16_31_28) IP16_31_28 FM(IP17_31_28) IP17_31_28
452 #define MOD_SEL0_31_30_29 FM(SEL_MSIOF3_0) FM(SEL_MSIOF3_1) FM(SEL_MSIOF3_2) FM(SEL_MSIOF3_3) FM(SEL_MSIOF3_4) F_(0, 0) F_(0, 0) F_(0, 0)
453 #define MOD_SEL0_28_27 FM(SEL_MSIOF2_0) FM(SEL_MSIOF2_1) FM(SEL_MSIOF2_2) FM(SEL_MSIOF2_3)
454 #define MOD_SEL0_26_25_24 FM(SEL_MSIOF1_0) FM(SEL_MSIOF1_1) FM(SEL_MSIOF1_2) FM(SEL_MSIOF1_3) FM(SEL_MSIOF1_4) FM(SEL_MSIOF1_5) FM(SEL_MSIOF1_6) F_(0, 0)
455 #define MOD_SEL0_23 FM(SEL_LBSC_0) FM(SEL_LBSC_1)
456 #define MOD_SEL0_22 FM(SEL_IEBUS_0) FM(SEL_IEBUS_1)
457 #define MOD_SEL0_21 FM(SEL_I2C2_0) FM(SEL_I2C2_1)
458 #define MOD_SEL0_20 FM(SEL_I2C1_0) FM(SEL_I2C1_1)
459 #define MOD_SEL0_19 FM(SEL_HSCIF4_0) FM(SEL_HSCIF4_1)
460 #define MOD_SEL0_18_17 FM(SEL_HSCIF3_0) FM(SEL_HSCIF3_1) FM(SEL_HSCIF3_2) FM(SEL_HSCIF3_3)
461 #define MOD_SEL0_16 FM(SEL_HSCIF1_0) FM(SEL_HSCIF1_1)
462 #define MOD_SEL0_14_13 FM(SEL_HSCIF2_0) FM(SEL_HSCIF2_1) FM(SEL_HSCIF2_2) F_(0, 0)
463 #define MOD_SEL0_12 FM(SEL_ETHERAVB_0) FM(SEL_ETHERAVB_1)
464 #define MOD_SEL0_11 FM(SEL_DRIF3_0) FM(SEL_DRIF3_1)
465 #define MOD_SEL0_10 FM(SEL_DRIF2_0) FM(SEL_DRIF2_1)
466 #define MOD_SEL0_9_8 FM(SEL_DRIF1_0) FM(SEL_DRIF1_1) FM(SEL_DRIF1_2) F_(0, 0)
467 #define MOD_SEL0_7_6 FM(SEL_DRIF0_0) FM(SEL_DRIF0_1) FM(SEL_DRIF0_2) F_(0, 0)
468 #define MOD_SEL0_5 FM(SEL_CANFD0_0) FM(SEL_CANFD0_1)
469 #define MOD_SEL0_4_3 FM(SEL_ADG_A_0) FM(SEL_ADG_A_1) FM(SEL_ADG_A_2) FM(SEL_ADG_A_3)
472 #define MOD_SEL1_31_30 FM(SEL_TSIF1_0) FM(SEL_TSIF1_1) FM(SEL_TSIF1_2) FM(SEL_TSIF1_3)
473 #define MOD_SEL1_29_28_27 FM(SEL_TSIF0_0) FM(SEL_TSIF0_1) FM(SEL_TSIF0_2) FM(SEL_TSIF0_3) FM(SEL_TSIF0_4) F_(0, 0) F_(0, 0) F_(0, 0)
474 #define MOD_SEL1_26 FM(SEL_TIMER_TMU_0) FM(SEL_TIMER_TMU_1)
475 #define MOD_SEL1_25_24 FM(SEL_SSP1_1_0) FM(SEL_SSP1_1_1) FM(SEL_SSP1_1_2) FM(SEL_SSP1_1_3)
476 #define MOD_SEL1_23_22_21 FM(SEL_SSP1_0_0) FM(SEL_SSP1_0_1) FM(SEL_SSP1_0_2) FM(SEL_SSP1_0_3) FM(SEL_SSP1_0_4) F_(0, 0) F_(0, 0) F_(0, 0)
477 #define MOD_SEL1_20 FM(SEL_SSI1_0) FM(SEL_SSI1_1)
478 #define MOD_SEL1_19 FM(SEL_SPEED_PULSE_0) FM(SEL_SPEED_PULSE_1)
479 #define MOD_SEL1_18_17 FM(SEL_SIMCARD_0) FM(SEL_SIMCARD_1) FM(SEL_SIMCARD_2) FM(SEL_SIMCARD_3)
480 #define MOD_SEL1_16 FM(SEL_SDHI2_0) FM(SEL_SDHI2_1)
481 #define MOD_SEL1_15_14 FM(SEL_SCIF4_0) FM(SEL_SCIF4_1) FM(SEL_SCIF4_2) F_(0, 0)
482 #define MOD_SEL1_13 FM(SEL_SCIF3_0) FM(SEL_SCIF3_1)
483 #define MOD_SEL1_12 FM(SEL_SCIF2_0) FM(SEL_SCIF2_1)
484 #define MOD_SEL1_11 FM(SEL_SCIF1_0) FM(SEL_SCIF1_1)
485 #define MOD_SEL1_10 FM(SEL_SCIF_0) FM(SEL_SCIF_1)
486 #define MOD_SEL1_9 FM(SEL_REMOCON_0) FM(SEL_REMOCON_1)
487 #define MOD_SEL1_6 FM(SEL_RCAN0_0) FM(SEL_RCAN0_1)
488 #define MOD_SEL1_5 FM(SEL_PWM6_0) FM(SEL_PWM6_1)
489 #define MOD_SEL1_4 FM(SEL_PWM5_0) FM(SEL_PWM5_1)
490 #define MOD_SEL1_3 FM(SEL_PWM4_0) FM(SEL_PWM4_1)
491 #define MOD_SEL1_2 FM(SEL_PWM3_0) FM(SEL_PWM3_1)
492 #define MOD_SEL1_1 FM(SEL_PWM2_0) FM(SEL_PWM2_1)
493 #define MOD_SEL1_0 FM(SEL_PWM1_0) FM(SEL_PWM1_1)
496 #define MOD_SEL2_31 FM(I2C_SEL_5_0) FM(I2C_SEL_5_1)
497 #define MOD_SEL2_30 FM(I2C_SEL_3_0) FM(I2C_SEL_3_1)
498 #define MOD_SEL2_29 FM(I2C_SEL_0_0) FM(I2C_SEL_0_1)
499 #define MOD_SEL2_28_27 FM(SEL_FM_0) FM(SEL_FM_1) FM(SEL_FM_2) FM(SEL_FM_3)
500 #define MOD_SEL2_26 FM(SEL_SCIF5_0) FM(SEL_SCIF5_1)
501 #define MOD_SEL2_25_24_23 FM(SEL_I2C6_0) FM(SEL_I2C6_1) FM(SEL_I2C6_2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
502 #define MOD_SEL2_22 FM(SEL_NDFC_0) FM(SEL_NDFC_1)
503 #define MOD_SEL2_21 FM(SEL_SSI2_0) FM(SEL_SSI2_1)
504 #define MOD_SEL2_20 FM(SEL_SSI9_0) FM(SEL_SSI9_1)
505 #define MOD_SEL2_19 FM(SEL_TIMER_TMU2_0) FM(SEL_TIMER_TMU2_1)
506 #define MOD_SEL2_18 FM(SEL_ADG_B_0) FM(SEL_ADG_B_1)
507 #define MOD_SEL2_17 FM(SEL_ADG_C_0) FM(SEL_ADG_C_1)
508 #define MOD_SEL2_0 FM(SEL_VIN4_0) FM(SEL_VIN4_1)
510 #define PINMUX_MOD_SELS \
511 \
512 MOD_SEL0_31_30_29 MOD_SEL1_31_30 MOD_SEL2_31 \
513 MOD_SEL2_30 \
514 MOD_SEL1_29_28_27 MOD_SEL2_29 \
515 MOD_SEL0_28_27 MOD_SEL2_28_27 \
516 MOD_SEL0_26_25_24 MOD_SEL1_26 MOD_SEL2_26 \
517 MOD_SEL1_25_24 MOD_SEL2_25_24_23 \
518 MOD_SEL0_23 MOD_SEL1_23_22_21 \
519 MOD_SEL0_22 MOD_SEL2_22 \
520 MOD_SEL0_21 MOD_SEL2_21 \
521 MOD_SEL0_20 MOD_SEL1_20 MOD_SEL2_20 \
522 MOD_SEL0_19 MOD_SEL1_19 MOD_SEL2_19 \
523 MOD_SEL0_18_17 MOD_SEL1_18_17 MOD_SEL2_18 \
524 MOD_SEL2_17 \
525 MOD_SEL0_16 MOD_SEL1_16 \
526 MOD_SEL1_15_14 \
527 MOD_SEL0_14_13 \
528 MOD_SEL1_13 \
529 MOD_SEL0_12 MOD_SEL1_12 \
530 MOD_SEL0_11 MOD_SEL1_11 \
531 MOD_SEL0_10 MOD_SEL1_10 \
532 MOD_SEL0_9_8 MOD_SEL1_9 \
533 MOD_SEL0_7_6 \
534 MOD_SEL1_6 \
535 MOD_SEL0_5 MOD_SEL1_5 \
536 MOD_SEL0_4_3 MOD_SEL1_4 \
537 MOD_SEL1_3 \
538 MOD_SEL1_2 \
539 MOD_SEL1_1 \
540 MOD_SEL1_0 MOD_SEL2_0
542 /*
543 * These pins are not able to be muxed but have other properties
544 * that can be set, such as drive-strength or pull-up/pull-down enable.
545 */
546 #define PINMUX_STATIC \
547 FM(QSPI0_SPCLK) FM(QSPI0_SSL) FM(QSPI0_MOSI_IO0) FM(QSPI0_MISO_IO1) \
548 FM(QSPI0_IO2) FM(QSPI0_IO3) \
549 FM(QSPI1_SPCLK) FM(QSPI1_SSL) FM(QSPI1_MOSI_IO0) FM(QSPI1_MISO_IO1) \
550 FM(QSPI1_IO2) FM(QSPI1_IO3) \
551 FM(RPC_INT) FM(RPC_WP) FM(RPC_RESET) \
552 FM(AVB_TX_CTL) FM(AVB_TXC) FM(AVB_TD0) FM(AVB_TD1) FM(AVB_TD2) FM(AVB_TD3) \
553 FM(AVB_RX_CTL) FM(AVB_RXC) FM(AVB_RD0) FM(AVB_RD1) FM(AVB_RD2) FM(AVB_RD3) \
554 FM(AVB_TXCREFCLK) FM(AVB_MDIO) \
555 FM(PRESETOUT) \
556 FM(DU_DOTCLKIN0) FM(DU_DOTCLKIN1) FM(DU_DOTCLKIN2) \
557 FM(TMS) FM(TDO) FM(ASEBRK) FM(MLB_REF) FM(TDI) FM(TCK) FM(TRST) FM(EXTALR)
559 #define PINMUX_PHYS \
560 FM(SCL0) FM(SDA0) FM(SCL3) FM(SDA3) FM(SCL5) FM(SDA5)
565 PINMUX_DATA_BEGIN,
567 PINMUX_DATA_END,
569 #define F_(x, y)
570 #define FM(x) FN_##x,
571 PINMUX_FUNCTION_BEGIN,
573 PINMUX_GPSR
574 PINMUX_IPSR
575 PINMUX_MOD_SELS
576 PINMUX_FUNCTION_END,
577 #undef F_
578 #undef FM
580 #define F_(x, y)
581 #define FM(x) x##_MARK,
582 PINMUX_MARK_BEGIN,
583 PINMUX_GPSR
584 PINMUX_IPSR
585 PINMUX_MOD_SELS
586 PINMUX_STATIC
587 PINMUX_PHYS
588 PINMUX_MARK_END,
589 #undef F_
590 #undef FM
591 };
608 /* IPSR0 */
650 /* IPSR1 */
702 /* IPSR2 */
763 /* IPSR3 */
817 /* IPSR4 */
863 /* IPSR5 */
913 /* IPSR6 */
965 /* IPSR7 */
1007 /* IPSR8 */
1056 /* IPSR9 */
1081 /* IPSR10 */
1109 /* IPSR11 */
1153 /* IPSR12 */
1214 /* IPSR13 */
1274 /* IPSR14 */
1315 /* IPSR15 */
1362 /* IPSR16 */
1414 /* IPSR17 */
1481 /* IPSR18 */
1502 /* I2C */
1507 /*
1508 * Static pins can not be muxed between different functions but
1509 * still need mark entries in the pinmux list. Add each static
1510 * pin to the list without an associated function. The sh-pfc
1511 * core will do the right thing and skip trying to mux the pin
1512 * while still applying configuration to it.
1513 */
1514 #define FM(x) PINMUX_DATA(x##_MARK, 0),
1515 PINMUX_STATIC
1516 #undef FM
1517 };
1519 /*
1520 * R8A7796 has 8 banks with 32 GPIOs in each => 256 GPIOs.
1521 * Physical layout rows: A - AW, cols: 1 - 39.
1522 */
1525 #define PIN_A_NUMBER(r, c) PIN_NUMBER(ROW_GROUP_A(r), c)
1526 #define PIN_NONE U16_MAX
1531 /*
1532 * Pins not associated with a GPIO port.
1533 *
1534 * The pin positions are different between different r8a7796
1535 * packages, all that is needed for the pfc driver is a unique
1536 * number for each pin. To this end use the pin layout from
1537 * R-Car M3SiP to calculate a unique number for each pin.
1538 */
1569 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 39, EXTALR, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1575 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 26, TRST#, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1576 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 29, TDI, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1578 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 27, TCK, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1581 };
1583 /* - AUDIO CLOCK ------------------------------------------------------------ */
1585 /* CLK A */
1587 };
1589 AUDIO_CLKA_A_MARK,
1590 };
1592 /* CLK A */
1594 };
1596 AUDIO_CLKA_B_MARK,
1597 };
1599 /* CLK A */
1601 };
1603 AUDIO_CLKA_C_MARK,
1604 };
1606 /* CLK B */
1608 };
1610 AUDIO_CLKB_A_MARK,
1611 };
1613 /* CLK B */
1615 };
1617 AUDIO_CLKB_B_MARK,
1618 };
1620 /* CLK C */
1622 };
1624 AUDIO_CLKC_A_MARK,
1625 };
1627 /* CLK C */
1629 };
1631 AUDIO_CLKC_B_MARK,
1632 };
1634 /* CLKOUT */
1636 };
1638 AUDIO_CLKOUT_A_MARK,
1639 };
1641 /* CLKOUT */
1643 };
1645 AUDIO_CLKOUT_B_MARK,
1646 };
1648 /* CLKOUT */
1650 };
1652 AUDIO_CLKOUT_C_MARK,
1653 };
1655 /* CLKOUT */
1657 };
1659 AUDIO_CLKOUT_D_MARK,
1660 };
1662 /* CLKOUT1 */
1664 };
1666 AUDIO_CLKOUT1_A_MARK,
1667 };
1669 /* CLKOUT1 */
1671 };
1673 AUDIO_CLKOUT1_B_MARK,
1674 };
1676 /* CLKOUT2 */
1678 };
1680 AUDIO_CLKOUT2_A_MARK,
1681 };
1683 /* CLKOUT2 */
1685 };
1687 AUDIO_CLKOUT2_B_MARK,
1688 };
1691 /* CLKOUT3 */
1693 };
1695 AUDIO_CLKOUT3_A_MARK,
1696 };
1698 /* CLKOUT3 */
1700 };
1702 AUDIO_CLKOUT3_B_MARK,
1703 };
1705 /* - EtherAVB --------------------------------------------------------------- */
1707 /* AVB_LINK */
1709 };
1711 AVB_LINK_MARK,
1712 };
1714 /* AVB_MAGIC_ */
1716 };
1718 AVB_MAGIC_MARK,
1719 };
1721 /* AVB_PHY_INT */
1723 };
1725 AVB_PHY_INT_MARK,
1726 };
1728 /* AVB_MDC, AVB_MDIO */
1730 };
1733 };
1735 /*
1736 * AVB_TX_CTL, AVB_TXC, AVB_TD0,
1737 * AVB_TD1, AVB_TD2, AVB_TD3,
1738 * AVB_RX_CTL, AVB_RXC, AVB_RD0,
1739 * AVB_RD1, AVB_RD2, AVB_RD3,
1740 * AVB_TXCREFCLK
1741 */
1748 };
1754 AVB_TXCREFCLK_MARK,
1755 };
1757 /* AVB_AVTP_PPS */
1759 };
1761 AVB_AVTP_PPS_MARK,
1762 };
1764 /* AVB_AVTP_MATCH_A */
1766 };
1768 AVB_AVTP_MATCH_A_MARK,
1769 };
1771 /* AVB_AVTP_CAPTURE_A */
1773 };
1775 AVB_AVTP_CAPTURE_A_MARK,
1776 };
1778 /* AVB_AVTP_MATCH_B */
1780 };
1782 AVB_AVTP_MATCH_B_MARK,
1783 };
1785 /* AVB_AVTP_CAPTURE_B */
1787 };
1789 AVB_AVTP_CAPTURE_B_MARK,
1790 };
1792 /* - CAN ------------------------------------------------------------------ */
1794 /* TX, RX */
1796 };
1799 };
1801 /* TX, RX */
1803 };
1806 };
1808 /* TX, RX */
1810 };
1813 };
1815 /* - CAN Clock -------------------------------------------------------------- */
1817 /* CLK */
1819 };
1821 CAN_CLK_MARK,
1822 };
1824 /* - CAN FD --------------------------------------------------------------- */
1826 /* TX, RX */
1828 };
1831 };
1833 /* TX, RX */
1835 };
1838 };
1840 /* TX, RX */
1842 };
1845 };
1847 /* - DRIF0 --------------------------------------------------------------- */
1849 /* CLK, SYNC */
1851 };
1854 };
1856 /* D0 */
1858 };
1860 RIF0_D0_A_MARK,
1861 };
1863 /* D1 */
1865 };
1867 RIF0_D1_A_MARK,
1868 };
1870 /* CLK, SYNC */
1872 };
1875 };
1877 /* D0 */
1879 };
1881 RIF0_D0_B_MARK,
1882 };
1884 /* D1 */
1886 };
1888 RIF0_D1_B_MARK,
1889 };
1891 /* CLK, SYNC */
1893 };
1896 };
1898 /* D0 */
1900 };
1902 RIF0_D0_C_MARK,
1903 };
1905 /* D1 */
1907 };
1909 RIF0_D1_C_MARK,
1910 };
1911 /* - DRIF1 --------------------------------------------------------------- */
1913 /* CLK, SYNC */
1915 };
1918 };
1920 /* D0 */
1922 };
1924 RIF1_D0_A_MARK,
1925 };
1927 /* D1 */
1929 };
1931 RIF1_D1_A_MARK,
1932 };
1934 /* CLK, SYNC */
1936 };
1939 };
1941 /* D0 */
1943 };
1945 RIF1_D0_B_MARK,
1946 };
1948 /* D1 */
1950 };
1952 RIF1_D1_B_MARK,
1953 };
1955 /* CLK, SYNC */
1957 };
1960 };
1962 /* D0 */
1964 };
1966 RIF1_D0_C_MARK,
1967 };
1969 /* D1 */
1971 };
1973 RIF1_D1_C_MARK,
1974 };
1975 /* - DRIF2 --------------------------------------------------------------- */
1977 /* CLK, SYNC */
1979 };
1982 };
1984 /* D0 */
1986 };
1988 RIF2_D0_A_MARK,
1989 };
1991 /* D1 */
1993 };
1995 RIF2_D1_A_MARK,
1996 };
1998 /* CLK, SYNC */
2000 };
2003 };
2005 /* D0 */
2007 };
2009 RIF2_D0_B_MARK,
2010 };
2012 /* D1 */
2014 };
2016 RIF2_D1_B_MARK,
2017 };
2018 /* - DRIF3 --------------------------------------------------------------- */
2020 /* CLK, SYNC */
2022 };
2025 };
2027 /* D0 */
2029 };
2031 RIF3_D0_A_MARK,
2032 };
2034 /* D1 */
2036 };
2038 RIF3_D1_A_MARK,
2039 };
2041 /* CLK, SYNC */
2043 };
2046 };
2048 /* D0 */
2050 };
2052 RIF3_D0_B_MARK,
2053 };
2055 /* D1 */
2057 };
2059 RIF3_D1_B_MARK,
2060 };
2062 /* - DU --------------------------------------------------------------------- */
2064 /* R[7:2], G[7:2], B[7:2] */
2071 };
2079 };
2081 /* R[7:0], G[7:0], B[7:0] */
2091 };
2099 };
2101 /* CLKOUT */
2103 };
2105 DU_DOTCLKOUT0_MARK
2106 };
2108 /* CLKOUT */
2110 };
2112 DU_DOTCLKOUT1_MARK
2113 };
2115 /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
2117 };
2119 DU_EXVSYNC_DU_VSYNC_MARK, DU_EXHSYNC_DU_HSYNC_MARK
2120 };
2122 /* EXDISP/EXODDF/EXCDE */
2124 };
2126 DU_EXODDF_DU_ODDF_DISP_CDE_MARK,
2127 };
2129 /* CDE */
2131 };
2133 DU_CDE_MARK,
2134 };
2136 /* DISP */
2138 };
2140 DU_DISP_MARK,
2141 };
2143 /* - HDMI ------------------------------------------------------------------- */
2145 /* HDMI0_CEC */
2147 };
2149 HDMI0_CEC_MARK,
2150 };
2152 /* - HSCIF0 ----------------------------------------------------------------- */
2154 /* RX, TX */
2156 };
2159 };
2161 /* SCK */
2163 };
2165 HSCK0_MARK,
2166 };
2168 /* RTS, CTS */
2170 };
2173 };
2174 /* - HSCIF1 ----------------------------------------------------------------- */
2176 /* RX, TX */
2178 };
2181 };
2183 /* SCK */
2185 };
2187 HSCK1_A_MARK,
2188 };
2190 /* RTS, CTS */
2192 };
2195 };
2198 /* RX, TX */
2200 };
2203 };
2205 /* SCK */
2207 };
2209 HSCK1_B_MARK,
2210 };
2212 /* RTS, CTS */
2214 };
2217 };
2218 /* - HSCIF2 ----------------------------------------------------------------- */
2220 /* RX, TX */
2222 };
2225 };
2227 /* SCK */
2229 };
2231 HSCK2_A_MARK,
2232 };
2234 /* RTS, CTS */
2236 };
2239 };
2242 /* RX, TX */
2244 };
2247 };
2249 /* SCK */
2251 };
2253 HSCK2_B_MARK,
2254 };
2256 /* RTS, CTS */
2258 };
2261 };
2264 /* RX, TX */
2266 };
2269 };
2271 /* SCK */
2273 };
2275 HSCK2_C_MARK,
2276 };
2278 /* RTS, CTS */
2280 };
2283 };
2284 /* - HSCIF3 ----------------------------------------------------------------- */
2286 /* RX, TX */
2288 };
2291 };
2293 /* SCK */
2295 };
2297 HSCK3_MARK,
2298 };
2300 /* RTS, CTS */
2302 };
2305 };
2308 /* RX, TX */
2310 };
2313 };
2315 /* RX, TX */
2317 };
2320 };
2322 /* RX, TX */
2324 };
2327 };
2328 /* - HSCIF4 ----------------------------------------------------------------- */
2330 /* RX, TX */
2332 };
2335 };
2337 /* SCK */
2339 };
2341 HSCK4_MARK,
2342 };
2344 /* RTS, CTS */
2346 };
2349 };
2352 /* RX, TX */
2354 };
2357 };
2359 /* - I2C -------------------------------------------------------------------- */
2361 /* SCL, SDA */
2363 };
2367 };
2370 /* SDA, SCL */
2372 };
2375 };
2377 /* SDA, SCL */
2379 };
2382 };
2384 /* SDA, SCL */
2386 };
2389 };
2391 /* SDA, SCL */
2393 };
2396 };
2399 /* SCL, SDA */
2401 };
2405 };
2408 /* SCL, SDA */
2410 };
2414 };
2417 /* SDA, SCL */
2419 };
2422 };
2424 /* SDA, SCL */
2426 };
2429 };
2431 /* SDA, SCL */
2433 };
2436 };
2438 /* - INTC-EX ---------------------------------------------------------------- */
2440 /* IRQ0 */
2442 };
2444 IRQ0_MARK,
2445 };
2447 /* IRQ1 */
2449 };
2451 IRQ1_MARK,
2452 };
2454 /* IRQ2 */
2456 };
2458 IRQ2_MARK,
2459 };
2461 /* IRQ3 */
2463 };
2465 IRQ3_MARK,
2466 };
2468 /* IRQ4 */
2470 };
2472 IRQ4_MARK,
2473 };
2475 /* IRQ5 */
2477 };
2479 IRQ5_MARK,
2480 };
2482 /* - MSIOF0 ----------------------------------------------------------------- */
2484 /* SCK */
2486 };
2488 MSIOF0_SCK_MARK,
2489 };
2491 /* SYNC */
2493 };
2495 MSIOF0_SYNC_MARK,
2496 };
2498 /* SS1 */
2500 };
2502 MSIOF0_SS1_MARK,
2503 };
2505 /* SS2 */
2507 };
2509 MSIOF0_SS2_MARK,
2510 };
2512 /* TXD */
2514 };
2516 MSIOF0_TXD_MARK,
2517 };
2519 /* RXD */
2521 };
2523 MSIOF0_RXD_MARK,
2524 };
2525 /* - MSIOF1 ----------------------------------------------------------------- */
2527 /* SCK */
2529 };
2531 MSIOF1_SCK_A_MARK,
2532 };
2534 /* SYNC */
2536 };
2538 MSIOF1_SYNC_A_MARK,
2539 };
2541 /* SS1 */
2543 };
2545 MSIOF1_SS1_A_MARK,
2546 };
2548 /* SS2 */
2550 };
2552 MSIOF1_SS2_A_MARK,
2553 };
2555 /* TXD */
2557 };
2559 MSIOF1_TXD_A_MARK,
2560 };
2562 /* RXD */
2564 };
2566 MSIOF1_RXD_A_MARK,
2567 };
2569 /* SCK */
2571 };
2573 MSIOF1_SCK_B_MARK,
2574 };
2576 /* SYNC */
2578 };
2580 MSIOF1_SYNC_B_MARK,
2581 };
2583 /* SS1 */
2585 };
2587 MSIOF1_SS1_B_MARK,
2588 };
2590 /* SS2 */
2592 };
2594 MSIOF1_SS2_B_MARK,
2595 };
2597 /* TXD */
2599 };
2601 MSIOF1_TXD_B_MARK,
2602 };
2604 /* RXD */
2606 };
2608 MSIOF1_RXD_B_MARK,
2609 };
2611 /* SCK */
2613 };
2615 MSIOF1_SCK_C_MARK,
2616 };
2618 /* SYNC */
2620 };
2622 MSIOF1_SYNC_C_MARK,
2623 };
2625 /* SS1 */
2627 };
2629 MSIOF1_SS1_C_MARK,
2630 };
2632 /* SS2 */
2634 };
2636 MSIOF1_SS2_C_MARK,
2637 };
2639 /* TXD */
2641 };
2643 MSIOF1_TXD_C_MARK,
2644 };
2646 /* RXD */
2648 };
2650 MSIOF1_RXD_C_MARK,
2651 };
2653 /* SCK */
2655 };
2657 MSIOF1_SCK_D_MARK,
2658 };
2660 /* SYNC */
2662 };
2664 MSIOF1_SYNC_D_MARK,
2665 };
2667 /* SS1 */
2669 };
2671 MSIOF1_SS1_D_MARK,
2672 };
2674 /* SS2 */
2676 };
2678 MSIOF1_SS2_D_MARK,
2679 };
2681 /* TXD */
2683 };
2685 MSIOF1_TXD_D_MARK,
2686 };
2688 /* RXD */
2690 };
2692 MSIOF1_RXD_D_MARK,
2693 };
2695 /* SCK */
2697 };
2699 MSIOF1_SCK_E_MARK,
2700 };
2702 /* SYNC */
2704 };
2706 MSIOF1_SYNC_E_MARK,
2707 };
2709 /* SS1 */
2711 };
2713 MSIOF1_SS1_E_MARK,
2714 };
2716 /* SS2 */
2718 };
2720 MSIOF1_SS2_E_MARK,
2721 };
2723 /* TXD */
2725 };
2727 MSIOF1_TXD_E_MARK,
2728 };
2730 /* RXD */
2732 };
2734 MSIOF1_RXD_E_MARK,
2735 };
2737 /* SCK */
2739 };
2741 MSIOF1_SCK_F_MARK,
2742 };
2744 /* SYNC */
2746 };
2748 MSIOF1_SYNC_F_MARK,
2749 };
2751 /* SS1 */
2753 };
2755 MSIOF1_SS1_F_MARK,
2756 };
2758 /* SS2 */
2760 };
2762 MSIOF1_SS2_F_MARK,
2763 };
2765 /* TXD */
2767 };
2769 MSIOF1_TXD_F_MARK,
2770 };
2772 /* RXD */
2774 };
2776 MSIOF1_RXD_F_MARK,
2777 };
2779 /* SCK */
2781 };
2783 MSIOF1_SCK_G_MARK,
2784 };
2786 /* SYNC */
2788 };
2790 MSIOF1_SYNC_G_MARK,
2791 };
2793 /* SS1 */
2795 };
2797 MSIOF1_SS1_G_MARK,
2798 };
2800 /* SS2 */
2802 };
2804 MSIOF1_SS2_G_MARK,
2805 };
2807 /* TXD */
2809 };
2811 MSIOF1_TXD_G_MARK,
2812 };
2814 /* RXD */
2816 };
2818 MSIOF1_RXD_G_MARK,
2819 };
2820 /* - MSIOF2 ----------------------------------------------------------------- */
2822 /* SCK */
2824 };
2826 MSIOF2_SCK_A_MARK,
2827 };
2829 /* SYNC */
2831 };
2833 MSIOF2_SYNC_A_MARK,
2834 };
2836 /* SS1 */
2838 };
2840 MSIOF2_SS1_A_MARK,
2841 };
2843 /* SS2 */
2845 };
2847 MSIOF2_SS2_A_MARK,
2848 };
2850 /* TXD */
2852 };
2854 MSIOF2_TXD_A_MARK,
2855 };
2857 /* RXD */
2859 };
2861 MSIOF2_RXD_A_MARK,
2862 };
2864 /* SCK */
2866 };
2868 MSIOF2_SCK_B_MARK,
2869 };
2871 /* SYNC */
2873 };
2875 MSIOF2_SYNC_B_MARK,
2876 };
2878 /* SS1 */
2880 };
2882 MSIOF2_SS1_B_MARK,
2883 };
2885 /* SS2 */
2887 };
2889 MSIOF2_SS2_B_MARK,
2890 };
2892 /* TXD */
2894 };
2896 MSIOF2_TXD_B_MARK,
2897 };
2899 /* RXD */
2901 };
2903 MSIOF2_RXD_B_MARK,
2904 };
2906 /* SCK */
2908 };
2910 MSIOF2_SCK_C_MARK,
2911 };
2913 /* SYNC */
2915 };
2917 MSIOF2_SYNC_C_MARK,
2918 };
2920 /* SS1 */
2922 };
2924 MSIOF2_SS1_C_MARK,
2925 };
2927 /* SS2 */
2929 };
2931 MSIOF2_SS2_C_MARK,
2932 };
2934 /* TXD */
2936 };
2938 MSIOF2_TXD_C_MARK,
2939 };
2941 /* RXD */
2943 };
2945 MSIOF2_RXD_C_MARK,
2946 };
2948 /* SCK */
2950 };
2952 MSIOF2_SCK_D_MARK,
2953 };
2955 /* SYNC */
2957 };
2959 MSIOF2_SYNC_D_MARK,
2960 };
2962 /* SS1 */
2964 };
2966 MSIOF2_SS1_D_MARK,
2967 };
2969 /* SS2 */
2971 };
2973 MSIOF2_SS2_D_MARK,
2974 };
2976 /* TXD */
2978 };
2980 MSIOF2_TXD_D_MARK,
2981 };
2983 /* RXD */
2985 };
2987 MSIOF2_RXD_D_MARK,
2988 };
2989 /* - MSIOF3 ----------------------------------------------------------------- */
2991 /* SCK */
2993 };
2995 MSIOF3_SCK_A_MARK,
2996 };
2998 /* SYNC */
3000 };
3002 MSIOF3_SYNC_A_MARK,
3003 };
3005 /* SS1 */
3007 };
3009 MSIOF3_SS1_A_MARK,
3010 };
3012 /* SS2 */
3014 };
3016 MSIOF3_SS2_A_MARK,
3017 };
3019 /* TXD */
3021 };
3023 MSIOF3_TXD_A_MARK,
3024 };
3026 /* RXD */
3028 };
3030 MSIOF3_RXD_A_MARK,
3031 };
3033 /* SCK */
3035 };
3037 MSIOF3_SCK_B_MARK,
3038 };
3040 /* SYNC */
3042 };
3044 MSIOF3_SYNC_B_MARK,
3045 };
3047 /* SS1 */
3049 };
3051 MSIOF3_SS1_B_MARK,
3052 };
3054 /* SS2 */
3056 };
3058 MSIOF3_SS2_B_MARK,
3059 };
3061 /* TXD */
3063 };
3065 MSIOF3_TXD_B_MARK,
3066 };
3068 /* RXD */
3070 };
3072 MSIOF3_RXD_B_MARK,
3073 };
3075 /* SCK */
3077 };
3079 MSIOF3_SCK_C_MARK,
3080 };
3082 /* SYNC */
3084 };
3086 MSIOF3_SYNC_C_MARK,
3087 };
3089 /* TXD */
3091 };
3093 MSIOF3_TXD_C_MARK,
3094 };
3096 /* RXD */
3098 };
3100 MSIOF3_RXD_C_MARK,
3101 };
3103 /* SCK */
3105 };
3107 MSIOF3_SCK_D_MARK,
3108 };
3110 /* SYNC */
3112 };
3114 MSIOF3_SYNC_D_MARK,
3115 };
3117 /* SS1 */
3119 };
3121 MSIOF3_SS1_D_MARK,
3122 };
3124 /* TXD */
3126 };
3128 MSIOF3_TXD_D_MARK,
3129 };
3131 /* RXD */
3133 };
3135 MSIOF3_RXD_D_MARK,
3136 };
3139 /* SCK */
3141 };
3143 MSIOF3_SCK_E_MARK,
3144 };
3146 /* SYNC */
3148 };
3150 MSIOF3_SYNC_E_MARK,
3151 };
3153 /* SS1 */
3155 };
3157 MSIOF3_SS1_E_MARK,
3158 };
3160 /* SS2 */
3162 };
3164 MSIOF3_SS2_E_MARK,
3165 };
3167 /* TXD */
3169 };
3171 MSIOF3_TXD_E_MARK,
3172 };
3174 /* RXD */
3176 };
3178 MSIOF3_RXD_E_MARK,
3179 };
3181 /* - PWM0 --------------------------------------------------------------------*/
3183 /* PWM */
3185 };
3187 PWM0_MARK,
3188 };
3189 /* - PWM1 --------------------------------------------------------------------*/
3191 /* PWM */
3193 };
3195 PWM1_A_MARK,
3196 };
3198 /* PWM */
3200 };
3202 PWM1_B_MARK,
3203 };
3204 /* - PWM2 --------------------------------------------------------------------*/
3206 /* PWM */
3208 };
3210 PWM2_A_MARK,
3211 };
3213 /* PWM */
3215 };
3217 PWM2_B_MARK,
3218 };
3219 /* - PWM3 --------------------------------------------------------------------*/
3221 /* PWM */
3223 };
3225 PWM3_A_MARK,
3226 };
3228 /* PWM */
3230 };
3232 PWM3_B_MARK,
3233 };
3234 /* - PWM4 --------------------------------------------------------------------*/
3236 /* PWM */
3238 };
3240 PWM4_A_MARK,
3241 };
3243 /* PWM */
3245 };
3247 PWM4_B_MARK,
3248 };
3249 /* - PWM5 --------------------------------------------------------------------*/
3251 /* PWM */
3253 };
3255 PWM5_A_MARK,
3256 };
3258 /* PWM */
3260 };
3262 PWM5_B_MARK,
3263 };
3264 /* - PWM6 --------------------------------------------------------------------*/
3266 /* PWM */
3268 };
3270 PWM6_A_MARK,
3271 };
3273 /* PWM */
3275 };
3277 PWM6_B_MARK,
3278 };
3280 /* - SCIF0 ------------------------------------------------------------------ */
3282 /* RX, TX */
3284 };
3287 };
3289 /* SCK */
3291 };
3293 SCK0_MARK,
3294 };
3296 /* RTS, CTS */
3298 };
3301 };
3302 /* - SCIF1 ------------------------------------------------------------------ */
3304 /* RX, TX */
3306 };
3309 };
3311 /* SCK */
3313 };
3315 SCK1_MARK,
3316 };
3318 /* RTS, CTS */
3320 };
3323 };
3326 /* RX, TX */
3328 };
3331 };
3332 /* - SCIF2 ------------------------------------------------------------------ */
3334 /* RX, TX */
3336 };
3339 };
3341 /* SCK */
3343 };
3345 SCK2_MARK,
3346 };
3348 /* RX, TX */
3350 };
3353 };
3354 /* - SCIF3 ------------------------------------------------------------------ */
3356 /* RX, TX */
3358 };
3361 };
3363 /* SCK */
3365 };
3367 SCK3_MARK,
3368 };
3370 /* RTS, CTS */
3372 };
3375 };
3377 /* RX, TX */
3379 };
3382 };
3383 /* - SCIF4 ------------------------------------------------------------------ */
3385 /* RX, TX */
3387 };
3390 };
3392 /* SCK */
3394 };
3396 SCK4_A_MARK,
3397 };
3399 /* RTS, CTS */
3401 };
3404 };
3406 /* RX, TX */
3408 };
3411 };
3413 /* SCK */
3415 };
3417 SCK4_B_MARK,
3418 };
3420 /* RTS, CTS */
3422 };
3425 };
3427 /* RX, TX */
3429 };
3432 };
3434 /* SCK */
3436 };
3438 SCK4_C_MARK,
3439 };
3441 /* RTS, CTS */
3443 };
3446 };
3447 /* - SCIF5 ------------------------------------------------------------------ */
3449 /* RX, TX */
3451 };
3454 };
3456 /* SCK */
3458 };
3460 SCK5_A_MARK,
3461 };
3464 /* RX, TX */
3466 };
3469 };
3471 /* SCK */
3473 };
3475 SCK5_B_MARK,
3476 };
3478 /* - SCIF Clock ------------------------------------------------------------- */
3480 /* SCIF_CLK */
3482 };
3484 SCIF_CLK_A_MARK,
3485 };
3487 /* SCIF_CLK */
3489 };
3491 SCIF_CLK_B_MARK,
3492 };
3494 /* - SDHI0 ------------------------------------------------------------------ */
3496 /* D0 */
3498 };
3500 SD0_DAT0_MARK,
3501 };
3503 /* D[0:3] */
3506 };
3510 };
3512 /* CLK, CMD */
3514 };
3517 };
3519 /* CD */
3521 };
3523 SD0_CD_MARK,
3524 };
3526 /* WP */
3528 };
3530 SD0_WP_MARK,
3531 };
3532 /* - SDHI1 ------------------------------------------------------------------ */
3534 /* D0 */
3536 };
3538 SD1_DAT0_MARK,
3539 };
3541 /* D[0:3] */
3544 };
3548 };
3550 /* CLK, CMD */
3552 };
3555 };
3557 /* CD */
3559 };
3561 SD1_CD_MARK,
3562 };
3564 /* WP */
3566 };
3568 SD1_WP_MARK,
3569 };
3570 /* - SDHI2 ------------------------------------------------------------------ */
3572 /* D0 */
3574 };
3576 SD2_DAT0_MARK,
3577 };
3579 /* D[0:3] */
3582 };
3586 };
3588 /* D[0:7] */
3593 };
3599 };
3601 /* CLK, CMD */
3603 };
3606 };
3608 /* CD */
3610 };
3612 SD2_CD_A_MARK,
3613 };
3615 /* CD */
3617 };
3619 SD2_CD_B_MARK,
3620 };
3622 /* WP */
3624 };
3626 SD2_WP_A_MARK,
3627 };
3629 /* WP */
3631 };
3633 SD2_WP_B_MARK,
3634 };
3636 /* DS */
3638 };
3640 SD2_DS_MARK,
3641 };
3642 /* - SDHI3 ------------------------------------------------------------------ */
3644 /* D0 */
3646 };
3648 SD3_DAT0_MARK,
3649 };
3651 /* D[0:3] */
3654 };
3658 };
3660 /* D[0:7] */
3665 };
3671 };
3673 /* CLK, CMD */
3675 };
3678 };
3680 /* CD */
3682 };
3684 SD3_CD_MARK,
3685 };
3687 /* WP */
3689 };
3691 SD3_WP_MARK,
3692 };
3694 /* DS */
3696 };
3698 SD3_DS_MARK,
3699 };
3701 /* - SSI -------------------------------------------------------------------- */
3703 /* SDATA */
3705 };
3707 SSI_SDATA0_MARK,
3708 };
3710 /* SCK, WS */
3712 };
3715 };
3717 /* SDATA */
3719 };
3721 SSI_SDATA1_A_MARK,
3722 };
3724 /* SDATA */
3726 };
3728 SSI_SDATA1_B_MARK,
3729 };
3731 /* SCK, WS */
3733 };
3736 };
3738 /* SCK, WS */
3740 };
3743 };
3745 /* SDATA */
3747 };
3749 SSI_SDATA2_A_MARK,
3750 };
3752 /* SDATA */
3754 };
3756 SSI_SDATA2_B_MARK,
3757 };
3759 /* SCK, WS */
3761 };
3764 };
3766 /* SCK, WS */
3768 };
3771 };
3773 /* SDATA */
3775 };
3777 SSI_SDATA3_MARK,
3778 };
3780 /* SCK, WS */
3782 };
3785 };
3787 /* SDATA */
3789 };
3791 SSI_SDATA4_MARK,
3792 };
3794 /* SCK, WS */
3796 };
3799 };
3801 /* SDATA */
3803 };
3805 SSI_SDATA5_MARK,
3806 };
3808 /* SCK, WS */
3810 };
3813 };
3815 /* SDATA */
3817 };
3819 SSI_SDATA6_MARK,
3820 };
3822 /* SCK, WS */
3824 };
3827 };
3829 /* SDATA */
3831 };
3833 SSI_SDATA7_MARK,
3834 };
3836 /* SCK, WS */
3838 };
3841 };
3843 /* SDATA */
3845 };
3847 SSI_SDATA8_MARK,
3848 };
3850 /* SDATA */
3852 };
3854 SSI_SDATA9_A_MARK,
3855 };
3857 /* SDATA */
3859 };
3861 SSI_SDATA9_B_MARK,
3862 };
3864 /* SCK, WS */
3866 };
3869 };
3871 /* SCK, WS */
3873 };
3876 };
3878 /* - TMU -------------------------------------------------------------------- */
3880 /* TCLK */
3882 };
3884 TCLK1_A_MARK,
3885 };
3887 /* TCLK */
3889 };
3891 TCLK1_B_MARK,
3892 };
3894 /* TCLK */
3896 };
3898 TCLK2_A_MARK,
3899 };
3901 /* TCLK */
3903 };
3905 TCLK2_B_MARK,
3906 };
3908 /* - USB0 ------------------------------------------------------------------- */
3910 /* PWEN, OVC */
3912 };
3915 };
3916 /* - USB1 ------------------------------------------------------------------- */
3918 /* PWEN, OVC */
3920 };
3923 };
3925 /* - USB30 ------------------------------------------------------------------ */
3927 /* PWEN, OVC */
3929 };
3932 };
3934 /* - VIN4 ------------------------------------------------------------------- */
3945 };
3956 };
3967 };
3978 };
3993 },
3994 };
4009 },
4010 };
4025 },
4026 };
4041 },
4042 };
4044 /* HSYNC#, VSYNC# */
4046 };
4049 };
4051 /* FIELD */
4053 };
4055 VI4_FIELD_MARK,
4056 };
4058 /* CLKENB */
4060 };
4062 VI4_CLKENB_MARK,
4063 };
4065 /* CLK */
4067 };
4069 VI4_CLK_MARK,
4070 };
4072 /* - VIN5 ------------------------------------------------------------------- */
4083 },
4084 };
4095 },
4096 };
4098 /* HSYNC#, VSYNC# */
4100 };
4103 };
4106 };
4108 /* FIELD */
4109 VI5_FIELD_MARK,
4110 };
4113 };
4115 /* CLKENB */
4116 VI5_CLKENB_MARK,
4117 };
4120 };
4122 /* CLK */
4123 VI5_CLK_MARK,
4124 };
4441 },
4476 }
4477 };
4497 };
4511 };
4516 };
4520 };
4524 };
4529 };
4533 };
4545 };
4557 };
4566 };
4575 };
4586 };
4590 };
4596 };
4605 };
4617 };
4626 };
4633 };
4637 };
4642 };
4647 };
4651 };
4655 };
4661 };
4670 };
4679 };
4724 };
4751 };
4781 };
4785 };
4790 };
4795 };
4800 };
4805 };
4810 };
4815 };
4821 };
4828 };
4834 };
4841 };
4853 };
4860 };
4865 };
4873 };
4881 };
4893 };
4903 };
4931 };
4938 };
4942 };
4946 };
4950 };
4971 };
4982 };
5037 },
5045 }
5046 };
5049 #define F_(x, y) FN_##y
5050 #define FM(x) FN_##x
5084 },
5118 },
5152 },
5186 },
5220 },
5254 },
5288 },
5322 },
5323 #undef F_
5324 #undef FM
5326 #define F_(x, y) x,
5327 #define FM(x) FN_##x,
5329 IP0_31_28
5330 IP0_27_24
5331 IP0_23_20
5332 IP0_19_16
5333 IP0_15_12
5334 IP0_11_8
5335 IP0_7_4
5336 IP0_3_0 }
5337 },
5339 IP1_31_28
5340 IP1_27_24
5341 IP1_23_20
5342 IP1_19_16
5343 IP1_15_12
5344 IP1_11_8
5345 IP1_7_4
5346 IP1_3_0 }
5347 },
5349 IP2_31_28
5350 IP2_27_24
5351 IP2_23_20
5352 IP2_19_16
5353 IP2_15_12
5354 IP2_11_8
5355 IP2_7_4
5356 IP2_3_0 }
5357 },
5359 IP3_31_28
5360 IP3_27_24
5361 IP3_23_20
5362 IP3_19_16
5363 IP3_15_12
5364 IP3_11_8
5365 IP3_7_4
5366 IP3_3_0 }
5367 },
5369 IP4_31_28
5370 IP4_27_24
5371 IP4_23_20
5372 IP4_19_16
5373 IP4_15_12
5374 IP4_11_8
5375 IP4_7_4
5376 IP4_3_0 }
5377 },
5379 IP5_31_28
5380 IP5_27_24
5381 IP5_23_20
5382 IP5_19_16
5383 IP5_15_12
5384 IP5_11_8
5385 IP5_7_4
5386 IP5_3_0 }
5387 },
5389 IP6_31_28
5390 IP6_27_24
5391 IP6_23_20
5392 IP6_19_16
5393 IP6_15_12
5394 IP6_11_8
5395 IP6_7_4
5396 IP6_3_0 }
5397 },
5399 IP7_31_28
5400 IP7_27_24
5401 IP7_23_20
5402 IP7_19_16
5404 IP7_11_8
5405 IP7_7_4
5406 IP7_3_0 }
5407 },
5409 IP8_31_28
5410 IP8_27_24
5411 IP8_23_20
5412 IP8_19_16
5413 IP8_15_12
5414 IP8_11_8
5415 IP8_7_4
5416 IP8_3_0 }
5417 },
5419 IP9_31_28
5420 IP9_27_24
5421 IP9_23_20
5422 IP9_19_16
5423 IP9_15_12
5424 IP9_11_8
5425 IP9_7_4
5426 IP9_3_0 }
5427 },
5429 IP10_31_28
5430 IP10_27_24
5431 IP10_23_20
5432 IP10_19_16
5433 IP10_15_12
5434 IP10_11_8
5435 IP10_7_4
5436 IP10_3_0 }
5437 },
5439 IP11_31_28
5440 IP11_27_24
5441 IP11_23_20
5442 IP11_19_16
5443 IP11_15_12
5444 IP11_11_8
5445 IP11_7_4
5446 IP11_3_0 }
5447 },
5449 IP12_31_28
5450 IP12_27_24
5451 IP12_23_20
5452 IP12_19_16
5453 IP12_15_12
5454 IP12_11_8
5455 IP12_7_4
5456 IP12_3_0 }
5457 },
5459 IP13_31_28
5460 IP13_27_24
5461 IP13_23_20
5462 IP13_19_16
5463 IP13_15_12
5464 IP13_11_8
5465 IP13_7_4
5466 IP13_3_0 }
5467 },
5469 IP14_31_28
5470 IP14_27_24
5471 IP14_23_20
5472 IP14_19_16
5473 IP14_15_12
5474 IP14_11_8
5475 IP14_7_4
5476 IP14_3_0 }
5477 },
5479 IP15_31_28
5480 IP15_27_24
5481 IP15_23_20
5482 IP15_19_16
5483 IP15_15_12
5484 IP15_11_8
5485 IP15_7_4
5486 IP15_3_0 }
5487 },
5489 IP16_31_28
5490 IP16_27_24
5491 IP16_23_20
5492 IP16_19_16
5493 IP16_15_12
5494 IP16_11_8
5495 IP16_7_4
5496 IP16_3_0 }
5497 },
5499 IP17_31_28
5500 IP17_27_24
5501 IP17_23_20
5502 IP17_19_16
5503 IP17_15_12
5504 IP17_11_8
5505 IP17_7_4
5506 IP17_3_0 }
5507 },
5515 IP18_7_4
5516 IP18_3_0 }
5517 },
5518 #undef F_
5519 #undef FM
5521 #define F_(x, y) x,
5522 #define FM(x) FN_##x,
5526 MOD_SEL0_31_30_29
5527 MOD_SEL0_28_27
5528 MOD_SEL0_26_25_24
5529 MOD_SEL0_23
5530 MOD_SEL0_22
5531 MOD_SEL0_21
5532 MOD_SEL0_20
5533 MOD_SEL0_19
5534 MOD_SEL0_18_17
5535 MOD_SEL0_16
5537 MOD_SEL0_14_13
5538 MOD_SEL0_12
5539 MOD_SEL0_11
5540 MOD_SEL0_10
5541 MOD_SEL0_9_8
5542 MOD_SEL0_7_6
5543 MOD_SEL0_5
5544 MOD_SEL0_4_3
5545 /* RESERVED 2, 1, 0 */
5547 },
5551 MOD_SEL1_31_30
5552 MOD_SEL1_29_28_27
5553 MOD_SEL1_26
5554 MOD_SEL1_25_24
5555 MOD_SEL1_23_22_21
5556 MOD_SEL1_20
5557 MOD_SEL1_19
5558 MOD_SEL1_18_17
5559 MOD_SEL1_16
5560 MOD_SEL1_15_14
5561 MOD_SEL1_13
5562 MOD_SEL1_12
5563 MOD_SEL1_11
5564 MOD_SEL1_10
5565 MOD_SEL1_9
5567 MOD_SEL1_6
5568 MOD_SEL1_5
5569 MOD_SEL1_4
5570 MOD_SEL1_3
5571 MOD_SEL1_2
5572 MOD_SEL1_1
5573 MOD_SEL1_0 }
5574 },
5578 MOD_SEL2_31
5579 MOD_SEL2_30
5580 MOD_SEL2_29
5581 MOD_SEL2_28_27
5582 MOD_SEL2_26
5583 MOD_SEL2_25_24_23
5584 MOD_SEL2_22
5585 MOD_SEL2_21
5586 MOD_SEL2_20
5587 MOD_SEL2_19
5588 MOD_SEL2_18
5589 MOD_SEL2_17
5590 /* RESERVED 16 */
5592 /* RESERVED 15, 14, 13, 12 */
5595 /* RESERVED 11, 10, 9, 8 */
5598 /* RESERVED 7, 6, 5, 4 */
5601 /* RESERVED 3, 2, 1 */
5603 MOD_SEL2_0 }
5604 },
5605 { },
5606 };
5618 } },
5628 } },
5638 } },
5648 } },
5658 } },
5668 } },
5678 } },
5688 } },
5698 } },
5708 } },
5718 } },
5728 } },
5733 } },
5743 } },
5753 } },
5763 } },
5773 } },
5783 } },
5793 } },
5803 } },
5813 } },
5823 } },
5833 } },
5843 } },
5852 } },
5853 { },
5854 };
5857 POCCTRL,
5858 };
5863 };
5866 {
5878 }
5914 } },
5948 } },
5982 } },
6016 } },
6050 } },
6084 } },
6118 } },
6120 };
6124 {
6136 else
6138 }
6142 {
6161 }
6167 };
6169 #ifdef CONFIG_PINCTRL_PFC_R8A774A1
6191 };
6192 #endif
6194 #ifdef CONFIG_PINCTRL_PFC_R8A7796
6218 };
6219 #endif