| blob | 14c4b671cddf46a1f929a709c9795f6af5d0a439 |
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * R8A77965 processor support - PFC hardware block.
4 *
5 * Copyright (C) 2018 Jacopo Mondi <jacopo+renesas@jmondi.org>
6 * Copyright (C) 2016 Renesas Electronics Corp.
7 *
8 * This file is based on the drivers/pinctrl/sh-pfc/pfc-r8a7796.c
9 *
10 * R-Car Gen3 processor support - PFC hardware block.
11 *
12 * Copyright (C) 2015 Renesas Electronics Corporation
13 */
15 #include <linux/kernel.h>
20 #define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | \
21 SH_PFC_PIN_CFG_PULL_UP | \
22 SH_PFC_PIN_CFG_PULL_DOWN)
24 #define CPU_ALL_PORT(fn, sfx) \
25 PORT_GP_CFG_16(0, fn, sfx, CFG_FLAGS), \
26 PORT_GP_CFG_29(1, fn, sfx, CFG_FLAGS), \
27 PORT_GP_CFG_15(2, fn, sfx, CFG_FLAGS), \
28 PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
29 PORT_GP_CFG_1(3, 12, fn, sfx, CFG_FLAGS), \
30 PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS), \
31 PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS), \
32 PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS), \
33 PORT_GP_CFG_18(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
34 PORT_GP_CFG_26(5, fn, sfx, CFG_FLAGS), \
35 PORT_GP_CFG_32(6, fn, sfx, CFG_FLAGS), \
36 PORT_GP_CFG_4(7, fn, sfx, CFG_FLAGS)
37 /*
38 * F_() : just information
39 * FM() : macro for FN_xxx / xxx_MARK
40 */
42 /* GPSR0 */
43 #define GPSR0_15 F_(D15, IP7_11_8)
44 #define GPSR0_14 F_(D14, IP7_7_4)
45 #define GPSR0_13 F_(D13, IP7_3_0)
46 #define GPSR0_12 F_(D12, IP6_31_28)
47 #define GPSR0_11 F_(D11, IP6_27_24)
48 #define GPSR0_10 F_(D10, IP6_23_20)
49 #define GPSR0_9 F_(D9, IP6_19_16)
50 #define GPSR0_8 F_(D8, IP6_15_12)
51 #define GPSR0_7 F_(D7, IP6_11_8)
52 #define GPSR0_6 F_(D6, IP6_7_4)
53 #define GPSR0_5 F_(D5, IP6_3_0)
54 #define GPSR0_4 F_(D4, IP5_31_28)
55 #define GPSR0_3 F_(D3, IP5_27_24)
56 #define GPSR0_2 F_(D2, IP5_23_20)
57 #define GPSR0_1 F_(D1, IP5_19_16)
58 #define GPSR0_0 F_(D0, IP5_15_12)
60 /* GPSR1 */
61 #define GPSR1_28 FM(CLKOUT)
62 #define GPSR1_27 F_(EX_WAIT0_A, IP5_11_8)
63 #define GPSR1_26 F_(WE1_N, IP5_7_4)
64 #define GPSR1_25 F_(WE0_N, IP5_3_0)
65 #define GPSR1_24 F_(RD_WR_N, IP4_31_28)
66 #define GPSR1_23 F_(RD_N, IP4_27_24)
67 #define GPSR1_22 F_(BS_N, IP4_23_20)
68 #define GPSR1_21 F_(CS1_N, IP4_19_16)
69 #define GPSR1_20 F_(CS0_N, IP4_15_12)
70 #define GPSR1_19 F_(A19, IP4_11_8)
71 #define GPSR1_18 F_(A18, IP4_7_4)
72 #define GPSR1_17 F_(A17, IP4_3_0)
73 #define GPSR1_16 F_(A16, IP3_31_28)
74 #define GPSR1_15 F_(A15, IP3_27_24)
75 #define GPSR1_14 F_(A14, IP3_23_20)
76 #define GPSR1_13 F_(A13, IP3_19_16)
77 #define GPSR1_12 F_(A12, IP3_15_12)
78 #define GPSR1_11 F_(A11, IP3_11_8)
79 #define GPSR1_10 F_(A10, IP3_7_4)
80 #define GPSR1_9 F_(A9, IP3_3_0)
81 #define GPSR1_8 F_(A8, IP2_31_28)
82 #define GPSR1_7 F_(A7, IP2_27_24)
83 #define GPSR1_6 F_(A6, IP2_23_20)
84 #define GPSR1_5 F_(A5, IP2_19_16)
85 #define GPSR1_4 F_(A4, IP2_15_12)
86 #define GPSR1_3 F_(A3, IP2_11_8)
87 #define GPSR1_2 F_(A2, IP2_7_4)
88 #define GPSR1_1 F_(A1, IP2_3_0)
89 #define GPSR1_0 F_(A0, IP1_31_28)
91 /* GPSR2 */
92 #define GPSR2_14 F_(AVB_AVTP_CAPTURE_A, IP0_23_20)
93 #define GPSR2_13 F_(AVB_AVTP_MATCH_A, IP0_19_16)
94 #define GPSR2_12 F_(AVB_LINK, IP0_15_12)
95 #define GPSR2_11 F_(AVB_PHY_INT, IP0_11_8)
96 #define GPSR2_10 F_(AVB_MAGIC, IP0_7_4)
97 #define GPSR2_9 F_(AVB_MDC, IP0_3_0)
98 #define GPSR2_8 F_(PWM2_A, IP1_27_24)
99 #define GPSR2_7 F_(PWM1_A, IP1_23_20)
100 #define GPSR2_6 F_(PWM0, IP1_19_16)
101 #define GPSR2_5 F_(IRQ5, IP1_15_12)
102 #define GPSR2_4 F_(IRQ4, IP1_11_8)
103 #define GPSR2_3 F_(IRQ3, IP1_7_4)
104 #define GPSR2_2 F_(IRQ2, IP1_3_0)
105 #define GPSR2_1 F_(IRQ1, IP0_31_28)
106 #define GPSR2_0 F_(IRQ0, IP0_27_24)
108 /* GPSR3 */
109 #define GPSR3_15 F_(SD1_WP, IP11_23_20)
110 #define GPSR3_14 F_(SD1_CD, IP11_19_16)
111 #define GPSR3_13 F_(SD0_WP, IP11_15_12)
112 #define GPSR3_12 F_(SD0_CD, IP11_11_8)
113 #define GPSR3_11 F_(SD1_DAT3, IP8_31_28)
114 #define GPSR3_10 F_(SD1_DAT2, IP8_27_24)
115 #define GPSR3_9 F_(SD1_DAT1, IP8_23_20)
116 #define GPSR3_8 F_(SD1_DAT0, IP8_19_16)
117 #define GPSR3_7 F_(SD1_CMD, IP8_15_12)
118 #define GPSR3_6 F_(SD1_CLK, IP8_11_8)
119 #define GPSR3_5 F_(SD0_DAT3, IP8_7_4)
120 #define GPSR3_4 F_(SD0_DAT2, IP8_3_0)
121 #define GPSR3_3 F_(SD0_DAT1, IP7_31_28)
122 #define GPSR3_2 F_(SD0_DAT0, IP7_27_24)
123 #define GPSR3_1 F_(SD0_CMD, IP7_23_20)
124 #define GPSR3_0 F_(SD0_CLK, IP7_19_16)
126 /* GPSR4 */
127 #define GPSR4_17 F_(SD3_DS, IP11_7_4)
128 #define GPSR4_16 F_(SD3_DAT7, IP11_3_0)
129 #define GPSR4_15 F_(SD3_DAT6, IP10_31_28)
130 #define GPSR4_14 F_(SD3_DAT5, IP10_27_24)
131 #define GPSR4_13 F_(SD3_DAT4, IP10_23_20)
132 #define GPSR4_12 F_(SD3_DAT3, IP10_19_16)
133 #define GPSR4_11 F_(SD3_DAT2, IP10_15_12)
134 #define GPSR4_10 F_(SD3_DAT1, IP10_11_8)
135 #define GPSR4_9 F_(SD3_DAT0, IP10_7_4)
136 #define GPSR4_8 F_(SD3_CMD, IP10_3_0)
137 #define GPSR4_7 F_(SD3_CLK, IP9_31_28)
138 #define GPSR4_6 F_(SD2_DS, IP9_27_24)
139 #define GPSR4_5 F_(SD2_DAT3, IP9_23_20)
140 #define GPSR4_4 F_(SD2_DAT2, IP9_19_16)
141 #define GPSR4_3 F_(SD2_DAT1, IP9_15_12)
142 #define GPSR4_2 F_(SD2_DAT0, IP9_11_8)
143 #define GPSR4_1 F_(SD2_CMD, IP9_7_4)
144 #define GPSR4_0 F_(SD2_CLK, IP9_3_0)
146 /* GPSR5 */
147 #define GPSR5_25 F_(MLB_DAT, IP14_19_16)
148 #define GPSR5_24 F_(MLB_SIG, IP14_15_12)
149 #define GPSR5_23 F_(MLB_CLK, IP14_11_8)
150 #define GPSR5_22 FM(MSIOF0_RXD)
151 #define GPSR5_21 F_(MSIOF0_SS2, IP14_7_4)
152 #define GPSR5_20 FM(MSIOF0_TXD)
153 #define GPSR5_19 F_(MSIOF0_SS1, IP14_3_0)
154 #define GPSR5_18 F_(MSIOF0_SYNC, IP13_31_28)
155 #define GPSR5_17 FM(MSIOF0_SCK)
156 #define GPSR5_16 F_(HRTS0_N, IP13_27_24)
157 #define GPSR5_15 F_(HCTS0_N, IP13_23_20)
158 #define GPSR5_14 F_(HTX0, IP13_19_16)
159 #define GPSR5_13 F_(HRX0, IP13_15_12)
160 #define GPSR5_12 F_(HSCK0, IP13_11_8)
161 #define GPSR5_11 F_(RX2_A, IP13_7_4)
162 #define GPSR5_10 F_(TX2_A, IP13_3_0)
163 #define GPSR5_9 F_(SCK2, IP12_31_28)
164 #define GPSR5_8 F_(RTS1_N, IP12_27_24)
165 #define GPSR5_7 F_(CTS1_N, IP12_23_20)
166 #define GPSR5_6 F_(TX1_A, IP12_19_16)
167 #define GPSR5_5 F_(RX1_A, IP12_15_12)
168 #define GPSR5_4 F_(RTS0_N, IP12_11_8)
169 #define GPSR5_3 F_(CTS0_N, IP12_7_4)
170 #define GPSR5_2 F_(TX0, IP12_3_0)
171 #define GPSR5_1 F_(RX0, IP11_31_28)
172 #define GPSR5_0 F_(SCK0, IP11_27_24)
174 /* GPSR6 */
175 #define GPSR6_31 F_(GP6_31, IP18_7_4)
176 #define GPSR6_30 F_(GP6_30, IP18_3_0)
177 #define GPSR6_29 F_(USB30_OVC, IP17_31_28)
178 #define GPSR6_28 F_(USB30_PWEN, IP17_27_24)
179 #define GPSR6_27 F_(USB1_OVC, IP17_23_20)
180 #define GPSR6_26 F_(USB1_PWEN, IP17_19_16)
181 #define GPSR6_25 F_(USB0_OVC, IP17_15_12)
182 #define GPSR6_24 F_(USB0_PWEN, IP17_11_8)
183 #define GPSR6_23 F_(AUDIO_CLKB_B, IP17_7_4)
184 #define GPSR6_22 F_(AUDIO_CLKA_A, IP17_3_0)
185 #define GPSR6_21 F_(SSI_SDATA9_A, IP16_31_28)
186 #define GPSR6_20 F_(SSI_SDATA8, IP16_27_24)
187 #define GPSR6_19 F_(SSI_SDATA7, IP16_23_20)
188 #define GPSR6_18 F_(SSI_WS78, IP16_19_16)
189 #define GPSR6_17 F_(SSI_SCK78, IP16_15_12)
190 #define GPSR6_16 F_(SSI_SDATA6, IP16_11_8)
191 #define GPSR6_15 F_(SSI_WS6, IP16_7_4)
192 #define GPSR6_14 F_(SSI_SCK6, IP16_3_0)
193 #define GPSR6_13 FM(SSI_SDATA5)
194 #define GPSR6_12 FM(SSI_WS5)
195 #define GPSR6_11 FM(SSI_SCK5)
196 #define GPSR6_10 F_(SSI_SDATA4, IP15_31_28)
197 #define GPSR6_9 F_(SSI_WS4, IP15_27_24)
198 #define GPSR6_8 F_(SSI_SCK4, IP15_23_20)
199 #define GPSR6_7 F_(SSI_SDATA3, IP15_19_16)
200 #define GPSR6_6 F_(SSI_WS349, IP15_15_12)
201 #define GPSR6_5 F_(SSI_SCK349, IP15_11_8)
202 #define GPSR6_4 F_(SSI_SDATA2_A, IP15_7_4)
203 #define GPSR6_3 F_(SSI_SDATA1_A, IP15_3_0)
204 #define GPSR6_2 F_(SSI_SDATA0, IP14_31_28)
205 #define GPSR6_1 F_(SSI_WS01239, IP14_27_24)
206 #define GPSR6_0 F_(SSI_SCK01239, IP14_23_20)
208 /* GPSR7 */
209 #define GPSR7_3 FM(GP7_03)
210 #define GPSR7_2 FM(HDMI0_CEC)
211 #define GPSR7_1 FM(AVS2)
212 #define GPSR7_0 FM(AVS1)
215 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
216 #define IP0_3_0 FM(AVB_MDC) F_(0, 0) FM(MSIOF2_SS2_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
217 #define IP0_7_4 FM(AVB_MAGIC) F_(0, 0) FM(MSIOF2_SS1_C) FM(SCK4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
218 #define IP0_11_8 FM(AVB_PHY_INT) F_(0, 0) FM(MSIOF2_SYNC_C) FM(RX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
219 #define IP0_15_12 FM(AVB_LINK) F_(0, 0) FM(MSIOF2_SCK_C) FM(TX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
220 #define IP0_19_16 FM(AVB_AVTP_MATCH_A) F_(0, 0) FM(MSIOF2_RXD_C) FM(CTS4_N_A) F_(0, 0) FM(FSCLKST2_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
221 #define IP0_23_20 FM(AVB_AVTP_CAPTURE_A) F_(0, 0) FM(MSIOF2_TXD_C) FM(RTS4_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
222 #define IP0_27_24 FM(IRQ0) FM(QPOLB) F_(0, 0) FM(DU_CDE) FM(VI4_DATA0_B) FM(CAN0_TX_B) FM(CANFD0_TX_B) FM(MSIOF3_SS2_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
223 #define IP0_31_28 FM(IRQ1) FM(QPOLA) F_(0, 0) FM(DU_DISP) FM(VI4_DATA1_B) FM(CAN0_RX_B) FM(CANFD0_RX_B) FM(MSIOF3_SS1_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
224 #define IP1_3_0 FM(IRQ2) FM(QCPV_QDE) F_(0, 0) FM(DU_EXODDF_DU_ODDF_DISP_CDE) FM(VI4_DATA2_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SYNC_E) F_(0, 0) FM(PWM3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
225 #define IP1_7_4 FM(IRQ3) FM(QSTVB_QVE) F_(0, 0) FM(DU_DOTCLKOUT1) FM(VI4_DATA3_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SCK_E) F_(0, 0) FM(PWM4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
226 #define IP1_11_8 FM(IRQ4) FM(QSTH_QHS) F_(0, 0) FM(DU_EXHSYNC_DU_HSYNC) FM(VI4_DATA4_B) F_(0, 0) F_(0, 0) FM(MSIOF3_RXD_E) F_(0, 0) FM(PWM5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
227 #define IP1_15_12 FM(IRQ5) FM(QSTB_QHE) F_(0, 0) FM(DU_EXVSYNC_DU_VSYNC) FM(VI4_DATA5_B) FM(FSCLKST2_N_B) F_(0, 0) FM(MSIOF3_TXD_E) F_(0, 0) FM(PWM6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
228 #define IP1_19_16 FM(PWM0) FM(AVB_AVTP_PPS)F_(0, 0) F_(0, 0) FM(VI4_DATA6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IECLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
229 #define IP1_23_20 FM(PWM1_A) F_(0, 0) F_(0, 0) FM(HRX3_D) FM(VI4_DATA7_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IERX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
230 #define IP1_27_24 FM(PWM2_A) F_(0, 0) F_(0, 0) FM(HTX3_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IETX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
231 #define IP1_31_28 FM(A0) FM(LCDOUT16) FM(MSIOF3_SYNC_B) F_(0, 0) FM(VI4_DATA8) F_(0, 0) FM(DU_DB0) F_(0, 0) F_(0, 0) FM(PWM3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
232 #define IP2_3_0 FM(A1) FM(LCDOUT17) FM(MSIOF3_TXD_B) F_(0, 0) FM(VI4_DATA9) F_(0, 0) FM(DU_DB1) F_(0, 0) F_(0, 0) FM(PWM4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
233 #define IP2_7_4 FM(A2) FM(LCDOUT18) FM(MSIOF3_SCK_B) F_(0, 0) FM(VI4_DATA10) F_(0, 0) FM(DU_DB2) F_(0, 0) F_(0, 0) FM(PWM5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
234 #define IP2_11_8 FM(A3) FM(LCDOUT19) FM(MSIOF3_RXD_B) F_(0, 0) FM(VI4_DATA11) F_(0, 0) FM(DU_DB3) F_(0, 0) F_(0, 0) FM(PWM6_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
235 #define IP2_15_12 FM(A4) FM(LCDOUT20) FM(MSIOF3_SS1_B) F_(0, 0) FM(VI4_DATA12) FM(VI5_DATA12) FM(DU_DB4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
236 #define IP2_19_16 FM(A5) FM(LCDOUT21) FM(MSIOF3_SS2_B) FM(SCK4_B) FM(VI4_DATA13) FM(VI5_DATA13) FM(DU_DB5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
237 #define IP2_23_20 FM(A6) FM(LCDOUT22) FM(MSIOF2_SS1_A) FM(RX4_B) FM(VI4_DATA14) FM(VI5_DATA14) FM(DU_DB6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
238 #define IP2_27_24 FM(A7) FM(LCDOUT23) FM(MSIOF2_SS2_A) FM(TX4_B) FM(VI4_DATA15) FM(VI5_DATA15) FM(DU_DB7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
239 #define IP2_31_28 FM(A8) FM(RX3_B) FM(MSIOF2_SYNC_A) FM(HRX4_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(SDA6_A) FM(AVB_AVTP_MATCH_B) FM(PWM1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
240 #define IP3_3_0 FM(A9) F_(0, 0) FM(MSIOF2_SCK_A) FM(CTS4_N_B) F_(0, 0) FM(VI5_VSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
241 #define IP3_7_4 FM(A10) F_(0, 0) FM(MSIOF2_RXD_A) FM(RTS4_N_B) F_(0, 0) FM(VI5_HSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
242 #define IP3_11_8 FM(A11) FM(TX3_B) FM(MSIOF2_TXD_A) FM(HTX4_B) FM(HSCK4) FM(VI5_FIELD) F_(0, 0) FM(SCL6_A) FM(AVB_AVTP_CAPTURE_B) FM(PWM2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
244 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
245 #define IP3_15_12 FM(A12) FM(LCDOUT12) FM(MSIOF3_SCK_C) F_(0, 0) FM(HRX4_A) FM(VI5_DATA8) FM(DU_DG4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
246 #define IP3_19_16 FM(A13) FM(LCDOUT13) FM(MSIOF3_SYNC_C) F_(0, 0) FM(HTX4_A) FM(VI5_DATA9) FM(DU_DG5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
247 #define IP3_23_20 FM(A14) FM(LCDOUT14) FM(MSIOF3_RXD_C) F_(0, 0) FM(HCTS4_N) FM(VI5_DATA10) FM(DU_DG6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
248 #define IP3_27_24 FM(A15) FM(LCDOUT15) FM(MSIOF3_TXD_C) F_(0, 0) FM(HRTS4_N) FM(VI5_DATA11) FM(DU_DG7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
249 #define IP3_31_28 FM(A16) FM(LCDOUT8) F_(0, 0) F_(0, 0) FM(VI4_FIELD) F_(0, 0) FM(DU_DG0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
250 #define IP4_3_0 FM(A17) FM(LCDOUT9) F_(0, 0) F_(0, 0) FM(VI4_VSYNC_N) F_(0, 0) FM(DU_DG1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
251 #define IP4_7_4 FM(A18) FM(LCDOUT10) F_(0, 0) F_(0, 0) FM(VI4_HSYNC_N) F_(0, 0) FM(DU_DG2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
252 #define IP4_11_8 FM(A19) FM(LCDOUT11) F_(0, 0) F_(0, 0) FM(VI4_CLKENB) F_(0, 0) FM(DU_DG3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
253 #define IP4_15_12 FM(CS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLKENB) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
254 #define IP4_19_16 FM(CS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLK) F_(0, 0) FM(EX_WAIT0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
255 #define IP4_23_20 FM(BS_N) FM(QSTVA_QVS) FM(MSIOF3_SCK_D) FM(SCK3) FM(HSCK3) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN1_TX) FM(CANFD1_TX) FM(IETX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
256 #define IP4_27_24 FM(RD_N) F_(0, 0) FM(MSIOF3_SYNC_D) FM(RX3_A) FM(HRX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_TX_A) FM(CANFD0_TX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
257 #define IP4_31_28 FM(RD_WR_N) F_(0, 0) FM(MSIOF3_RXD_D) FM(TX3_A) FM(HTX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_RX_A) FM(CANFD0_RX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
258 #define IP5_3_0 FM(WE0_N) F_(0, 0) FM(MSIOF3_TXD_D) FM(CTS3_N) FM(HCTS3_N) F_(0, 0) F_(0, 0) FM(SCL6_B) FM(CAN_CLK) F_(0, 0) FM(IECLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
259 #define IP5_7_4 FM(WE1_N) F_(0, 0) FM(MSIOF3_SS1_D) FM(RTS3_N) FM(HRTS3_N) F_(0, 0) F_(0, 0) FM(SDA6_B) FM(CAN1_RX) FM(CANFD1_RX) FM(IERX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
260 #define IP5_11_8 FM(EX_WAIT0_A) FM(QCLK) F_(0, 0) F_(0, 0) FM(VI4_CLK) F_(0, 0) FM(DU_DOTCLKOUT0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
261 #define IP5_15_12 FM(D0) FM(MSIOF2_SS1_B)FM(MSIOF3_SCK_A) F_(0, 0) FM(VI4_DATA16) FM(VI5_DATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
262 #define IP5_19_16 FM(D1) FM(MSIOF2_SS2_B)FM(MSIOF3_SYNC_A) F_(0, 0) FM(VI4_DATA17) FM(VI5_DATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
263 #define IP5_23_20 FM(D2) F_(0, 0) FM(MSIOF3_RXD_A) F_(0, 0) FM(VI4_DATA18) FM(VI5_DATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
264 #define IP5_27_24 FM(D3) F_(0, 0) FM(MSIOF3_TXD_A) F_(0, 0) FM(VI4_DATA19) FM(VI5_DATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
265 #define IP5_31_28 FM(D4) FM(MSIOF2_SCK_B)F_(0, 0) F_(0, 0) FM(VI4_DATA20) FM(VI5_DATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
266 #define IP6_3_0 FM(D5) FM(MSIOF2_SYNC_B)F_(0, 0) F_(0, 0) FM(VI4_DATA21) FM(VI5_DATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
267 #define IP6_7_4 FM(D6) FM(MSIOF2_RXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA22) FM(VI5_DATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
268 #define IP6_11_8 FM(D7) FM(MSIOF2_TXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA23) FM(VI5_DATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
269 #define IP6_15_12 FM(D8) FM(LCDOUT0) FM(MSIOF2_SCK_D) FM(SCK4_C) FM(VI4_DATA0_A) F_(0, 0) FM(DU_DR0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
270 #define IP6_19_16 FM(D9) FM(LCDOUT1) FM(MSIOF2_SYNC_D) F_(0, 0) FM(VI4_DATA1_A) F_(0, 0) FM(DU_DR1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
271 #define IP6_23_20 FM(D10) FM(LCDOUT2) FM(MSIOF2_RXD_D) FM(HRX3_B) FM(VI4_DATA2_A) FM(CTS4_N_C) FM(DU_DR2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
272 #define IP6_27_24 FM(D11) FM(LCDOUT3) FM(MSIOF2_TXD_D) FM(HTX3_B) FM(VI4_DATA3_A) FM(RTS4_N_C) FM(DU_DR3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
273 #define IP6_31_28 FM(D12) FM(LCDOUT4) FM(MSIOF2_SS1_D) FM(RX4_C) FM(VI4_DATA4_A) F_(0, 0) FM(DU_DR4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
275 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
276 #define IP7_3_0 FM(D13) FM(LCDOUT5) FM(MSIOF2_SS2_D) FM(TX4_C) FM(VI4_DATA5_A) F_(0, 0) FM(DU_DR5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
277 #define IP7_7_4 FM(D14) FM(LCDOUT6) FM(MSIOF3_SS1_A) FM(HRX3_C) FM(VI4_DATA6_A) F_(0, 0) FM(DU_DR6) FM(SCL6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
278 #define IP7_11_8 FM(D15) FM(LCDOUT7) FM(MSIOF3_SS2_A) FM(HTX3_C) FM(VI4_DATA7_A) F_(0, 0) FM(DU_DR7) FM(SDA6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
279 #define IP7_19_16 FM(SD0_CLK) F_(0, 0) FM(MSIOF1_SCK_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
280 #define IP7_23_20 FM(SD0_CMD) F_(0, 0) FM(MSIOF1_SYNC_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
281 #define IP7_27_24 FM(SD0_DAT0) F_(0, 0) FM(MSIOF1_RXD_E) F_(0, 0) F_(0, 0) FM(TS_SCK0_B) FM(STP_ISCLK_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
282 #define IP7_31_28 FM(SD0_DAT1) F_(0, 0) FM(MSIOF1_TXD_E) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_B)FM(STP_ISSYNC_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
283 #define IP8_3_0 FM(SD0_DAT2) F_(0, 0) FM(MSIOF1_SS1_E) F_(0, 0) F_(0, 0) FM(TS_SDAT0_B) FM(STP_ISD_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
284 #define IP8_7_4 FM(SD0_DAT3) F_(0, 0) FM(MSIOF1_SS2_E) F_(0, 0) F_(0, 0) FM(TS_SDEN0_B) FM(STP_ISEN_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
285 #define IP8_11_8 FM(SD1_CLK) F_(0, 0) FM(MSIOF1_SCK_G) F_(0, 0) F_(0, 0) FM(SIM0_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
286 #define IP8_15_12 FM(SD1_CMD) F_(0, 0) FM(MSIOF1_SYNC_G) FM(NFCE_N_B) F_(0, 0) FM(SIM0_D_A) FM(STP_IVCXO27_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
287 #define IP8_19_16 FM(SD1_DAT0) FM(SD2_DAT4) FM(MSIOF1_RXD_G) FM(NFWP_N_B) F_(0, 0) FM(TS_SCK1_B) FM(STP_ISCLK_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
288 #define IP8_23_20 FM(SD1_DAT1) FM(SD2_DAT5) FM(MSIOF1_TXD_G) FM(NFDATA14_B) F_(0, 0) FM(TS_SPSYNC1_B)FM(STP_ISSYNC_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
289 #define IP8_27_24 FM(SD1_DAT2) FM(SD2_DAT6) FM(MSIOF1_SS1_G) FM(NFDATA15_B) F_(0, 0) FM(TS_SDAT1_B) FM(STP_ISD_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
290 #define IP8_31_28 FM(SD1_DAT3) FM(SD2_DAT7) FM(MSIOF1_SS2_G) FM(NFRB_N_B) F_(0, 0) FM(TS_SDEN1_B) FM(STP_ISEN_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
291 #define IP9_3_0 FM(SD2_CLK) F_(0, 0) FM(NFDATA8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
292 #define IP9_7_4 FM(SD2_CMD) F_(0, 0) FM(NFDATA9) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
293 #define IP9_11_8 FM(SD2_DAT0) F_(0, 0) FM(NFDATA10) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
294 #define IP9_15_12 FM(SD2_DAT1) F_(0, 0) FM(NFDATA11) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
295 #define IP9_19_16 FM(SD2_DAT2) F_(0, 0) FM(NFDATA12) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
296 #define IP9_23_20 FM(SD2_DAT3) F_(0, 0) FM(NFDATA13) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
297 #define IP9_27_24 FM(SD2_DS) F_(0, 0) FM(NFALE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SATA_DEVSLP_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
298 #define IP9_31_28 FM(SD3_CLK) F_(0, 0) FM(NFWE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
299 #define IP10_3_0 FM(SD3_CMD) F_(0, 0) FM(NFRE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
300 #define IP10_7_4 FM(SD3_DAT0) F_(0, 0) FM(NFDATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
301 #define IP10_11_8 FM(SD3_DAT1) F_(0, 0) FM(NFDATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
302 #define IP10_15_12 FM(SD3_DAT2) F_(0, 0) FM(NFDATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
303 #define IP10_19_16 FM(SD3_DAT3) F_(0, 0) FM(NFDATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
304 #define IP10_23_20 FM(SD3_DAT4) FM(SD2_CD_A) FM(NFDATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
305 #define IP10_27_24 FM(SD3_DAT5) FM(SD2_WP_A) FM(NFDATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
306 #define IP10_31_28 FM(SD3_DAT6) FM(SD3_CD) FM(NFDATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
307 #define IP11_3_0 FM(SD3_DAT7) FM(SD3_WP) FM(NFDATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
308 #define IP11_7_4 FM(SD3_DS) F_(0, 0) FM(NFCLE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
309 #define IP11_11_8 FM(SD0_CD) F_(0, 0) FM(NFDATA14_A) F_(0, 0) FM(SCL2_B) FM(SIM0_RST_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
311 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
312 #define IP11_15_12 FM(SD0_WP) F_(0, 0) FM(NFDATA15_A) F_(0, 0) FM(SDA2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
313 #define IP11_19_16 FM(SD1_CD) F_(0, 0) FM(NFRB_N_A) F_(0, 0) F_(0, 0) FM(SIM0_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
314 #define IP11_23_20 FM(SD1_WP) F_(0, 0) FM(NFCE_N_A) F_(0, 0) F_(0, 0) FM(SIM0_D_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
315 #define IP11_27_24 FM(SCK0) FM(HSCK1_B) FM(MSIOF1_SS2_B) FM(AUDIO_CLKC_B) FM(SDA2_A) FM(SIM0_RST_B) FM(STP_OPWM_0_C) FM(RIF0_CLK_B) F_(0, 0) FM(ADICHS2) FM(SCK5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
316 #define IP11_31_28 FM(RX0) FM(HRX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SCK0_C) FM(STP_ISCLK_0_C) FM(RIF0_D0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
317 #define IP12_3_0 FM(TX0) FM(HTX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_C)FM(STP_ISSYNC_0_C) FM(RIF0_D1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
318 #define IP12_7_4 FM(CTS0_N) FM(HCTS1_N_B) FM(MSIOF1_SYNC_B) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_C)FM(STP_ISSYNC_1_C) FM(RIF1_SYNC_B) FM(AUDIO_CLKOUT_C) FM(ADICS_SAMP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
319 #define IP12_11_8 FM(RTS0_N) FM(HRTS1_N_B) FM(MSIOF1_SS1_B) FM(AUDIO_CLKA_B) FM(SCL2_A) F_(0, 0) FM(STP_IVCXO27_1_C) FM(RIF0_SYNC_B) F_(0, 0) FM(ADICHS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
320 #define IP12_15_12 FM(RX1_A) FM(HRX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDAT0_C) FM(STP_ISD_0_C) FM(RIF1_CLK_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
321 #define IP12_19_16 FM(TX1_A) FM(HTX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDEN0_C) FM(STP_ISEN_0_C) FM(RIF1_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
322 #define IP12_23_20 FM(CTS1_N) FM(HCTS1_N_A) FM(MSIOF1_RXD_B) F_(0, 0) F_(0, 0) FM(TS_SDEN1_C) FM(STP_ISEN_1_C) FM(RIF1_D0_B) F_(0, 0) FM(ADIDATA) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
323 #define IP12_27_24 FM(RTS1_N) FM(HRTS1_N_A) FM(MSIOF1_TXD_B) F_(0, 0) F_(0, 0) FM(TS_SDAT1_C) FM(STP_ISD_1_C) FM(RIF1_D1_B) F_(0, 0) FM(ADICHS0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
324 #define IP12_31_28 FM(SCK2) FM(SCIF_CLK_B) FM(MSIOF1_SCK_B) F_(0, 0) F_(0, 0) FM(TS_SCK1_C) FM(STP_ISCLK_1_C) FM(RIF1_CLK_B) F_(0, 0) FM(ADICLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
325 #define IP13_3_0 FM(TX2_A) F_(0, 0) F_(0, 0) FM(SD2_CD_B) FM(SCL1_A) F_(0, 0) FM(FMCLK_A) FM(RIF1_D1_C) F_(0, 0) FM(FSO_CFE_0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
326 #define IP13_7_4 FM(RX2_A) F_(0, 0) F_(0, 0) FM(SD2_WP_B) FM(SDA1_A) F_(0, 0) FM(FMIN_A) FM(RIF1_SYNC_C) F_(0, 0) FM(FSO_CFE_1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
327 #define IP13_11_8 FM(HSCK0) F_(0, 0) FM(MSIOF1_SCK_D) FM(AUDIO_CLKB_A) FM(SSI_SDATA1_B)FM(TS_SCK0_D) FM(STP_ISCLK_0_D) FM(RIF0_CLK_C) F_(0, 0) F_(0, 0) FM(RX5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
328 #define IP13_15_12 FM(HRX0) F_(0, 0) FM(MSIOF1_RXD_D) F_(0, 0) FM(SSI_SDATA2_B)FM(TS_SDEN0_D) FM(STP_ISEN_0_D) FM(RIF0_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
329 #define IP13_19_16 FM(HTX0) F_(0, 0) FM(MSIOF1_TXD_D) F_(0, 0) FM(SSI_SDATA9_B)FM(TS_SDAT0_D) FM(STP_ISD_0_D) FM(RIF0_D1_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
330 #define IP13_23_20 FM(HCTS0_N) FM(RX2_B) FM(MSIOF1_SYNC_D) F_(0, 0) FM(SSI_SCK9_A) FM(TS_SPSYNC0_D)FM(STP_ISSYNC_0_D) FM(RIF0_SYNC_C) FM(AUDIO_CLKOUT1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
331 #define IP13_27_24 FM(HRTS0_N) FM(TX2_B) FM(MSIOF1_SS1_D) F_(0, 0) FM(SSI_WS9_A) F_(0, 0) FM(STP_IVCXO27_0_D) FM(BPFCLK_A) FM(AUDIO_CLKOUT2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
332 #define IP13_31_28 FM(MSIOF0_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_A) F_(0, 0) FM(TX5_B) F_(0, 0) F_(0, 0) FM(BPFCLK_D) F_(0, 0) F_(0, 0)
333 #define IP14_3_0 FM(MSIOF0_SS1) FM(RX5_A) FM(NFWP_N_A) FM(AUDIO_CLKA_C) FM(SSI_SCK2_A) F_(0, 0) FM(STP_IVCXO27_0_C) F_(0, 0) FM(AUDIO_CLKOUT3_A) F_(0, 0) FM(TCLK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
334 #define IP14_7_4 FM(MSIOF0_SS2) FM(TX5_A) FM(MSIOF1_SS2_D) FM(AUDIO_CLKC_A) FM(SSI_WS2_A) F_(0, 0) FM(STP_OPWM_0_D) F_(0, 0) FM(AUDIO_CLKOUT_D) F_(0, 0) FM(SPEEDIN_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
335 #define IP14_11_8 FM(MLB_CLK) F_(0, 0) FM(MSIOF1_SCK_F) F_(0, 0) FM(SCL1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
336 #define IP14_15_12 FM(MLB_SIG) FM(RX1_B) FM(MSIOF1_SYNC_F) F_(0, 0) FM(SDA1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
337 #define IP14_19_16 FM(MLB_DAT) FM(TX1_B) FM(MSIOF1_RXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
338 #define IP14_23_20 FM(SSI_SCK01239) F_(0, 0) FM(MSIOF1_TXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
339 #define IP14_27_24 FM(SSI_WS01239) F_(0, 0) FM(MSIOF1_SS1_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
341 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
342 #define IP14_31_28 FM(SSI_SDATA0) F_(0, 0) FM(MSIOF1_SS2_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
343 #define IP15_3_0 FM(SSI_SDATA1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
344 #define IP15_7_4 FM(SSI_SDATA2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(SSI_SCK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
345 #define IP15_11_8 FM(SSI_SCK349) F_(0, 0) FM(MSIOF1_SS1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
346 #define IP15_15_12 FM(SSI_WS349) FM(HCTS2_N_A) FM(MSIOF1_SS2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
347 #define IP15_19_16 FM(SSI_SDATA3) FM(HRTS2_N_A) FM(MSIOF1_TXD_A) F_(0, 0) F_(0, 0) FM(TS_SCK0_A) FM(STP_ISCLK_0_A) FM(RIF0_D1_A) FM(RIF2_D0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
348 #define IP15_23_20 FM(SSI_SCK4) FM(HRX2_A) FM(MSIOF1_SCK_A) F_(0, 0) F_(0, 0) FM(TS_SDAT0_A) FM(STP_ISD_0_A) FM(RIF0_CLK_A) FM(RIF2_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
349 #define IP15_27_24 FM(SSI_WS4) FM(HTX2_A) FM(MSIOF1_SYNC_A) F_(0, 0) F_(0, 0) FM(TS_SDEN0_A) FM(STP_ISEN_0_A) FM(RIF0_SYNC_A) FM(RIF2_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
350 #define IP15_31_28 FM(SSI_SDATA4) FM(HSCK2_A) FM(MSIOF1_RXD_A) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_A)FM(STP_ISSYNC_0_A) FM(RIF0_D0_A) FM(RIF2_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
351 #define IP16_3_0 FM(SSI_SCK6) F_(0, 0) F_(0, 0) FM(SIM0_RST_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
352 #define IP16_7_4 FM(SSI_WS6) F_(0, 0) F_(0, 0) FM(SIM0_D_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
353 #define IP16_11_8 FM(SSI_SDATA6) F_(0, 0) F_(0, 0) FM(SIM0_CLK_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SATA_DEVSLP_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
354 #define IP16_15_12 FM(SSI_SCK78) FM(HRX2_B) FM(MSIOF1_SCK_C) F_(0, 0) F_(0, 0) FM(TS_SCK1_A) FM(STP_ISCLK_1_A) FM(RIF1_CLK_A) FM(RIF3_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
355 #define IP16_19_16 FM(SSI_WS78) FM(HTX2_B) FM(MSIOF1_SYNC_C) F_(0, 0) F_(0, 0) FM(TS_SDAT1_A) FM(STP_ISD_1_A) FM(RIF1_SYNC_A) FM(RIF3_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
356 #define IP16_23_20 FM(SSI_SDATA7) FM(HCTS2_N_B) FM(MSIOF1_RXD_C) F_(0, 0) F_(0, 0) FM(TS_SDEN1_A) FM(STP_ISEN_1_A) FM(RIF1_D0_A) FM(RIF3_D0_A) F_(0, 0) FM(TCLK2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
357 #define IP16_27_24 FM(SSI_SDATA8) FM(HRTS2_N_B) FM(MSIOF1_TXD_C) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_A)FM(STP_ISSYNC_1_A) FM(RIF1_D1_A) FM(RIF3_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
358 #define IP16_31_28 FM(SSI_SDATA9_A) FM(HSCK2_B) FM(MSIOF1_SS1_C) FM(HSCK1_A) FM(SSI_WS1_B) FM(SCK1) FM(STP_IVCXO27_1_A) FM(SCK5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
359 #define IP17_3_0 FM(AUDIO_CLKA_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(CC5_OSCOUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
360 #define IP17_7_4 FM(AUDIO_CLKB_B) FM(SCIF_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_1_D) FM(REMOCON_A) F_(0, 0) F_(0, 0) FM(TCLK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
361 #define IP17_11_8 FM(USB0_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_RST_C) F_(0, 0) FM(TS_SCK1_D) FM(STP_ISCLK_1_D) FM(BPFCLK_B) FM(RIF3_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HSCK2_C) F_(0, 0) F_(0, 0)
362 #define IP17_15_12 FM(USB0_OVC) F_(0, 0) F_(0, 0) FM(SIM0_D_C) F_(0, 0) FM(TS_SDAT1_D) FM(STP_ISD_1_D) F_(0, 0) FM(RIF3_SYNC_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HRX2_C) F_(0, 0) F_(0, 0)
363 #define IP17_19_16 FM(USB1_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_CLK_C) FM(SSI_SCK1_A) FM(TS_SCK0_E) FM(STP_ISCLK_0_E) FM(FMCLK_B) FM(RIF2_CLK_B) F_(0, 0) FM(SPEEDIN_A) F_(0, 0) F_(0, 0) FM(HTX2_C) F_(0, 0) F_(0, 0)
364 #define IP17_23_20 FM(USB1_OVC) F_(0, 0) FM(MSIOF1_SS2_C) F_(0, 0) FM(SSI_WS1_A) FM(TS_SDAT0_E) FM(STP_ISD_0_E) FM(FMIN_B) FM(RIF2_SYNC_B) F_(0, 0) FM(REMOCON_B) F_(0, 0) F_(0, 0) FM(HCTS2_N_C) F_(0, 0) F_(0, 0)
365 #define IP17_27_24 FM(USB30_PWEN) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_B) FM(SSI_SCK2_B) FM(TS_SDEN1_D) FM(STP_ISEN_1_D) FM(STP_OPWM_0_E)FM(RIF3_D0_B) F_(0, 0) FM(TCLK2_B) FM(TPU0TO0) FM(BPFCLK_C) FM(HRTS2_N_C) F_(0, 0) F_(0, 0)
366 #define IP17_31_28 FM(USB30_OVC) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT1_B) FM(SSI_WS2_B) FM(TS_SPSYNC1_D)FM(STP_ISSYNC_1_D) FM(STP_IVCXO27_0_E)FM(RIF3_D1_B) F_(0, 0) FM(FSO_TOE_N) FM(TPU0TO1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
367 #define IP18_3_0 FM(GP6_30) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT2_B) FM(SSI_SCK9_B) FM(TS_SDEN0_E) FM(STP_ISEN_0_E) F_(0, 0) FM(RIF2_D0_B) F_(0, 0) F_(0, 0) FM(TPU0TO2) FM(FMCLK_C) FM(FMCLK_D) F_(0, 0) F_(0, 0)
368 #define IP18_7_4 FM(GP6_31) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT3_B) FM(SSI_WS9_B) FM(TS_SPSYNC0_E)FM(STP_ISSYNC_0_E) F_(0, 0) FM(RIF2_D1_B) F_(0, 0) F_(0, 0) FM(TPU0TO3) FM(FMIN_C) FM(FMIN_D) F_(0, 0) F_(0, 0)
370 #define PINMUX_GPSR \
371 \
372 GPSR6_31 \
373 GPSR6_30 \
374 GPSR6_29 \
375 GPSR1_28 GPSR6_28 \
376 GPSR1_27 GPSR6_27 \
377 GPSR1_26 GPSR6_26 \
378 GPSR1_25 GPSR5_25 GPSR6_25 \
379 GPSR1_24 GPSR5_24 GPSR6_24 \
380 GPSR1_23 GPSR5_23 GPSR6_23 \
381 GPSR1_22 GPSR5_22 GPSR6_22 \
382 GPSR1_21 GPSR5_21 GPSR6_21 \
383 GPSR1_20 GPSR5_20 GPSR6_20 \
384 GPSR1_19 GPSR5_19 GPSR6_19 \
385 GPSR1_18 GPSR5_18 GPSR6_18 \
386 GPSR1_17 GPSR4_17 GPSR5_17 GPSR6_17 \
387 GPSR1_16 GPSR4_16 GPSR5_16 GPSR6_16 \
388 GPSR0_15 GPSR1_15 GPSR3_15 GPSR4_15 GPSR5_15 GPSR6_15 \
389 GPSR0_14 GPSR1_14 GPSR2_14 GPSR3_14 GPSR4_14 GPSR5_14 GPSR6_14 \
390 GPSR0_13 GPSR1_13 GPSR2_13 GPSR3_13 GPSR4_13 GPSR5_13 GPSR6_13 \
391 GPSR0_12 GPSR1_12 GPSR2_12 GPSR3_12 GPSR4_12 GPSR5_12 GPSR6_12 \
392 GPSR0_11 GPSR1_11 GPSR2_11 GPSR3_11 GPSR4_11 GPSR5_11 GPSR6_11 \
393 GPSR0_10 GPSR1_10 GPSR2_10 GPSR3_10 GPSR4_10 GPSR5_10 GPSR6_10 \
394 GPSR0_9 GPSR1_9 GPSR2_9 GPSR3_9 GPSR4_9 GPSR5_9 GPSR6_9 \
395 GPSR0_8 GPSR1_8 GPSR2_8 GPSR3_8 GPSR4_8 GPSR5_8 GPSR6_8 \
396 GPSR0_7 GPSR1_7 GPSR2_7 GPSR3_7 GPSR4_7 GPSR5_7 GPSR6_7 \
397 GPSR0_6 GPSR1_6 GPSR2_6 GPSR3_6 GPSR4_6 GPSR5_6 GPSR6_6 \
398 GPSR0_5 GPSR1_5 GPSR2_5 GPSR3_5 GPSR4_5 GPSR5_5 GPSR6_5 \
399 GPSR0_4 GPSR1_4 GPSR2_4 GPSR3_4 GPSR4_4 GPSR5_4 GPSR6_4 \
400 GPSR0_3 GPSR1_3 GPSR2_3 GPSR3_3 GPSR4_3 GPSR5_3 GPSR6_3 GPSR7_3 \
401 GPSR0_2 GPSR1_2 GPSR2_2 GPSR3_2 GPSR4_2 GPSR5_2 GPSR6_2 GPSR7_2 \
402 GPSR0_1 GPSR1_1 GPSR2_1 GPSR3_1 GPSR4_1 GPSR5_1 GPSR6_1 GPSR7_1 \
403 GPSR0_0 GPSR1_0 GPSR2_0 GPSR3_0 GPSR4_0 GPSR5_0 GPSR6_0 GPSR7_0
405 #define PINMUX_IPSR \
406 \
407 FM(IP0_3_0) IP0_3_0 FM(IP1_3_0) IP1_3_0 FM(IP2_3_0) IP2_3_0 FM(IP3_3_0) IP3_3_0 \
408 FM(IP0_7_4) IP0_7_4 FM(IP1_7_4) IP1_7_4 FM(IP2_7_4) IP2_7_4 FM(IP3_7_4) IP3_7_4 \
409 FM(IP0_11_8) IP0_11_8 FM(IP1_11_8) IP1_11_8 FM(IP2_11_8) IP2_11_8 FM(IP3_11_8) IP3_11_8 \
410 FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \
411 FM(IP0_19_16) IP0_19_16 FM(IP1_19_16) IP1_19_16 FM(IP2_19_16) IP2_19_16 FM(IP3_19_16) IP3_19_16 \
412 FM(IP0_23_20) IP0_23_20 FM(IP1_23_20) IP1_23_20 FM(IP2_23_20) IP2_23_20 FM(IP3_23_20) IP3_23_20 \
413 FM(IP0_27_24) IP0_27_24 FM(IP1_27_24) IP1_27_24 FM(IP2_27_24) IP2_27_24 FM(IP3_27_24) IP3_27_24 \
414 FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \
415 \
416 FM(IP4_3_0) IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) IP6_3_0 FM(IP7_3_0) IP7_3_0 \
417 FM(IP4_7_4) IP4_7_4 FM(IP5_7_4) IP5_7_4 FM(IP6_7_4) IP6_7_4 FM(IP7_7_4) IP7_7_4 \
418 FM(IP4_11_8) IP4_11_8 FM(IP5_11_8) IP5_11_8 FM(IP6_11_8) IP6_11_8 FM(IP7_11_8) IP7_11_8 \
419 FM(IP4_15_12) IP4_15_12 FM(IP5_15_12) IP5_15_12 FM(IP6_15_12) IP6_15_12 \
420 FM(IP4_19_16) IP4_19_16 FM(IP5_19_16) IP5_19_16 FM(IP6_19_16) IP6_19_16 FM(IP7_19_16) IP7_19_16 \
421 FM(IP4_23_20) IP4_23_20 FM(IP5_23_20) IP5_23_20 FM(IP6_23_20) IP6_23_20 FM(IP7_23_20) IP7_23_20 \
422 FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \
423 FM(IP4_31_28) IP4_31_28 FM(IP5_31_28) IP5_31_28 FM(IP6_31_28) IP6_31_28 FM(IP7_31_28) IP7_31_28 \
424 \
425 FM(IP8_3_0) IP8_3_0 FM(IP9_3_0) IP9_3_0 FM(IP10_3_0) IP10_3_0 FM(IP11_3_0) IP11_3_0 \
426 FM(IP8_7_4) IP8_7_4 FM(IP9_7_4) IP9_7_4 FM(IP10_7_4) IP10_7_4 FM(IP11_7_4) IP11_7_4 \
427 FM(IP8_11_8) IP8_11_8 FM(IP9_11_8) IP9_11_8 FM(IP10_11_8) IP10_11_8 FM(IP11_11_8) IP11_11_8 \
428 FM(IP8_15_12) IP8_15_12 FM(IP9_15_12) IP9_15_12 FM(IP10_15_12) IP10_15_12 FM(IP11_15_12) IP11_15_12 \
429 FM(IP8_19_16) IP8_19_16 FM(IP9_19_16) IP9_19_16 FM(IP10_19_16) IP10_19_16 FM(IP11_19_16) IP11_19_16 \
430 FM(IP8_23_20) IP8_23_20 FM(IP9_23_20) IP9_23_20 FM(IP10_23_20) IP10_23_20 FM(IP11_23_20) IP11_23_20 \
431 FM(IP8_27_24) IP8_27_24 FM(IP9_27_24) IP9_27_24 FM(IP10_27_24) IP10_27_24 FM(IP11_27_24) IP11_27_24 \
432 FM(IP8_31_28) IP8_31_28 FM(IP9_31_28) IP9_31_28 FM(IP10_31_28) IP10_31_28 FM(IP11_31_28) IP11_31_28 \
433 \
434 FM(IP12_3_0) IP12_3_0 FM(IP13_3_0) IP13_3_0 FM(IP14_3_0) IP14_3_0 FM(IP15_3_0) IP15_3_0 \
435 FM(IP12_7_4) IP12_7_4 FM(IP13_7_4) IP13_7_4 FM(IP14_7_4) IP14_7_4 FM(IP15_7_4) IP15_7_4 \
436 FM(IP12_11_8) IP12_11_8 FM(IP13_11_8) IP13_11_8 FM(IP14_11_8) IP14_11_8 FM(IP15_11_8) IP15_11_8 \
437 FM(IP12_15_12) IP12_15_12 FM(IP13_15_12) IP13_15_12 FM(IP14_15_12) IP14_15_12 FM(IP15_15_12) IP15_15_12 \
438 FM(IP12_19_16) IP12_19_16 FM(IP13_19_16) IP13_19_16 FM(IP14_19_16) IP14_19_16 FM(IP15_19_16) IP15_19_16 \
439 FM(IP12_23_20) IP12_23_20 FM(IP13_23_20) IP13_23_20 FM(IP14_23_20) IP14_23_20 FM(IP15_23_20) IP15_23_20 \
440 FM(IP12_27_24) IP12_27_24 FM(IP13_27_24) IP13_27_24 FM(IP14_27_24) IP14_27_24 FM(IP15_27_24) IP15_27_24 \
441 FM(IP12_31_28) IP12_31_28 FM(IP13_31_28) IP13_31_28 FM(IP14_31_28) IP14_31_28 FM(IP15_31_28) IP15_31_28 \
442 \
443 FM(IP16_3_0) IP16_3_0 FM(IP17_3_0) IP17_3_0 FM(IP18_3_0) IP18_3_0 \
444 FM(IP16_7_4) IP16_7_4 FM(IP17_7_4) IP17_7_4 FM(IP18_7_4) IP18_7_4 \
445 FM(IP16_11_8) IP16_11_8 FM(IP17_11_8) IP17_11_8 \
446 FM(IP16_15_12) IP16_15_12 FM(IP17_15_12) IP17_15_12 \
447 FM(IP16_19_16) IP16_19_16 FM(IP17_19_16) IP17_19_16 \
448 FM(IP16_23_20) IP16_23_20 FM(IP17_23_20) IP17_23_20 \
449 FM(IP16_27_24) IP16_27_24 FM(IP17_27_24) IP17_27_24 \
450 FM(IP16_31_28) IP16_31_28 FM(IP17_31_28) IP17_31_28
453 #define MOD_SEL0_31_30_29 FM(SEL_MSIOF3_0) FM(SEL_MSIOF3_1) FM(SEL_MSIOF3_2) FM(SEL_MSIOF3_3) FM(SEL_MSIOF3_4) F_(0, 0) F_(0, 0) F_(0, 0)
454 #define MOD_SEL0_28_27 FM(SEL_MSIOF2_0) FM(SEL_MSIOF2_1) FM(SEL_MSIOF2_2) FM(SEL_MSIOF2_3)
455 #define MOD_SEL0_26_25_24 FM(SEL_MSIOF1_0) FM(SEL_MSIOF1_1) FM(SEL_MSIOF1_2) FM(SEL_MSIOF1_3) FM(SEL_MSIOF1_4) FM(SEL_MSIOF1_5) FM(SEL_MSIOF1_6) F_(0, 0)
456 #define MOD_SEL0_23 FM(SEL_LBSC_0) FM(SEL_LBSC_1)
457 #define MOD_SEL0_22 FM(SEL_IEBUS_0) FM(SEL_IEBUS_1)
458 #define MOD_SEL0_21 FM(SEL_I2C2_0) FM(SEL_I2C2_1)
459 #define MOD_SEL0_20 FM(SEL_I2C1_0) FM(SEL_I2C1_1)
460 #define MOD_SEL0_19 FM(SEL_HSCIF4_0) FM(SEL_HSCIF4_1)
461 #define MOD_SEL0_18_17 FM(SEL_HSCIF3_0) FM(SEL_HSCIF3_1) FM(SEL_HSCIF3_2) FM(SEL_HSCIF3_3)
462 #define MOD_SEL0_16 FM(SEL_HSCIF1_0) FM(SEL_HSCIF1_1)
463 #define MOD_SEL0_14_13 FM(SEL_HSCIF2_0) FM(SEL_HSCIF2_1) FM(SEL_HSCIF2_2) F_(0, 0)
464 #define MOD_SEL0_12 FM(SEL_ETHERAVB_0) FM(SEL_ETHERAVB_1)
465 #define MOD_SEL0_11 FM(SEL_DRIF3_0) FM(SEL_DRIF3_1)
466 #define MOD_SEL0_10 FM(SEL_DRIF2_0) FM(SEL_DRIF2_1)
467 #define MOD_SEL0_9_8 FM(SEL_DRIF1_0) FM(SEL_DRIF1_1) FM(SEL_DRIF1_2) F_(0, 0)
468 #define MOD_SEL0_7_6 FM(SEL_DRIF0_0) FM(SEL_DRIF0_1) FM(SEL_DRIF0_2) F_(0, 0)
469 #define MOD_SEL0_5 FM(SEL_CANFD0_0) FM(SEL_CANFD0_1)
470 #define MOD_SEL0_4_3 FM(SEL_ADG_A_0) FM(SEL_ADG_A_1) FM(SEL_ADG_A_2) FM(SEL_ADG_A_3)
473 #define MOD_SEL1_31_30 FM(SEL_TSIF1_0) FM(SEL_TSIF1_1) FM(SEL_TSIF1_2) FM(SEL_TSIF1_3)
474 #define MOD_SEL1_29_28_27 FM(SEL_TSIF0_0) FM(SEL_TSIF0_1) FM(SEL_TSIF0_2) FM(SEL_TSIF0_3) FM(SEL_TSIF0_4) F_(0, 0) F_(0, 0) F_(0, 0)
475 #define MOD_SEL1_26 FM(SEL_TIMER_TMU_0) FM(SEL_TIMER_TMU_1)
476 #define MOD_SEL1_25_24 FM(SEL_SSP1_1_0) FM(SEL_SSP1_1_1) FM(SEL_SSP1_1_2) FM(SEL_SSP1_1_3)
477 #define MOD_SEL1_23_22_21 FM(SEL_SSP1_0_0) FM(SEL_SSP1_0_1) FM(SEL_SSP1_0_2) FM(SEL_SSP1_0_3) FM(SEL_SSP1_0_4) F_(0, 0) F_(0, 0) F_(0, 0)
478 #define MOD_SEL1_20 FM(SEL_SSI1_0) FM(SEL_SSI1_1)
479 #define MOD_SEL1_19 FM(SEL_SPEED_PULSE_0) FM(SEL_SPEED_PULSE_1)
480 #define MOD_SEL1_18_17 FM(SEL_SIMCARD_0) FM(SEL_SIMCARD_1) FM(SEL_SIMCARD_2) FM(SEL_SIMCARD_3)
481 #define MOD_SEL1_16 FM(SEL_SDHI2_0) FM(SEL_SDHI2_1)
482 #define MOD_SEL1_15_14 FM(SEL_SCIF4_0) FM(SEL_SCIF4_1) FM(SEL_SCIF4_2) F_(0, 0)
483 #define MOD_SEL1_13 FM(SEL_SCIF3_0) FM(SEL_SCIF3_1)
484 #define MOD_SEL1_12 FM(SEL_SCIF2_0) FM(SEL_SCIF2_1)
485 #define MOD_SEL1_11 FM(SEL_SCIF1_0) FM(SEL_SCIF1_1)
486 #define MOD_SEL1_10 FM(SEL_SCIF_0) FM(SEL_SCIF_1)
487 #define MOD_SEL1_9 FM(SEL_REMOCON_0) FM(SEL_REMOCON_1)
488 #define MOD_SEL1_6 FM(SEL_RCAN0_0) FM(SEL_RCAN0_1)
489 #define MOD_SEL1_5 FM(SEL_PWM6_0) FM(SEL_PWM6_1)
490 #define MOD_SEL1_4 FM(SEL_PWM5_0) FM(SEL_PWM5_1)
491 #define MOD_SEL1_3 FM(SEL_PWM4_0) FM(SEL_PWM4_1)
492 #define MOD_SEL1_2 FM(SEL_PWM3_0) FM(SEL_PWM3_1)
493 #define MOD_SEL1_1 FM(SEL_PWM2_0) FM(SEL_PWM2_1)
494 #define MOD_SEL1_0 FM(SEL_PWM1_0) FM(SEL_PWM1_1)
497 #define MOD_SEL2_31 FM(I2C_SEL_5_0) FM(I2C_SEL_5_1)
498 #define MOD_SEL2_30 FM(I2C_SEL_3_0) FM(I2C_SEL_3_1)
499 #define MOD_SEL2_29 FM(I2C_SEL_0_0) FM(I2C_SEL_0_1)
500 #define MOD_SEL2_28_27 FM(SEL_FM_0) FM(SEL_FM_1) FM(SEL_FM_2) FM(SEL_FM_3)
501 #define MOD_SEL2_26 FM(SEL_SCIF5_0) FM(SEL_SCIF5_1)
502 #define MOD_SEL2_25_24_23 FM(SEL_I2C6_0) FM(SEL_I2C6_1) FM(SEL_I2C6_2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
503 #define MOD_SEL2_22 FM(SEL_NDFC_0) FM(SEL_NDFC_1)
504 #define MOD_SEL2_21 FM(SEL_SSI2_0) FM(SEL_SSI2_1)
505 #define MOD_SEL2_20 FM(SEL_SSI9_0) FM(SEL_SSI9_1)
506 #define MOD_SEL2_19 FM(SEL_TIMER_TMU2_0) FM(SEL_TIMER_TMU2_1)
507 #define MOD_SEL2_18 FM(SEL_ADG_B_0) FM(SEL_ADG_B_1)
508 #define MOD_SEL2_17 FM(SEL_ADG_C_0) FM(SEL_ADG_C_1)
509 #define MOD_SEL2_0 FM(SEL_VIN4_0) FM(SEL_VIN4_1)
511 #define PINMUX_MOD_SELS \
512 \
513 MOD_SEL0_31_30_29 MOD_SEL1_31_30 MOD_SEL2_31 \
514 MOD_SEL2_30 \
515 MOD_SEL1_29_28_27 MOD_SEL2_29 \
516 MOD_SEL0_28_27 MOD_SEL2_28_27 \
517 MOD_SEL0_26_25_24 MOD_SEL1_26 MOD_SEL2_26 \
518 MOD_SEL1_25_24 MOD_SEL2_25_24_23 \
519 MOD_SEL0_23 MOD_SEL1_23_22_21 \
520 MOD_SEL0_22 MOD_SEL2_22 \
521 MOD_SEL0_21 MOD_SEL2_21 \
522 MOD_SEL0_20 MOD_SEL1_20 MOD_SEL2_20 \
523 MOD_SEL0_19 MOD_SEL1_19 MOD_SEL2_19 \
524 MOD_SEL0_18_17 MOD_SEL1_18_17 MOD_SEL2_18 \
525 MOD_SEL2_17 \
526 MOD_SEL0_16 MOD_SEL1_16 \
527 MOD_SEL1_15_14 \
528 MOD_SEL0_14_13 \
529 MOD_SEL1_13 \
530 MOD_SEL0_12 MOD_SEL1_12 \
531 MOD_SEL0_11 MOD_SEL1_11 \
532 MOD_SEL0_10 MOD_SEL1_10 \
533 MOD_SEL0_9_8 MOD_SEL1_9 \
534 MOD_SEL0_7_6 \
535 MOD_SEL1_6 \
536 MOD_SEL0_5 MOD_SEL1_5 \
537 MOD_SEL0_4_3 MOD_SEL1_4 \
538 MOD_SEL1_3 \
539 MOD_SEL1_2 \
540 MOD_SEL1_1 \
541 MOD_SEL1_0 MOD_SEL2_0
543 /*
544 * These pins are not able to be muxed but have other properties
545 * that can be set, such as drive-strength or pull-up/pull-down enable.
546 */
547 #define PINMUX_STATIC \
548 FM(QSPI0_SPCLK) FM(QSPI0_SSL) FM(QSPI0_MOSI_IO0) FM(QSPI0_MISO_IO1) \
549 FM(QSPI0_IO2) FM(QSPI0_IO3) \
550 FM(QSPI1_SPCLK) FM(QSPI1_SSL) FM(QSPI1_MOSI_IO0) FM(QSPI1_MISO_IO1) \
551 FM(QSPI1_IO2) FM(QSPI1_IO3) \
552 FM(RPC_INT) FM(RPC_WP) FM(RPC_RESET) \
553 FM(AVB_TX_CTL) FM(AVB_TXC) FM(AVB_TD0) FM(AVB_TD1) FM(AVB_TD2) FM(AVB_TD3) \
554 FM(AVB_RX_CTL) FM(AVB_RXC) FM(AVB_RD0) FM(AVB_RD1) FM(AVB_RD2) FM(AVB_RD3) \
555 FM(AVB_TXCREFCLK) FM(AVB_MDIO) \
556 FM(PRESETOUT) \
557 FM(DU_DOTCLKIN0) FM(DU_DOTCLKIN1) FM(DU_DOTCLKIN3) \
558 FM(TMS) FM(TDO) FM(ASEBRK) FM(MLB_REF) FM(TDI) FM(TCK) FM(TRST) FM(EXTALR)
563 PINMUX_DATA_BEGIN,
565 PINMUX_DATA_END,
567 #define F_(x, y)
568 #define FM(x) FN_##x,
569 PINMUX_FUNCTION_BEGIN,
571 PINMUX_GPSR
572 PINMUX_IPSR
573 PINMUX_MOD_SELS
574 PINMUX_FUNCTION_END,
575 #undef F_
576 #undef FM
578 #define F_(x, y)
579 #define FM(x) x##_MARK,
580 PINMUX_MARK_BEGIN,
581 PINMUX_GPSR
582 PINMUX_IPSR
583 PINMUX_MOD_SELS
584 PINMUX_STATIC
585 PINMUX_MARK_END,
586 #undef F_
587 #undef FM
588 };
605 /* IPSR0 */
646 /* IPSR1 */
697 /* IPSR2 */
758 /* IPSR3 */
812 /* IPSR4 */
858 /* IPSR5 */
908 /* IPSR6 */
960 /* IPSR7 */
1002 /* IPSR8 */
1051 /* IPSR9 */
1077 /* IPSR10 */
1105 /* IPSR11 */
1147 /* IPSR12 */
1208 /* IPSR13 */
1268 /* IPSR14 */
1309 /* IPSR15 */
1356 /* IPSR16 */
1409 /* IPSR17 */
1476 /* IPSR18 */
1497 /* I2C */
1502 /*
1503 * Static pins can not be muxed between different functions but
1504 * still need mark entries in the pinmux list. Add each static
1505 * pin to the list without an associated function. The sh-pfc
1506 * core will do the right thing and skip trying to mux the pin
1507 * while still applying configuration to it.
1508 */
1509 #define FM(x) PINMUX_DATA(x##_MARK, 0),
1510 PINMUX_STATIC
1511 #undef FM
1512 };
1514 /*
1515 * R8A77965 has 8 banks with 32 GPIOs in each => 256 GPIOs.
1516 * Physical layout rows: A - AW, cols: 1 - 39.
1517 */
1520 #define PIN_A_NUMBER(r, c) PIN_NUMBER(ROW_GROUP_A(r), c)
1521 #define PIN_NONE U16_MAX
1526 /*
1527 * Pins not associated with a GPIO port.
1528 *
1529 * The pin positions are different between different r8a77965
1530 * packages, all that is needed for the pfc driver is a unique
1531 * number for each pin. To this end use the pin layout from
1532 * R-Car M3SiP to calculate a unique number for each pin.
1533 */
1564 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 39, EXTALR, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1570 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 26, TRST#, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1571 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 29, TDI, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1573 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 27, TCK, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1576 };
1578 /* - AUDIO CLOCK ------------------------------------------------------------ */
1580 /* CLK A */
1582 };
1584 AUDIO_CLKA_A_MARK,
1585 };
1587 /* CLK A */
1589 };
1591 AUDIO_CLKA_B_MARK,
1592 };
1594 /* CLK A */
1596 };
1598 AUDIO_CLKA_C_MARK,
1599 };
1601 /* CLK B */
1603 };
1605 AUDIO_CLKB_A_MARK,
1606 };
1608 /* CLK B */
1610 };
1612 AUDIO_CLKB_B_MARK,
1613 };
1615 /* CLK C */
1617 };
1619 AUDIO_CLKC_A_MARK,
1620 };
1622 /* CLK C */
1624 };
1626 AUDIO_CLKC_B_MARK,
1627 };
1629 /* CLKOUT */
1631 };
1633 AUDIO_CLKOUT_A_MARK,
1634 };
1636 /* CLKOUT */
1638 };
1640 AUDIO_CLKOUT_B_MARK,
1641 };
1643 /* CLKOUT */
1645 };
1647 AUDIO_CLKOUT_C_MARK,
1648 };
1650 /* CLKOUT */
1652 };
1654 AUDIO_CLKOUT_D_MARK,
1655 };
1657 /* CLKOUT1 */
1659 };
1661 AUDIO_CLKOUT1_A_MARK,
1662 };
1664 /* CLKOUT1 */
1666 };
1668 AUDIO_CLKOUT1_B_MARK,
1669 };
1671 /* CLKOUT2 */
1673 };
1675 AUDIO_CLKOUT2_A_MARK,
1676 };
1678 /* CLKOUT2 */
1680 };
1682 AUDIO_CLKOUT2_B_MARK,
1683 };
1686 /* CLKOUT3 */
1688 };
1690 AUDIO_CLKOUT3_A_MARK,
1691 };
1693 /* CLKOUT3 */
1695 };
1697 AUDIO_CLKOUT3_B_MARK,
1698 };
1700 /* - EtherAVB --------------------------------------------------------------- */
1702 /* AVB_LINK */
1704 };
1706 AVB_LINK_MARK,
1707 };
1709 /* AVB_MAGIC_ */
1711 };
1713 AVB_MAGIC_MARK,
1714 };
1716 /* AVB_PHY_INT */
1718 };
1720 AVB_PHY_INT_MARK,
1721 };
1723 /* AVB_MDC, AVB_MDIO */
1725 };
1728 };
1730 /*
1731 * AVB_TX_CTL, AVB_TXC, AVB_TD0,
1732 * AVB_TD1, AVB_TD2, AVB_TD3,
1733 * AVB_RX_CTL, AVB_RXC, AVB_RD0,
1734 * AVB_RD1, AVB_RD2, AVB_RD3,
1735 * AVB_TXCREFCLK
1736 */
1743 };
1749 AVB_TXCREFCLK_MARK,
1750 };
1752 /* AVB_AVTP_PPS */
1754 };
1756 AVB_AVTP_PPS_MARK,
1757 };
1759 /* AVB_AVTP_MATCH_A */
1761 };
1763 AVB_AVTP_MATCH_A_MARK,
1764 };
1766 /* AVB_AVTP_CAPTURE_A */
1768 };
1770 AVB_AVTP_CAPTURE_A_MARK,
1771 };
1773 /* AVB_AVTP_MATCH_B */
1775 };
1777 AVB_AVTP_MATCH_B_MARK,
1778 };
1780 /* AVB_AVTP_CAPTURE_B */
1782 };
1784 AVB_AVTP_CAPTURE_B_MARK,
1785 };
1787 /* - CAN ------------------------------------------------------------------ */
1789 /* TX, RX */
1791 };
1795 };
1798 /* TX, RX */
1800 };
1804 };
1807 /* TX, RX */
1809 };
1813 };
1815 /* - CAN Clock -------------------------------------------------------------- */
1817 /* CLK */
1819 };
1822 CAN_CLK_MARK,
1823 };
1825 /* - CAN FD --------------------------------------------------------------- */
1827 /* TX, RX */
1829 };
1833 };
1836 /* TX, RX */
1838 };
1842 };
1845 /* TX, RX */
1847 };
1851 };
1853 /* - DRIF0 --------------------------------------------------------------- */
1855 /* CLK, SYNC */
1857 };
1861 };
1864 /* D0 */
1866 };
1869 RIF0_D0_A_MARK,
1870 };
1873 /* D1 */
1875 };
1878 RIF0_D1_A_MARK,
1879 };
1882 /* CLK, SYNC */
1884 };
1888 };
1891 /* D0 */
1893 };
1896 RIF0_D0_B_MARK,
1897 };
1900 /* D1 */
1902 };
1905 RIF0_D1_B_MARK,
1906 };
1909 /* CLK, SYNC */
1911 };
1915 };
1918 /* D0 */
1920 };
1923 RIF0_D0_C_MARK,
1924 };
1927 /* D1 */
1929 };
1932 RIF0_D1_C_MARK,
1933 };
1935 /* - DRIF1 --------------------------------------------------------------- */
1937 /* CLK, SYNC */
1939 };
1943 };
1946 /* D0 */
1948 };
1951 RIF1_D0_A_MARK,
1952 };
1955 /* D1 */
1957 };
1960 RIF1_D1_A_MARK,
1961 };
1964 /* CLK, SYNC */
1966 };
1970 };
1973 /* D0 */
1975 };
1978 RIF1_D0_B_MARK,
1979 };
1982 /* D1 */
1984 };
1987 RIF1_D1_B_MARK,
1988 };
1991 /* CLK, SYNC */
1993 };
1997 };
2000 /* D0 */
2002 };
2005 RIF1_D0_C_MARK,
2006 };
2009 /* D1 */
2011 };
2014 RIF1_D1_C_MARK,
2015 };
2017 /* - DRIF2 --------------------------------------------------------------- */
2019 /* CLK, SYNC */
2021 };
2025 };
2028 /* D0 */
2030 };
2033 RIF2_D0_A_MARK,
2034 };
2037 /* D1 */
2039 };
2042 RIF2_D1_A_MARK,
2043 };
2046 /* CLK, SYNC */
2048 };
2052 };
2055 /* D0 */
2057 };
2060 RIF2_D0_B_MARK,
2061 };
2064 /* D1 */
2066 };
2069 RIF2_D1_B_MARK,
2070 };
2072 /* - DRIF3 --------------------------------------------------------------- */
2074 /* CLK, SYNC */
2076 };
2080 };
2083 /* D0 */
2085 };
2088 RIF3_D0_A_MARK,
2089 };
2092 /* D1 */
2094 };
2097 RIF3_D1_A_MARK,
2098 };
2101 /* CLK, SYNC */
2103 };
2107 };
2110 /* D0 */
2112 };
2115 RIF3_D0_B_MARK,
2116 };
2119 /* D1 */
2121 };
2124 RIF3_D1_B_MARK,
2125 };
2127 /* - DU --------------------------------------------------------------------- */
2129 /* R[7:2], G[7:2], B[7:2] */
2136 };
2145 };
2148 /* R[7:0], G[7:0], B[7:0] */
2158 };
2167 };
2170 /* CLKOUT */
2172 };
2175 DU_DOTCLKOUT0_MARK
2176 };
2179 /* CLKOUT */
2181 };
2184 DU_DOTCLKOUT1_MARK
2185 };
2188 /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
2190 };
2193 DU_EXVSYNC_DU_VSYNC_MARK, DU_EXHSYNC_DU_HSYNC_MARK
2194 };
2197 /* EXDISP/EXODDF/EXCDE */
2199 };
2202 DU_EXODDF_DU_ODDF_DISP_CDE_MARK,
2203 };
2206 /* CDE */
2208 };
2211 DU_CDE_MARK,
2212 };
2215 /* DISP */
2217 };
2220 DU_DISP_MARK,
2221 };
2223 /* - HSCIF0 ----------------------------------------------------------------- */
2225 /* RX, TX */
2227 };
2231 };
2234 /* SCK */
2236 };
2239 HSCK0_MARK,
2240 };
2243 /* RTS, CTS */
2245 };
2249 };
2251 /* - HSCIF1 ----------------------------------------------------------------- */
2253 /* RX, TX */
2255 };
2259 };
2262 /* SCK */
2264 };
2267 HSCK1_A_MARK,
2268 };
2271 /* RTS, CTS */
2273 };
2277 };
2280 /* RX, TX */
2282 };
2286 };
2289 /* SCK */
2291 };
2294 HSCK1_B_MARK,
2295 };
2298 /* RTS, CTS */
2300 };
2304 };
2306 /* - HSCIF2 ----------------------------------------------------------------- */
2308 /* RX, TX */
2310 };
2314 };
2317 /* SCK */
2319 };
2322 HSCK2_A_MARK,
2323 };
2326 /* RTS, CTS */
2328 };
2332 };
2335 /* RX, TX */
2337 };
2341 };
2344 /* SCK */
2346 };
2349 HSCK2_B_MARK,
2350 };
2353 /* RTS, CTS */
2355 };
2359 };
2362 /* RX, TX */
2364 };
2368 };
2371 /* SCK */
2373 };
2376 HSCK2_C_MARK,
2377 };
2380 /* RTS, CTS */
2382 };
2386 };
2388 /* - HSCIF3 ----------------------------------------------------------------- */
2390 /* RX, TX */
2392 };
2396 };
2399 /* SCK */
2401 };
2404 HSCK3_MARK,
2405 };
2408 /* RTS, CTS */
2410 };
2414 };
2417 /* RX, TX */
2419 };
2423 };
2426 /* RX, TX */
2428 };
2432 };
2435 /* RX, TX */
2437 };
2441 };
2443 /* - HSCIF4 ----------------------------------------------------------------- */
2445 /* RX, TX */
2447 };
2451 };
2454 /* SCK */
2456 };
2459 HSCK4_MARK,
2460 };
2463 /* RTS, CTS */
2465 };
2469 };
2472 /* RX, TX */
2474 };
2478 };
2480 /* - I2C -------------------------------------------------------------------- */
2482 /* SDA, SCL */
2484 };
2487 };
2489 /* SDA, SCL */
2491 };
2494 };
2496 /* SDA, SCL */
2498 };
2501 };
2503 /* SDA, SCL */
2505 };
2508 };
2510 /* SDA, SCL */
2512 };
2515 };
2517 /* SDA, SCL */
2519 };
2522 };
2524 /* SDA, SCL */
2526 };
2529 };
2531 /* - INTC-EX ---------------------------------------------------------------- */
2533 /* IRQ0 */
2535 };
2537 IRQ0_MARK,
2538 };
2540 /* IRQ1 */
2542 };
2544 IRQ1_MARK,
2545 };
2547 /* IRQ2 */
2549 };
2551 IRQ2_MARK,
2552 };
2554 /* IRQ3 */
2556 };
2558 IRQ3_MARK,
2559 };
2561 /* IRQ4 */
2563 };
2565 IRQ4_MARK,
2566 };
2568 /* IRQ5 */
2570 };
2572 IRQ5_MARK,
2573 };
2575 /* - MSIOF0 ----------------------------------------------------------------- */
2577 /* SCK */
2579 };
2581 MSIOF0_SCK_MARK,
2582 };
2584 /* SYNC */
2586 };
2588 MSIOF0_SYNC_MARK,
2589 };
2591 /* SS1 */
2593 };
2595 MSIOF0_SS1_MARK,
2596 };
2598 /* SS2 */
2600 };
2602 MSIOF0_SS2_MARK,
2603 };
2605 /* TXD */
2607 };
2609 MSIOF0_TXD_MARK,
2610 };
2612 /* RXD */
2614 };
2616 MSIOF0_RXD_MARK,
2617 };
2618 /* - MSIOF1 ----------------------------------------------------------------- */
2620 /* SCK */
2622 };
2624 MSIOF1_SCK_A_MARK,
2625 };
2627 /* SYNC */
2629 };
2631 MSIOF1_SYNC_A_MARK,
2632 };
2634 /* SS1 */
2636 };
2638 MSIOF1_SS1_A_MARK,
2639 };
2641 /* SS2 */
2643 };
2645 MSIOF1_SS2_A_MARK,
2646 };
2648 /* TXD */
2650 };
2652 MSIOF1_TXD_A_MARK,
2653 };
2655 /* RXD */
2657 };
2659 MSIOF1_RXD_A_MARK,
2660 };
2662 /* SCK */
2664 };
2666 MSIOF1_SCK_B_MARK,
2667 };
2669 /* SYNC */
2671 };
2673 MSIOF1_SYNC_B_MARK,
2674 };
2676 /* SS1 */
2678 };
2680 MSIOF1_SS1_B_MARK,
2681 };
2683 /* SS2 */
2685 };
2687 MSIOF1_SS2_B_MARK,
2688 };
2690 /* TXD */
2692 };
2694 MSIOF1_TXD_B_MARK,
2695 };
2697 /* RXD */
2699 };
2701 MSIOF1_RXD_B_MARK,
2702 };
2704 /* SCK */
2706 };
2708 MSIOF1_SCK_C_MARK,
2709 };
2711 /* SYNC */
2713 };
2715 MSIOF1_SYNC_C_MARK,
2716 };
2718 /* SS1 */
2720 };
2722 MSIOF1_SS1_C_MARK,
2723 };
2725 /* SS2 */
2727 };
2729 MSIOF1_SS2_C_MARK,
2730 };
2732 /* TXD */
2734 };
2736 MSIOF1_TXD_C_MARK,
2737 };
2739 /* RXD */
2741 };
2743 MSIOF1_RXD_C_MARK,
2744 };
2746 /* SCK */
2748 };
2750 MSIOF1_SCK_D_MARK,
2751 };
2753 /* SYNC */
2755 };
2757 MSIOF1_SYNC_D_MARK,
2758 };
2760 /* SS1 */
2762 };
2764 MSIOF1_SS1_D_MARK,
2765 };
2767 /* SS2 */
2769 };
2771 MSIOF1_SS2_D_MARK,
2772 };
2774 /* TXD */
2776 };
2778 MSIOF1_TXD_D_MARK,
2779 };
2781 /* RXD */
2783 };
2785 MSIOF1_RXD_D_MARK,
2786 };
2788 /* SCK */
2790 };
2792 MSIOF1_SCK_E_MARK,
2793 };
2795 /* SYNC */
2797 };
2799 MSIOF1_SYNC_E_MARK,
2800 };
2802 /* SS1 */
2804 };
2806 MSIOF1_SS1_E_MARK,
2807 };
2809 /* SS2 */
2811 };
2813 MSIOF1_SS2_E_MARK,
2814 };
2816 /* TXD */
2818 };
2820 MSIOF1_TXD_E_MARK,
2821 };
2823 /* RXD */
2825 };
2827 MSIOF1_RXD_E_MARK,
2828 };
2830 /* SCK */
2832 };
2834 MSIOF1_SCK_F_MARK,
2835 };
2837 /* SYNC */
2839 };
2841 MSIOF1_SYNC_F_MARK,
2842 };
2844 /* SS1 */
2846 };
2848 MSIOF1_SS1_F_MARK,
2849 };
2851 /* SS2 */
2853 };
2855 MSIOF1_SS2_F_MARK,
2856 };
2858 /* TXD */
2860 };
2862 MSIOF1_TXD_F_MARK,
2863 };
2865 /* RXD */
2867 };
2869 MSIOF1_RXD_F_MARK,
2870 };
2872 /* SCK */
2874 };
2876 MSIOF1_SCK_G_MARK,
2877 };
2879 /* SYNC */
2881 };
2883 MSIOF1_SYNC_G_MARK,
2884 };
2886 /* SS1 */
2888 };
2890 MSIOF1_SS1_G_MARK,
2891 };
2893 /* SS2 */
2895 };
2897 MSIOF1_SS2_G_MARK,
2898 };
2900 /* TXD */
2902 };
2904 MSIOF1_TXD_G_MARK,
2905 };
2907 /* RXD */
2909 };
2911 MSIOF1_RXD_G_MARK,
2912 };
2913 /* - MSIOF2 ----------------------------------------------------------------- */
2915 /* SCK */
2917 };
2919 MSIOF2_SCK_A_MARK,
2920 };
2922 /* SYNC */
2924 };
2926 MSIOF2_SYNC_A_MARK,
2927 };
2929 /* SS1 */
2931 };
2933 MSIOF2_SS1_A_MARK,
2934 };
2936 /* SS2 */
2938 };
2940 MSIOF2_SS2_A_MARK,
2941 };
2943 /* TXD */
2945 };
2947 MSIOF2_TXD_A_MARK,
2948 };
2950 /* RXD */
2952 };
2954 MSIOF2_RXD_A_MARK,
2955 };
2957 /* SCK */
2959 };
2961 MSIOF2_SCK_B_MARK,
2962 };
2964 /* SYNC */
2966 };
2968 MSIOF2_SYNC_B_MARK,
2969 };
2971 /* SS1 */
2973 };
2975 MSIOF2_SS1_B_MARK,
2976 };
2978 /* SS2 */
2980 };
2982 MSIOF2_SS2_B_MARK,
2983 };
2985 /* TXD */
2987 };
2989 MSIOF2_TXD_B_MARK,
2990 };
2992 /* RXD */
2994 };
2996 MSIOF2_RXD_B_MARK,
2997 };
2999 /* SCK */
3001 };
3003 MSIOF2_SCK_C_MARK,
3004 };
3006 /* SYNC */
3008 };
3010 MSIOF2_SYNC_C_MARK,
3011 };
3013 /* SS1 */
3015 };
3017 MSIOF2_SS1_C_MARK,
3018 };
3020 /* SS2 */
3022 };
3024 MSIOF2_SS2_C_MARK,
3025 };
3027 /* TXD */
3029 };
3031 MSIOF2_TXD_C_MARK,
3032 };
3034 /* RXD */
3036 };
3038 MSIOF2_RXD_C_MARK,
3039 };
3041 /* SCK */
3043 };
3045 MSIOF2_SCK_D_MARK,
3046 };
3048 /* SYNC */
3050 };
3052 MSIOF2_SYNC_D_MARK,
3053 };
3055 /* SS1 */
3057 };
3059 MSIOF2_SS1_D_MARK,
3060 };
3062 /* SS2 */
3064 };
3066 MSIOF2_SS2_D_MARK,
3067 };
3069 /* TXD */
3071 };
3073 MSIOF2_TXD_D_MARK,
3074 };
3076 /* RXD */
3078 };
3080 MSIOF2_RXD_D_MARK,
3081 };
3082 /* - MSIOF3 ----------------------------------------------------------------- */
3084 /* SCK */
3086 };
3088 MSIOF3_SCK_A_MARK,
3089 };
3091 /* SYNC */
3093 };
3095 MSIOF3_SYNC_A_MARK,
3096 };
3098 /* SS1 */
3100 };
3102 MSIOF3_SS1_A_MARK,
3103 };
3105 /* SS2 */
3107 };
3109 MSIOF3_SS2_A_MARK,
3110 };
3112 /* TXD */
3114 };
3116 MSIOF3_TXD_A_MARK,
3117 };
3119 /* RXD */
3121 };
3123 MSIOF3_RXD_A_MARK,
3124 };
3126 /* SCK */
3128 };
3130 MSIOF3_SCK_B_MARK,
3131 };
3133 /* SYNC */
3135 };
3137 MSIOF3_SYNC_B_MARK,
3138 };
3140 /* SS1 */
3142 };
3144 MSIOF3_SS1_B_MARK,
3145 };
3147 /* SS2 */
3149 };
3151 MSIOF3_SS2_B_MARK,
3152 };
3154 /* TXD */
3156 };
3158 MSIOF3_TXD_B_MARK,
3159 };
3161 /* RXD */
3163 };
3165 MSIOF3_RXD_B_MARK,
3166 };
3168 /* SCK */
3170 };
3172 MSIOF3_SCK_C_MARK,
3173 };
3175 /* SYNC */
3177 };
3179 MSIOF3_SYNC_C_MARK,
3180 };
3182 /* TXD */
3184 };
3186 MSIOF3_TXD_C_MARK,
3187 };
3189 /* RXD */
3191 };
3193 MSIOF3_RXD_C_MARK,
3194 };
3196 /* SCK */
3198 };
3200 MSIOF3_SCK_D_MARK,
3201 };
3203 /* SYNC */
3205 };
3207 MSIOF3_SYNC_D_MARK,
3208 };
3210 /* SS1 */
3212 };
3214 MSIOF3_SS1_D_MARK,
3215 };
3217 /* TXD */
3219 };
3221 MSIOF3_TXD_D_MARK,
3222 };
3224 /* RXD */
3226 };
3228 MSIOF3_RXD_D_MARK,
3229 };
3231 /* SCK */
3233 };
3235 MSIOF3_SCK_E_MARK,
3236 };
3238 /* SYNC */
3240 };
3242 MSIOF3_SYNC_E_MARK,
3243 };
3245 /* SS1 */
3247 };
3249 MSIOF3_SS1_E_MARK,
3250 };
3252 /* SS2 */
3254 };
3256 MSIOF3_SS2_E_MARK,
3257 };
3259 /* TXD */
3261 };
3263 MSIOF3_TXD_E_MARK,
3264 };
3266 /* RXD */
3268 };
3270 MSIOF3_RXD_E_MARK,
3271 };
3273 /* - PWM0 --------------------------------------------------------------------*/
3275 /* PWM */
3277 };
3279 PWM0_MARK,
3280 };
3281 /* - PWM1 --------------------------------------------------------------------*/
3283 /* PWM */
3285 };
3287 PWM1_A_MARK,
3288 };
3290 /* PWM */
3292 };
3294 PWM1_B_MARK,
3295 };
3296 /* - PWM2 --------------------------------------------------------------------*/
3298 /* PWM */
3300 };
3302 PWM2_A_MARK,
3303 };
3305 /* PWM */
3307 };
3309 PWM2_B_MARK,
3310 };
3311 /* - PWM3 --------------------------------------------------------------------*/
3313 /* PWM */
3315 };
3317 PWM3_A_MARK,
3318 };
3320 /* PWM */
3322 };
3324 PWM3_B_MARK,
3325 };
3326 /* - PWM4 --------------------------------------------------------------------*/
3328 /* PWM */
3330 };
3332 PWM4_A_MARK,
3333 };
3335 /* PWM */
3337 };
3339 PWM4_B_MARK,
3340 };
3341 /* - PWM5 --------------------------------------------------------------------*/
3343 /* PWM */
3345 };
3347 PWM5_A_MARK,
3348 };
3350 /* PWM */
3352 };
3354 PWM5_B_MARK,
3355 };
3356 /* - PWM6 --------------------------------------------------------------------*/
3358 /* PWM */
3360 };
3362 PWM6_A_MARK,
3363 };
3365 /* PWM */
3367 };
3369 PWM6_B_MARK,
3370 };
3372 /* - SATA --------------------------------------------------------------------*/
3374 /* DEVSLP */
3376 };
3379 SATA_DEVSLP_A_MARK,
3380 };
3383 /* DEVSLP */
3385 };
3388 SATA_DEVSLP_B_MARK,
3389 };
3391 /* - SCIF0 ------------------------------------------------------------------ */
3393 /* RX, TX */
3395 };
3398 };
3400 /* SCK */
3402 };
3404 SCK0_MARK,
3405 };
3407 /* RTS, CTS */
3409 };
3412 };
3413 /* - SCIF1 ------------------------------------------------------------------ */
3415 /* RX, TX */
3417 };
3420 };
3422 /* SCK */
3424 };
3426 SCK1_MARK,
3427 };
3429 /* RTS, CTS */
3431 };
3434 };
3436 /* RX, TX */
3438 };
3441 };
3442 /* - SCIF2 ------------------------------------------------------------------ */
3444 /* RX, TX */
3446 };
3449 };
3451 /* SCK */
3453 };
3455 SCK2_MARK,
3456 };
3458 /* RX, TX */
3460 };
3463 };
3464 /* - SCIF3 ------------------------------------------------------------------ */
3466 /* RX, TX */
3468 };
3471 };
3473 /* SCK */
3475 };
3477 SCK3_MARK,
3478 };
3480 /* RTS, CTS */
3482 };
3485 };
3487 /* RX, TX */
3489 };
3492 };
3493 /* - SCIF4 ------------------------------------------------------------------ */
3495 /* RX, TX */
3497 };
3500 };
3502 /* SCK */
3504 };
3506 SCK4_A_MARK,
3507 };
3509 /* RTS, CTS */
3511 };
3514 };
3516 /* RX, TX */
3518 };
3521 };
3523 /* SCK */
3525 };
3527 SCK4_B_MARK,
3528 };
3530 /* RTS, CTS */
3532 };
3535 };
3537 /* RX, TX */
3539 };
3542 };
3544 /* SCK */
3546 };
3548 SCK4_C_MARK,
3549 };
3551 /* RTS, CTS */
3553 };
3556 };
3557 /* - SCIF5 ------------------------------------------------------------------ */
3559 /* RX, TX */
3561 };
3564 };
3566 /* SCK */
3568 };
3570 SCK5_A_MARK,
3571 };
3573 /* RX, TX */
3575 };
3578 };
3580 /* SCK */
3582 };
3584 SCK5_B_MARK,
3585 };
3586 /* - SCIF Clock ------------------------------------------------------------- */
3588 /* SCIF_CLK */
3590 };
3592 SCIF_CLK_A_MARK,
3593 };
3595 /* SCIF_CLK */
3597 };
3599 SCIF_CLK_B_MARK,
3600 };
3602 /* - SDHI0 ------------------------------------------------------------------ */
3604 /* D0 */
3606 };
3609 SD0_DAT0_MARK,
3610 };
3613 /* D[0:3] */
3616 };
3621 };
3624 /* CLK, CMD */
3626 };
3630 };
3633 /* CD */
3635 };
3638 SD0_CD_MARK,
3639 };
3642 /* WP */
3644 };
3647 SD0_WP_MARK,
3648 };
3650 /* - SDHI1 ------------------------------------------------------------------ */
3652 /* D0 */
3654 };
3657 SD1_DAT0_MARK,
3658 };
3661 /* D[0:3] */
3664 };
3669 };
3672 /* CLK, CMD */
3674 };
3678 };
3681 /* CD */
3683 };
3686 SD1_CD_MARK,
3687 };
3690 /* WP */
3692 };
3695 SD1_WP_MARK,
3696 };
3698 /* - SDHI2 ------------------------------------------------------------------ */
3700 /* D0 */
3702 };
3705 SD2_DAT0_MARK,
3706 };
3709 /* D[0:3] */
3712 };
3717 };
3720 /* D[0:7] */
3725 };
3732 };
3735 /* CLK, CMD */
3737 };
3741 };
3744 /* CD */
3746 };
3749 SD2_CD_A_MARK,
3750 };
3753 /* CD */
3755 };
3758 SD2_CD_B_MARK,
3759 };
3762 /* WP */
3764 };
3767 SD2_WP_A_MARK,
3768 };
3771 /* WP */
3773 };
3776 SD2_WP_B_MARK,
3777 };
3780 /* DS */
3782 };
3785 SD2_DS_MARK,
3786 };
3788 /* - SDHI3 ------------------------------------------------------------------ */
3790 /* D0 */
3792 };
3795 SD3_DAT0_MARK,
3796 };
3799 /* D[0:3] */
3802 };
3807 };
3810 /* D[0:7] */
3815 };
3822 };
3825 /* CLK, CMD */
3827 };
3831 };
3834 /* CD */
3836 };
3839 SD3_CD_MARK,
3840 };
3843 /* WP */
3845 };
3848 SD3_WP_MARK,
3849 };
3852 /* DS */
3854 };
3857 SD3_DS_MARK,
3858 };
3860 /* - SSI -------------------------------------------------------------------- */
3862 /* SDATA */
3864 };
3866 SSI_SDATA0_MARK,
3867 };
3869 /* SCK, WS */
3871 };
3874 };
3876 /* SDATA */
3878 };
3880 SSI_SDATA1_A_MARK,
3881 };
3883 /* SDATA */
3885 };
3887 SSI_SDATA1_B_MARK,
3888 };
3890 /* SCK, WS */
3892 };
3895 };
3897 /* SCK, WS */
3899 };
3902 };
3904 /* SDATA */
3906 };
3908 SSI_SDATA2_A_MARK,
3909 };
3911 /* SDATA */
3913 };
3915 SSI_SDATA2_B_MARK,
3916 };
3918 /* SCK, WS */
3920 };
3923 };
3925 /* SCK, WS */
3927 };
3930 };
3932 /* SDATA */
3934 };
3936 SSI_SDATA3_MARK,
3937 };
3939 /* SCK, WS */
3941 };
3944 };
3946 /* SDATA */
3948 };
3950 SSI_SDATA4_MARK,
3951 };
3953 /* SCK, WS */
3955 };
3958 };
3960 /* SDATA */
3962 };
3964 SSI_SDATA5_MARK,
3965 };
3967 /* SCK, WS */
3969 };
3972 };
3974 /* SDATA */
3976 };
3978 SSI_SDATA6_MARK,
3979 };
3981 /* SCK, WS */
3983 };
3986 };
3988 /* SDATA */
3990 };
3992 SSI_SDATA7_MARK,
3993 };
3995 /* SCK, WS */
3997 };
4000 };
4002 /* SDATA */
4004 };
4006 SSI_SDATA8_MARK,
4007 };
4009 /* SDATA */
4011 };
4013 SSI_SDATA9_A_MARK,
4014 };
4016 /* SDATA */
4018 };
4020 SSI_SDATA9_B_MARK,
4021 };
4023 /* SCK, WS */
4025 };
4028 };
4030 /* SCK, WS */
4032 };
4035 };
4037 /* - TMU -------------------------------------------------------------------- */
4039 /* TCLK */
4041 };
4044 TCLK1_A_MARK,
4045 };
4048 /* TCLK */
4050 };
4053 TCLK1_B_MARK,
4054 };
4057 /* TCLK */
4059 };
4062 TCLK2_A_MARK,
4063 };
4066 /* TCLK */
4068 };
4071 TCLK2_B_MARK,
4072 };
4074 /* - USB0 ------------------------------------------------------------------- */
4076 /* PWEN, OVC */
4078 };
4082 };
4084 /* - USB1 ------------------------------------------------------------------- */
4086 /* PWEN, OVC */
4088 };
4092 };
4094 /* - USB30 ------------------------------------------------------------------ */
4096 /* PWEN, OVC */
4098 };
4102 };
4104 /* - VIN4 ------------------------------------------------------------------- */
4115 };
4127 };
4143 },
4144 };
4160 },
4161 };
4173 };
4185 };
4201 },
4202 };
4218 },
4219 };
4222 /* VSYNC_N, HSYNC_N */
4224 };
4228 };
4232 };
4235 VI4_FIELD_MARK,
4236 };
4240 };
4243 VI4_CLKENB_MARK,
4244 };
4248 };
4251 VI4_CLK_MARK,
4252 };
4254 /* - VIN5 ------------------------------------------------------------------- */
4265 },
4266 };
4278 },
4279 };
4282 /* VSYNC_N, HSYNC_N */
4284 };
4288 };
4292 };
4295 VI5_FIELD_MARK,
4296 };
4300 };
4303 VI5_CLKENB_MARK,
4304 };
4308 };
4311 VI5_CLK_MARK,
4312 };
4656 };
4676 };
4690 };
4695 };
4699 };
4703 };
4708 };
4712 };
4724 };
4736 };
4745 };
4754 };
4765 };
4771 };
4780 };
4792 };
4801 };
4808 };
4813 };
4818 };
4824 };
4833 };
4842 };
4887 };
4914 };
4944 };
4948 };
4953 };
4958 };
4963 };
4968 };
4973 };
4978 };
4983 };
4989 };
4996 };
5001 };
5008 };
5020 };
5027 };
5032 };
5040 };
5048 };
5060 };
5070 };
5098 };
5105 };
5109 };
5113 };
5117 };
5138 };
5149 };
5203 };
5206 #define F_(x, y) FN_##y
5207 #define FM(x) FN_##x
5241 },
5275 },
5309 },
5343 },
5377 },
5411 },
5445 },
5479 },
5480 #undef F_
5481 #undef FM
5483 #define F_(x, y) x,
5484 #define FM(x) FN_##x,
5486 IP0_31_28
5487 IP0_27_24
5488 IP0_23_20
5489 IP0_19_16
5490 IP0_15_12
5491 IP0_11_8
5492 IP0_7_4
5493 IP0_3_0 }
5494 },
5496 IP1_31_28
5497 IP1_27_24
5498 IP1_23_20
5499 IP1_19_16
5500 IP1_15_12
5501 IP1_11_8
5502 IP1_7_4
5503 IP1_3_0 }
5504 },
5506 IP2_31_28
5507 IP2_27_24
5508 IP2_23_20
5509 IP2_19_16
5510 IP2_15_12
5511 IP2_11_8
5512 IP2_7_4
5513 IP2_3_0 }
5514 },
5516 IP3_31_28
5517 IP3_27_24
5518 IP3_23_20
5519 IP3_19_16
5520 IP3_15_12
5521 IP3_11_8
5522 IP3_7_4
5523 IP3_3_0 }
5524 },
5526 IP4_31_28
5527 IP4_27_24
5528 IP4_23_20
5529 IP4_19_16
5530 IP4_15_12
5531 IP4_11_8
5532 IP4_7_4
5533 IP4_3_0 }
5534 },
5536 IP5_31_28
5537 IP5_27_24
5538 IP5_23_20
5539 IP5_19_16
5540 IP5_15_12
5541 IP5_11_8
5542 IP5_7_4
5543 IP5_3_0 }
5544 },
5546 IP6_31_28
5547 IP6_27_24
5548 IP6_23_20
5549 IP6_19_16
5550 IP6_15_12
5551 IP6_11_8
5552 IP6_7_4
5553 IP6_3_0 }
5554 },
5556 IP7_31_28
5557 IP7_27_24
5558 IP7_23_20
5559 IP7_19_16
5561 IP7_11_8
5562 IP7_7_4
5563 IP7_3_0 }
5564 },
5566 IP8_31_28
5567 IP8_27_24
5568 IP8_23_20
5569 IP8_19_16
5570 IP8_15_12
5571 IP8_11_8
5572 IP8_7_4
5573 IP8_3_0 }
5574 },
5576 IP9_31_28
5577 IP9_27_24
5578 IP9_23_20
5579 IP9_19_16
5580 IP9_15_12
5581 IP9_11_8
5582 IP9_7_4
5583 IP9_3_0 }
5584 },
5586 IP10_31_28
5587 IP10_27_24
5588 IP10_23_20
5589 IP10_19_16
5590 IP10_15_12
5591 IP10_11_8
5592 IP10_7_4
5593 IP10_3_0 }
5594 },
5596 IP11_31_28
5597 IP11_27_24
5598 IP11_23_20
5599 IP11_19_16
5600 IP11_15_12
5601 IP11_11_8
5602 IP11_7_4
5603 IP11_3_0 }
5604 },
5606 IP12_31_28
5607 IP12_27_24
5608 IP12_23_20
5609 IP12_19_16
5610 IP12_15_12
5611 IP12_11_8
5612 IP12_7_4
5613 IP12_3_0 }
5614 },
5616 IP13_31_28
5617 IP13_27_24
5618 IP13_23_20
5619 IP13_19_16
5620 IP13_15_12
5621 IP13_11_8
5622 IP13_7_4
5623 IP13_3_0 }
5624 },
5626 IP14_31_28
5627 IP14_27_24
5628 IP14_23_20
5629 IP14_19_16
5630 IP14_15_12
5631 IP14_11_8
5632 IP14_7_4
5633 IP14_3_0 }
5634 },
5636 IP15_31_28
5637 IP15_27_24
5638 IP15_23_20
5639 IP15_19_16
5640 IP15_15_12
5641 IP15_11_8
5642 IP15_7_4
5643 IP15_3_0 }
5644 },
5646 IP16_31_28
5647 IP16_27_24
5648 IP16_23_20
5649 IP16_19_16
5650 IP16_15_12
5651 IP16_11_8
5652 IP16_7_4
5653 IP16_3_0 }
5654 },
5656 IP17_31_28
5657 IP17_27_24
5658 IP17_23_20
5659 IP17_19_16
5660 IP17_15_12
5661 IP17_11_8
5662 IP17_7_4
5663 IP17_3_0 }
5664 },
5672 IP18_7_4
5673 IP18_3_0 }
5674 },
5675 #undef F_
5676 #undef FM
5678 #define F_(x, y) x,
5679 #define FM(x) FN_##x,
5683 MOD_SEL0_31_30_29
5684 MOD_SEL0_28_27
5685 MOD_SEL0_26_25_24
5686 MOD_SEL0_23
5687 MOD_SEL0_22
5688 MOD_SEL0_21
5689 MOD_SEL0_20
5690 MOD_SEL0_19
5691 MOD_SEL0_18_17
5692 MOD_SEL0_16
5694 MOD_SEL0_14_13
5695 MOD_SEL0_12
5696 MOD_SEL0_11
5697 MOD_SEL0_10
5698 MOD_SEL0_9_8
5699 MOD_SEL0_7_6
5700 MOD_SEL0_5
5701 MOD_SEL0_4_3
5702 /* RESERVED 2, 1, 0 */
5704 },
5708 MOD_SEL1_31_30
5709 MOD_SEL1_29_28_27
5710 MOD_SEL1_26
5711 MOD_SEL1_25_24
5712 MOD_SEL1_23_22_21
5713 MOD_SEL1_20
5714 MOD_SEL1_19
5715 MOD_SEL1_18_17
5716 MOD_SEL1_16
5717 MOD_SEL1_15_14
5718 MOD_SEL1_13
5719 MOD_SEL1_12
5720 MOD_SEL1_11
5721 MOD_SEL1_10
5722 MOD_SEL1_9
5724 MOD_SEL1_6
5725 MOD_SEL1_5
5726 MOD_SEL1_4
5727 MOD_SEL1_3
5728 MOD_SEL1_2
5729 MOD_SEL1_1
5730 MOD_SEL1_0 }
5731 },
5735 MOD_SEL2_31
5736 MOD_SEL2_30
5737 MOD_SEL2_29
5738 MOD_SEL2_28_27
5739 MOD_SEL2_26
5740 MOD_SEL2_25_24_23
5741 MOD_SEL2_22
5742 MOD_SEL2_21
5743 MOD_SEL2_20
5744 MOD_SEL2_19
5745 MOD_SEL2_18
5746 MOD_SEL2_17
5747 /* RESERVED 16 */
5749 /* RESERVED 15, 14, 13, 12 */
5752 /* RESERVED 11, 10, 9, 8 */
5755 /* RESERVED 7, 6, 5, 4 */
5758 /* RESERVED 3, 2, 1 */
5760 MOD_SEL2_0 }
5761 },
5762 { },
5763 };
5775 } },
5785 } },
5795 } },
5805 } },
5815 } },
5825 } },
5835 } },
5845 } },
5855 } },
5865 } },
5875 } },
5885 } },
5890 } },
5900 } },
5910 } },
5920 } },
5930 } },
5940 } },
5950 } },
5960 } },
5970 } },
5980 } },
5990 } },
6000 } },
6009 } },
6010 { },
6011 };
6014 POCCTRL,
6015 };
6020 };
6023 {
6035 }
6071 } },
6105 } },
6139 } },
6173 } },
6207 } },
6241 } },
6275 } },
6277 };
6281 {
6293 else
6295 }
6299 {
6318 }
6324 };
6347 };