Linux 5.1.15
[linux/fpc-iii.git] / drivers / pinctrl / sh-pfc / pfc-r8a77970.c
blobc5e67ba29f7c88cdc0024e732c7f9458146dba38
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * R8A77970 processor support - PFC hardware block.
5 * Copyright (C) 2016 Renesas Electronics Corp.
6 * Copyright (C) 2017 Cogent Embedded, Inc. <source@cogentembedded.com>
8 * This file is based on the drivers/pinctrl/sh-pfc/pfc-r8a7795.c
10 * R-Car Gen3 processor support - PFC hardware block.
12 * Copyright (C) 2015 Renesas Electronics Corporation
15 #include <linux/io.h>
16 #include <linux/kernel.h>
18 #include "core.h"
19 #include "sh_pfc.h"
21 #define CPU_ALL_PORT(fn, sfx) \
22 PORT_GP_CFG_22(0, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
23 PORT_GP_28(1, fn, sfx), \
24 PORT_GP_CFG_17(2, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
25 PORT_GP_CFG_17(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
26 PORT_GP_6(4, fn, sfx), \
27 PORT_GP_15(5, fn, sfx)
29 * F_() : just information
30 * FM() : macro for FN_xxx / xxx_MARK
33 /* GPSR0 */
34 #define GPSR0_21 F_(DU_EXODDF_DU_ODDF_DISP_CDE, IP2_23_20)
35 #define GPSR0_20 F_(DU_EXVSYNC_DU_VSYNC, IP2_19_16)
36 #define GPSR0_19 F_(DU_EXHSYNC_DU_HSYNC, IP2_15_12)
37 #define GPSR0_18 F_(DU_DOTCLKOUT, IP2_11_8)
38 #define GPSR0_17 F_(DU_DB7, IP2_7_4)
39 #define GPSR0_16 F_(DU_DB6, IP2_3_0)
40 #define GPSR0_15 F_(DU_DB5, IP1_31_28)
41 #define GPSR0_14 F_(DU_DB4, IP1_27_24)
42 #define GPSR0_13 F_(DU_DB3, IP1_23_20)
43 #define GPSR0_12 F_(DU_DB2, IP1_19_16)
44 #define GPSR0_11 F_(DU_DG7, IP1_15_12)
45 #define GPSR0_10 F_(DU_DG6, IP1_11_8)
46 #define GPSR0_9 F_(DU_DG5, IP1_7_4)
47 #define GPSR0_8 F_(DU_DG4, IP1_3_0)
48 #define GPSR0_7 F_(DU_DG3, IP0_31_28)
49 #define GPSR0_6 F_(DU_DG2, IP0_27_24)
50 #define GPSR0_5 F_(DU_DR7, IP0_23_20)
51 #define GPSR0_4 F_(DU_DR6, IP0_19_16)
52 #define GPSR0_3 F_(DU_DR5, IP0_15_12)
53 #define GPSR0_2 F_(DU_DR4, IP0_11_8)
54 #define GPSR0_1 F_(DU_DR3, IP0_7_4)
55 #define GPSR0_0 F_(DU_DR2, IP0_3_0)
57 /* GPSR1 */
58 #define GPSR1_27 F_(DIGRF_CLKOUT, IP8_27_24)
59 #define GPSR1_26 F_(DIGRF_CLKIN, IP8_23_20)
60 #define GPSR1_25 F_(CANFD_CLK_A, IP8_19_16)
61 #define GPSR1_24 F_(CANFD1_RX, IP8_15_12)
62 #define GPSR1_23 F_(CANFD1_TX, IP8_11_8)
63 #define GPSR1_22 F_(CANFD0_RX_A, IP8_7_4)
64 #define GPSR1_21 F_(CANFD0_TX_A, IP8_3_0)
65 #define GPSR1_20 F_(AVB0_AVTP_CAPTURE, IP7_31_28)
66 #define GPSR1_19 FM(AVB0_AVTP_MATCH)
67 #define GPSR1_18 FM(AVB0_LINK)
68 #define GPSR1_17 FM(AVB0_PHY_INT)
69 #define GPSR1_16 FM(AVB0_MAGIC)
70 #define GPSR1_15 FM(AVB0_MDC)
71 #define GPSR1_14 FM(AVB0_MDIO)
72 #define GPSR1_13 FM(AVB0_TXCREFCLK)
73 #define GPSR1_12 FM(AVB0_TD3)
74 #define GPSR1_11 FM(AVB0_TD2)
75 #define GPSR1_10 FM(AVB0_TD1)
76 #define GPSR1_9 FM(AVB0_TD0)
77 #define GPSR1_8 FM(AVB0_TXC)
78 #define GPSR1_7 FM(AVB0_TX_CTL)
79 #define GPSR1_6 FM(AVB0_RD3)
80 #define GPSR1_5 FM(AVB0_RD2)
81 #define GPSR1_4 FM(AVB0_RD1)
82 #define GPSR1_3 FM(AVB0_RD0)
83 #define GPSR1_2 FM(AVB0_RXC)
84 #define GPSR1_1 FM(AVB0_RX_CTL)
85 #define GPSR1_0 F_(IRQ0, IP2_27_24)
87 /* GPSR2 */
88 #define GPSR2_16 F_(VI0_FIELD, IP4_31_28)
89 #define GPSR2_15 F_(VI0_DATA11, IP4_27_24)
90 #define GPSR2_14 F_(VI0_DATA10, IP4_23_20)
91 #define GPSR2_13 F_(VI0_DATA9, IP4_19_16)
92 #define GPSR2_12 F_(VI0_DATA8, IP4_15_12)
93 #define GPSR2_11 F_(VI0_DATA7, IP4_11_8)
94 #define GPSR2_10 F_(VI0_DATA6, IP4_7_4)
95 #define GPSR2_9 F_(VI0_DATA5, IP4_3_0)
96 #define GPSR2_8 F_(VI0_DATA4, IP3_31_28)
97 #define GPSR2_7 F_(VI0_DATA3, IP3_27_24)
98 #define GPSR2_6 F_(VI0_DATA2, IP3_23_20)
99 #define GPSR2_5 F_(VI0_DATA1, IP3_19_16)
100 #define GPSR2_4 F_(VI0_DATA0, IP3_15_12)
101 #define GPSR2_3 F_(VI0_VSYNC_N, IP3_11_8)
102 #define GPSR2_2 F_(VI0_HSYNC_N, IP3_7_4)
103 #define GPSR2_1 F_(VI0_CLKENB, IP3_3_0)
104 #define GPSR2_0 F_(VI0_CLK, IP2_31_28)
106 /* GPSR3 */
107 #define GPSR3_16 F_(VI1_FIELD, IP7_3_0)
108 #define GPSR3_15 F_(VI1_DATA11, IP6_31_28)
109 #define GPSR3_14 F_(VI1_DATA10, IP6_27_24)
110 #define GPSR3_13 F_(VI1_DATA9, IP6_23_20)
111 #define GPSR3_12 F_(VI1_DATA8, IP6_19_16)
112 #define GPSR3_11 F_(VI1_DATA7, IP6_15_12)
113 #define GPSR3_10 F_(VI1_DATA6, IP6_11_8)
114 #define GPSR3_9 F_(VI1_DATA5, IP6_7_4)
115 #define GPSR3_8 F_(VI1_DATA4, IP6_3_0)
116 #define GPSR3_7 F_(VI1_DATA3, IP5_31_28)
117 #define GPSR3_6 F_(VI1_DATA2, IP5_27_24)
118 #define GPSR3_5 F_(VI1_DATA1, IP5_23_20)
119 #define GPSR3_4 F_(VI1_DATA0, IP5_19_16)
120 #define GPSR3_3 F_(VI1_VSYNC_N, IP5_15_12)
121 #define GPSR3_2 F_(VI1_HSYNC_N, IP5_11_8)
122 #define GPSR3_1 F_(VI1_CLKENB, IP5_7_4)
123 #define GPSR3_0 F_(VI1_CLK, IP5_3_0)
125 /* GPSR4 */
126 #define GPSR4_5 F_(SDA2, IP7_27_24)
127 #define GPSR4_4 F_(SCL2, IP7_23_20)
128 #define GPSR4_3 F_(SDA1, IP7_19_16)
129 #define GPSR4_2 F_(SCL1, IP7_15_12)
130 #define GPSR4_1 F_(SDA0, IP7_11_8)
131 #define GPSR4_0 F_(SCL0, IP7_7_4)
133 /* GPSR5 */
134 #define GPSR5_14 FM(RPC_INT_N)
135 #define GPSR5_13 FM(RPC_WP_N)
136 #define GPSR5_12 FM(RPC_RESET_N)
137 #define GPSR5_11 FM(QSPI1_SSL)
138 #define GPSR5_10 FM(QSPI1_IO3)
139 #define GPSR5_9 FM(QSPI1_IO2)
140 #define GPSR5_8 FM(QSPI1_MISO_IO1)
141 #define GPSR5_7 FM(QSPI1_MOSI_IO0)
142 #define GPSR5_6 FM(QSPI1_SPCLK)
143 #define GPSR5_5 FM(QSPI0_SSL)
144 #define GPSR5_4 FM(QSPI0_IO3)
145 #define GPSR5_3 FM(QSPI0_IO2)
146 #define GPSR5_2 FM(QSPI0_MISO_IO1)
147 #define GPSR5_1 FM(QSPI0_MOSI_IO0)
148 #define GPSR5_0 FM(QSPI0_SPCLK)
151 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */
152 #define IP0_3_0 FM(DU_DR2) FM(HSCK0) F_(0, 0) FM(A0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
153 #define IP0_7_4 FM(DU_DR3) FM(HRTS0_N) F_(0, 0) FM(A1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
154 #define IP0_11_8 FM(DU_DR4) FM(HCTS0_N) F_(0, 0) FM(A2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
155 #define IP0_15_12 FM(DU_DR5) FM(HTX0) F_(0, 0) FM(A3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
156 #define IP0_19_16 FM(DU_DR6) FM(MSIOF3_RXD) F_(0, 0) FM(A4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
157 #define IP0_23_20 FM(DU_DR7) FM(MSIOF3_TXD) F_(0, 0) FM(A5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
158 #define IP0_27_24 FM(DU_DG2) FM(MSIOF3_SS1) F_(0, 0) FM(A6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
159 #define IP0_31_28 FM(DU_DG3) FM(MSIOF3_SS2) F_(0, 0) FM(A7) FM(PWMFSW0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
160 #define IP1_3_0 FM(DU_DG4) F_(0, 0) F_(0, 0) FM(A8) FM(FSO_CFE_0_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
161 #define IP1_7_4 FM(DU_DG5) F_(0, 0) F_(0, 0) FM(A9) FM(FSO_CFE_1_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
162 #define IP1_11_8 FM(DU_DG6) F_(0, 0) F_(0, 0) FM(A10) FM(FSO_TOE_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
163 #define IP1_15_12 FM(DU_DG7) F_(0, 0) F_(0, 0) FM(A11) FM(IRQ1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
164 #define IP1_19_16 FM(DU_DB2) F_(0, 0) F_(0, 0) FM(A12) FM(IRQ2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
165 #define IP1_23_20 FM(DU_DB3) F_(0, 0) F_(0, 0) FM(A13) FM(FXR_CLKOUT1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
166 #define IP1_27_24 FM(DU_DB4) F_(0, 0) F_(0, 0) FM(A14) FM(FXR_CLKOUT2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
167 #define IP1_31_28 FM(DU_DB5) F_(0, 0) F_(0, 0) FM(A15) FM(FXR_TXENA_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
168 #define IP2_3_0 FM(DU_DB6) F_(0, 0) F_(0, 0) FM(A16) FM(FXR_TXENB_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
169 #define IP2_7_4 FM(DU_DB7) F_(0, 0) F_(0, 0) FM(A17) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
170 #define IP2_11_8 FM(DU_DOTCLKOUT) FM(SCIF_CLK_A) F_(0, 0) FM(A18) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
171 #define IP2_15_12 FM(DU_EXHSYNC_DU_HSYNC) FM(HRX0) F_(0, 0) FM(A19) FM(IRQ3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
172 #define IP2_19_16 FM(DU_EXVSYNC_DU_VSYNC) FM(MSIOF3_SCK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
173 #define IP2_23_20 FM(DU_EXODDF_DU_ODDF_DISP_CDE) FM(MSIOF3_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
174 #define IP2_27_24 FM(IRQ0) FM(CC5_OSCOUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
175 #define IP2_31_28 FM(VI0_CLK) FM(MSIOF2_SCK) FM(SCK3) F_(0, 0) FM(HSCK3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
176 #define IP3_3_0 FM(VI0_CLKENB) FM(MSIOF2_RXD) FM(RX3) FM(RD_WR_N) FM(HCTS3_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
177 #define IP3_7_4 FM(VI0_HSYNC_N) FM(MSIOF2_TXD) FM(TX3) F_(0, 0) FM(HRTS3_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
178 #define IP3_11_8 FM(VI0_VSYNC_N) FM(MSIOF2_SYNC) FM(CTS3_N) F_(0, 0) FM(HTX3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
179 #define IP3_15_12 FM(VI0_DATA0) FM(MSIOF2_SS1) FM(RTS3_N_TANS) F_(0, 0) FM(HRX3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
180 #define IP3_19_16 FM(VI0_DATA1) FM(MSIOF2_SS2) FM(SCK1) F_(0, 0) FM(SPEEDIN_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
181 #define IP3_23_20 FM(VI0_DATA2) FM(AVB0_AVTP_PPS) FM(SDA3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
182 #define IP3_27_24 FM(VI0_DATA3) FM(HSCK1) FM(SCL3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
183 #define IP3_31_28 FM(VI0_DATA4) FM(HRTS1_N) FM(RX1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
184 #define IP4_3_0 FM(VI0_DATA5) FM(HCTS1_N) FM(TX1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
185 #define IP4_7_4 FM(VI0_DATA6) FM(HTX1) FM(CTS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
186 #define IP4_11_8 FM(VI0_DATA7) FM(HRX1) FM(RTS1_N_TANS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
187 #define IP4_15_12 FM(VI0_DATA8) FM(HSCK2) FM(PWM0_A) FM(A22) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
188 #define IP4_19_16 FM(VI0_DATA9) FM(HCTS2_N) FM(PWM1_A) FM(A23) FM(FSO_CFE_0_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
189 #define IP4_23_20 FM(VI0_DATA10) FM(HRTS2_N) FM(PWM2_A) FM(A24) FM(FSO_CFE_1_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
190 #define IP4_27_24 FM(VI0_DATA11) FM(HTX2) FM(PWM3_A) FM(A25) FM(FSO_TOE_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
191 #define IP4_31_28 FM(VI0_FIELD) FM(HRX2) FM(PWM4_A) FM(CS1_N) FM(FSCLKST2_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
192 #define IP5_3_0 FM(VI1_CLK) FM(MSIOF1_RXD) F_(0, 0) FM(CS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
193 #define IP5_7_4 FM(VI1_CLKENB) FM(MSIOF1_TXD) F_(0, 0) FM(D0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
194 #define IP5_11_8 FM(VI1_HSYNC_N) FM(MSIOF1_SCK) F_(0, 0) FM(D1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
195 #define IP5_15_12 FM(VI1_VSYNC_N) FM(MSIOF1_SYNC) F_(0, 0) FM(D2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
196 #define IP5_19_16 FM(VI1_DATA0) FM(MSIOF1_SS1) F_(0, 0) FM(D3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
197 #define IP5_23_20 FM(VI1_DATA1) FM(MSIOF1_SS2) F_(0, 0) FM(D4) FM(MMC_CMD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
198 #define IP5_27_24 FM(VI1_DATA2) FM(CANFD0_TX_B) F_(0, 0) FM(D5) FM(MMC_D0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
199 #define IP5_31_28 FM(VI1_DATA3) FM(CANFD0_RX_B) F_(0, 0) FM(D6) FM(MMC_D1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
200 #define IP6_3_0 FM(VI1_DATA4) FM(CANFD_CLK_B) F_(0, 0) FM(D7) FM(MMC_D2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
201 #define IP6_7_4 FM(VI1_DATA5) F_(0,0) FM(SCK4) FM(D8) FM(MMC_D3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
202 #define IP6_11_8 FM(VI1_DATA6) F_(0,0) FM(RX4) FM(D9) FM(MMC_CLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
203 #define IP6_15_12 FM(VI1_DATA7) F_(0,0) FM(TX4) FM(D10) FM(MMC_D4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
204 #define IP6_19_16 FM(VI1_DATA8) F_(0,0) FM(CTS4_N) FM(D11) FM(MMC_D5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
205 #define IP6_23_20 FM(VI1_DATA9) F_(0,0) FM(RTS4_N_TANS) FM(D12) FM(MMC_D6) FM(SCL3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
206 #define IP6_27_24 FM(VI1_DATA10) F_(0,0) F_(0, 0) FM(D13) FM(MMC_D7) FM(SDA3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
207 #define IP6_31_28 FM(VI1_DATA11) FM(SCL4) FM(IRQ4) FM(D14) FM(MMC_WP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
208 #define IP7_3_0 FM(VI1_FIELD) FM(SDA4) FM(IRQ5) FM(D15) FM(MMC_CD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
209 #define IP7_7_4 FM(SCL0) FM(DU_DR0) FM(TPU0TO0) FM(CLKOUT) F_(0, 0) FM(MSIOF0_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
210 #define IP7_11_8 FM(SDA0) FM(DU_DR1) FM(TPU0TO1) FM(BS_N) FM(SCK0) FM(MSIOF0_TXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
211 #define IP7_15_12 FM(SCL1) FM(DU_DG0) FM(TPU0TO2) FM(RD_N) FM(CTS0_N) FM(MSIOF0_SCK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
212 #define IP7_19_16 FM(SDA1) FM(DU_DG1) FM(TPU0TO3) FM(WE0_N) FM(RTS0_N_TANS) FM(MSIOF0_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
213 #define IP7_23_20 FM(SCL2) FM(DU_DB0) FM(TCLK1_A) FM(WE1_N) FM(RX0) FM(MSIOF0_SS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
214 #define IP7_27_24 FM(SDA2) FM(DU_DB1) FM(TCLK2_A) FM(EX_WAIT0) FM(TX0) FM(MSIOF0_SS2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
215 #define IP7_31_28 FM(AVB0_AVTP_CAPTURE) F_(0, 0) F_(0, 0) F_(0, 0) FM(FSCLKST2_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
216 #define IP8_3_0 FM(CANFD0_TX_A) FM(FXR_TXDA) FM(PWM0_B) FM(DU_DISP) FM(FSCLKST2_N_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
217 #define IP8_7_4 FM(CANFD0_RX_A) FM(RXDA_EXTFXR) FM(PWM1_B) FM(DU_CDE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
218 #define IP8_11_8 FM(CANFD1_TX) FM(FXR_TXDB) FM(PWM2_B) FM(TCLK1_B) FM(TX1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
219 #define IP8_15_12 FM(CANFD1_RX) FM(RXDB_EXTFXR) FM(PWM3_B) FM(TCLK2_B) FM(RX1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
220 #define IP8_19_16 FM(CANFD_CLK_A) FM(CLK_EXTFXR) FM(PWM4_B) FM(SPEEDIN_B) FM(SCIF_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
221 #define IP8_23_20 FM(DIGRF_CLKIN) FM(DIGRF_CLKEN_IN) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
222 #define IP8_27_24 FM(DIGRF_CLKOUT) FM(DIGRF_CLKEN_OUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
223 #define IP8_31_28 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
225 #define PINMUX_GPSR \
227 GPSR1_27 \
228 GPSR1_26 \
229 GPSR1_25 \
230 GPSR1_24 \
231 GPSR1_23 \
232 GPSR1_22 \
233 GPSR0_21 GPSR1_21 \
234 GPSR0_20 GPSR1_20 \
235 GPSR0_19 GPSR1_19 \
236 GPSR0_18 GPSR1_18 \
237 GPSR0_17 GPSR1_17 \
238 GPSR0_16 GPSR1_16 GPSR2_16 GPSR3_16 \
239 GPSR0_15 GPSR1_15 GPSR2_15 GPSR3_15 \
240 GPSR0_14 GPSR1_14 GPSR2_14 GPSR3_14 GPSR5_14 \
241 GPSR0_13 GPSR1_13 GPSR2_13 GPSR3_13 GPSR5_13 \
242 GPSR0_12 GPSR1_12 GPSR2_12 GPSR3_12 GPSR5_12 \
243 GPSR0_11 GPSR1_11 GPSR2_11 GPSR3_11 GPSR5_11 \
244 GPSR0_10 GPSR1_10 GPSR2_10 GPSR3_10 GPSR5_10 \
245 GPSR0_9 GPSR1_9 GPSR2_9 GPSR3_9 GPSR5_9 \
246 GPSR0_8 GPSR1_8 GPSR2_8 GPSR3_8 GPSR5_8 \
247 GPSR0_7 GPSR1_7 GPSR2_7 GPSR3_7 GPSR5_7 \
248 GPSR0_6 GPSR1_6 GPSR2_6 GPSR3_6 GPSR5_6 \
249 GPSR0_5 GPSR1_5 GPSR2_5 GPSR3_5 GPSR4_5 GPSR5_5 \
250 GPSR0_4 GPSR1_4 GPSR2_4 GPSR3_4 GPSR4_4 GPSR5_4 \
251 GPSR0_3 GPSR1_3 GPSR2_3 GPSR3_3 GPSR4_3 GPSR5_3 \
252 GPSR0_2 GPSR1_2 GPSR2_2 GPSR3_2 GPSR4_2 GPSR5_2 \
253 GPSR0_1 GPSR1_1 GPSR2_1 GPSR3_1 GPSR4_1 GPSR5_1 \
254 GPSR0_0 GPSR1_0 GPSR2_0 GPSR3_0 GPSR4_0 GPSR5_0
256 #define PINMUX_IPSR \
258 FM(IP0_3_0) IP0_3_0 FM(IP1_3_0) IP1_3_0 FM(IP2_3_0) IP2_3_0 FM(IP3_3_0) IP3_3_0 \
259 FM(IP0_7_4) IP0_7_4 FM(IP1_7_4) IP1_7_4 FM(IP2_7_4) IP2_7_4 FM(IP3_7_4) IP3_7_4 \
260 FM(IP0_11_8) IP0_11_8 FM(IP1_11_8) IP1_11_8 FM(IP2_11_8) IP2_11_8 FM(IP3_11_8) IP3_11_8 \
261 FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \
262 FM(IP0_19_16) IP0_19_16 FM(IP1_19_16) IP1_19_16 FM(IP2_19_16) IP2_19_16 FM(IP3_19_16) IP3_19_16 \
263 FM(IP0_23_20) IP0_23_20 FM(IP1_23_20) IP1_23_20 FM(IP2_23_20) IP2_23_20 FM(IP3_23_20) IP3_23_20 \
264 FM(IP0_27_24) IP0_27_24 FM(IP1_27_24) IP1_27_24 FM(IP2_27_24) IP2_27_24 FM(IP3_27_24) IP3_27_24 \
265 FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \
267 FM(IP4_3_0) IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) IP6_3_0 FM(IP7_3_0) IP7_3_0 \
268 FM(IP4_7_4) IP4_7_4 FM(IP5_7_4) IP5_7_4 FM(IP6_7_4) IP6_7_4 FM(IP7_7_4) IP7_7_4 \
269 FM(IP4_11_8) IP4_11_8 FM(IP5_11_8) IP5_11_8 FM(IP6_11_8) IP6_11_8 FM(IP7_11_8) IP7_11_8 \
270 FM(IP4_15_12) IP4_15_12 FM(IP5_15_12) IP5_15_12 FM(IP6_15_12) IP6_15_12 FM(IP7_15_12) IP7_15_12 \
271 FM(IP4_19_16) IP4_19_16 FM(IP5_19_16) IP5_19_16 FM(IP6_19_16) IP6_19_16 FM(IP7_19_16) IP7_19_16 \
272 FM(IP4_23_20) IP4_23_20 FM(IP5_23_20) IP5_23_20 FM(IP6_23_20) IP6_23_20 FM(IP7_23_20) IP7_23_20 \
273 FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \
274 FM(IP4_31_28) IP4_31_28 FM(IP5_31_28) IP5_31_28 FM(IP6_31_28) IP6_31_28 FM(IP7_31_28) IP7_31_28 \
276 FM(IP8_3_0) IP8_3_0 \
277 FM(IP8_7_4) IP8_7_4 \
278 FM(IP8_11_8) IP8_11_8 \
279 FM(IP8_15_12) IP8_15_12 \
280 FM(IP8_19_16) IP8_19_16 \
281 FM(IP8_23_20) IP8_23_20 \
282 FM(IP8_27_24) IP8_27_24 \
283 FM(IP8_31_28) IP8_31_28
285 /* MOD_SEL0 */ /* 0 */ /* 1 */
286 #define MOD_SEL0_11 FM(SEL_I2C3_0) FM(SEL_I2C3_1)
287 #define MOD_SEL0_10 FM(SEL_HSCIF0_0) FM(SEL_HSCIF0_1)
288 #define MOD_SEL0_9 FM(SEL_SCIF1_0) FM(SEL_SCIF1_1)
289 #define MOD_SEL0_8 FM(SEL_CANFD0_0) FM(SEL_CANFD0_1)
290 #define MOD_SEL0_7 FM(SEL_PWM4_0) FM(SEL_PWM4_1)
291 #define MOD_SEL0_6 FM(SEL_PWM3_0) FM(SEL_PWM3_1)
292 #define MOD_SEL0_5 FM(SEL_PWM2_0) FM(SEL_PWM2_1)
293 #define MOD_SEL0_4 FM(SEL_PWM1_0) FM(SEL_PWM1_1)
294 #define MOD_SEL0_3 FM(SEL_PWM0_0) FM(SEL_PWM0_1)
295 #define MOD_SEL0_2 FM(SEL_RFSO_0) FM(SEL_RFSO_1)
296 #define MOD_SEL0_1 FM(SEL_RSP_0) FM(SEL_RSP_1)
297 #define MOD_SEL0_0 FM(SEL_TMU_0) FM(SEL_TMU_1)
299 #define PINMUX_MOD_SELS \
301 MOD_SEL0_11 \
302 MOD_SEL0_10 \
303 MOD_SEL0_9 \
304 MOD_SEL0_8 \
305 MOD_SEL0_7 \
306 MOD_SEL0_6 \
307 MOD_SEL0_5 \
308 MOD_SEL0_4 \
309 MOD_SEL0_3 \
310 MOD_SEL0_2 \
311 MOD_SEL0_1 \
312 MOD_SEL0_0
314 enum {
315 PINMUX_RESERVED = 0,
317 PINMUX_DATA_BEGIN,
318 GP_ALL(DATA),
319 PINMUX_DATA_END,
321 #define F_(x, y)
322 #define FM(x) FN_##x,
323 PINMUX_FUNCTION_BEGIN,
324 GP_ALL(FN),
325 PINMUX_GPSR
326 PINMUX_IPSR
327 PINMUX_MOD_SELS
328 PINMUX_FUNCTION_END,
329 #undef F_
330 #undef FM
332 #define F_(x, y)
333 #define FM(x) x##_MARK,
334 PINMUX_MARK_BEGIN,
335 PINMUX_GPSR
336 PINMUX_IPSR
337 PINMUX_MOD_SELS
338 PINMUX_MARK_END,
339 #undef F_
340 #undef FM
343 static const u16 pinmux_data[] = {
344 PINMUX_DATA_GP_ALL(),
346 PINMUX_SINGLE(AVB0_RX_CTL),
347 PINMUX_SINGLE(AVB0_RXC),
348 PINMUX_SINGLE(AVB0_RD0),
349 PINMUX_SINGLE(AVB0_RD1),
350 PINMUX_SINGLE(AVB0_RD2),
351 PINMUX_SINGLE(AVB0_RD3),
352 PINMUX_SINGLE(AVB0_TX_CTL),
353 PINMUX_SINGLE(AVB0_TXC),
354 PINMUX_SINGLE(AVB0_TD0),
355 PINMUX_SINGLE(AVB0_TD1),
356 PINMUX_SINGLE(AVB0_TD2),
357 PINMUX_SINGLE(AVB0_TD3),
358 PINMUX_SINGLE(AVB0_TXCREFCLK),
359 PINMUX_SINGLE(AVB0_MDIO),
360 PINMUX_SINGLE(AVB0_MDC),
361 PINMUX_SINGLE(AVB0_MAGIC),
362 PINMUX_SINGLE(AVB0_PHY_INT),
363 PINMUX_SINGLE(AVB0_LINK),
364 PINMUX_SINGLE(AVB0_AVTP_MATCH),
366 PINMUX_SINGLE(QSPI0_SPCLK),
367 PINMUX_SINGLE(QSPI0_MOSI_IO0),
368 PINMUX_SINGLE(QSPI0_MISO_IO1),
369 PINMUX_SINGLE(QSPI0_IO2),
370 PINMUX_SINGLE(QSPI0_IO3),
371 PINMUX_SINGLE(QSPI0_SSL),
372 PINMUX_SINGLE(QSPI1_SPCLK),
373 PINMUX_SINGLE(QSPI1_MOSI_IO0),
374 PINMUX_SINGLE(QSPI1_MISO_IO1),
375 PINMUX_SINGLE(QSPI1_IO2),
376 PINMUX_SINGLE(QSPI1_IO3),
377 PINMUX_SINGLE(QSPI1_SSL),
378 PINMUX_SINGLE(RPC_RESET_N),
379 PINMUX_SINGLE(RPC_WP_N),
380 PINMUX_SINGLE(RPC_INT_N),
382 /* IPSR0 */
383 PINMUX_IPSR_GPSR(IP0_3_0, DU_DR2),
384 PINMUX_IPSR_GPSR(IP0_3_0, HSCK0),
385 PINMUX_IPSR_GPSR(IP0_3_0, A0),
387 PINMUX_IPSR_GPSR(IP0_7_4, DU_DR3),
388 PINMUX_IPSR_GPSR(IP0_7_4, HRTS0_N),
389 PINMUX_IPSR_GPSR(IP0_7_4, A1),
391 PINMUX_IPSR_GPSR(IP0_11_8, DU_DR4),
392 PINMUX_IPSR_GPSR(IP0_11_8, HCTS0_N),
393 PINMUX_IPSR_GPSR(IP0_11_8, A2),
395 PINMUX_IPSR_GPSR(IP0_15_12, DU_DR5),
396 PINMUX_IPSR_GPSR(IP0_15_12, HTX0),
397 PINMUX_IPSR_GPSR(IP0_15_12, A3),
399 PINMUX_IPSR_GPSR(IP0_19_16, DU_DR6),
400 PINMUX_IPSR_GPSR(IP0_19_16, MSIOF3_RXD),
401 PINMUX_IPSR_GPSR(IP0_19_16, A4),
403 PINMUX_IPSR_GPSR(IP0_23_20, DU_DR7),
404 PINMUX_IPSR_GPSR(IP0_23_20, MSIOF3_TXD),
405 PINMUX_IPSR_GPSR(IP0_23_20, A5),
407 PINMUX_IPSR_GPSR(IP0_27_24, DU_DG2),
408 PINMUX_IPSR_GPSR(IP0_27_24, MSIOF3_SS1),
409 PINMUX_IPSR_GPSR(IP0_27_24, A6),
411 PINMUX_IPSR_GPSR(IP0_31_28, DU_DG3),
412 PINMUX_IPSR_GPSR(IP0_31_28, MSIOF3_SS2),
413 PINMUX_IPSR_GPSR(IP0_31_28, A7),
414 PINMUX_IPSR_GPSR(IP0_31_28, PWMFSW0),
416 /* IPSR1 */
417 PINMUX_IPSR_GPSR(IP1_3_0, DU_DG4),
418 PINMUX_IPSR_GPSR(IP1_3_0, A8),
419 PINMUX_IPSR_MSEL(IP1_3_0, FSO_CFE_0_N_A, SEL_RFSO_0),
421 PINMUX_IPSR_GPSR(IP1_7_4, DU_DG5),
422 PINMUX_IPSR_GPSR(IP1_7_4, A9),
423 PINMUX_IPSR_MSEL(IP1_7_4, FSO_CFE_1_N_A, SEL_RFSO_0),
425 PINMUX_IPSR_GPSR(IP1_11_8, DU_DG6),
426 PINMUX_IPSR_GPSR(IP1_11_8, A10),
427 PINMUX_IPSR_MSEL(IP1_11_8, FSO_TOE_N_A, SEL_RFSO_0),
429 PINMUX_IPSR_GPSR(IP1_15_12, DU_DG7),
430 PINMUX_IPSR_GPSR(IP1_15_12, A11),
431 PINMUX_IPSR_GPSR(IP1_15_12, IRQ1),
433 PINMUX_IPSR_GPSR(IP1_19_16, DU_DB2),
434 PINMUX_IPSR_GPSR(IP1_19_16, A12),
435 PINMUX_IPSR_GPSR(IP1_19_16, IRQ2),
437 PINMUX_IPSR_GPSR(IP1_23_20, DU_DB3),
438 PINMUX_IPSR_GPSR(IP1_23_20, A13),
439 PINMUX_IPSR_GPSR(IP1_23_20, FXR_CLKOUT1),
441 PINMUX_IPSR_GPSR(IP1_27_24, DU_DB4),
442 PINMUX_IPSR_GPSR(IP1_27_24, A14),
443 PINMUX_IPSR_GPSR(IP1_27_24, FXR_CLKOUT2),
445 PINMUX_IPSR_GPSR(IP1_31_28, DU_DB5),
446 PINMUX_IPSR_GPSR(IP1_31_28, A15),
447 PINMUX_IPSR_GPSR(IP1_31_28, FXR_TXENA_N),
449 /* IPSR2 */
450 PINMUX_IPSR_GPSR(IP2_3_0, DU_DB6),
451 PINMUX_IPSR_GPSR(IP2_3_0, A16),
452 PINMUX_IPSR_GPSR(IP2_3_0, FXR_TXENB_N),
454 PINMUX_IPSR_GPSR(IP2_7_4, DU_DB7),
455 PINMUX_IPSR_GPSR(IP2_7_4, A17),
457 PINMUX_IPSR_GPSR(IP2_11_8, DU_DOTCLKOUT),
458 PINMUX_IPSR_MSEL(IP2_11_8, SCIF_CLK_A, SEL_HSCIF0_0),
459 PINMUX_IPSR_GPSR(IP2_11_8, A18),
461 PINMUX_IPSR_GPSR(IP2_15_12, DU_EXHSYNC_DU_HSYNC),
462 PINMUX_IPSR_GPSR(IP2_15_12, HRX0),
463 PINMUX_IPSR_GPSR(IP2_15_12, A19),
464 PINMUX_IPSR_GPSR(IP2_15_12, IRQ3),
466 PINMUX_IPSR_GPSR(IP2_19_16, DU_EXVSYNC_DU_VSYNC),
467 PINMUX_IPSR_GPSR(IP2_19_16, MSIOF3_SCK),
469 PINMUX_IPSR_GPSR(IP2_23_20, DU_EXODDF_DU_ODDF_DISP_CDE),
470 PINMUX_IPSR_GPSR(IP2_23_20, MSIOF3_SYNC),
472 PINMUX_IPSR_GPSR(IP2_27_24, IRQ0),
473 PINMUX_IPSR_GPSR(IP2_27_24, CC5_OSCOUT),
475 PINMUX_IPSR_GPSR(IP2_31_28, VI0_CLK),
476 PINMUX_IPSR_GPSR(IP2_31_28, MSIOF2_SCK),
477 PINMUX_IPSR_GPSR(IP2_31_28, SCK3),
478 PINMUX_IPSR_GPSR(IP2_31_28, HSCK3),
480 /* IPSR3 */
481 PINMUX_IPSR_GPSR(IP3_3_0, VI0_CLKENB),
482 PINMUX_IPSR_GPSR(IP3_3_0, MSIOF2_RXD),
483 PINMUX_IPSR_GPSR(IP3_3_0, RX3),
484 PINMUX_IPSR_GPSR(IP3_3_0, RD_WR_N),
485 PINMUX_IPSR_GPSR(IP3_3_0, HCTS3_N),
487 PINMUX_IPSR_GPSR(IP3_7_4, VI0_HSYNC_N),
488 PINMUX_IPSR_GPSR(IP3_7_4, MSIOF2_TXD),
489 PINMUX_IPSR_GPSR(IP3_7_4, TX3),
490 PINMUX_IPSR_GPSR(IP3_7_4, HRTS3_N),
492 PINMUX_IPSR_GPSR(IP3_11_8, VI0_VSYNC_N),
493 PINMUX_IPSR_GPSR(IP3_11_8, MSIOF2_SYNC),
494 PINMUX_IPSR_GPSR(IP3_11_8, CTS3_N),
495 PINMUX_IPSR_GPSR(IP3_11_8, HTX3),
497 PINMUX_IPSR_GPSR(IP3_15_12, VI0_DATA0),
498 PINMUX_IPSR_GPSR(IP3_15_12, MSIOF2_SS1),
499 PINMUX_IPSR_GPSR(IP3_15_12, RTS3_N_TANS),
500 PINMUX_IPSR_GPSR(IP3_15_12, HRX3),
502 PINMUX_IPSR_GPSR(IP3_19_16, VI0_DATA1),
503 PINMUX_IPSR_GPSR(IP3_19_16, MSIOF2_SS2),
504 PINMUX_IPSR_GPSR(IP3_19_16, SCK1),
505 PINMUX_IPSR_MSEL(IP3_19_16, SPEEDIN_A, SEL_RSP_0),
507 PINMUX_IPSR_GPSR(IP3_23_20, VI0_DATA2),
508 PINMUX_IPSR_GPSR(IP3_23_20, AVB0_AVTP_PPS),
509 PINMUX_IPSR_MSEL(IP3_23_20, SDA3_A, SEL_I2C3_0),
511 PINMUX_IPSR_GPSR(IP3_27_24, VI0_DATA3),
512 PINMUX_IPSR_GPSR(IP3_27_24, HSCK1),
513 PINMUX_IPSR_MSEL(IP3_27_24, SCL3_A, SEL_I2C3_0),
515 PINMUX_IPSR_GPSR(IP3_31_28, VI0_DATA4),
516 PINMUX_IPSR_GPSR(IP3_31_28, HRTS1_N),
517 PINMUX_IPSR_MSEL(IP3_31_28, RX1_A, SEL_SCIF1_0),
519 /* IPSR4 */
520 PINMUX_IPSR_GPSR(IP4_3_0, VI0_DATA5),
521 PINMUX_IPSR_GPSR(IP4_3_0, HCTS1_N),
522 PINMUX_IPSR_MSEL(IP4_3_0, TX1_A, SEL_SCIF1_0),
524 PINMUX_IPSR_GPSR(IP4_7_4, VI0_DATA6),
525 PINMUX_IPSR_GPSR(IP4_7_4, HTX1),
526 PINMUX_IPSR_GPSR(IP4_7_4, CTS1_N),
528 PINMUX_IPSR_GPSR(IP4_11_8, VI0_DATA7),
529 PINMUX_IPSR_GPSR(IP4_11_8, HRX1),
530 PINMUX_IPSR_GPSR(IP4_11_8, RTS1_N_TANS),
532 PINMUX_IPSR_GPSR(IP4_15_12, VI0_DATA8),
533 PINMUX_IPSR_GPSR(IP4_15_12, HSCK2),
534 PINMUX_IPSR_MSEL(IP4_15_12, PWM0_A, SEL_PWM0_0),
536 PINMUX_IPSR_GPSR(IP4_19_16, VI0_DATA9),
537 PINMUX_IPSR_GPSR(IP4_19_16, HCTS2_N),
538 PINMUX_IPSR_MSEL(IP4_19_16, PWM1_A, SEL_PWM1_0),
539 PINMUX_IPSR_MSEL(IP4_19_16, FSO_CFE_0_N_B, SEL_RFSO_1),
541 PINMUX_IPSR_GPSR(IP4_23_20, VI0_DATA10),
542 PINMUX_IPSR_GPSR(IP4_23_20, HRTS2_N),
543 PINMUX_IPSR_MSEL(IP4_23_20, PWM2_A, SEL_PWM2_0),
544 PINMUX_IPSR_MSEL(IP4_23_20, FSO_CFE_1_N_B, SEL_RFSO_1),
546 PINMUX_IPSR_GPSR(IP4_27_24, VI0_DATA11),
547 PINMUX_IPSR_GPSR(IP4_27_24, HTX2),
548 PINMUX_IPSR_MSEL(IP4_27_24, PWM3_A, SEL_PWM3_0),
549 PINMUX_IPSR_MSEL(IP4_27_24, FSO_TOE_N_B, SEL_RFSO_1),
551 PINMUX_IPSR_GPSR(IP4_31_28, VI0_FIELD),
552 PINMUX_IPSR_GPSR(IP4_31_28, HRX2),
553 PINMUX_IPSR_MSEL(IP4_31_28, PWM4_A, SEL_PWM4_0),
554 PINMUX_IPSR_GPSR(IP4_31_28, CS1_N),
555 PINMUX_IPSR_GPSR(IP4_31_28, FSCLKST2_N_A),
557 /* IPSR5 */
558 PINMUX_IPSR_GPSR(IP5_3_0, VI1_CLK),
559 PINMUX_IPSR_GPSR(IP5_3_0, MSIOF1_RXD),
560 PINMUX_IPSR_GPSR(IP5_3_0, CS0_N),
562 PINMUX_IPSR_GPSR(IP5_7_4, VI1_CLKENB),
563 PINMUX_IPSR_GPSR(IP5_7_4, MSIOF1_TXD),
564 PINMUX_IPSR_GPSR(IP5_7_4, D0),
566 PINMUX_IPSR_GPSR(IP5_11_8, VI1_HSYNC_N),
567 PINMUX_IPSR_GPSR(IP5_11_8, MSIOF1_SCK),
568 PINMUX_IPSR_GPSR(IP5_11_8, D1),
570 PINMUX_IPSR_GPSR(IP5_15_12, VI1_VSYNC_N),
571 PINMUX_IPSR_GPSR(IP5_15_12, MSIOF1_SYNC),
572 PINMUX_IPSR_GPSR(IP5_15_12, D2),
574 PINMUX_IPSR_GPSR(IP5_19_16, VI1_DATA0),
575 PINMUX_IPSR_GPSR(IP5_19_16, MSIOF1_SS1),
576 PINMUX_IPSR_GPSR(IP5_19_16, D3),
578 PINMUX_IPSR_GPSR(IP5_23_20, VI1_DATA1),
579 PINMUX_IPSR_GPSR(IP5_23_20, MSIOF1_SS2),
580 PINMUX_IPSR_GPSR(IP5_23_20, D4),
581 PINMUX_IPSR_GPSR(IP5_23_20, MMC_CMD),
583 PINMUX_IPSR_GPSR(IP5_27_24, VI1_DATA2),
584 PINMUX_IPSR_MSEL(IP5_27_24, CANFD0_TX_B, SEL_CANFD0_1),
585 PINMUX_IPSR_GPSR(IP5_27_24, D5),
586 PINMUX_IPSR_GPSR(IP5_27_24, MMC_D0),
588 PINMUX_IPSR_GPSR(IP5_31_28, VI1_DATA3),
589 PINMUX_IPSR_MSEL(IP5_31_28, CANFD0_RX_B, SEL_CANFD0_1),
590 PINMUX_IPSR_GPSR(IP5_31_28, D6),
591 PINMUX_IPSR_GPSR(IP5_31_28, MMC_D1),
593 /* IPSR6 */
594 PINMUX_IPSR_GPSR(IP6_3_0, VI1_DATA4),
595 PINMUX_IPSR_MSEL(IP6_3_0, CANFD_CLK_B, SEL_CANFD0_1),
596 PINMUX_IPSR_GPSR(IP6_3_0, D7),
597 PINMUX_IPSR_GPSR(IP6_3_0, MMC_D2),
599 PINMUX_IPSR_GPSR(IP6_7_4, VI1_DATA5),
600 PINMUX_IPSR_GPSR(IP6_7_4, SCK4),
601 PINMUX_IPSR_GPSR(IP6_7_4, D8),
602 PINMUX_IPSR_GPSR(IP6_7_4, MMC_D3),
604 PINMUX_IPSR_GPSR(IP6_11_8, VI1_DATA6),
605 PINMUX_IPSR_GPSR(IP6_11_8, RX4),
606 PINMUX_IPSR_GPSR(IP6_11_8, D9),
607 PINMUX_IPSR_GPSR(IP6_11_8, MMC_CLK),
609 PINMUX_IPSR_GPSR(IP6_15_12, VI1_DATA7),
610 PINMUX_IPSR_GPSR(IP6_15_12, TX4),
611 PINMUX_IPSR_GPSR(IP6_15_12, D10),
612 PINMUX_IPSR_GPSR(IP6_15_12, MMC_D4),
614 PINMUX_IPSR_GPSR(IP6_19_16, VI1_DATA8),
615 PINMUX_IPSR_GPSR(IP6_19_16, CTS4_N),
616 PINMUX_IPSR_GPSR(IP6_19_16, D11),
617 PINMUX_IPSR_GPSR(IP6_19_16, MMC_D5),
619 PINMUX_IPSR_GPSR(IP6_23_20, VI1_DATA9),
620 PINMUX_IPSR_GPSR(IP6_23_20, RTS4_N_TANS),
621 PINMUX_IPSR_GPSR(IP6_23_20, D12),
622 PINMUX_IPSR_GPSR(IP6_23_20, MMC_D6),
623 PINMUX_IPSR_MSEL(IP6_23_20, SCL3_B, SEL_I2C3_1),
625 PINMUX_IPSR_GPSR(IP6_27_24, VI1_DATA10),
626 PINMUX_IPSR_GPSR(IP6_27_24, D13),
627 PINMUX_IPSR_GPSR(IP6_27_24, MMC_D7),
628 PINMUX_IPSR_MSEL(IP6_27_24, SDA3_B, SEL_I2C3_1),
630 PINMUX_IPSR_GPSR(IP6_31_28, VI1_DATA11),
631 PINMUX_IPSR_GPSR(IP6_31_28, SCL4),
632 PINMUX_IPSR_GPSR(IP6_31_28, IRQ4),
633 PINMUX_IPSR_GPSR(IP6_31_28, D14),
634 PINMUX_IPSR_GPSR(IP6_31_28, MMC_WP),
636 /* IPSR7 */
637 PINMUX_IPSR_GPSR(IP7_3_0, VI1_FIELD),
638 PINMUX_IPSR_GPSR(IP7_3_0, SDA4),
639 PINMUX_IPSR_GPSR(IP7_3_0, IRQ5),
640 PINMUX_IPSR_GPSR(IP7_3_0, D15),
641 PINMUX_IPSR_GPSR(IP7_3_0, MMC_CD),
643 PINMUX_IPSR_GPSR(IP7_7_4, SCL0),
644 PINMUX_IPSR_GPSR(IP7_7_4, DU_DR0),
645 PINMUX_IPSR_GPSR(IP7_7_4, TPU0TO0),
646 PINMUX_IPSR_GPSR(IP7_7_4, CLKOUT),
647 PINMUX_IPSR_GPSR(IP7_7_4, MSIOF0_RXD),
649 PINMUX_IPSR_GPSR(IP7_11_8, SDA0),
650 PINMUX_IPSR_GPSR(IP7_11_8, DU_DR1),
651 PINMUX_IPSR_GPSR(IP7_11_8, TPU0TO1),
652 PINMUX_IPSR_GPSR(IP7_11_8, BS_N),
653 PINMUX_IPSR_GPSR(IP7_11_8, SCK0),
654 PINMUX_IPSR_GPSR(IP7_11_8, MSIOF0_TXD),
656 PINMUX_IPSR_GPSR(IP7_15_12, SCL1),
657 PINMUX_IPSR_GPSR(IP7_15_12, DU_DG0),
658 PINMUX_IPSR_GPSR(IP7_15_12, TPU0TO2),
659 PINMUX_IPSR_GPSR(IP7_15_12, RD_N),
660 PINMUX_IPSR_GPSR(IP7_15_12, CTS0_N),
661 PINMUX_IPSR_GPSR(IP7_15_12, MSIOF0_SCK),
663 PINMUX_IPSR_GPSR(IP7_19_16, SDA1),
664 PINMUX_IPSR_GPSR(IP7_19_16, DU_DG1),
665 PINMUX_IPSR_GPSR(IP7_19_16, TPU0TO3),
666 PINMUX_IPSR_GPSR(IP7_19_16, WE0_N),
667 PINMUX_IPSR_GPSR(IP7_19_16, RTS0_N_TANS),
668 PINMUX_IPSR_GPSR(IP7_19_16, MSIOF0_SYNC),
670 PINMUX_IPSR_GPSR(IP7_23_20, SCL2),
671 PINMUX_IPSR_GPSR(IP7_23_20, DU_DB0),
672 PINMUX_IPSR_MSEL(IP7_23_20, TCLK1_A, SEL_TMU_0),
673 PINMUX_IPSR_GPSR(IP7_23_20, WE1_N),
674 PINMUX_IPSR_GPSR(IP7_23_20, RX0),
675 PINMUX_IPSR_GPSR(IP7_23_20, MSIOF0_SS1),
677 PINMUX_IPSR_GPSR(IP7_27_24, SDA2),
678 PINMUX_IPSR_GPSR(IP7_27_24, DU_DB1),
679 PINMUX_IPSR_MSEL(IP7_27_24, TCLK2_A, SEL_TMU_0),
680 PINMUX_IPSR_GPSR(IP7_27_24, EX_WAIT0),
681 PINMUX_IPSR_GPSR(IP7_27_24, TX0),
682 PINMUX_IPSR_GPSR(IP7_27_24, MSIOF0_SS2),
684 PINMUX_IPSR_GPSR(IP7_31_28, AVB0_AVTP_CAPTURE),
685 PINMUX_IPSR_GPSR(IP7_31_28, FSCLKST2_N_B),
687 /* IPSR8 */
688 PINMUX_IPSR_MSEL(IP8_3_0, CANFD0_TX_A, SEL_CANFD0_0),
689 PINMUX_IPSR_GPSR(IP8_3_0, FXR_TXDA),
690 PINMUX_IPSR_MSEL(IP8_3_0, PWM0_B, SEL_PWM0_1),
691 PINMUX_IPSR_GPSR(IP8_3_0, DU_DISP),
692 PINMUX_IPSR_GPSR(IP8_3_0, FSCLKST2_N_C),
694 PINMUX_IPSR_MSEL(IP8_7_4, CANFD0_RX_A, SEL_CANFD0_0),
695 PINMUX_IPSR_GPSR(IP8_7_4, RXDA_EXTFXR),
696 PINMUX_IPSR_MSEL(IP8_7_4, PWM1_B, SEL_PWM1_1),
697 PINMUX_IPSR_GPSR(IP8_7_4, DU_CDE),
699 PINMUX_IPSR_GPSR(IP8_11_8, CANFD1_TX),
700 PINMUX_IPSR_GPSR(IP8_11_8, FXR_TXDB),
701 PINMUX_IPSR_MSEL(IP8_11_8, PWM2_B, SEL_PWM2_1),
702 PINMUX_IPSR_MSEL(IP8_11_8, TCLK1_B, SEL_TMU_1),
703 PINMUX_IPSR_MSEL(IP8_11_8, TX1_B, SEL_SCIF1_1),
705 PINMUX_IPSR_GPSR(IP8_15_12, CANFD1_RX),
706 PINMUX_IPSR_GPSR(IP8_15_12, RXDB_EXTFXR),
707 PINMUX_IPSR_MSEL(IP8_15_12, PWM3_B, SEL_PWM3_1),
708 PINMUX_IPSR_MSEL(IP8_15_12, TCLK2_B, SEL_TMU_1),
709 PINMUX_IPSR_MSEL(IP8_15_12, RX1_B, SEL_SCIF1_1),
711 PINMUX_IPSR_MSEL(IP8_19_16, CANFD_CLK_A, SEL_CANFD0_0),
712 PINMUX_IPSR_GPSR(IP8_19_16, CLK_EXTFXR),
713 PINMUX_IPSR_MSEL(IP8_19_16, PWM4_B, SEL_PWM4_1),
714 PINMUX_IPSR_MSEL(IP8_19_16, SPEEDIN_B, SEL_RSP_1),
715 PINMUX_IPSR_MSEL(IP8_19_16, SCIF_CLK_B, SEL_HSCIF0_1),
717 PINMUX_IPSR_GPSR(IP8_23_20, DIGRF_CLKIN),
718 PINMUX_IPSR_GPSR(IP8_23_20, DIGRF_CLKEN_IN),
720 PINMUX_IPSR_GPSR(IP8_27_24, DIGRF_CLKOUT),
721 PINMUX_IPSR_GPSR(IP8_27_24, DIGRF_CLKEN_OUT),
724 static const struct sh_pfc_pin pinmux_pins[] = {
725 PINMUX_GPIO_GP_ALL(),
728 /* - AVB0 ------------------------------------------------------------------- */
729 static const unsigned int avb0_link_pins[] = {
730 /* AVB0_LINK */
731 RCAR_GP_PIN(1, 18),
733 static const unsigned int avb0_link_mux[] = {
734 AVB0_LINK_MARK,
736 static const unsigned int avb0_magic_pins[] = {
737 /* AVB0_MAGIC */
738 RCAR_GP_PIN(1, 16),
740 static const unsigned int avb0_magic_mux[] = {
741 AVB0_MAGIC_MARK,
743 static const unsigned int avb0_phy_int_pins[] = {
744 /* AVB0_PHY_INT */
745 RCAR_GP_PIN(1, 17),
747 static const unsigned int avb0_phy_int_mux[] = {
748 AVB0_PHY_INT_MARK,
750 static const unsigned int avb0_mdio_pins[] = {
751 /* AVB0_MDC, AVB0_MDIO */
752 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14),
754 static const unsigned int avb0_mdio_mux[] = {
755 AVB0_MDC_MARK, AVB0_MDIO_MARK,
757 static const unsigned int avb0_rgmii_pins[] = {
759 * AVB0_TX_CTL, AVB0_TXC, AVB0_TD0, AVB0_TD1, AVB0_TD2, AVB0_TD3,
760 * AVB0_RX_CTL, AVB0_RXC, AVB0_RD0, AVB0_RD1, AVB0_RD2, AVB0_RD3
762 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 8),
763 RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 10),
764 RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 12),
765 RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 2),
766 RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 4),
767 RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
769 static const unsigned int avb0_rgmii_mux[] = {
770 AVB0_TX_CTL_MARK, AVB0_TXC_MARK,
771 AVB0_TD0_MARK, AVB0_TD1_MARK, AVB0_TD2_MARK, AVB0_TD3_MARK,
772 AVB0_RX_CTL_MARK, AVB0_RXC_MARK,
773 AVB0_RD0_MARK, AVB0_RD1_MARK, AVB0_RD2_MARK, AVB0_RD3_MARK,
775 static const unsigned int avb0_txcrefclk_pins[] = {
776 /* AVB0_TXCREFCLK */
777 RCAR_GP_PIN(1, 13),
779 static const unsigned int avb0_txcrefclk_mux[] = {
780 AVB0_TXCREFCLK_MARK,
782 static const unsigned int avb0_avtp_pps_pins[] = {
783 /* AVB0_AVTP_PPS */
784 RCAR_GP_PIN(2, 6),
786 static const unsigned int avb0_avtp_pps_mux[] = {
787 AVB0_AVTP_PPS_MARK,
789 static const unsigned int avb0_avtp_capture_pins[] = {
790 /* AVB0_AVTP_CAPTURE */
791 RCAR_GP_PIN(1, 20),
793 static const unsigned int avb0_avtp_capture_mux[] = {
794 AVB0_AVTP_CAPTURE_MARK,
796 static const unsigned int avb0_avtp_match_pins[] = {
797 /* AVB0_AVTP_MATCH */
798 RCAR_GP_PIN(1, 19),
800 static const unsigned int avb0_avtp_match_mux[] = {
801 AVB0_AVTP_MATCH_MARK,
804 /* - CANFD Clock ------------------------------------------------------------ */
805 static const unsigned int canfd_clk_a_pins[] = {
806 /* CANFD_CLK */
807 RCAR_GP_PIN(1, 25),
809 static const unsigned int canfd_clk_a_mux[] = {
810 CANFD_CLK_A_MARK,
812 static const unsigned int canfd_clk_b_pins[] = {
813 /* CANFD_CLK */
814 RCAR_GP_PIN(3, 8),
816 static const unsigned int canfd_clk_b_mux[] = {
817 CANFD_CLK_B_MARK,
820 /* - CANFD0 ----------------------------------------------------------------- */
821 static const unsigned int canfd0_data_a_pins[] = {
822 /* TX, RX */
823 RCAR_GP_PIN(1, 21), RCAR_GP_PIN(1, 22),
825 static const unsigned int canfd0_data_a_mux[] = {
826 CANFD0_TX_A_MARK, CANFD0_RX_A_MARK,
828 static const unsigned int canfd0_data_b_pins[] = {
829 /* TX, RX */
830 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
832 static const unsigned int canfd0_data_b_mux[] = {
833 CANFD0_TX_B_MARK, CANFD0_RX_B_MARK,
836 /* - CANFD1 ----------------------------------------------------------------- */
837 static const unsigned int canfd1_data_pins[] = {
838 /* TX, RX */
839 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
841 static const unsigned int canfd1_data_mux[] = {
842 CANFD1_TX_MARK, CANFD1_RX_MARK,
845 /* - DU --------------------------------------------------------------------- */
846 static const unsigned int du_rgb666_pins[] = {
847 /* R[7:2], G[7:2], B[7:2] */
848 RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 3),
849 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 0),
850 RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 9),
851 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 6),
852 RCAR_GP_PIN(0, 17), RCAR_GP_PIN(0, 16), RCAR_GP_PIN(0, 15),
853 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 12),
855 static const unsigned int du_rgb666_mux[] = {
856 DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK,
857 DU_DR4_MARK, DU_DR3_MARK, DU_DR2_MARK,
858 DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK,
859 DU_DG4_MARK, DU_DG3_MARK, DU_DG2_MARK,
860 DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK,
861 DU_DB4_MARK, DU_DB3_MARK, DU_DB2_MARK,
863 static const unsigned int du_clk_out_pins[] = {
864 /* DOTCLKOUT */
865 RCAR_GP_PIN(0, 18),
867 static const unsigned int du_clk_out_mux[] = {
868 DU_DOTCLKOUT_MARK,
870 static const unsigned int du_sync_pins[] = {
871 /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
872 RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 19),
874 static const unsigned int du_sync_mux[] = {
875 DU_EXVSYNC_DU_VSYNC_MARK, DU_EXHSYNC_DU_HSYNC_MARK
877 static const unsigned int du_oddf_pins[] = {
878 /* EXODDF/ODDF/DISP/CDE */
879 RCAR_GP_PIN(0, 21),
881 static const unsigned int du_oddf_mux[] = {
882 DU_EXODDF_DU_ODDF_DISP_CDE_MARK,
884 static const unsigned int du_cde_pins[] = {
885 /* CDE */
886 RCAR_GP_PIN(1, 22),
888 static const unsigned int du_cde_mux[] = {
889 DU_CDE_MARK,
891 static const unsigned int du_disp_pins[] = {
892 /* DISP */
893 RCAR_GP_PIN(1, 21),
895 static const unsigned int du_disp_mux[] = {
896 DU_DISP_MARK,
899 /* - HSCIF0 ----------------------------------------------------------------- */
900 static const unsigned int hscif0_data_pins[] = {
901 /* HRX, HTX */
902 RCAR_GP_PIN(0, 19), RCAR_GP_PIN(0, 3),
904 static const unsigned int hscif0_data_mux[] = {
905 HRX0_MARK, HTX0_MARK,
907 static const unsigned int hscif0_clk_pins[] = {
908 /* HSCK */
909 RCAR_GP_PIN(0, 0),
911 static const unsigned int hscif0_clk_mux[] = {
912 HSCK0_MARK,
914 static const unsigned int hscif0_ctrl_pins[] = {
915 /* HRTS#, HCTS# */
916 RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 2),
918 static const unsigned int hscif0_ctrl_mux[] = {
919 HRTS0_N_MARK, HCTS0_N_MARK,
922 /* - HSCIF1 ----------------------------------------------------------------- */
923 static const unsigned int hscif1_data_pins[] = {
924 /* HRX, HTX */
925 RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 10),
927 static const unsigned int hscif1_data_mux[] = {
928 HRX1_MARK, HTX1_MARK,
930 static const unsigned int hscif1_clk_pins[] = {
931 /* HSCK */
932 RCAR_GP_PIN(2, 7),
934 static const unsigned int hscif1_clk_mux[] = {
935 HSCK1_MARK,
937 static const unsigned int hscif1_ctrl_pins[] = {
938 /* HRTS#, HCTS# */
939 RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
941 static const unsigned int hscif1_ctrl_mux[] = {
942 HRTS1_N_MARK, HCTS1_N_MARK,
945 /* - HSCIF2 ----------------------------------------------------------------- */
946 static const unsigned int hscif2_data_pins[] = {
947 /* HRX, HTX */
948 RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 15),
950 static const unsigned int hscif2_data_mux[] = {
951 HRX2_MARK, HTX2_MARK,
953 static const unsigned int hscif2_clk_pins[] = {
954 /* HSCK */
955 RCAR_GP_PIN(2, 12),
957 static const unsigned int hscif2_clk_mux[] = {
958 HSCK2_MARK,
960 static const unsigned int hscif2_ctrl_pins[] = {
961 /* HRTS#, HCTS# */
962 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
964 static const unsigned int hscif2_ctrl_mux[] = {
965 HRTS2_N_MARK, HCTS2_N_MARK,
968 /* - HSCIF3 ----------------------------------------------------------------- */
969 static const unsigned int hscif3_data_pins[] = {
970 /* HRX, HTX */
971 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 3),
973 static const unsigned int hscif3_data_mux[] = {
974 HRX3_MARK, HTX3_MARK,
976 static const unsigned int hscif3_clk_pins[] = {
977 /* HSCK */
978 RCAR_GP_PIN(2, 0),
980 static const unsigned int hscif3_clk_mux[] = {
981 HSCK3_MARK,
983 static const unsigned int hscif3_ctrl_pins[] = {
984 /* HRTS#, HCTS# */
985 RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 1),
987 static const unsigned int hscif3_ctrl_mux[] = {
988 HRTS3_N_MARK, HCTS3_N_MARK,
991 /* - I2C0 ------------------------------------------------------------------- */
992 static const unsigned int i2c0_pins[] = {
993 /* SDA, SCL */
994 RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 0),
996 static const unsigned int i2c0_mux[] = {
997 SDA0_MARK, SCL0_MARK,
1000 /* - I2C1 ------------------------------------------------------------------- */
1001 static const unsigned int i2c1_pins[] = {
1002 /* SDA, SCL */
1003 RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 2),
1005 static const unsigned int i2c1_mux[] = {
1006 SDA1_MARK, SCL1_MARK,
1009 /* - I2C2 ------------------------------------------------------------------- */
1010 static const unsigned int i2c2_pins[] = {
1011 /* SDA, SCL */
1012 RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 4),
1014 static const unsigned int i2c2_mux[] = {
1015 SDA2_MARK, SCL2_MARK,
1018 /* - I2C3 ------------------------------------------------------------------- */
1019 static const unsigned int i2c3_a_pins[] = {
1020 /* SDA, SCL */
1021 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
1023 static const unsigned int i2c3_a_mux[] = {
1024 SDA3_A_MARK, SCL3_A_MARK,
1026 static const unsigned int i2c3_b_pins[] = {
1027 /* SDA, SCL */
1028 RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 13),
1030 static const unsigned int i2c3_b_mux[] = {
1031 SDA3_B_MARK, SCL3_B_MARK,
1034 /* - I2C4 ------------------------------------------------------------------- */
1035 static const unsigned int i2c4_pins[] = {
1036 /* SDA, SCL */
1037 RCAR_GP_PIN(3, 16), RCAR_GP_PIN(3, 15),
1039 static const unsigned int i2c4_mux[] = {
1040 SDA4_MARK, SCL4_MARK,
1043 /* - INTC-EX ---------------------------------------------------------------- */
1044 static const unsigned int intc_ex_irq0_pins[] = {
1045 /* IRQ0 */
1046 RCAR_GP_PIN(1, 0),
1048 static const unsigned int intc_ex_irq0_mux[] = {
1049 IRQ0_MARK,
1051 static const unsigned int intc_ex_irq1_pins[] = {
1052 /* IRQ1 */
1053 RCAR_GP_PIN(0, 11),
1055 static const unsigned int intc_ex_irq1_mux[] = {
1056 IRQ1_MARK,
1058 static const unsigned int intc_ex_irq2_pins[] = {
1059 /* IRQ2 */
1060 RCAR_GP_PIN(0, 12),
1062 static const unsigned int intc_ex_irq2_mux[] = {
1063 IRQ2_MARK,
1065 static const unsigned int intc_ex_irq3_pins[] = {
1066 /* IRQ3 */
1067 RCAR_GP_PIN(0, 19),
1069 static const unsigned int intc_ex_irq3_mux[] = {
1070 IRQ3_MARK,
1072 static const unsigned int intc_ex_irq4_pins[] = {
1073 /* IRQ4 */
1074 RCAR_GP_PIN(3, 15),
1076 static const unsigned int intc_ex_irq4_mux[] = {
1077 IRQ4_MARK,
1079 static const unsigned int intc_ex_irq5_pins[] = {
1080 /* IRQ5 */
1081 RCAR_GP_PIN(3, 16),
1083 static const unsigned int intc_ex_irq5_mux[] = {
1084 IRQ5_MARK,
1087 /* - MMC -------------------------------------------------------------------- */
1088 static const unsigned int mmc_data1_pins[] = {
1089 /* D0 */
1090 RCAR_GP_PIN(3, 6),
1092 static const unsigned int mmc_data1_mux[] = {
1093 MMC_D0_MARK,
1095 static const unsigned int mmc_data4_pins[] = {
1096 /* D[0:3] */
1097 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
1098 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
1100 static const unsigned int mmc_data4_mux[] = {
1101 MMC_D0_MARK, MMC_D1_MARK,
1102 MMC_D2_MARK, MMC_D3_MARK,
1104 static const unsigned int mmc_data8_pins[] = {
1105 /* D[0:7] */
1106 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
1107 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
1108 RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 12),
1109 RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14),
1111 static const unsigned int mmc_data8_mux[] = {
1112 MMC_D0_MARK, MMC_D1_MARK,
1113 MMC_D2_MARK, MMC_D3_MARK,
1114 MMC_D4_MARK, MMC_D5_MARK,
1115 MMC_D6_MARK, MMC_D7_MARK,
1117 static const unsigned int mmc_ctrl_pins[] = {
1118 /* CLK, CMD */
1119 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 5),
1121 static const unsigned int mmc_ctrl_mux[] = {
1122 MMC_CLK_MARK, MMC_CMD_MARK,
1124 static const unsigned int mmc_cd_pins[] = {
1125 /* CD */
1126 RCAR_GP_PIN(3, 16),
1128 static const unsigned int mmc_cd_mux[] = {
1129 MMC_CD_MARK,
1131 static const unsigned int mmc_wp_pins[] = {
1132 /* WP */
1133 RCAR_GP_PIN(3, 15),
1135 static const unsigned int mmc_wp_mux[] = {
1136 MMC_WP_MARK,
1139 /* - MSIOF0 ----------------------------------------------------------------- */
1140 static const unsigned int msiof0_clk_pins[] = {
1141 /* SCK */
1142 RCAR_GP_PIN(4, 2),
1144 static const unsigned int msiof0_clk_mux[] = {
1145 MSIOF0_SCK_MARK,
1147 static const unsigned int msiof0_sync_pins[] = {
1148 /* SYNC */
1149 RCAR_GP_PIN(4, 3),
1151 static const unsigned int msiof0_sync_mux[] = {
1152 MSIOF0_SYNC_MARK,
1154 static const unsigned int msiof0_ss1_pins[] = {
1155 /* SS1 */
1156 RCAR_GP_PIN(4, 4),
1158 static const unsigned int msiof0_ss1_mux[] = {
1159 MSIOF0_SS1_MARK,
1161 static const unsigned int msiof0_ss2_pins[] = {
1162 /* SS2 */
1163 RCAR_GP_PIN(4, 5),
1165 static const unsigned int msiof0_ss2_mux[] = {
1166 MSIOF0_SS2_MARK,
1168 static const unsigned int msiof0_txd_pins[] = {
1169 /* TXD */
1170 RCAR_GP_PIN(4, 1),
1172 static const unsigned int msiof0_txd_mux[] = {
1173 MSIOF0_TXD_MARK,
1175 static const unsigned int msiof0_rxd_pins[] = {
1176 /* RXD */
1177 RCAR_GP_PIN(4, 0),
1179 static const unsigned int msiof0_rxd_mux[] = {
1180 MSIOF0_RXD_MARK,
1183 /* - MSIOF1 ----------------------------------------------------------------- */
1184 static const unsigned int msiof1_clk_pins[] = {
1185 /* SCK */
1186 RCAR_GP_PIN(3, 2),
1188 static const unsigned int msiof1_clk_mux[] = {
1189 MSIOF1_SCK_MARK,
1191 static const unsigned int msiof1_sync_pins[] = {
1192 /* SYNC */
1193 RCAR_GP_PIN(3, 3),
1195 static const unsigned int msiof1_sync_mux[] = {
1196 MSIOF1_SYNC_MARK,
1198 static const unsigned int msiof1_ss1_pins[] = {
1199 /* SS1 */
1200 RCAR_GP_PIN(3, 4),
1202 static const unsigned int msiof1_ss1_mux[] = {
1203 MSIOF1_SS1_MARK,
1205 static const unsigned int msiof1_ss2_pins[] = {
1206 /* SS2 */
1207 RCAR_GP_PIN(3, 5),
1209 static const unsigned int msiof1_ss2_mux[] = {
1210 MSIOF1_SS2_MARK,
1212 static const unsigned int msiof1_txd_pins[] = {
1213 /* TXD */
1214 RCAR_GP_PIN(3, 1),
1216 static const unsigned int msiof1_txd_mux[] = {
1217 MSIOF1_TXD_MARK,
1219 static const unsigned int msiof1_rxd_pins[] = {
1220 /* RXD */
1221 RCAR_GP_PIN(3, 0),
1223 static const unsigned int msiof1_rxd_mux[] = {
1224 MSIOF1_RXD_MARK,
1227 /* - MSIOF2 ----------------------------------------------------------------- */
1228 static const unsigned int msiof2_clk_pins[] = {
1229 /* SCK */
1230 RCAR_GP_PIN(2, 0),
1232 static const unsigned int msiof2_clk_mux[] = {
1233 MSIOF2_SCK_MARK,
1235 static const unsigned int msiof2_sync_pins[] = {
1236 /* SYNC */
1237 RCAR_GP_PIN(2, 3),
1239 static const unsigned int msiof2_sync_mux[] = {
1240 MSIOF2_SYNC_MARK,
1242 static const unsigned int msiof2_ss1_pins[] = {
1243 /* SS1 */
1244 RCAR_GP_PIN(2, 4),
1246 static const unsigned int msiof2_ss1_mux[] = {
1247 MSIOF2_SS1_MARK,
1249 static const unsigned int msiof2_ss2_pins[] = {
1250 /* SS2 */
1251 RCAR_GP_PIN(2, 5),
1253 static const unsigned int msiof2_ss2_mux[] = {
1254 MSIOF2_SS2_MARK,
1256 static const unsigned int msiof2_txd_pins[] = {
1257 /* TXD */
1258 RCAR_GP_PIN(2, 2),
1260 static const unsigned int msiof2_txd_mux[] = {
1261 MSIOF2_TXD_MARK,
1263 static const unsigned int msiof2_rxd_pins[] = {
1264 /* RXD */
1265 RCAR_GP_PIN(2, 1),
1267 static const unsigned int msiof2_rxd_mux[] = {
1268 MSIOF2_RXD_MARK,
1271 /* - MSIOF3 ----------------------------------------------------------------- */
1272 static const unsigned int msiof3_clk_pins[] = {
1273 /* SCK */
1274 RCAR_GP_PIN(0, 20),
1276 static const unsigned int msiof3_clk_mux[] = {
1277 MSIOF3_SCK_MARK,
1279 static const unsigned int msiof3_sync_pins[] = {
1280 /* SYNC */
1281 RCAR_GP_PIN(0, 21),
1283 static const unsigned int msiof3_sync_mux[] = {
1284 MSIOF3_SYNC_MARK,
1286 static const unsigned int msiof3_ss1_pins[] = {
1287 /* SS1 */
1288 RCAR_GP_PIN(0, 6),
1290 static const unsigned int msiof3_ss1_mux[] = {
1291 MSIOF3_SS1_MARK,
1293 static const unsigned int msiof3_ss2_pins[] = {
1294 /* SS2 */
1295 RCAR_GP_PIN(0, 7),
1297 static const unsigned int msiof3_ss2_mux[] = {
1298 MSIOF3_SS2_MARK,
1300 static const unsigned int msiof3_txd_pins[] = {
1301 /* TXD */
1302 RCAR_GP_PIN(0, 5),
1304 static const unsigned int msiof3_txd_mux[] = {
1305 MSIOF3_TXD_MARK,
1307 static const unsigned int msiof3_rxd_pins[] = {
1308 /* RXD */
1309 RCAR_GP_PIN(0, 4),
1311 static const unsigned int msiof3_rxd_mux[] = {
1312 MSIOF3_RXD_MARK,
1315 /* - PWM0 ------------------------------------------------------------------- */
1316 static const unsigned int pwm0_a_pins[] = {
1317 RCAR_GP_PIN(2, 12),
1319 static const unsigned int pwm0_a_mux[] = {
1320 PWM0_A_MARK,
1322 static const unsigned int pwm0_b_pins[] = {
1323 RCAR_GP_PIN(1, 21),
1325 static const unsigned int pwm0_b_mux[] = {
1326 PWM0_B_MARK,
1329 /* - PWM1 ------------------------------------------------------------------- */
1330 static const unsigned int pwm1_a_pins[] = {
1331 RCAR_GP_PIN(2, 13),
1333 static const unsigned int pwm1_a_mux[] = {
1334 PWM1_A_MARK,
1336 static const unsigned int pwm1_b_pins[] = {
1337 RCAR_GP_PIN(1, 22),
1339 static const unsigned int pwm1_b_mux[] = {
1340 PWM1_B_MARK,
1343 /* - PWM2 ------------------------------------------------------------------- */
1344 static const unsigned int pwm2_a_pins[] = {
1345 RCAR_GP_PIN(2, 14),
1347 static const unsigned int pwm2_a_mux[] = {
1348 PWM2_A_MARK,
1350 static const unsigned int pwm2_b_pins[] = {
1351 RCAR_GP_PIN(1, 23),
1353 static const unsigned int pwm2_b_mux[] = {
1354 PWM2_B_MARK,
1357 /* - PWM3 ------------------------------------------------------------------- */
1358 static const unsigned int pwm3_a_pins[] = {
1359 RCAR_GP_PIN(2, 15),
1361 static const unsigned int pwm3_a_mux[] = {
1362 PWM3_A_MARK,
1364 static const unsigned int pwm3_b_pins[] = {
1365 RCAR_GP_PIN(1, 24),
1367 static const unsigned int pwm3_b_mux[] = {
1368 PWM3_B_MARK,
1371 /* - PWM4 ------------------------------------------------------------------- */
1372 static const unsigned int pwm4_a_pins[] = {
1373 RCAR_GP_PIN(2, 16),
1375 static const unsigned int pwm4_a_mux[] = {
1376 PWM4_A_MARK,
1378 static const unsigned int pwm4_b_pins[] = {
1379 RCAR_GP_PIN(1, 25),
1381 static const unsigned int pwm4_b_mux[] = {
1382 PWM4_B_MARK,
1385 /* - QSPI0 ------------------------------------------------------------------ */
1386 static const unsigned int qspi0_ctrl_pins[] = {
1387 /* SPCLK, SSL */
1388 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 5),
1390 static const unsigned int qspi0_ctrl_mux[] = {
1391 QSPI0_SPCLK_MARK, QSPI0_SSL_MARK,
1393 static const unsigned int qspi0_data2_pins[] = {
1394 /* MOSI_IO0, MISO_IO1 */
1395 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
1397 static const unsigned int qspi0_data2_mux[] = {
1398 QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
1400 static const unsigned int qspi0_data4_pins[] = {
1401 /* MOSI_IO0, MISO_IO1, IO2, IO3 */
1402 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
1403 RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 4),
1405 static const unsigned int qspi0_data4_mux[] = {
1406 QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
1407 QSPI0_IO2_MARK, QSPI0_IO3_MARK
1410 /* - QSPI1 ------------------------------------------------------------------ */
1411 static const unsigned int qspi1_ctrl_pins[] = {
1412 /* SPCLK, SSL */
1413 RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 11),
1415 static const unsigned int qspi1_ctrl_mux[] = {
1416 QSPI1_SPCLK_MARK, QSPI1_SSL_MARK,
1418 static const unsigned int qspi1_data2_pins[] = {
1419 /* MOSI_IO0, MISO_IO1 */
1420 RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 8),
1422 static const unsigned int qspi1_data2_mux[] = {
1423 QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
1425 static const unsigned int qspi1_data4_pins[] = {
1426 /* MOSI_IO0, MISO_IO1, IO2, IO3 */
1427 RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 8),
1428 RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 10),
1430 static const unsigned int qspi1_data4_mux[] = {
1431 QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
1432 QSPI1_IO2_MARK, QSPI1_IO3_MARK
1435 /* - SCIF Clock ------------------------------------------------------------- */
1436 static const unsigned int scif_clk_a_pins[] = {
1437 /* SCIF_CLK */
1438 RCAR_GP_PIN(0, 18),
1440 static const unsigned int scif_clk_a_mux[] = {
1441 SCIF_CLK_A_MARK,
1443 static const unsigned int scif_clk_b_pins[] = {
1444 /* SCIF_CLK */
1445 RCAR_GP_PIN(1, 25),
1447 static const unsigned int scif_clk_b_mux[] = {
1448 SCIF_CLK_B_MARK,
1451 /* - SCIF0 ------------------------------------------------------------------ */
1452 static const unsigned int scif0_data_pins[] = {
1453 /* RX, TX */
1454 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
1456 static const unsigned int scif0_data_mux[] = {
1457 RX0_MARK, TX0_MARK,
1459 static const unsigned int scif0_clk_pins[] = {
1460 /* SCK */
1461 RCAR_GP_PIN(4, 1),
1463 static const unsigned int scif0_clk_mux[] = {
1464 SCK0_MARK,
1466 static const unsigned int scif0_ctrl_pins[] = {
1467 /* RTS#, CTS# */
1468 RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 2),
1470 static const unsigned int scif0_ctrl_mux[] = {
1471 RTS0_N_TANS_MARK, CTS0_N_MARK,
1474 /* - SCIF1 ------------------------------------------------------------------ */
1475 static const unsigned int scif1_data_a_pins[] = {
1476 /* RX, TX */
1477 RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
1479 static const unsigned int scif1_data_a_mux[] = {
1480 RX1_A_MARK, TX1_A_MARK,
1482 static const unsigned int scif1_clk_pins[] = {
1483 /* SCK */
1484 RCAR_GP_PIN(2, 5),
1486 static const unsigned int scif1_clk_mux[] = {
1487 SCK1_MARK,
1489 static const unsigned int scif1_ctrl_pins[] = {
1490 /* RTS#, CTS# */
1491 RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 10),
1493 static const unsigned int scif1_ctrl_mux[] = {
1494 RTS1_N_TANS_MARK, CTS1_N_MARK,
1496 static const unsigned int scif1_data_b_pins[] = {
1497 /* RX, TX */
1498 RCAR_GP_PIN(1, 24), RCAR_GP_PIN(1, 23),
1500 static const unsigned int scif1_data_b_mux[] = {
1501 RX1_B_MARK, TX1_B_MARK,
1504 /* - SCIF3 ------------------------------------------------------------------ */
1505 static const unsigned int scif3_data_pins[] = {
1506 /* RX, TX */
1507 RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2),
1509 static const unsigned int scif3_data_mux[] = {
1510 RX3_MARK, TX3_MARK,
1512 static const unsigned int scif3_clk_pins[] = {
1513 /* SCK */
1514 RCAR_GP_PIN(2, 0),
1516 static const unsigned int scif3_clk_mux[] = {
1517 SCK3_MARK,
1519 static const unsigned int scif3_ctrl_pins[] = {
1520 /* RTS#, CTS# */
1521 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 3),
1523 static const unsigned int scif3_ctrl_mux[] = {
1524 RTS3_N_TANS_MARK, CTS3_N_MARK,
1527 /* - SCIF4 ------------------------------------------------------------------ */
1528 static const unsigned int scif4_data_pins[] = {
1529 /* RX, TX */
1530 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
1532 static const unsigned int scif4_data_mux[] = {
1533 RX4_MARK, TX4_MARK,
1535 static const unsigned int scif4_clk_pins[] = {
1536 /* SCK */
1537 RCAR_GP_PIN(3, 9),
1539 static const unsigned int scif4_clk_mux[] = {
1540 SCK4_MARK,
1542 static const unsigned int scif4_ctrl_pins[] = {
1543 /* RTS#, CTS# */
1544 RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12),
1546 static const unsigned int scif4_ctrl_mux[] = {
1547 RTS4_N_TANS_MARK, CTS4_N_MARK,
1550 /* - TMU -------------------------------------------------------------------- */
1551 static const unsigned int tmu_tclk1_a_pins[] = {
1552 /* TCLK1 */
1553 RCAR_GP_PIN(4, 4),
1555 static const unsigned int tmu_tclk1_a_mux[] = {
1556 TCLK1_A_MARK,
1558 static const unsigned int tmu_tclk1_b_pins[] = {
1559 /* TCLK1 */
1560 RCAR_GP_PIN(1, 23),
1562 static const unsigned int tmu_tclk1_b_mux[] = {
1563 TCLK1_B_MARK,
1565 static const unsigned int tmu_tclk2_a_pins[] = {
1566 /* TCLK2 */
1567 RCAR_GP_PIN(4, 5),
1569 static const unsigned int tmu_tclk2_a_mux[] = {
1570 TCLK2_A_MARK,
1572 static const unsigned int tmu_tclk2_b_pins[] = {
1573 /* TCLK2 */
1574 RCAR_GP_PIN(1, 24),
1576 static const unsigned int tmu_tclk2_b_mux[] = {
1577 TCLK2_B_MARK,
1580 /* - VIN0 ------------------------------------------------------------------- */
1581 static const union vin_data12 vin0_data_pins = {
1582 .data12 = {
1583 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
1584 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
1585 RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
1586 RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
1587 RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
1588 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15),
1591 static const union vin_data12 vin0_data_mux = {
1592 .data12 = {
1593 VI0_DATA0_MARK, VI0_DATA1_MARK,
1594 VI0_DATA2_MARK, VI0_DATA3_MARK,
1595 VI0_DATA4_MARK, VI0_DATA5_MARK,
1596 VI0_DATA6_MARK, VI0_DATA7_MARK,
1597 VI0_DATA8_MARK, VI0_DATA9_MARK,
1598 VI0_DATA10_MARK, VI0_DATA11_MARK,
1601 static const unsigned int vin0_sync_pins[] = {
1602 /* HSYNC#, VSYNC# */
1603 RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
1605 static const unsigned int vin0_sync_mux[] = {
1606 VI0_HSYNC_N_MARK, VI0_VSYNC_N_MARK,
1608 static const unsigned int vin0_field_pins[] = {
1609 /* FIELD */
1610 RCAR_GP_PIN(2, 16),
1612 static const unsigned int vin0_field_mux[] = {
1613 VI0_FIELD_MARK,
1615 static const unsigned int vin0_clkenb_pins[] = {
1616 /* CLKENB */
1617 RCAR_GP_PIN(2, 1),
1619 static const unsigned int vin0_clkenb_mux[] = {
1620 VI0_CLKENB_MARK,
1622 static const unsigned int vin0_clk_pins[] = {
1623 /* CLK */
1624 RCAR_GP_PIN(2, 0),
1626 static const unsigned int vin0_clk_mux[] = {
1627 VI0_CLK_MARK,
1630 /* - VIN1 ------------------------------------------------------------------- */
1631 static const union vin_data12 vin1_data_pins = {
1632 .data12 = {
1633 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
1634 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
1635 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
1636 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
1637 RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
1638 RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
1641 static const union vin_data12 vin1_data_mux = {
1642 .data12 = {
1643 VI1_DATA0_MARK, VI1_DATA1_MARK,
1644 VI1_DATA2_MARK, VI1_DATA3_MARK,
1645 VI1_DATA4_MARK, VI1_DATA5_MARK,
1646 VI1_DATA6_MARK, VI1_DATA7_MARK,
1647 VI1_DATA8_MARK, VI1_DATA9_MARK,
1648 VI1_DATA10_MARK, VI1_DATA11_MARK,
1651 static const unsigned int vin1_sync_pins[] = {
1652 /* HSYNC#, VSYNC# */
1653 RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
1655 static const unsigned int vin1_sync_mux[] = {
1656 VI1_HSYNC_N_MARK, VI1_VSYNC_N_MARK,
1658 static const unsigned int vin1_field_pins[] = {
1659 RCAR_GP_PIN(3, 16),
1661 static const unsigned int vin1_field_mux[] = {
1662 /* FIELD */
1663 VI1_FIELD_MARK,
1665 static const unsigned int vin1_clkenb_pins[] = {
1666 RCAR_GP_PIN(3, 1),
1668 static const unsigned int vin1_clkenb_mux[] = {
1669 /* CLKENB */
1670 VI1_CLKENB_MARK,
1672 static const unsigned int vin1_clk_pins[] = {
1673 RCAR_GP_PIN(3, 0),
1675 static const unsigned int vin1_clk_mux[] = {
1676 /* CLK */
1677 VI1_CLK_MARK,
1680 static const struct sh_pfc_pin_group pinmux_groups[] = {
1681 SH_PFC_PIN_GROUP(avb0_link),
1682 SH_PFC_PIN_GROUP(avb0_magic),
1683 SH_PFC_PIN_GROUP(avb0_phy_int),
1684 SH_PFC_PIN_GROUP(avb0_mdio),
1685 SH_PFC_PIN_GROUP(avb0_rgmii),
1686 SH_PFC_PIN_GROUP(avb0_txcrefclk),
1687 SH_PFC_PIN_GROUP(avb0_avtp_pps),
1688 SH_PFC_PIN_GROUP(avb0_avtp_capture),
1689 SH_PFC_PIN_GROUP(avb0_avtp_match),
1690 SH_PFC_PIN_GROUP(canfd_clk_a),
1691 SH_PFC_PIN_GROUP(canfd_clk_b),
1692 SH_PFC_PIN_GROUP(canfd0_data_a),
1693 SH_PFC_PIN_GROUP(canfd0_data_b),
1694 SH_PFC_PIN_GROUP(canfd1_data),
1695 SH_PFC_PIN_GROUP(du_rgb666),
1696 SH_PFC_PIN_GROUP(du_clk_out),
1697 SH_PFC_PIN_GROUP(du_sync),
1698 SH_PFC_PIN_GROUP(du_oddf),
1699 SH_PFC_PIN_GROUP(du_cde),
1700 SH_PFC_PIN_GROUP(du_disp),
1701 SH_PFC_PIN_GROUP(hscif0_data),
1702 SH_PFC_PIN_GROUP(hscif0_clk),
1703 SH_PFC_PIN_GROUP(hscif0_ctrl),
1704 SH_PFC_PIN_GROUP(hscif1_data),
1705 SH_PFC_PIN_GROUP(hscif1_clk),
1706 SH_PFC_PIN_GROUP(hscif1_ctrl),
1707 SH_PFC_PIN_GROUP(hscif2_data),
1708 SH_PFC_PIN_GROUP(hscif2_clk),
1709 SH_PFC_PIN_GROUP(hscif2_ctrl),
1710 SH_PFC_PIN_GROUP(hscif3_data),
1711 SH_PFC_PIN_GROUP(hscif3_clk),
1712 SH_PFC_PIN_GROUP(hscif3_ctrl),
1713 SH_PFC_PIN_GROUP(i2c0),
1714 SH_PFC_PIN_GROUP(i2c1),
1715 SH_PFC_PIN_GROUP(i2c2),
1716 SH_PFC_PIN_GROUP(i2c3_a),
1717 SH_PFC_PIN_GROUP(i2c3_b),
1718 SH_PFC_PIN_GROUP(i2c4),
1719 SH_PFC_PIN_GROUP(intc_ex_irq0),
1720 SH_PFC_PIN_GROUP(intc_ex_irq1),
1721 SH_PFC_PIN_GROUP(intc_ex_irq2),
1722 SH_PFC_PIN_GROUP(intc_ex_irq3),
1723 SH_PFC_PIN_GROUP(intc_ex_irq4),
1724 SH_PFC_PIN_GROUP(intc_ex_irq5),
1725 SH_PFC_PIN_GROUP(mmc_data1),
1726 SH_PFC_PIN_GROUP(mmc_data4),
1727 SH_PFC_PIN_GROUP(mmc_data8),
1728 SH_PFC_PIN_GROUP(mmc_ctrl),
1729 SH_PFC_PIN_GROUP(mmc_cd),
1730 SH_PFC_PIN_GROUP(mmc_wp),
1731 SH_PFC_PIN_GROUP(msiof0_clk),
1732 SH_PFC_PIN_GROUP(msiof0_sync),
1733 SH_PFC_PIN_GROUP(msiof0_ss1),
1734 SH_PFC_PIN_GROUP(msiof0_ss2),
1735 SH_PFC_PIN_GROUP(msiof0_txd),
1736 SH_PFC_PIN_GROUP(msiof0_rxd),
1737 SH_PFC_PIN_GROUP(msiof1_clk),
1738 SH_PFC_PIN_GROUP(msiof1_sync),
1739 SH_PFC_PIN_GROUP(msiof1_ss1),
1740 SH_PFC_PIN_GROUP(msiof1_ss2),
1741 SH_PFC_PIN_GROUP(msiof1_txd),
1742 SH_PFC_PIN_GROUP(msiof1_rxd),
1743 SH_PFC_PIN_GROUP(msiof2_clk),
1744 SH_PFC_PIN_GROUP(msiof2_sync),
1745 SH_PFC_PIN_GROUP(msiof2_ss1),
1746 SH_PFC_PIN_GROUP(msiof2_ss2),
1747 SH_PFC_PIN_GROUP(msiof2_txd),
1748 SH_PFC_PIN_GROUP(msiof2_rxd),
1749 SH_PFC_PIN_GROUP(msiof3_clk),
1750 SH_PFC_PIN_GROUP(msiof3_sync),
1751 SH_PFC_PIN_GROUP(msiof3_ss1),
1752 SH_PFC_PIN_GROUP(msiof3_ss2),
1753 SH_PFC_PIN_GROUP(msiof3_txd),
1754 SH_PFC_PIN_GROUP(msiof3_rxd),
1755 SH_PFC_PIN_GROUP(pwm0_a),
1756 SH_PFC_PIN_GROUP(pwm0_b),
1757 SH_PFC_PIN_GROUP(pwm1_a),
1758 SH_PFC_PIN_GROUP(pwm1_b),
1759 SH_PFC_PIN_GROUP(pwm2_a),
1760 SH_PFC_PIN_GROUP(pwm2_b),
1761 SH_PFC_PIN_GROUP(pwm3_a),
1762 SH_PFC_PIN_GROUP(pwm3_b),
1763 SH_PFC_PIN_GROUP(pwm4_a),
1764 SH_PFC_PIN_GROUP(pwm4_b),
1765 SH_PFC_PIN_GROUP(qspi0_ctrl),
1766 SH_PFC_PIN_GROUP(qspi0_data2),
1767 SH_PFC_PIN_GROUP(qspi0_data4),
1768 SH_PFC_PIN_GROUP(qspi1_ctrl),
1769 SH_PFC_PIN_GROUP(qspi1_data2),
1770 SH_PFC_PIN_GROUP(qspi1_data4),
1771 SH_PFC_PIN_GROUP(scif_clk_a),
1772 SH_PFC_PIN_GROUP(scif_clk_b),
1773 SH_PFC_PIN_GROUP(scif0_data),
1774 SH_PFC_PIN_GROUP(scif0_clk),
1775 SH_PFC_PIN_GROUP(scif0_ctrl),
1776 SH_PFC_PIN_GROUP(scif1_data_a),
1777 SH_PFC_PIN_GROUP(scif1_clk),
1778 SH_PFC_PIN_GROUP(scif1_ctrl),
1779 SH_PFC_PIN_GROUP(scif1_data_b),
1780 SH_PFC_PIN_GROUP(scif3_data),
1781 SH_PFC_PIN_GROUP(scif3_clk),
1782 SH_PFC_PIN_GROUP(scif3_ctrl),
1783 SH_PFC_PIN_GROUP(scif4_data),
1784 SH_PFC_PIN_GROUP(scif4_clk),
1785 SH_PFC_PIN_GROUP(scif4_ctrl),
1786 SH_PFC_PIN_GROUP(tmu_tclk1_a),
1787 SH_PFC_PIN_GROUP(tmu_tclk1_b),
1788 SH_PFC_PIN_GROUP(tmu_tclk2_a),
1789 SH_PFC_PIN_GROUP(tmu_tclk2_b),
1790 VIN_DATA_PIN_GROUP(vin0_data, 8),
1791 VIN_DATA_PIN_GROUP(vin0_data, 10),
1792 VIN_DATA_PIN_GROUP(vin0_data, 12),
1793 SH_PFC_PIN_GROUP(vin0_sync),
1794 SH_PFC_PIN_GROUP(vin0_field),
1795 SH_PFC_PIN_GROUP(vin0_clkenb),
1796 SH_PFC_PIN_GROUP(vin0_clk),
1797 VIN_DATA_PIN_GROUP(vin1_data, 8),
1798 VIN_DATA_PIN_GROUP(vin1_data, 10),
1799 VIN_DATA_PIN_GROUP(vin1_data, 12),
1800 SH_PFC_PIN_GROUP(vin1_sync),
1801 SH_PFC_PIN_GROUP(vin1_field),
1802 SH_PFC_PIN_GROUP(vin1_clkenb),
1803 SH_PFC_PIN_GROUP(vin1_clk),
1806 static const char * const avb0_groups[] = {
1807 "avb0_link",
1808 "avb0_magic",
1809 "avb0_phy_int",
1810 "avb0_mdio",
1811 "avb0_rgmii",
1812 "avb0_txcrefclk",
1813 "avb0_avtp_pps",
1814 "avb0_avtp_capture",
1815 "avb0_avtp_match",
1818 static const char * const canfd_clk_groups[] = {
1819 "canfd_clk_a",
1820 "canfd_clk_b",
1823 static const char * const canfd0_groups[] = {
1824 "canfd0_data_a",
1825 "canfd0_data_b",
1828 static const char * const canfd1_groups[] = {
1829 "canfd1_data",
1832 static const char * const du_groups[] = {
1833 "du_rgb666",
1834 "du_clk_out",
1835 "du_sync",
1836 "du_oddf",
1837 "du_cde",
1838 "du_disp",
1841 static const char * const hscif0_groups[] = {
1842 "hscif0_data",
1843 "hscif0_clk",
1844 "hscif0_ctrl",
1847 static const char * const hscif1_groups[] = {
1848 "hscif1_data",
1849 "hscif1_clk",
1850 "hscif1_ctrl",
1853 static const char * const hscif2_groups[] = {
1854 "hscif2_data",
1855 "hscif2_clk",
1856 "hscif2_ctrl",
1859 static const char * const hscif3_groups[] = {
1860 "hscif3_data",
1861 "hscif3_clk",
1862 "hscif3_ctrl",
1865 static const char * const i2c0_groups[] = {
1866 "i2c0",
1869 static const char * const i2c1_groups[] = {
1870 "i2c1",
1873 static const char * const i2c2_groups[] = {
1874 "i2c2",
1877 static const char * const i2c3_groups[] = {
1878 "i2c3_a",
1879 "i2c3_b",
1882 static const char * const i2c4_groups[] = {
1883 "i2c4",
1886 static const char * const intc_ex_groups[] = {
1887 "intc_ex_irq0",
1888 "intc_ex_irq1",
1889 "intc_ex_irq2",
1890 "intc_ex_irq3",
1891 "intc_ex_irq4",
1892 "intc_ex_irq5",
1895 static const char * const mmc_groups[] = {
1896 "mmc_data1",
1897 "mmc_data4",
1898 "mmc_data8",
1899 "mmc_ctrl",
1900 "mmc_cd",
1901 "mmc_wp",
1904 static const char * const msiof0_groups[] = {
1905 "msiof0_clk",
1906 "msiof0_sync",
1907 "msiof0_ss1",
1908 "msiof0_ss2",
1909 "msiof0_txd",
1910 "msiof0_rxd",
1913 static const char * const msiof1_groups[] = {
1914 "msiof1_clk",
1915 "msiof1_sync",
1916 "msiof1_ss1",
1917 "msiof1_ss2",
1918 "msiof1_txd",
1919 "msiof1_rxd",
1922 static const char * const msiof2_groups[] = {
1923 "msiof2_clk",
1924 "msiof2_sync",
1925 "msiof2_ss1",
1926 "msiof2_ss2",
1927 "msiof2_txd",
1928 "msiof2_rxd",
1931 static const char * const msiof3_groups[] = {
1932 "msiof3_clk",
1933 "msiof3_sync",
1934 "msiof3_ss1",
1935 "msiof3_ss2",
1936 "msiof3_txd",
1937 "msiof3_rxd",
1940 static const char * const pwm0_groups[] = {
1941 "pwm0_a",
1942 "pwm0_b",
1945 static const char * const pwm1_groups[] = {
1946 "pwm1_a",
1947 "pwm1_b",
1950 static const char * const pwm2_groups[] = {
1951 "pwm2_a",
1952 "pwm2_b",
1955 static const char * const pwm3_groups[] = {
1956 "pwm3_a",
1957 "pwm3_b",
1960 static const char * const pwm4_groups[] = {
1961 "pwm4_a",
1962 "pwm4_b",
1965 static const char * const qspi0_groups[] = {
1966 "qspi0_ctrl",
1967 "qspi0_data2",
1968 "qspi0_data4",
1971 static const char * const qspi1_groups[] = {
1972 "qspi1_ctrl",
1973 "qspi1_data2",
1974 "qspi1_data4",
1977 static const char * const scif_clk_groups[] = {
1978 "scif_clk_a",
1979 "scif_clk_b",
1982 static const char * const scif0_groups[] = {
1983 "scif0_data",
1984 "scif0_clk",
1985 "scif0_ctrl",
1988 static const char * const scif1_groups[] = {
1989 "scif1_data_a",
1990 "scif1_clk",
1991 "scif1_ctrl",
1992 "scif1_data_b",
1995 static const char * const scif3_groups[] = {
1996 "scif3_data",
1997 "scif3_clk",
1998 "scif3_ctrl",
2001 static const char * const scif4_groups[] = {
2002 "scif4_data",
2003 "scif4_clk",
2004 "scif4_ctrl",
2007 static const char * const tmu_groups[] = {
2008 "tmu_tclk1_a",
2009 "tmu_tclk1_b",
2010 "tmu_tclk2_a",
2011 "tmu_tclk2_b",
2014 static const char * const vin0_groups[] = {
2015 "vin0_data8",
2016 "vin0_data10",
2017 "vin0_data12",
2018 "vin0_sync",
2019 "vin0_field",
2020 "vin0_clkenb",
2021 "vin0_clk",
2024 static const char * const vin1_groups[] = {
2025 "vin1_data8",
2026 "vin1_data10",
2027 "vin1_data12",
2028 "vin1_sync",
2029 "vin1_field",
2030 "vin1_clkenb",
2031 "vin1_clk",
2034 static const struct sh_pfc_function pinmux_functions[] = {
2035 SH_PFC_FUNCTION(avb0),
2036 SH_PFC_FUNCTION(canfd_clk),
2037 SH_PFC_FUNCTION(canfd0),
2038 SH_PFC_FUNCTION(canfd1),
2039 SH_PFC_FUNCTION(du),
2040 SH_PFC_FUNCTION(hscif0),
2041 SH_PFC_FUNCTION(hscif1),
2042 SH_PFC_FUNCTION(hscif2),
2043 SH_PFC_FUNCTION(hscif3),
2044 SH_PFC_FUNCTION(i2c0),
2045 SH_PFC_FUNCTION(i2c1),
2046 SH_PFC_FUNCTION(i2c2),
2047 SH_PFC_FUNCTION(i2c3),
2048 SH_PFC_FUNCTION(i2c4),
2049 SH_PFC_FUNCTION(intc_ex),
2050 SH_PFC_FUNCTION(mmc),
2051 SH_PFC_FUNCTION(msiof0),
2052 SH_PFC_FUNCTION(msiof1),
2053 SH_PFC_FUNCTION(msiof2),
2054 SH_PFC_FUNCTION(msiof3),
2055 SH_PFC_FUNCTION(pwm0),
2056 SH_PFC_FUNCTION(pwm1),
2057 SH_PFC_FUNCTION(pwm2),
2058 SH_PFC_FUNCTION(pwm3),
2059 SH_PFC_FUNCTION(pwm4),
2060 SH_PFC_FUNCTION(qspi0),
2061 SH_PFC_FUNCTION(qspi1),
2062 SH_PFC_FUNCTION(scif_clk),
2063 SH_PFC_FUNCTION(scif0),
2064 SH_PFC_FUNCTION(scif1),
2065 SH_PFC_FUNCTION(scif3),
2066 SH_PFC_FUNCTION(scif4),
2067 SH_PFC_FUNCTION(tmu),
2068 SH_PFC_FUNCTION(vin0),
2069 SH_PFC_FUNCTION(vin1),
2072 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2073 #define F_(x, y) FN_##y
2074 #define FM(x) FN_##x
2075 { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1) {
2076 0, 0,
2077 0, 0,
2078 0, 0,
2079 0, 0,
2080 0, 0,
2081 0, 0,
2082 0, 0,
2083 0, 0,
2084 0, 0,
2085 0, 0,
2086 GP_0_21_FN, GPSR0_21,
2087 GP_0_20_FN, GPSR0_20,
2088 GP_0_19_FN, GPSR0_19,
2089 GP_0_18_FN, GPSR0_18,
2090 GP_0_17_FN, GPSR0_17,
2091 GP_0_16_FN, GPSR0_16,
2092 GP_0_15_FN, GPSR0_15,
2093 GP_0_14_FN, GPSR0_14,
2094 GP_0_13_FN, GPSR0_13,
2095 GP_0_12_FN, GPSR0_12,
2096 GP_0_11_FN, GPSR0_11,
2097 GP_0_10_FN, GPSR0_10,
2098 GP_0_9_FN, GPSR0_9,
2099 GP_0_8_FN, GPSR0_8,
2100 GP_0_7_FN, GPSR0_7,
2101 GP_0_6_FN, GPSR0_6,
2102 GP_0_5_FN, GPSR0_5,
2103 GP_0_4_FN, GPSR0_4,
2104 GP_0_3_FN, GPSR0_3,
2105 GP_0_2_FN, GPSR0_2,
2106 GP_0_1_FN, GPSR0_1,
2107 GP_0_0_FN, GPSR0_0, }
2109 { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1) {
2110 0, 0,
2111 0, 0,
2112 0, 0,
2113 0, 0,
2114 GP_1_27_FN, GPSR1_27,
2115 GP_1_26_FN, GPSR1_26,
2116 GP_1_25_FN, GPSR1_25,
2117 GP_1_24_FN, GPSR1_24,
2118 GP_1_23_FN, GPSR1_23,
2119 GP_1_22_FN, GPSR1_22,
2120 GP_1_21_FN, GPSR1_21,
2121 GP_1_20_FN, GPSR1_20,
2122 GP_1_19_FN, GPSR1_19,
2123 GP_1_18_FN, GPSR1_18,
2124 GP_1_17_FN, GPSR1_17,
2125 GP_1_16_FN, GPSR1_16,
2126 GP_1_15_FN, GPSR1_15,
2127 GP_1_14_FN, GPSR1_14,
2128 GP_1_13_FN, GPSR1_13,
2129 GP_1_12_FN, GPSR1_12,
2130 GP_1_11_FN, GPSR1_11,
2131 GP_1_10_FN, GPSR1_10,
2132 GP_1_9_FN, GPSR1_9,
2133 GP_1_8_FN, GPSR1_8,
2134 GP_1_7_FN, GPSR1_7,
2135 GP_1_6_FN, GPSR1_6,
2136 GP_1_5_FN, GPSR1_5,
2137 GP_1_4_FN, GPSR1_4,
2138 GP_1_3_FN, GPSR1_3,
2139 GP_1_2_FN, GPSR1_2,
2140 GP_1_1_FN, GPSR1_1,
2141 GP_1_0_FN, GPSR1_0, }
2143 { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1) {
2144 0, 0,
2145 0, 0,
2146 0, 0,
2147 0, 0,
2148 0, 0,
2149 0, 0,
2150 0, 0,
2151 0, 0,
2152 0, 0,
2153 0, 0,
2154 0, 0,
2155 0, 0,
2156 0, 0,
2157 0, 0,
2158 0, 0,
2159 GP_2_16_FN, GPSR2_16,
2160 GP_2_15_FN, GPSR2_15,
2161 GP_2_14_FN, GPSR2_14,
2162 GP_2_13_FN, GPSR2_13,
2163 GP_2_12_FN, GPSR2_12,
2164 GP_2_11_FN, GPSR2_11,
2165 GP_2_10_FN, GPSR2_10,
2166 GP_2_9_FN, GPSR2_9,
2167 GP_2_8_FN, GPSR2_8,
2168 GP_2_7_FN, GPSR2_7,
2169 GP_2_6_FN, GPSR2_6,
2170 GP_2_5_FN, GPSR2_5,
2171 GP_2_4_FN, GPSR2_4,
2172 GP_2_3_FN, GPSR2_3,
2173 GP_2_2_FN, GPSR2_2,
2174 GP_2_1_FN, GPSR2_1,
2175 GP_2_0_FN, GPSR2_0, }
2177 { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1) {
2178 0, 0,
2179 0, 0,
2180 0, 0,
2181 0, 0,
2182 0, 0,
2183 0, 0,
2184 0, 0,
2185 0, 0,
2186 0, 0,
2187 0, 0,
2188 0, 0,
2189 0, 0,
2190 0, 0,
2191 0, 0,
2192 0, 0,
2193 GP_3_16_FN, GPSR3_16,
2194 GP_3_15_FN, GPSR3_15,
2195 GP_3_14_FN, GPSR3_14,
2196 GP_3_13_FN, GPSR3_13,
2197 GP_3_12_FN, GPSR3_12,
2198 GP_3_11_FN, GPSR3_11,
2199 GP_3_10_FN, GPSR3_10,
2200 GP_3_9_FN, GPSR3_9,
2201 GP_3_8_FN, GPSR3_8,
2202 GP_3_7_FN, GPSR3_7,
2203 GP_3_6_FN, GPSR3_6,
2204 GP_3_5_FN, GPSR3_5,
2205 GP_3_4_FN, GPSR3_4,
2206 GP_3_3_FN, GPSR3_3,
2207 GP_3_2_FN, GPSR3_2,
2208 GP_3_1_FN, GPSR3_1,
2209 GP_3_0_FN, GPSR3_0, }
2211 { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1) {
2212 0, 0,
2213 0, 0,
2214 0, 0,
2215 0, 0,
2216 0, 0,
2217 0, 0,
2218 0, 0,
2219 0, 0,
2220 0, 0,
2221 0, 0,
2222 0, 0,
2223 0, 0,
2224 0, 0,
2225 0, 0,
2226 0, 0,
2227 0, 0,
2228 0, 0,
2229 0, 0,
2230 0, 0,
2231 0, 0,
2232 0, 0,
2233 0, 0,
2234 0, 0,
2235 0, 0,
2236 0, 0,
2237 0, 0,
2238 GP_4_5_FN, GPSR4_5,
2239 GP_4_4_FN, GPSR4_4,
2240 GP_4_3_FN, GPSR4_3,
2241 GP_4_2_FN, GPSR4_2,
2242 GP_4_1_FN, GPSR4_1,
2243 GP_4_0_FN, GPSR4_0, }
2245 { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1) {
2246 0, 0,
2247 0, 0,
2248 0, 0,
2249 0, 0,
2250 0, 0,
2251 0, 0,
2252 0, 0,
2253 0, 0,
2254 0, 0,
2255 0, 0,
2256 0, 0,
2257 0, 0,
2258 0, 0,
2259 0, 0,
2260 0, 0,
2261 0, 0,
2262 0, 0,
2263 GP_5_14_FN, GPSR5_14,
2264 GP_5_13_FN, GPSR5_13,
2265 GP_5_12_FN, GPSR5_12,
2266 GP_5_11_FN, GPSR5_11,
2267 GP_5_10_FN, GPSR5_10,
2268 GP_5_9_FN, GPSR5_9,
2269 GP_5_8_FN, GPSR5_8,
2270 GP_5_7_FN, GPSR5_7,
2271 GP_5_6_FN, GPSR5_6,
2272 GP_5_5_FN, GPSR5_5,
2273 GP_5_4_FN, GPSR5_4,
2274 GP_5_3_FN, GPSR5_3,
2275 GP_5_2_FN, GPSR5_2,
2276 GP_5_1_FN, GPSR5_1,
2277 GP_5_0_FN, GPSR5_0, }
2279 #undef F_
2280 #undef FM
2282 #define F_(x, y) x,
2283 #define FM(x) FN_##x,
2284 { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4) {
2285 IP0_31_28
2286 IP0_27_24
2287 IP0_23_20
2288 IP0_19_16
2289 IP0_15_12
2290 IP0_11_8
2291 IP0_7_4
2292 IP0_3_0 }
2294 { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4) {
2295 IP1_31_28
2296 IP1_27_24
2297 IP1_23_20
2298 IP1_19_16
2299 IP1_15_12
2300 IP1_11_8
2301 IP1_7_4
2302 IP1_3_0 }
2304 { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4) {
2305 IP2_31_28
2306 IP2_27_24
2307 IP2_23_20
2308 IP2_19_16
2309 IP2_15_12
2310 IP2_11_8
2311 IP2_7_4
2312 IP2_3_0 }
2314 { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4) {
2315 IP3_31_28
2316 IP3_27_24
2317 IP3_23_20
2318 IP3_19_16
2319 IP3_15_12
2320 IP3_11_8
2321 IP3_7_4
2322 IP3_3_0 }
2324 { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4) {
2325 IP4_31_28
2326 IP4_27_24
2327 IP4_23_20
2328 IP4_19_16
2329 IP4_15_12
2330 IP4_11_8
2331 IP4_7_4
2332 IP4_3_0 }
2334 { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4) {
2335 IP5_31_28
2336 IP5_27_24
2337 IP5_23_20
2338 IP5_19_16
2339 IP5_15_12
2340 IP5_11_8
2341 IP5_7_4
2342 IP5_3_0 }
2344 { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4) {
2345 IP6_31_28
2346 IP6_27_24
2347 IP6_23_20
2348 IP6_19_16
2349 IP6_15_12
2350 IP6_11_8
2351 IP6_7_4
2352 IP6_3_0 }
2354 { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4) {
2355 IP7_31_28
2356 IP7_27_24
2357 IP7_23_20
2358 IP7_19_16
2359 IP7_15_12
2360 IP7_11_8
2361 IP7_7_4
2362 IP7_3_0 }
2364 { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4) {
2365 IP8_31_28
2366 IP8_27_24
2367 IP8_23_20
2368 IP8_19_16
2369 IP8_15_12
2370 IP8_11_8
2371 IP8_7_4
2372 IP8_3_0 }
2374 #undef F_
2375 #undef FM
2377 #define F_(x, y) x,
2378 #define FM(x) FN_##x,
2379 { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
2380 4, 4, 4, 4, 4,
2381 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) {
2382 /* RESERVED 31, 30, 29, 28 */
2383 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2384 /* RESERVED 27, 26, 25, 24 */
2385 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2386 /* RESERVED 23, 22, 21, 20 */
2387 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2388 /* RESERVED 19, 18, 17, 16 */
2389 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2390 /* RESERVED 15, 14, 13, 12 */
2391 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2392 MOD_SEL0_11
2393 MOD_SEL0_10
2394 MOD_SEL0_9
2395 MOD_SEL0_8
2396 MOD_SEL0_7
2397 MOD_SEL0_6
2398 MOD_SEL0_5
2399 MOD_SEL0_4
2400 MOD_SEL0_3
2401 MOD_SEL0_2
2402 MOD_SEL0_1
2403 MOD_SEL0_0 }
2405 { },
2408 enum ioctrl_regs {
2409 IOCTRL30,
2410 IOCTRL31,
2411 IOCTRL32,
2414 static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
2415 [IOCTRL30] = { 0xe6060380 },
2416 [IOCTRL31] = { 0xe6060384 },
2417 [IOCTRL32] = { 0xe6060388 },
2418 { /* sentinel */ },
2421 static int r8a77970_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin,
2422 u32 *pocctrl)
2424 int bit = pin & 0x1f;
2426 *pocctrl = pinmux_ioctrl_regs[IOCTRL30].reg;
2427 if (pin >= RCAR_GP_PIN(0, 0) && pin <= RCAR_GP_PIN(0, 21))
2428 return bit;
2429 if (pin >= RCAR_GP_PIN(2, 0) && pin <= RCAR_GP_PIN(2, 9))
2430 return bit + 22;
2432 *pocctrl = pinmux_ioctrl_regs[IOCTRL31].reg;
2433 if (pin >= RCAR_GP_PIN(2, 10) && pin <= RCAR_GP_PIN(2, 16))
2434 return bit - 10;
2435 if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 16))
2436 return bit + 7;
2438 return -EINVAL;
2441 static const struct sh_pfc_soc_operations pinmux_ops = {
2442 .pin_to_pocctrl = r8a77970_pin_to_pocctrl,
2445 const struct sh_pfc_soc_info r8a77970_pinmux_info = {
2446 .name = "r8a77970_pfc",
2447 .ops = &pinmux_ops,
2448 .unlock_reg = 0xe6060000, /* PMMR */
2450 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
2452 .pins = pinmux_pins,
2453 .nr_pins = ARRAY_SIZE(pinmux_pins),
2454 .groups = pinmux_groups,
2455 .nr_groups = ARRAY_SIZE(pinmux_groups),
2456 .functions = pinmux_functions,
2457 .nr_functions = ARRAY_SIZE(pinmux_functions),
2459 .cfg_regs = pinmux_config_regs,
2460 .ioctrl_regs = pinmux_ioctrl_regs,
2462 .pinmux_data = pinmux_data,
2463 .pinmux_data_size = ARRAY_SIZE(pinmux_data),