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Linux 5.1.15
[linux/fpc-iii.git] / drivers / pinctrl / sunxi / pinctrl-sun50i-h6.c
blobef4268cc62275057016846703cca8de58f8386f6
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Allwinner H6 SoC pinctrl driver.
4 *
5 * Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
6 */
7
8 #include <linux/module.h>
9 #include <linux/platform_device.h>
10 #include <linux/of.h>
11 #include <linux/of_device.h>
12 #include <linux/pinctrl/pinctrl.h>
13
14 #include "pinctrl-sunxi.h"
15
16 static const struct sunxi_desc_pin h6_pins[] = {
17 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 0),
18 SUNXI_FUNCTION(0x2, "emac")), /* ERXD1 */
19 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 1),
20 SUNXI_FUNCTION(0x2, "emac")), /* ERXD0 */
21 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 2),
22 SUNXI_FUNCTION(0x2, "emac")), /* ECRS_DV */
23 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 3),
24 SUNXI_FUNCTION(0x2, "emac")), /* ERXERR */
25 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 4),
26 SUNXI_FUNCTION(0x2, "emac")), /* ETXD1 */
27 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 5),
28 SUNXI_FUNCTION(0x2, "emac")), /* ETXD0 */
29 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 6),
30 SUNXI_FUNCTION(0x2, "emac")), /* ETXCK */
31 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 7),
32 SUNXI_FUNCTION(0x2, "emac")), /* ETXEN */
33 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 8),
34 SUNXI_FUNCTION(0x2, "emac")), /* EMDC */
35 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 9),
36 SUNXI_FUNCTION(0x2, "emac")), /* EMDIO */
37 /* Hole */
38 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 0),
39 SUNXI_FUNCTION(0x2, "ccir"), /* CLK */
40 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)),
41 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 1),
42 SUNXI_FUNCTION(0x2, "ccir"), /* DE */
43 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)),
44 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 2),
45 SUNXI_FUNCTION(0x2, "ccir"), /* HSYNC */
46 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 2)),
47 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 3),
48 SUNXI_FUNCTION(0x2, "ccir"), /* VSYNC */
49 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)),
50 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 4),
51 SUNXI_FUNCTION(0x2, "ccir"), /* DO0 */
52 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 4)),
53 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 5),
54 SUNXI_FUNCTION(0x2, "ccir"), /* DO1 */
55 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 5)),
56 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 6),
57 SUNXI_FUNCTION(0x2, "ccir"), /* DO2 */
58 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 6)),
59 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 7),
60 SUNXI_FUNCTION(0x2, "ccir"), /* DO3 */
61 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 7)),
62 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 8),
63 SUNXI_FUNCTION(0x2, "ccir"), /* DO4 */
64 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 8)),
65 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 9),
66 SUNXI_FUNCTION(0x2, "ccir"), /* DO5 */
67 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 9)),
68 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 10),
69 SUNXI_FUNCTION(0x2, "ccir"), /* DO6 */
70 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 10)),
71 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 11),
72 SUNXI_FUNCTION(0x2, "ccir"), /* DO7 */
73 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 11)),
74 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 12),
75 SUNXI_FUNCTION(0x2, "i2s3"), /* SYNC */
76 SUNXI_FUNCTION(0x4, "h_i2s3"), /* SYNC */
77 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 12)),
78 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 13),
79 SUNXI_FUNCTION(0x2, "i2s3"), /* CLK */
80 SUNXI_FUNCTION(0x4, "h_i2s3"), /* CLK */
81 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 13)),
82 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 14),
83 SUNXI_FUNCTION(0x2, "i2s3"), /* DOUT */
84 SUNXI_FUNCTION(0x4, "h_i2s3"), /* DOUT */
85 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 14)),
86 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 15),
87 SUNXI_FUNCTION(0x2, "i2s3"), /* DIN */
88 SUNXI_FUNCTION(0x4, "h_i2s3"), /* DIN */
89 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 15)),
90 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 16),
91 SUNXI_FUNCTION(0x2, "i2s3"), /* MCLK */
92 SUNXI_FUNCTION(0x4, "h_i2s3"), /* MCLK */
93 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 16)),
94 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 17),
95 SUNXI_FUNCTION(0x2, "i2c3"), /* SCK */
96 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 17)),
97 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 18),
98 SUNXI_FUNCTION(0x2, "i2c3"), /* SDA */
99 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 18)),
100 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 19),
101 SUNXI_FUNCTION(0x2, "pwm1"),
102 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 19)),
103 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 20),
104 SUNXI_FUNCTION(0x0, "gpio_in"),
105 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 20)),
106 /* Hole */
107 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0),
108 SUNXI_FUNCTION(0x0, "gpio_in"),
109 SUNXI_FUNCTION(0x1, "gpio_out"),
110 SUNXI_FUNCTION(0x2, "nand0"), /* WE */
111 SUNXI_FUNCTION(0x4, "spi0")), /* CLK */
112 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1),
113 SUNXI_FUNCTION(0x0, "gpio_in"),
114 SUNXI_FUNCTION(0x1, "gpio_out"),
115 SUNXI_FUNCTION(0x2, "nand0"), /* ALE */
116 SUNXI_FUNCTION(0x3, "mmc2")), /* DS */
117 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2),
118 SUNXI_FUNCTION(0x0, "gpio_in"),
119 SUNXI_FUNCTION(0x1, "gpio_out"),
120 SUNXI_FUNCTION(0x2, "nand0"), /* CLE */
121 SUNXI_FUNCTION(0x4, "spi0")), /* MOSI */
122 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3),
123 SUNXI_FUNCTION(0x0, "gpio_in"),
124 SUNXI_FUNCTION(0x1, "gpio_out"),
125 SUNXI_FUNCTION(0x2, "nand0"), /* CE0 */
126 SUNXI_FUNCTION(0x4, "spi0")), /* MISO */
127 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 4),
128 SUNXI_FUNCTION(0x0, "gpio_in"),
129 SUNXI_FUNCTION(0x1, "gpio_out"),
130 SUNXI_FUNCTION(0x2, "nand0"), /* RE */
131 SUNXI_FUNCTION(0x3, "mmc2")), /* CLK */
132 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 5),
133 SUNXI_FUNCTION(0x0, "gpio_in"),
134 SUNXI_FUNCTION(0x1, "gpio_out"),
135 SUNXI_FUNCTION(0x2, "nand0"), /* RB0 */
136 SUNXI_FUNCTION(0x3, "mmc2"), /* CMD */
137 SUNXI_FUNCTION(0x4, "spi0")), /* CS */
138 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 6),
139 SUNXI_FUNCTION(0x0, "gpio_in"),
140 SUNXI_FUNCTION(0x1, "gpio_out"),
141 SUNXI_FUNCTION(0x2, "nand0"), /* DQ0 */
142 SUNXI_FUNCTION(0x3, "mmc2"), /* D0 */
143 SUNXI_FUNCTION(0x4, "spi0")), /* HOLD */
144 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 7),
145 SUNXI_FUNCTION(0x0, "gpio_in"),
146 SUNXI_FUNCTION(0x1, "gpio_out"),
147 SUNXI_FUNCTION(0x2, "nand0"), /* DQ1 */
148 SUNXI_FUNCTION(0x3, "mmc2"), /* D1 */
149 SUNXI_FUNCTION(0x4, "spi0")), /* WP */
150 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 8),
151 SUNXI_FUNCTION(0x0, "gpio_in"),
152 SUNXI_FUNCTION(0x1, "gpio_out"),
153 SUNXI_FUNCTION(0x2, "nand0"), /* DQ2 */
154 SUNXI_FUNCTION(0x3, "mmc2")), /* D2 */
155 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 9),
156 SUNXI_FUNCTION(0x0, "gpio_in"),
157 SUNXI_FUNCTION(0x1, "gpio_out"),
158 SUNXI_FUNCTION(0x2, "nand0"), /* DQ3 */
159 SUNXI_FUNCTION(0x3, "mmc2")), /* D3 */
160 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 10),
161 SUNXI_FUNCTION(0x0, "gpio_in"),
162 SUNXI_FUNCTION(0x1, "gpio_out"),
163 SUNXI_FUNCTION(0x2, "nand0"), /* DQ4 */
164 SUNXI_FUNCTION(0x3, "mmc2")), /* D4 */
165 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 11),
166 SUNXI_FUNCTION(0x0, "gpio_in"),
167 SUNXI_FUNCTION(0x1, "gpio_out"),
168 SUNXI_FUNCTION(0x2, "nand0"), /* DQ5 */
169 SUNXI_FUNCTION(0x3, "mmc2")), /* D5 */
170 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 12),
171 SUNXI_FUNCTION(0x0, "gpio_in"),
172 SUNXI_FUNCTION(0x1, "gpio_out"),
173 SUNXI_FUNCTION(0x2, "nand0"), /* DQ6 */
174 SUNXI_FUNCTION(0x3, "mmc2")), /* D6 */
175 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 13),
176 SUNXI_FUNCTION(0x0, "gpio_in"),
177 SUNXI_FUNCTION(0x1, "gpio_out"),
178 SUNXI_FUNCTION(0x2, "nand0"), /* DQ7 */
179 SUNXI_FUNCTION(0x3, "mmc2")), /* D7 */
180 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 14),
181 SUNXI_FUNCTION(0x0, "gpio_in"),
182 SUNXI_FUNCTION(0x1, "gpio_out"),
183 SUNXI_FUNCTION(0x2, "nand0"), /* DQS */
184 SUNXI_FUNCTION(0x3, "mmc2")), /* RST */
185 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 15),
186 SUNXI_FUNCTION(0x0, "gpio_in"),
187 SUNXI_FUNCTION(0x1, "gpio_out"),
188 SUNXI_FUNCTION(0x2, "nand0")), /* CE1 */
189 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 16),
190 SUNXI_FUNCTION(0x0, "gpio_in"),
191 SUNXI_FUNCTION(0x1, "gpio_out"),
192 SUNXI_FUNCTION(0x2, "nand0")), /* RB1 */
193 /* Hole */
194 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 0),
195 SUNXI_FUNCTION(0x0, "gpio_in"),
196 SUNXI_FUNCTION(0x1, "gpio_out"),
197 SUNXI_FUNCTION(0x2, "lcd0"), /* D2 */
198 SUNXI_FUNCTION(0x3, "ts0"), /* CLK */
199 SUNXI_FUNCTION(0x4, "csi"), /* PCLK */
200 SUNXI_FUNCTION(0x5, "emac")), /* ERXD3 */
201 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 1),
202 SUNXI_FUNCTION(0x0, "gpio_in"),
203 SUNXI_FUNCTION(0x1, "gpio_out"),
204 SUNXI_FUNCTION(0x2, "lcd0"), /* D3 */
205 SUNXI_FUNCTION(0x3, "ts0"), /* ERR */
206 SUNXI_FUNCTION(0x4, "csi"), /* MCLK */
207 SUNXI_FUNCTION(0x5, "emac")), /* ERXD2 */
208 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 2),
209 SUNXI_FUNCTION(0x0, "gpio_in"),
210 SUNXI_FUNCTION(0x1, "gpio_out"),
211 SUNXI_FUNCTION(0x2, "lcd0"), /* D4 */
212 SUNXI_FUNCTION(0x3, "ts0"), /* SYNC */
213 SUNXI_FUNCTION(0x4, "csi"), /* HSYNC */
214 SUNXI_FUNCTION(0x5, "emac")), /* ERXD1 */
215 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 3),
216 SUNXI_FUNCTION(0x0, "gpio_in"),
217 SUNXI_FUNCTION(0x1, "gpio_out"),
218 SUNXI_FUNCTION(0x2, "lcd0"), /* D5 */
219 SUNXI_FUNCTION(0x3, "ts0"), /* DVLD */
220 SUNXI_FUNCTION(0x4, "csi"), /* VSYNC */
221 SUNXI_FUNCTION(0x5, "emac")), /* ERXD0 */
222 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 4),
223 SUNXI_FUNCTION(0x0, "gpio_in"),
224 SUNXI_FUNCTION(0x1, "gpio_out"),
225 SUNXI_FUNCTION(0x2, "lcd0"), /* D6 */
226 SUNXI_FUNCTION(0x3, "ts0"), /* D0 */
227 SUNXI_FUNCTION(0x4, "csi"), /* D0 */
228 SUNXI_FUNCTION(0x5, "emac")), /* ERXCK */
229 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 5),
230 SUNXI_FUNCTION(0x0, "gpio_in"),
231 SUNXI_FUNCTION(0x1, "gpio_out"),
232 SUNXI_FUNCTION(0x2, "lcd0"), /* D7 */
233 SUNXI_FUNCTION(0x3, "ts0"), /* D1 */
234 SUNXI_FUNCTION(0x4, "csi"), /* D1 */
235 SUNXI_FUNCTION(0x5, "emac")), /* ERXCTL */
236 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 6),
237 SUNXI_FUNCTION(0x0, "gpio_in"),
238 SUNXI_FUNCTION(0x1, "gpio_out"),
239 SUNXI_FUNCTION(0x2, "lcd0"), /* D10 */
240 SUNXI_FUNCTION(0x3, "ts0"), /* D2 */
241 SUNXI_FUNCTION(0x4, "csi"), /* D2 */
242 SUNXI_FUNCTION(0x5, "emac")), /* ENULL */
243 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 7),
244 SUNXI_FUNCTION(0x0, "gpio_in"),
245 SUNXI_FUNCTION(0x1, "gpio_out"),
246 SUNXI_FUNCTION(0x2, "lcd0"), /* D11 */
247 SUNXI_FUNCTION(0x3, "ts0"), /* D3 */
248 SUNXI_FUNCTION(0x4, "csi"), /* D3 */
249 SUNXI_FUNCTION(0x5, "emac")), /* ETXD3 */
250 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 8),
251 SUNXI_FUNCTION(0x0, "gpio_in"),
252 SUNXI_FUNCTION(0x1, "gpio_out"),
253 SUNXI_FUNCTION(0x2, "lcd0"), /* D12 */
254 SUNXI_FUNCTION(0x3, "ts0"), /* D4 */
255 SUNXI_FUNCTION(0x4, "csi"), /* D4 */
256 SUNXI_FUNCTION(0x5, "emac")), /* ETXD2 */
257 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 9),
258 SUNXI_FUNCTION(0x0, "gpio_in"),
259 SUNXI_FUNCTION(0x1, "gpio_out"),
260 SUNXI_FUNCTION(0x2, "lcd0"), /* D13 */
261 SUNXI_FUNCTION(0x3, "ts0"), /* D5 */
262 SUNXI_FUNCTION(0x4, "csi"), /* D5 */
263 SUNXI_FUNCTION(0x5, "emac")), /* ETXD1 */
264 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 10),
265 SUNXI_FUNCTION(0x0, "gpio_in"),
266 SUNXI_FUNCTION(0x1, "gpio_out"),
267 SUNXI_FUNCTION(0x2, "lcd0"), /* D14 */
268 SUNXI_FUNCTION(0x3, "ts0"), /* D6 */
269 SUNXI_FUNCTION(0x4, "csi"), /* D6 */
270 SUNXI_FUNCTION(0x5, "emac")), /* ETXD0 */
271 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 11),
272 SUNXI_FUNCTION(0x0, "gpio_in"),
273 SUNXI_FUNCTION(0x1, "gpio_out"),
274 SUNXI_FUNCTION(0x2, "lcd0"), /* D15 */
275 SUNXI_FUNCTION(0x3, "ts0"), /* D7 */
276 SUNXI_FUNCTION(0x4, "csi"), /* D7 */
277 SUNXI_FUNCTION(0x5, "emac")), /* ETXCK */
278 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 12),
279 SUNXI_FUNCTION(0x0, "gpio_in"),
280 SUNXI_FUNCTION(0x1, "gpio_out"),
281 SUNXI_FUNCTION(0x2, "lcd0"), /* D18 */
282 SUNXI_FUNCTION(0x3, "ts1"), /* CLK */
283 SUNXI_FUNCTION(0x4, "csi"), /* SCK */
284 SUNXI_FUNCTION(0x5, "emac")), /* ETXCTL */
285 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 13),
286 SUNXI_FUNCTION(0x0, "gpio_in"),
287 SUNXI_FUNCTION(0x1, "gpio_out"),
288 SUNXI_FUNCTION(0x2, "lcd0"), /* D19 */
289 SUNXI_FUNCTION(0x3, "ts1"), /* ERR */
290 SUNXI_FUNCTION(0x4, "csi"), /* SDA */
291 SUNXI_FUNCTION(0x5, "emac")), /* ECLKIN */
292 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 14),
293 SUNXI_FUNCTION(0x0, "gpio_in"),
294 SUNXI_FUNCTION(0x1, "gpio_out"),
295 SUNXI_FUNCTION(0x2, "lcd0"), /* D20 */
296 SUNXI_FUNCTION(0x3, "ts1"), /* SYNC */
297 SUNXI_FUNCTION(0x4, "dmic"), /* CLK */
298 SUNXI_FUNCTION(0x5, "csi")), /* D8 */
299 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 15),
300 SUNXI_FUNCTION(0x0, "gpio_in"),
301 SUNXI_FUNCTION(0x1, "gpio_out"),
302 SUNXI_FUNCTION(0x2, "lcd0"), /* D21 */
303 SUNXI_FUNCTION(0x3, "ts1"), /* DVLD */
304 SUNXI_FUNCTION(0x4, "dmic"), /* DATA0 */
305 SUNXI_FUNCTION(0x5, "csi")), /* D9 */
306 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 16),
307 SUNXI_FUNCTION(0x0, "gpio_in"),
308 SUNXI_FUNCTION(0x1, "gpio_out"),
309 SUNXI_FUNCTION(0x2, "lcd0"), /* D22 */
310 SUNXI_FUNCTION(0x3, "ts1"), /* D0 */
311 SUNXI_FUNCTION(0x4, "dmic")), /* DATA1 */
312 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 17),
313 SUNXI_FUNCTION(0x0, "gpio_in"),
314 SUNXI_FUNCTION(0x1, "gpio_out"),
315 SUNXI_FUNCTION(0x2, "lcd0"), /* D23 */
316 SUNXI_FUNCTION(0x3, "ts2"), /* CLK */
317 SUNXI_FUNCTION(0x4, "dmic")), /* DATA2 */
318 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 18),
319 SUNXI_FUNCTION(0x0, "gpio_in"),
320 SUNXI_FUNCTION(0x1, "gpio_out"),
321 SUNXI_FUNCTION(0x2, "lcd0"), /* CLK */
322 SUNXI_FUNCTION(0x3, "ts2"), /* ERR */
323 SUNXI_FUNCTION(0x4, "dmic")), /* DATA3 */
324 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 19),
325 SUNXI_FUNCTION(0x0, "gpio_in"),
326 SUNXI_FUNCTION(0x1, "gpio_out"),
327 SUNXI_FUNCTION(0x2, "lcd0"), /* DE */
328 SUNXI_FUNCTION(0x3, "ts2"), /* SYNC */
329 SUNXI_FUNCTION(0x4, "uart2"), /* TX */
330 SUNXI_FUNCTION(0x5, "emac")), /* EMDC */
331 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 20),
332 SUNXI_FUNCTION(0x0, "gpio_in"),
333 SUNXI_FUNCTION(0x1, "gpio_out"),
334 SUNXI_FUNCTION(0x2, "lcd0"), /* HSYNC */
335 SUNXI_FUNCTION(0x3, "ts2"), /* DVLD */
336 SUNXI_FUNCTION(0x4, "uart2"), /* RX */
337 SUNXI_FUNCTION(0x5, "emac")), /* EMDIO */
338 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 21),
339 SUNXI_FUNCTION(0x0, "gpio_in"),
340 SUNXI_FUNCTION(0x1, "gpio_out"),
341 SUNXI_FUNCTION(0x2, "lcd0"), /* VSYNC */
342 SUNXI_FUNCTION(0x3, "ts2"), /* D0 */
343 SUNXI_FUNCTION(0x4, "uart2")), /* RTS */
344 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 22),
345 SUNXI_FUNCTION(0x0, "gpio_in"),
346 SUNXI_FUNCTION(0x1, "gpio_out"),
347 SUNXI_FUNCTION(0x2, "pwm"), /* PWM0 */
348 SUNXI_FUNCTION(0x3, "ts3"), /* CLK */
349 SUNXI_FUNCTION(0x4, "uart2")), /* CTS */
350 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 23),
351 SUNXI_FUNCTION(0x0, "gpio_in"),
352 SUNXI_FUNCTION(0x1, "gpio_out"),
353 SUNXI_FUNCTION(0x2, "i2c2"), /* SCK */
354 SUNXI_FUNCTION(0x3, "ts3"), /* ERR */
355 SUNXI_FUNCTION(0x4, "uart3"), /* TX */
356 SUNXI_FUNCTION(0x5, "jtag")), /* MS */
357 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 24),
358 SUNXI_FUNCTION(0x0, "gpio_in"),
359 SUNXI_FUNCTION(0x1, "gpio_out"),
360 SUNXI_FUNCTION(0x2, "i2c2"), /* SDA */
361 SUNXI_FUNCTION(0x3, "ts3"), /* SYNC */
362 SUNXI_FUNCTION(0x4, "uart3"), /* RX */
363 SUNXI_FUNCTION(0x5, "jtag")), /* CK */
364 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 25),
365 SUNXI_FUNCTION(0x0, "gpio_in"),
366 SUNXI_FUNCTION(0x1, "gpio_out"),
367 SUNXI_FUNCTION(0x2, "i2c0"), /* SCK */
368 SUNXI_FUNCTION(0x3, "ts3"), /* DVLD */
369 SUNXI_FUNCTION(0x4, "uart3"), /* RTS */
370 SUNXI_FUNCTION(0x5, "jtag")), /* DO */
371 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 26),
372 SUNXI_FUNCTION(0x0, "gpio_in"),
373 SUNXI_FUNCTION(0x1, "gpio_out"),
374 SUNXI_FUNCTION(0x2, "i2c0"), /* SDA */
375 SUNXI_FUNCTION(0x3, "ts3"), /* D0 */
376 SUNXI_FUNCTION(0x4, "uart3"), /* CTS */
377 SUNXI_FUNCTION(0x5, "jtag")), /* DI */
378 /* Hole */
379 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0),
380 SUNXI_FUNCTION(0x0, "gpio_in"),
381 SUNXI_FUNCTION(0x1, "gpio_out"),
382 SUNXI_FUNCTION(0x2, "mmc0"), /* D1 */
383 SUNXI_FUNCTION(0x3, "jtag"), /* MS */
384 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 0)), /* PF_EINT0 */
385 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 1),
386 SUNXI_FUNCTION(0x0, "gpio_in"),
387 SUNXI_FUNCTION(0x1, "gpio_out"),
388 SUNXI_FUNCTION(0x2, "mmc0"), /* D0 */
389 SUNXI_FUNCTION(0x3, "jtag"), /* DI */
390 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 1)), /* PF_EINT1 */
391 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 2),
392 SUNXI_FUNCTION(0x0, "gpio_in"),
393 SUNXI_FUNCTION(0x1, "gpio_out"),
394 SUNXI_FUNCTION(0x2, "mmc0"), /* CLK */
395 SUNXI_FUNCTION(0x3, "uart0"), /* TX */
396 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 2)), /* PF_EINT2 */
397 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 3),
398 SUNXI_FUNCTION(0x0, "gpio_in"),
399 SUNXI_FUNCTION(0x1, "gpio_out"),
400 SUNXI_FUNCTION(0x2, "mmc0"), /* CMD */
401 SUNXI_FUNCTION(0x3, "jtag"), /* DO */
402 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 3)), /* PF_EINT3 */
403 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 4),
404 SUNXI_FUNCTION(0x0, "gpio_in"),
405 SUNXI_FUNCTION(0x1, "gpio_out"),
406 SUNXI_FUNCTION(0x2, "mmc0"), /* D3 */
407 SUNXI_FUNCTION(0x3, "uart0"), /* RX */
408 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 4)), /* PF_EINT4 */
409 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5),
410 SUNXI_FUNCTION(0x0, "gpio_in"),
411 SUNXI_FUNCTION(0x1, "gpio_out"),
412 SUNXI_FUNCTION(0x2, "mmc0"), /* D2 */
413 SUNXI_FUNCTION(0x3, "jtag"), /* CK */
414 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 5)), /* PF_EINT5 */
415 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 6),
416 SUNXI_FUNCTION(0x0, "gpio_in"),
417 SUNXI_FUNCTION(0x1, "gpio_out"),
418 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 6)), /* PF_EINT6 */
419 /* Hole */
420 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 0),
421 SUNXI_FUNCTION(0x0, "gpio_in"),
422 SUNXI_FUNCTION(0x1, "gpio_out"),
423 SUNXI_FUNCTION(0x2, "mmc1"), /* CLK */
424 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 0)), /* PG_EINT0 */
425 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 1),
426 SUNXI_FUNCTION(0x0, "gpio_in"),
427 SUNXI_FUNCTION(0x1, "gpio_out"),
428 SUNXI_FUNCTION(0x2, "mmc1"), /* CMD */
429 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 1)), /* PG_EINT1 */
430 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 2),
431 SUNXI_FUNCTION(0x0, "gpio_in"),
432 SUNXI_FUNCTION(0x1, "gpio_out"),
433 SUNXI_FUNCTION(0x2, "mmc1"), /* D0 */
434 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 2)), /* PG_EINT2 */
435 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 3),
436 SUNXI_FUNCTION(0x0, "gpio_in"),
437 SUNXI_FUNCTION(0x1, "gpio_out"),
438 SUNXI_FUNCTION(0x2, "mmc1"), /* D1 */
439 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 3)), /* PG_EINT3 */
440 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 4),
441 SUNXI_FUNCTION(0x0, "gpio_in"),
442 SUNXI_FUNCTION(0x1, "gpio_out"),
443 SUNXI_FUNCTION(0x2, "mmc1"), /* D2 */
444 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 4)), /* PG_EINT4 */
445 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 5),
446 SUNXI_FUNCTION(0x0, "gpio_in"),
447 SUNXI_FUNCTION(0x1, "gpio_out"),
448 SUNXI_FUNCTION(0x2, "mmc1"), /* D3 */
449 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 5)), /* PG_EINT5 */
450 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 6),
451 SUNXI_FUNCTION(0x0, "gpio_in"),
452 SUNXI_FUNCTION(0x1, "gpio_out"),
453 SUNXI_FUNCTION(0x2, "uart1"), /* TX */
454 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 6)), /* PG_EINT6 */
455 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 7),
456 SUNXI_FUNCTION(0x0, "gpio_in"),
457 SUNXI_FUNCTION(0x1, "gpio_out"),
458 SUNXI_FUNCTION(0x2, "uart1"), /* RX */
459 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 7)), /* PG_EINT7 */
460 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 8),
461 SUNXI_FUNCTION(0x0, "gpio_in"),
462 SUNXI_FUNCTION(0x1, "gpio_out"),
463 SUNXI_FUNCTION(0x2, "uart1"), /* RTS */
464 SUNXI_FUNCTION(0x4, "sim0"), /* VPPEN */
465 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 8)), /* PG_EINT8 */
466 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 9),
467 SUNXI_FUNCTION(0x0, "gpio_in"),
468 SUNXI_FUNCTION(0x1, "gpio_out"),
469 SUNXI_FUNCTION(0x2, "uart1"), /* CTS */
470 SUNXI_FUNCTION(0x4, "sim0"), /* VPPPP */
471 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 9)), /* PG_EINT9 */
472 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 10),
473 SUNXI_FUNCTION(0x0, "gpio_in"),
474 SUNXI_FUNCTION(0x1, "gpio_out"),
475 SUNXI_FUNCTION(0x2, "i2s2"), /* SYNC */
476 SUNXI_FUNCTION(0x3, "h_i2s2"), /* SYNC */
477 SUNXI_FUNCTION(0x4, "sim0"), /* PWREN */
478 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 10)), /* PG_EINT10 */
479 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 11),
480 SUNXI_FUNCTION(0x0, "gpio_in"),
481 SUNXI_FUNCTION(0x1, "gpio_out"),
482 SUNXI_FUNCTION(0x2, "i2s2"), /* CLK */
483 SUNXI_FUNCTION(0x3, "h_i2s2"), /* CLK */
484 SUNXI_FUNCTION(0x4, "sim0"), /* CLK */
485 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 11)), /* PG_EINT11 */
486 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 12),
487 SUNXI_FUNCTION(0x0, "gpio_in"),
488 SUNXI_FUNCTION(0x1, "gpio_out"),
489 SUNXI_FUNCTION(0x2, "i2s2"), /* DOUT */
490 SUNXI_FUNCTION(0x3, "h_i2s2"), /* DOUT */
491 SUNXI_FUNCTION(0x4, "sim0"), /* DATA */
492 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 12)), /* PG_EINT12 */
493 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 13),
494 SUNXI_FUNCTION(0x0, "gpio_in"),
495 SUNXI_FUNCTION(0x1, "gpio_out"),
496 SUNXI_FUNCTION(0x2, "i2s2"), /* DIN */
497 SUNXI_FUNCTION(0x3, "h_i2s2"), /* DIN */
498 SUNXI_FUNCTION(0x4, "sim0"), /* RST */
499 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 13)), /* PG_EINT13 */
500 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 14),
501 SUNXI_FUNCTION(0x0, "gpio_in"),
502 SUNXI_FUNCTION(0x1, "gpio_out"),
503 SUNXI_FUNCTION(0x2, "i2s2"), /* MCLK */
504 SUNXI_FUNCTION(0x3, "h_i2s2"), /* MCLK */
505 SUNXI_FUNCTION(0x4, "sim0"), /* DET */
506 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 14)), /* PG_EINT14 */
507 /* Hole */
508 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 0),
509 SUNXI_FUNCTION(0x0, "gpio_in"),
510 SUNXI_FUNCTION(0x1, "gpio_out"),
511 SUNXI_FUNCTION(0x2, "uart0"), /* TX */
512 SUNXI_FUNCTION(0x3, "i2s0"), /* SYNC */
513 SUNXI_FUNCTION(0x4, "h_i2s0"), /* SYNC */
514 SUNXI_FUNCTION(0x5, "sim1"), /* VPPEN */
515 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 0)), /* PH_EINT0 */
516 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 1),
517 SUNXI_FUNCTION(0x0, "gpio_in"),
518 SUNXI_FUNCTION(0x1, "gpio_out"),
519 SUNXI_FUNCTION(0x2, "uart0"), /* RX */
520 SUNXI_FUNCTION(0x3, "i2s0"), /* CLK */
521 SUNXI_FUNCTION(0x4, "h_i2s0"), /* CLK */
522 SUNXI_FUNCTION(0x5, "sim1"), /* VPPPP */
523 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 1)), /* PH_EINT1 */
524 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 2),
525 SUNXI_FUNCTION(0x0, "gpio_in"),
526 SUNXI_FUNCTION(0x1, "gpio_out"),
527 SUNXI_FUNCTION(0x2, "ir_tx"),
528 SUNXI_FUNCTION(0x3, "i2s0"), /* DOUT */
529 SUNXI_FUNCTION(0x4, "h_i2s0"), /* DOUT */
530 SUNXI_FUNCTION(0x5, "sim1"), /* PWREN */
531 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 2)), /* PH_EINT2 */
532 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 3),
533 SUNXI_FUNCTION(0x0, "gpio_in"),
534 SUNXI_FUNCTION(0x1, "gpio_out"),
535 SUNXI_FUNCTION(0x2, "spi1"), /* CS */
536 SUNXI_FUNCTION(0x3, "i2s0"), /* DIN */
537 SUNXI_FUNCTION(0x4, "h_i2s0"), /* DIN */
538 SUNXI_FUNCTION(0x5, "sim1"), /* CLK */
539 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 3)), /* PH_EINT3 */
540 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 4),
541 SUNXI_FUNCTION(0x0, "gpio_in"),
542 SUNXI_FUNCTION(0x1, "gpio_out"),
543 SUNXI_FUNCTION(0x2, "spi1"), /* CLK */
544 SUNXI_FUNCTION(0x3, "i2s0"), /* MCLK */
545 SUNXI_FUNCTION(0x4, "h_i2s0"), /* MCLK */
546 SUNXI_FUNCTION(0x5, "sim1"), /* DATA */
547 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 4)), /* PH_EINT4 */
548 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 5),
549 SUNXI_FUNCTION(0x0, "gpio_in"),
550 SUNXI_FUNCTION(0x1, "gpio_out"),
551 SUNXI_FUNCTION(0x2, "spi1"), /* MOSI */
552 SUNXI_FUNCTION(0x3, "spdif"), /* MCLK */
553 SUNXI_FUNCTION(0x4, "i2c1"), /* SCK */
554 SUNXI_FUNCTION(0x5, "sim1"), /* RST */
555 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 5)), /* PH_EINT5 */
556 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 6),
557 SUNXI_FUNCTION(0x0, "gpio_in"),
558 SUNXI_FUNCTION(0x1, "gpio_out"),
559 SUNXI_FUNCTION(0x2, "spi1"), /* MISO */
560 SUNXI_FUNCTION(0x3, "spdif"), /* IN */
561 SUNXI_FUNCTION(0x4, "i2c1"), /* SDA */
562 SUNXI_FUNCTION(0x5, "sim1"), /* DET */
563 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 6)), /* PH_EINT6 */
564 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 7),
565 SUNXI_FUNCTION(0x0, "gpio_in"),
566 SUNXI_FUNCTION(0x1, "gpio_out"),
567 SUNXI_FUNCTION(0x3, "spdif"), /* OUT */
568 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 7)), /* PH_EINT7 */
569 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 8),
570 SUNXI_FUNCTION(0x0, "gpio_in"),
571 SUNXI_FUNCTION(0x1, "gpio_out"),
572 SUNXI_FUNCTION(0x2, "hdmi"), /* HSCL */
573 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 8)), /* PH_EINT8 */
574 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 9),
575 SUNXI_FUNCTION(0x0, "gpio_in"),
576 SUNXI_FUNCTION(0x1, "gpio_out"),
577 SUNXI_FUNCTION(0x2, "hdmi"), /* HSDA */
578 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 9)), /* PH_EINT9 */
579 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 10),
580 SUNXI_FUNCTION(0x0, "gpio_in"),
581 SUNXI_FUNCTION(0x1, "gpio_out"),
582 SUNXI_FUNCTION(0x2, "hdmi"), /* HCEC */
583 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 10)), /* PH_EINT10 */
584 };
585
586 static const unsigned int h6_irq_bank_map[] = { 1, 5, 6, 7 };
587
588 static const struct sunxi_pinctrl_desc h6_pinctrl_data = {
589 .pins = h6_pins,
590 .npins = ARRAY_SIZE(h6_pins),
591 .irq_banks = 4,
592 .irq_bank_map = h6_irq_bank_map,
593 .irq_read_needs_mux = true,
594 };
595
596 static int h6_pinctrl_probe(struct platform_device *pdev)
597 {
598 return sunxi_pinctrl_init(pdev,
599 &h6_pinctrl_data);
600 }
601
602 static const struct of_device_id h6_pinctrl_match[] = {
603 { .compatible = "allwinner,sun50i-h6-pinctrl", },
604 {}
605 };
606
607 static struct platform_driver h6_pinctrl_driver = {
608 .probe = h6_pinctrl_probe,
609 .driver = {
610 .name = "sun50i-h6-pinctrl",
611 .of_match_table = h6_pinctrl_match,
612 },
613 };
614 builtin_platform_driver(h6_pinctrl_driver);
Linux with added FPC-III support