drivers/power/reset/at91-reset.c

   1 /*
   2  * Atmel AT91 SAM9 & SAMA5 SoCs reset code
   3  *
   4  * Copyright (C) 2007 Atmel Corporation.
   5  * Copyright (C) BitBox Ltd 2010
   6  * Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcosoft.com>
   7  * Copyright (C) 2014 Free Electrons
   8  *
   9  * This file is licensed under the terms of the GNU General Public
  10  * License version 2.  This program is licensed "as is" without any
  11  * warranty of any kind, whether express or implied.
  12  */
  13
  14 #include <linux/clk.h>
  15 #include <linux/io.h>
  16 #include <linux/module.h>
  17 #include <linux/of_address.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/reboot.h>
  20
  21 #include <soc/at91/at91sam9_ddrsdr.h>
  22 #include <soc/at91/at91sam9_sdramc.h>
  23
  24 #define AT91_RSTC_CR    0x00            /* Reset Controller Control Register */
  25 #define AT91_RSTC_PROCRST       BIT(0)          /* Processor Reset */
  26 #define AT91_RSTC_PERRST        BIT(2)          /* Peripheral Reset */
  27 #define AT91_RSTC_EXTRST        BIT(3)          /* External Reset */
  28 #define AT91_RSTC_KEY           (0xa5 << 24)    /* KEY Password */
  29
  30 #define AT91_RSTC_SR    0x04            /* Reset Controller Status Register */
  31 #define AT91_RSTC_URSTS         BIT(0)          /* User Reset Status */
  32 #define AT91_RSTC_RSTTYP        GENMASK(10, 8)  /* Reset Type */
  33 #define AT91_RSTC_NRSTL         BIT(16)         /* NRST Pin Level */
  34 #define AT91_RSTC_SRCMP         BIT(17)         /* Software Reset Command in Progress */
  35
  36 #define AT91_RSTC_MR    0x08            /* Reset Controller Mode Register */
  37 #define AT91_RSTC_URSTEN        BIT(0)          /* User Reset Enable */
  38 #define AT91_RSTC_URSTIEN       BIT(4)          /* User Reset Interrupt Enable */
  39 #define AT91_RSTC_ERSTL         GENMASK(11, 8)  /* External Reset Length */
  40
  41 enum reset_type {
  42         RESET_TYPE_GENERAL      = 0,
  43         RESET_TYPE_WAKEUP       = 1,
  44         RESET_TYPE_WATCHDOG     = 2,
  45         RESET_TYPE_SOFTWARE     = 3,
  46         RESET_TYPE_USER         = 4,
  47         RESET_TYPE_CPU_FAIL     = 6,
  48         RESET_TYPE_XTAL_FAIL    = 7,
  49         RESET_TYPE_ULP2         = 8,
  50 };
  51
  52 static void __iomem *at91_ramc_base[2], *at91_rstc_base;
  53 static struct clk *sclk;
  54
  55 /*
  56 * unless the SDRAM is cleanly shutdown before we hit the
  57 * reset register it can be left driving the data bus and
  58 * killing the chance of a subsequent boot from NAND
  59 */
  60 static int at91sam9260_restart(struct notifier_block *this, unsigned long mode,
  61                                void *cmd)
  62 {
  63         asm volatile(
  64                 /* Align to cache lines */
  65                 ".balign 32\n\t"
  66
  67                 /* Disable SDRAM accesses */
  68                 "str    %2, [%0, #" __stringify(AT91_SDRAMC_TR) "]\n\t"
  69
  70                 /* Power down SDRAM */
  71                 "str    %3, [%0, #" __stringify(AT91_SDRAMC_LPR) "]\n\t"
  72
  73                 /* Reset CPU */
  74                 "str    %4, [%1, #" __stringify(AT91_RSTC_CR) "]\n\t"
  75
  76                 "b      .\n\t"
  77                 :
  78                 : "r" (at91_ramc_base[0]),
  79                   "r" (at91_rstc_base),
  80                   "r" (1),
  81                   "r" cpu_to_le32(AT91_SDRAMC_LPCB_POWER_DOWN),
  82                   "r" cpu_to_le32(AT91_RSTC_KEY | AT91_RSTC_PERRST | AT91_RSTC_PROCRST));
  83
  84         return NOTIFY_DONE;
  85 }
  86
  87 static int at91sam9g45_restart(struct notifier_block *this, unsigned long mode,
  88                                void *cmd)
  89 {
  90         asm volatile(
  91                 /*
  92                  * Test wether we have a second RAM controller to care
  93                  * about.
  94                  *
  95                  * First, test that we can dereference the virtual address.
  96                  */
  97                 "cmp    %1, #0\n\t"
  98                 "beq    1f\n\t"
  99
 100                 /* Then, test that the RAM controller is enabled */
 101                 "ldr    r0, [%1]\n\t"
 102                 "cmp    r0, #0\n\t"
 103
 104                 /* Align to cache lines */
 105                 ".balign 32\n\t"
 106
 107                 /* Disable SDRAM0 accesses */
 108                 "1:     str     %3, [%0, #" __stringify(AT91_DDRSDRC_RTR) "]\n\t"
 109                 /* Power down SDRAM0 */
 110                 "       str     %4, [%0, #" __stringify(AT91_DDRSDRC_LPR) "]\n\t"
 111                 /* Disable SDRAM1 accesses */
 112                 "       strne   %3, [%1, #" __stringify(AT91_DDRSDRC_RTR) "]\n\t"
 113                 /* Power down SDRAM1 */
 114                 "       strne   %4, [%1, #" __stringify(AT91_DDRSDRC_LPR) "]\n\t"
 115                 /* Reset CPU */
 116                 "       str     %5, [%2, #" __stringify(AT91_RSTC_CR) "]\n\t"
 117
 118                 "       b       .\n\t"
 119                 :
 120                 : "r" (at91_ramc_base[0]),
 121                   "r" (at91_ramc_base[1]),
 122                   "r" (at91_rstc_base),
 123                   "r" (1),
 124                   "r" cpu_to_le32(AT91_DDRSDRC_LPCB_POWER_DOWN),
 125                   "r" cpu_to_le32(AT91_RSTC_KEY | AT91_RSTC_PERRST | AT91_RSTC_PROCRST)
 126                 : "r0");
 127
 128         return NOTIFY_DONE;
 129 }
 130
 131 static int sama5d3_restart(struct notifier_block *this, unsigned long mode,
 132                            void *cmd)
 133 {
 134         writel(cpu_to_le32(AT91_RSTC_KEY | AT91_RSTC_PERRST | AT91_RSTC_PROCRST),
 135                at91_rstc_base);
 136
 137         return NOTIFY_DONE;
 138 }
 139
 140 static int samx7_restart(struct notifier_block *this, unsigned long mode,
 141                          void *cmd)
 142 {
 143         writel(cpu_to_le32(AT91_RSTC_KEY | AT91_RSTC_PROCRST),
 144                at91_rstc_base);
 145
 146         return NOTIFY_DONE;
 147 }
 148
 149 static void __init at91_reset_status(struct platform_device *pdev)
 150 {
 151         const char *reason;
 152         u32 reg = readl(at91_rstc_base + AT91_RSTC_SR);
 153
 154         switch ((reg & AT91_RSTC_RSTTYP) >> 8) {
 155         case RESET_TYPE_GENERAL:
 156                 reason = "general reset";
 157                 break;
 158         case RESET_TYPE_WAKEUP:
 159                 reason = "wakeup";
 160                 break;
 161         case RESET_TYPE_WATCHDOG:
 162                 reason = "watchdog reset";
 163                 break;
 164         case RESET_TYPE_SOFTWARE:
 165                 reason = "software reset";
 166                 break;
 167         case RESET_TYPE_USER:
 168                 reason = "user reset";
 169                 break;
 170         case RESET_TYPE_CPU_FAIL:
 171                 reason = "CPU clock failure detection";
 172                 break;
 173         case RESET_TYPE_XTAL_FAIL:
 174                 reason = "32.768 kHz crystal failure detection";
 175                 break;
 176         case RESET_TYPE_ULP2:
 177                 reason = "ULP2 reset";
 178                 break;
 179         default:
 180                 reason = "unknown reset";
 181                 break;
 182         }
 183
 184         dev_info(&pdev->dev, "Starting after %s\n", reason);
 185 }
 186
 187 static const struct of_device_id at91_ramc_of_match[] = {
 188         { .compatible = "atmel,at91sam9260-sdramc", },
 189         { .compatible = "atmel,at91sam9g45-ddramc", },
 190         { /* sentinel */ }
 191 };
 192
 193 static const struct of_device_id at91_reset_of_match[] = {
 194         { .compatible = "atmel,at91sam9260-rstc", .data = at91sam9260_restart },
 195         { .compatible = "atmel,at91sam9g45-rstc", .data = at91sam9g45_restart },
 196         { .compatible = "atmel,sama5d3-rstc", .data = sama5d3_restart },
 197         { .compatible = "atmel,samx7-rstc", .data = samx7_restart },
 198         { .compatible = "microchip,sam9x60-rstc", .data = samx7_restart },
 199         { /* sentinel */ }
 200 };
 201 MODULE_DEVICE_TABLE(of, at91_reset_of_match);
 202
 203 static struct notifier_block at91_restart_nb = {
 204         .priority = 192,
 205 };
 206
 207 static int __init at91_reset_probe(struct platform_device *pdev)
 208 {
 209         const struct of_device_id *match;
 210         struct device_node *np;
 211         int ret, idx = 0;
 212
 213         at91_rstc_base = of_iomap(pdev->dev.of_node, 0);
 214         if (!at91_rstc_base) {
 215                 dev_err(&pdev->dev, "Could not map reset controller address\n");
 216                 return -ENODEV;
 217         }
 218
 219         if (!of_device_is_compatible(pdev->dev.of_node, "atmel,sama5d3-rstc")) {
 220                 /* we need to shutdown the ddr controller, so get ramc base */
 221                 for_each_matching_node(np, at91_ramc_of_match) {
 222                         at91_ramc_base[idx] = of_iomap(np, 0);
 223                         if (!at91_ramc_base[idx]) {
 224                                 dev_err(&pdev->dev, "Could not map ram controller address\n");
 225                                 of_node_put(np);
 226                                 return -ENODEV;
 227                         }
 228                         idx++;
 229                 }
 230         }
 231
 232         match = of_match_node(at91_reset_of_match, pdev->dev.of_node);
 233         at91_restart_nb.notifier_call = match->data;
 234
 235         sclk = devm_clk_get(&pdev->dev, NULL);
 236         if (IS_ERR(sclk))
 237                 return PTR_ERR(sclk);
 238
 239         ret = clk_prepare_enable(sclk);
 240         if (ret) {
 241                 dev_err(&pdev->dev, "Could not enable slow clock\n");
 242                 return ret;
 243         }
 244
 245         ret = register_restart_handler(&at91_restart_nb);
 246         if (ret) {
 247                 clk_disable_unprepare(sclk);
 248                 return ret;
 249         }
 250
 251         at91_reset_status(pdev);
 252
 253         return 0;
 254 }
 255
 256 static int __exit at91_reset_remove(struct platform_device *pdev)
 257 {
 258         unregister_restart_handler(&at91_restart_nb);
 259         clk_disable_unprepare(sclk);
 260
 261         return 0;
 262 }
 263
 264 static struct platform_driver at91_reset_driver = {
 265         .remove = __exit_p(at91_reset_remove),
 266         .driver = {
 267                 .name = "at91-reset",
 268                 .of_match_table = at91_reset_of_match,
 269         },
 270 };
 271 module_platform_driver_probe(at91_reset_driver, at91_reset_probe);
 272
 273 MODULE_AUTHOR("Atmel Corporation");
 274 MODULE_DESCRIPTION("Reset driver for Atmel SoCs");
 275 MODULE_LICENSE("GPL v2");