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Linux 5.1.15
[linux/fpc-iii.git] / drivers / scsi / hisi_sas / hisi_sas_v2_hw.c
blob89160ab3efb05648dc6a7b23acd8a45e87ca61a6
1 /*
2 * Copyright (c) 2016 Linaro Ltd.
3 * Copyright (c) 2016 Hisilicon Limited.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 */
11
12 #include "hisi_sas.h"
13 #define DRV_NAME "hisi_sas_v2_hw"
14
15 /* global registers need init*/
16 #define DLVRY_QUEUE_ENABLE 0x0
17 #define IOST_BASE_ADDR_LO 0x8
18 #define IOST_BASE_ADDR_HI 0xc
19 #define ITCT_BASE_ADDR_LO 0x10
20 #define ITCT_BASE_ADDR_HI 0x14
21 #define IO_BROKEN_MSG_ADDR_LO 0x18
22 #define IO_BROKEN_MSG_ADDR_HI 0x1c
23 #define PHY_CONTEXT 0x20
24 #define PHY_STATE 0x24
25 #define PHY_PORT_NUM_MA 0x28
26 #define PORT_STATE 0x2c
27 #define PORT_STATE_PHY8_PORT_NUM_OFF 16
28 #define PORT_STATE_PHY8_PORT_NUM_MSK (0xf << PORT_STATE_PHY8_PORT_NUM_OFF)
29 #define PORT_STATE_PHY8_CONN_RATE_OFF 20
30 #define PORT_STATE_PHY8_CONN_RATE_MSK (0xf << PORT_STATE_PHY8_CONN_RATE_OFF)
31 #define PHY_CONN_RATE 0x30
32 #define HGC_TRANS_TASK_CNT_LIMIT 0x38
33 #define AXI_AHB_CLK_CFG 0x3c
34 #define ITCT_CLR 0x44
35 #define ITCT_CLR_EN_OFF 16
36 #define ITCT_CLR_EN_MSK (0x1 << ITCT_CLR_EN_OFF)
37 #define ITCT_DEV_OFF 0
38 #define ITCT_DEV_MSK (0x7ff << ITCT_DEV_OFF)
39 #define AXI_USER1 0x48
40 #define AXI_USER2 0x4c
41 #define IO_SATA_BROKEN_MSG_ADDR_LO 0x58
42 #define IO_SATA_BROKEN_MSG_ADDR_HI 0x5c
43 #define SATA_INITI_D2H_STORE_ADDR_LO 0x60
44 #define SATA_INITI_D2H_STORE_ADDR_HI 0x64
45 #define HGC_SAS_TX_OPEN_FAIL_RETRY_CTRL 0x84
46 #define HGC_SAS_TXFAIL_RETRY_CTRL 0x88
47 #define HGC_GET_ITV_TIME 0x90
48 #define DEVICE_MSG_WORK_MODE 0x94
49 #define OPENA_WT_CONTI_TIME 0x9c
50 #define I_T_NEXUS_LOSS_TIME 0xa0
51 #define MAX_CON_TIME_LIMIT_TIME 0xa4
52 #define BUS_INACTIVE_LIMIT_TIME 0xa8
53 #define REJECT_TO_OPEN_LIMIT_TIME 0xac
54 #define CFG_AGING_TIME 0xbc
55 #define HGC_DFX_CFG2 0xc0
56 #define HGC_IOMB_PROC1_STATUS 0x104
57 #define CFG_1US_TIMER_TRSH 0xcc
58 #define HGC_LM_DFX_STATUS2 0x128
59 #define HGC_LM_DFX_STATUS2_IOSTLIST_OFF 0
60 #define HGC_LM_DFX_STATUS2_IOSTLIST_MSK (0xfff << \
61 HGC_LM_DFX_STATUS2_IOSTLIST_OFF)
62 #define HGC_LM_DFX_STATUS2_ITCTLIST_OFF 12
63 #define HGC_LM_DFX_STATUS2_ITCTLIST_MSK (0x7ff << \
64 HGC_LM_DFX_STATUS2_ITCTLIST_OFF)
65 #define HGC_CQE_ECC_ADDR 0x13c
66 #define HGC_CQE_ECC_1B_ADDR_OFF 0
67 #define HGC_CQE_ECC_1B_ADDR_MSK (0x3f << HGC_CQE_ECC_1B_ADDR_OFF)
68 #define HGC_CQE_ECC_MB_ADDR_OFF 8
69 #define HGC_CQE_ECC_MB_ADDR_MSK (0x3f << HGC_CQE_ECC_MB_ADDR_OFF)
70 #define HGC_IOST_ECC_ADDR 0x140
71 #define HGC_IOST_ECC_1B_ADDR_OFF 0
72 #define HGC_IOST_ECC_1B_ADDR_MSK (0x3ff << HGC_IOST_ECC_1B_ADDR_OFF)
73 #define HGC_IOST_ECC_MB_ADDR_OFF 16
74 #define HGC_IOST_ECC_MB_ADDR_MSK (0x3ff << HGC_IOST_ECC_MB_ADDR_OFF)
75 #define HGC_DQE_ECC_ADDR 0x144
76 #define HGC_DQE_ECC_1B_ADDR_OFF 0
77 #define HGC_DQE_ECC_1B_ADDR_MSK (0xfff << HGC_DQE_ECC_1B_ADDR_OFF)
78 #define HGC_DQE_ECC_MB_ADDR_OFF 16
79 #define HGC_DQE_ECC_MB_ADDR_MSK (0xfff << HGC_DQE_ECC_MB_ADDR_OFF)
80 #define HGC_INVLD_DQE_INFO 0x148
81 #define HGC_INVLD_DQE_INFO_FB_CH0_OFF 9
82 #define HGC_INVLD_DQE_INFO_FB_CH0_MSK (0x1 << HGC_INVLD_DQE_INFO_FB_CH0_OFF)
83 #define HGC_INVLD_DQE_INFO_FB_CH3_OFF 18
84 #define HGC_ITCT_ECC_ADDR 0x150
85 #define HGC_ITCT_ECC_1B_ADDR_OFF 0
86 #define HGC_ITCT_ECC_1B_ADDR_MSK (0x3ff << \
87 HGC_ITCT_ECC_1B_ADDR_OFF)
88 #define HGC_ITCT_ECC_MB_ADDR_OFF 16
89 #define HGC_ITCT_ECC_MB_ADDR_MSK (0x3ff << \
90 HGC_ITCT_ECC_MB_ADDR_OFF)
91 #define HGC_AXI_FIFO_ERR_INFO 0x154
92 #define AXI_ERR_INFO_OFF 0
93 #define AXI_ERR_INFO_MSK (0xff << AXI_ERR_INFO_OFF)
94 #define FIFO_ERR_INFO_OFF 8
95 #define FIFO_ERR_INFO_MSK (0xff << FIFO_ERR_INFO_OFF)
96 #define INT_COAL_EN 0x19c
97 #define OQ_INT_COAL_TIME 0x1a0
98 #define OQ_INT_COAL_CNT 0x1a4
99 #define ENT_INT_COAL_TIME 0x1a8
100 #define ENT_INT_COAL_CNT 0x1ac
101 #define OQ_INT_SRC 0x1b0
102 #define OQ_INT_SRC_MSK 0x1b4
103 #define ENT_INT_SRC1 0x1b8
104 #define ENT_INT_SRC1_D2H_FIS_CH0_OFF 0
105 #define ENT_INT_SRC1_D2H_FIS_CH0_MSK (0x1 << ENT_INT_SRC1_D2H_FIS_CH0_OFF)
106 #define ENT_INT_SRC1_D2H_FIS_CH1_OFF 8
107 #define ENT_INT_SRC1_D2H_FIS_CH1_MSK (0x1 << ENT_INT_SRC1_D2H_FIS_CH1_OFF)
108 #define ENT_INT_SRC2 0x1bc
109 #define ENT_INT_SRC3 0x1c0
110 #define ENT_INT_SRC3_WP_DEPTH_OFF 8
111 #define ENT_INT_SRC3_IPTT_SLOT_NOMATCH_OFF 9
112 #define ENT_INT_SRC3_RP_DEPTH_OFF 10
113 #define ENT_INT_SRC3_AXI_OFF 11
114 #define ENT_INT_SRC3_FIFO_OFF 12
115 #define ENT_INT_SRC3_LM_OFF 14
116 #define ENT_INT_SRC3_ITC_INT_OFF 15
117 #define ENT_INT_SRC3_ITC_INT_MSK (0x1 << ENT_INT_SRC3_ITC_INT_OFF)
118 #define ENT_INT_SRC3_ABT_OFF 16
119 #define ENT_INT_SRC_MSK1 0x1c4
120 #define ENT_INT_SRC_MSK2 0x1c8
121 #define ENT_INT_SRC_MSK3 0x1cc
122 #define ENT_INT_SRC_MSK3_ENT95_MSK_OFF 31
123 #define ENT_INT_SRC_MSK3_ENT95_MSK_MSK (0x1 << ENT_INT_SRC_MSK3_ENT95_MSK_OFF)
124 #define SAS_ECC_INTR 0x1e8
125 #define SAS_ECC_INTR_DQE_ECC_1B_OFF 0
126 #define SAS_ECC_INTR_DQE_ECC_MB_OFF 1
127 #define SAS_ECC_INTR_IOST_ECC_1B_OFF 2
128 #define SAS_ECC_INTR_IOST_ECC_MB_OFF 3
129 #define SAS_ECC_INTR_ITCT_ECC_MB_OFF 4
130 #define SAS_ECC_INTR_ITCT_ECC_1B_OFF 5
131 #define SAS_ECC_INTR_IOSTLIST_ECC_MB_OFF 6
132 #define SAS_ECC_INTR_IOSTLIST_ECC_1B_OFF 7
133 #define SAS_ECC_INTR_ITCTLIST_ECC_1B_OFF 8
134 #define SAS_ECC_INTR_ITCTLIST_ECC_MB_OFF 9
135 #define SAS_ECC_INTR_CQE_ECC_1B_OFF 10
136 #define SAS_ECC_INTR_CQE_ECC_MB_OFF 11
137 #define SAS_ECC_INTR_NCQ_MEM0_ECC_MB_OFF 12
138 #define SAS_ECC_INTR_NCQ_MEM0_ECC_1B_OFF 13
139 #define SAS_ECC_INTR_NCQ_MEM1_ECC_MB_OFF 14
140 #define SAS_ECC_INTR_NCQ_MEM1_ECC_1B_OFF 15
141 #define SAS_ECC_INTR_NCQ_MEM2_ECC_MB_OFF 16
142 #define SAS_ECC_INTR_NCQ_MEM2_ECC_1B_OFF 17
143 #define SAS_ECC_INTR_NCQ_MEM3_ECC_MB_OFF 18
144 #define SAS_ECC_INTR_NCQ_MEM3_ECC_1B_OFF 19
145 #define SAS_ECC_INTR_MSK 0x1ec
146 #define HGC_ERR_STAT_EN 0x238
147 #define CQE_SEND_CNT 0x248
148 #define DLVRY_Q_0_BASE_ADDR_LO 0x260
149 #define DLVRY_Q_0_BASE_ADDR_HI 0x264
150 #define DLVRY_Q_0_DEPTH 0x268
151 #define DLVRY_Q_0_WR_PTR 0x26c
152 #define DLVRY_Q_0_RD_PTR 0x270
153 #define HYPER_STREAM_ID_EN_CFG 0xc80
154 #define OQ0_INT_SRC_MSK 0xc90
155 #define COMPL_Q_0_BASE_ADDR_LO 0x4e0
156 #define COMPL_Q_0_BASE_ADDR_HI 0x4e4
157 #define COMPL_Q_0_DEPTH 0x4e8
158 #define COMPL_Q_0_WR_PTR 0x4ec
159 #define COMPL_Q_0_RD_PTR 0x4f0
160 #define HGC_RXM_DFX_STATUS14 0xae8
161 #define HGC_RXM_DFX_STATUS14_MEM0_OFF 0
162 #define HGC_RXM_DFX_STATUS14_MEM0_MSK (0x1ff << \
163 HGC_RXM_DFX_STATUS14_MEM0_OFF)
164 #define HGC_RXM_DFX_STATUS14_MEM1_OFF 9
165 #define HGC_RXM_DFX_STATUS14_MEM1_MSK (0x1ff << \
166 HGC_RXM_DFX_STATUS14_MEM1_OFF)
167 #define HGC_RXM_DFX_STATUS14_MEM2_OFF 18
168 #define HGC_RXM_DFX_STATUS14_MEM2_MSK (0x1ff << \
169 HGC_RXM_DFX_STATUS14_MEM2_OFF)
170 #define HGC_RXM_DFX_STATUS15 0xaec
171 #define HGC_RXM_DFX_STATUS15_MEM3_OFF 0
172 #define HGC_RXM_DFX_STATUS15_MEM3_MSK (0x1ff << \
173 HGC_RXM_DFX_STATUS15_MEM3_OFF)
174 /* phy registers need init */
175 #define PORT_BASE (0x2000)
176
177 #define PHY_CFG (PORT_BASE + 0x0)
178 #define HARD_PHY_LINKRATE (PORT_BASE + 0x4)
179 #define PHY_CFG_ENA_OFF 0
180 #define PHY_CFG_ENA_MSK (0x1 << PHY_CFG_ENA_OFF)
181 #define PHY_CFG_DC_OPT_OFF 2
182 #define PHY_CFG_DC_OPT_MSK (0x1 << PHY_CFG_DC_OPT_OFF)
183 #define PROG_PHY_LINK_RATE (PORT_BASE + 0x8)
184 #define PROG_PHY_LINK_RATE_MAX_OFF 0
185 #define PROG_PHY_LINK_RATE_MAX_MSK (0xff << PROG_PHY_LINK_RATE_MAX_OFF)
186 #define PHY_CTRL (PORT_BASE + 0x14)
187 #define PHY_CTRL_RESET_OFF 0
188 #define PHY_CTRL_RESET_MSK (0x1 << PHY_CTRL_RESET_OFF)
189 #define SAS_PHY_CTRL (PORT_BASE + 0x20)
190 #define SL_CFG (PORT_BASE + 0x84)
191 #define PHY_PCN (PORT_BASE + 0x44)
192 #define SL_TOUT_CFG (PORT_BASE + 0x8c)
193 #define SL_CONTROL (PORT_BASE + 0x94)
194 #define SL_CONTROL_NOTIFY_EN_OFF 0
195 #define SL_CONTROL_NOTIFY_EN_MSK (0x1 << SL_CONTROL_NOTIFY_EN_OFF)
196 #define SL_CONTROL_CTA_OFF 17
197 #define SL_CONTROL_CTA_MSK (0x1 << SL_CONTROL_CTA_OFF)
198 #define RX_PRIMS_STATUS (PORT_BASE + 0x98)
199 #define RX_BCAST_CHG_OFF 1
200 #define RX_BCAST_CHG_MSK (0x1 << RX_BCAST_CHG_OFF)
201 #define TX_ID_DWORD0 (PORT_BASE + 0x9c)
202 #define TX_ID_DWORD1 (PORT_BASE + 0xa0)
203 #define TX_ID_DWORD2 (PORT_BASE + 0xa4)
204 #define TX_ID_DWORD3 (PORT_BASE + 0xa8)
205 #define TX_ID_DWORD4 (PORT_BASE + 0xaC)
206 #define TX_ID_DWORD5 (PORT_BASE + 0xb0)
207 #define TX_ID_DWORD6 (PORT_BASE + 0xb4)
208 #define TXID_AUTO (PORT_BASE + 0xb8)
209 #define TXID_AUTO_CT3_OFF 1
210 #define TXID_AUTO_CT3_MSK (0x1 << TXID_AUTO_CT3_OFF)
211 #define TXID_AUTO_CTB_OFF 11
212 #define TXID_AUTO_CTB_MSK (0x1 << TXID_AUTO_CTB_OFF)
213 #define TX_HARDRST_OFF 2
214 #define TX_HARDRST_MSK (0x1 << TX_HARDRST_OFF)
215 #define RX_IDAF_DWORD0 (PORT_BASE + 0xc4)
216 #define RX_IDAF_DWORD1 (PORT_BASE + 0xc8)
217 #define RX_IDAF_DWORD2 (PORT_BASE + 0xcc)
218 #define RX_IDAF_DWORD3 (PORT_BASE + 0xd0)
219 #define RX_IDAF_DWORD4 (PORT_BASE + 0xd4)
220 #define RX_IDAF_DWORD5 (PORT_BASE + 0xd8)
221 #define RX_IDAF_DWORD6 (PORT_BASE + 0xdc)
222 #define RXOP_CHECK_CFG_H (PORT_BASE + 0xfc)
223 #define CON_CONTROL (PORT_BASE + 0x118)
224 #define CON_CONTROL_CFG_OPEN_ACC_STP_OFF 0
225 #define CON_CONTROL_CFG_OPEN_ACC_STP_MSK \
226 (0x01 << CON_CONTROL_CFG_OPEN_ACC_STP_OFF)
227 #define DONE_RECEIVED_TIME (PORT_BASE + 0x11c)
228 #define CHL_INT0 (PORT_BASE + 0x1b4)
229 #define CHL_INT0_HOTPLUG_TOUT_OFF 0
230 #define CHL_INT0_HOTPLUG_TOUT_MSK (0x1 << CHL_INT0_HOTPLUG_TOUT_OFF)
231 #define CHL_INT0_SL_RX_BCST_ACK_OFF 1
232 #define CHL_INT0_SL_RX_BCST_ACK_MSK (0x1 << CHL_INT0_SL_RX_BCST_ACK_OFF)
233 #define CHL_INT0_SL_PHY_ENABLE_OFF 2
234 #define CHL_INT0_SL_PHY_ENABLE_MSK (0x1 << CHL_INT0_SL_PHY_ENABLE_OFF)
235 #define CHL_INT0_NOT_RDY_OFF 4
236 #define CHL_INT0_NOT_RDY_MSK (0x1 << CHL_INT0_NOT_RDY_OFF)
237 #define CHL_INT0_PHY_RDY_OFF 5
238 #define CHL_INT0_PHY_RDY_MSK (0x1 << CHL_INT0_PHY_RDY_OFF)
239 #define CHL_INT1 (PORT_BASE + 0x1b8)
240 #define CHL_INT1_DMAC_TX_ECC_ERR_OFF 15
241 #define CHL_INT1_DMAC_TX_ECC_ERR_MSK (0x1 << CHL_INT1_DMAC_TX_ECC_ERR_OFF)
242 #define CHL_INT1_DMAC_RX_ECC_ERR_OFF 17
243 #define CHL_INT1_DMAC_RX_ECC_ERR_MSK (0x1 << CHL_INT1_DMAC_RX_ECC_ERR_OFF)
244 #define CHL_INT1_DMAC_TX_AXI_WR_ERR_OFF 19
245 #define CHL_INT1_DMAC_TX_AXI_RD_ERR_OFF 20
246 #define CHL_INT1_DMAC_RX_AXI_WR_ERR_OFF 21
247 #define CHL_INT1_DMAC_RX_AXI_RD_ERR_OFF 22
248 #define CHL_INT2 (PORT_BASE + 0x1bc)
249 #define CHL_INT2_SL_IDAF_TOUT_CONF_OFF 0
250 #define CHL_INT0_MSK (PORT_BASE + 0x1c0)
251 #define CHL_INT1_MSK (PORT_BASE + 0x1c4)
252 #define CHL_INT2_MSK (PORT_BASE + 0x1c8)
253 #define CHL_INT_COAL_EN (PORT_BASE + 0x1d0)
254 #define DMA_TX_DFX0 (PORT_BASE + 0x200)
255 #define DMA_TX_DFX1 (PORT_BASE + 0x204)
256 #define DMA_TX_DFX1_IPTT_OFF 0
257 #define DMA_TX_DFX1_IPTT_MSK (0xffff << DMA_TX_DFX1_IPTT_OFF)
258 #define DMA_TX_FIFO_DFX0 (PORT_BASE + 0x240)
259 #define PORT_DFX0 (PORT_BASE + 0x258)
260 #define LINK_DFX2 (PORT_BASE + 0X264)
261 #define LINK_DFX2_RCVR_HOLD_STS_OFF 9
262 #define LINK_DFX2_RCVR_HOLD_STS_MSK (0x1 << LINK_DFX2_RCVR_HOLD_STS_OFF)
263 #define LINK_DFX2_SEND_HOLD_STS_OFF 10
264 #define LINK_DFX2_SEND_HOLD_STS_MSK (0x1 << LINK_DFX2_SEND_HOLD_STS_OFF)
265 #define SAS_ERR_CNT4_REG (PORT_BASE + 0x290)
266 #define SAS_ERR_CNT6_REG (PORT_BASE + 0x298)
267 #define PHY_CTRL_RDY_MSK (PORT_BASE + 0x2b0)
268 #define PHYCTRL_NOT_RDY_MSK (PORT_BASE + 0x2b4)
269 #define PHYCTRL_DWS_RESET_MSK (PORT_BASE + 0x2b8)
270 #define PHYCTRL_PHY_ENA_MSK (PORT_BASE + 0x2bc)
271 #define SL_RX_BCAST_CHK_MSK (PORT_BASE + 0x2c0)
272 #define PHYCTRL_OOB_RESTART_MSK (PORT_BASE + 0x2c4)
273 #define DMA_TX_STATUS (PORT_BASE + 0x2d0)
274 #define DMA_TX_STATUS_BUSY_OFF 0
275 #define DMA_TX_STATUS_BUSY_MSK (0x1 << DMA_TX_STATUS_BUSY_OFF)
276 #define DMA_RX_STATUS (PORT_BASE + 0x2e8)
277 #define DMA_RX_STATUS_BUSY_OFF 0
278 #define DMA_RX_STATUS_BUSY_MSK (0x1 << DMA_RX_STATUS_BUSY_OFF)
279
280 #define AXI_CFG (0x5100)
281 #define AM_CFG_MAX_TRANS (0x5010)
282 #define AM_CFG_SINGLE_PORT_MAX_TRANS (0x5014)
283
284 #define AXI_MASTER_CFG_BASE (0x5000)
285 #define AM_CTRL_GLOBAL (0x0)
286 #define AM_CURR_TRANS_RETURN (0x150)
287
288 /* HW dma structures */
289 /* Delivery queue header */
290 /* dw0 */
291 #define CMD_HDR_ABORT_FLAG_OFF 0
292 #define CMD_HDR_ABORT_FLAG_MSK (0x3 << CMD_HDR_ABORT_FLAG_OFF)
293 #define CMD_HDR_ABORT_DEVICE_TYPE_OFF 2
294 #define CMD_HDR_ABORT_DEVICE_TYPE_MSK (0x1 << CMD_HDR_ABORT_DEVICE_TYPE_OFF)
295 #define CMD_HDR_RESP_REPORT_OFF 5
296 #define CMD_HDR_RESP_REPORT_MSK (0x1 << CMD_HDR_RESP_REPORT_OFF)
297 #define CMD_HDR_TLR_CTRL_OFF 6
298 #define CMD_HDR_TLR_CTRL_MSK (0x3 << CMD_HDR_TLR_CTRL_OFF)
299 #define CMD_HDR_PHY_ID_OFF 8
300 #define CMD_HDR_PHY_ID_MSK (0x1ff << CMD_HDR_PHY_ID_OFF)
301 #define CMD_HDR_FORCE_PHY_OFF 17
302 #define CMD_HDR_FORCE_PHY_MSK (0x1 << CMD_HDR_FORCE_PHY_OFF)
303 #define CMD_HDR_PORT_OFF 18
304 #define CMD_HDR_PORT_MSK (0xf << CMD_HDR_PORT_OFF)
305 #define CMD_HDR_PRIORITY_OFF 27
306 #define CMD_HDR_PRIORITY_MSK (0x1 << CMD_HDR_PRIORITY_OFF)
307 #define CMD_HDR_CMD_OFF 29
308 #define CMD_HDR_CMD_MSK (0x7 << CMD_HDR_CMD_OFF)
309 /* dw1 */
310 #define CMD_HDR_DIR_OFF 5
311 #define CMD_HDR_DIR_MSK (0x3 << CMD_HDR_DIR_OFF)
312 #define CMD_HDR_RESET_OFF 7
313 #define CMD_HDR_RESET_MSK (0x1 << CMD_HDR_RESET_OFF)
314 #define CMD_HDR_VDTL_OFF 10
315 #define CMD_HDR_VDTL_MSK (0x1 << CMD_HDR_VDTL_OFF)
316 #define CMD_HDR_FRAME_TYPE_OFF 11
317 #define CMD_HDR_FRAME_TYPE_MSK (0x1f << CMD_HDR_FRAME_TYPE_OFF)
318 #define CMD_HDR_DEV_ID_OFF 16
319 #define CMD_HDR_DEV_ID_MSK (0xffff << CMD_HDR_DEV_ID_OFF)
320 /* dw2 */
321 #define CMD_HDR_CFL_OFF 0
322 #define CMD_HDR_CFL_MSK (0x1ff << CMD_HDR_CFL_OFF)
323 #define CMD_HDR_NCQ_TAG_OFF 10
324 #define CMD_HDR_NCQ_TAG_MSK (0x1f << CMD_HDR_NCQ_TAG_OFF)
325 #define CMD_HDR_MRFL_OFF 15
326 #define CMD_HDR_MRFL_MSK (0x1ff << CMD_HDR_MRFL_OFF)
327 #define CMD_HDR_SG_MOD_OFF 24
328 #define CMD_HDR_SG_MOD_MSK (0x3 << CMD_HDR_SG_MOD_OFF)
329 #define CMD_HDR_FIRST_BURST_OFF 26
330 #define CMD_HDR_FIRST_BURST_MSK (0x1 << CMD_HDR_SG_MOD_OFF)
331 /* dw3 */
332 #define CMD_HDR_IPTT_OFF 0
333 #define CMD_HDR_IPTT_MSK (0xffff << CMD_HDR_IPTT_OFF)
334 /* dw6 */
335 #define CMD_HDR_DIF_SGL_LEN_OFF 0
336 #define CMD_HDR_DIF_SGL_LEN_MSK (0xffff << CMD_HDR_DIF_SGL_LEN_OFF)
337 #define CMD_HDR_DATA_SGL_LEN_OFF 16
338 #define CMD_HDR_DATA_SGL_LEN_MSK (0xffff << CMD_HDR_DATA_SGL_LEN_OFF)
339 #define CMD_HDR_ABORT_IPTT_OFF 16
340 #define CMD_HDR_ABORT_IPTT_MSK (0xffff << CMD_HDR_ABORT_IPTT_OFF)
341
342 /* Completion header */
343 /* dw0 */
344 #define CMPLT_HDR_ERR_PHASE_OFF 2
345 #define CMPLT_HDR_ERR_PHASE_MSK (0xff << CMPLT_HDR_ERR_PHASE_OFF)
346 #define CMPLT_HDR_RSPNS_XFRD_OFF 10
347 #define CMPLT_HDR_RSPNS_XFRD_MSK (0x1 << CMPLT_HDR_RSPNS_XFRD_OFF)
348 #define CMPLT_HDR_ERX_OFF 12
349 #define CMPLT_HDR_ERX_MSK (0x1 << CMPLT_HDR_ERX_OFF)
350 #define CMPLT_HDR_ABORT_STAT_OFF 13
351 #define CMPLT_HDR_ABORT_STAT_MSK (0x7 << CMPLT_HDR_ABORT_STAT_OFF)
352 /* abort_stat */
353 #define STAT_IO_NOT_VALID 0x1
354 #define STAT_IO_NO_DEVICE 0x2
355 #define STAT_IO_COMPLETE 0x3
356 #define STAT_IO_ABORTED 0x4
357 /* dw1 */
358 #define CMPLT_HDR_IPTT_OFF 0
359 #define CMPLT_HDR_IPTT_MSK (0xffff << CMPLT_HDR_IPTT_OFF)
360 #define CMPLT_HDR_DEV_ID_OFF 16
361 #define CMPLT_HDR_DEV_ID_MSK (0xffff << CMPLT_HDR_DEV_ID_OFF)
362
363 /* ITCT header */
364 /* qw0 */
365 #define ITCT_HDR_DEV_TYPE_OFF 0
366 #define ITCT_HDR_DEV_TYPE_MSK (0x3 << ITCT_HDR_DEV_TYPE_OFF)
367 #define ITCT_HDR_VALID_OFF 2
368 #define ITCT_HDR_VALID_MSK (0x1 << ITCT_HDR_VALID_OFF)
369 #define ITCT_HDR_MCR_OFF 5
370 #define ITCT_HDR_MCR_MSK (0xf << ITCT_HDR_MCR_OFF)
371 #define ITCT_HDR_VLN_OFF 9
372 #define ITCT_HDR_VLN_MSK (0xf << ITCT_HDR_VLN_OFF)
373 #define ITCT_HDR_SMP_TIMEOUT_OFF 16
374 #define ITCT_HDR_SMP_TIMEOUT_8US 1
375 #define ITCT_HDR_SMP_TIMEOUT (ITCT_HDR_SMP_TIMEOUT_8US * \
376 250) /* 2ms */
377 #define ITCT_HDR_AWT_CONTINUE_OFF 25
378 #define ITCT_HDR_PORT_ID_OFF 28
379 #define ITCT_HDR_PORT_ID_MSK (0xf << ITCT_HDR_PORT_ID_OFF)
380 /* qw2 */
381 #define ITCT_HDR_INLT_OFF 0
382 #define ITCT_HDR_INLT_MSK (0xffffULL << ITCT_HDR_INLT_OFF)
383 #define ITCT_HDR_BITLT_OFF 16
384 #define ITCT_HDR_BITLT_MSK (0xffffULL << ITCT_HDR_BITLT_OFF)
385 #define ITCT_HDR_MCTLT_OFF 32
386 #define ITCT_HDR_MCTLT_MSK (0xffffULL << ITCT_HDR_MCTLT_OFF)
387 #define ITCT_HDR_RTOLT_OFF 48
388 #define ITCT_HDR_RTOLT_MSK (0xffffULL << ITCT_HDR_RTOLT_OFF)
389
390 #define HISI_SAS_FATAL_INT_NR 2
391
392 struct hisi_sas_complete_v2_hdr {
393 __le32 dw0;
394 __le32 dw1;
395 __le32 act;
396 __le32 dw3;
397 };
398
399 struct hisi_sas_err_record_v2 {
400 /* dw0 */
401 __le32 trans_tx_fail_type;
402
403 /* dw1 */
404 __le32 trans_rx_fail_type;
405
406 /* dw2 */
407 __le16 dma_tx_err_type;
408 __le16 sipc_rx_err_type;
409
410 /* dw3 */
411 __le32 dma_rx_err_type;
412 };
413
414 struct signal_attenuation_s {
415 u32 de_emphasis;
416 u32 preshoot;
417 u32 boost;
418 };
419
420 struct sig_atten_lu_s {
421 const struct signal_attenuation_s *att;
422 u32 sas_phy_ctrl;
423 };
424
425 static const struct hisi_sas_hw_error one_bit_ecc_errors[] = {
426 {
427 .irq_msk = BIT(SAS_ECC_INTR_DQE_ECC_1B_OFF),
428 .msk = HGC_DQE_ECC_1B_ADDR_MSK,
429 .shift = HGC_DQE_ECC_1B_ADDR_OFF,
430 .msg = "hgc_dqe_acc1b_intr found: Ram address is 0x%08X\n",
431 .reg = HGC_DQE_ECC_ADDR,
432 },
433 {
434 .irq_msk = BIT(SAS_ECC_INTR_IOST_ECC_1B_OFF),
435 .msk = HGC_IOST_ECC_1B_ADDR_MSK,
436 .shift = HGC_IOST_ECC_1B_ADDR_OFF,
437 .msg = "hgc_iost_acc1b_intr found: Ram address is 0x%08X\n",
438 .reg = HGC_IOST_ECC_ADDR,
439 },
440 {
441 .irq_msk = BIT(SAS_ECC_INTR_ITCT_ECC_1B_OFF),
442 .msk = HGC_ITCT_ECC_1B_ADDR_MSK,
443 .shift = HGC_ITCT_ECC_1B_ADDR_OFF,
444 .msg = "hgc_itct_acc1b_intr found: am address is 0x%08X\n",
445 .reg = HGC_ITCT_ECC_ADDR,
446 },
447 {
448 .irq_msk = BIT(SAS_ECC_INTR_IOSTLIST_ECC_1B_OFF),
449 .msk = HGC_LM_DFX_STATUS2_IOSTLIST_MSK,
450 .shift = HGC_LM_DFX_STATUS2_IOSTLIST_OFF,
451 .msg = "hgc_iostl_acc1b_intr found: memory address is 0x%08X\n",
452 .reg = HGC_LM_DFX_STATUS2,
453 },
454 {
455 .irq_msk = BIT(SAS_ECC_INTR_ITCTLIST_ECC_1B_OFF),
456 .msk = HGC_LM_DFX_STATUS2_ITCTLIST_MSK,
457 .shift = HGC_LM_DFX_STATUS2_ITCTLIST_OFF,
458 .msg = "hgc_itctl_acc1b_intr found: memory address is 0x%08X\n",
459 .reg = HGC_LM_DFX_STATUS2,
460 },
461 {
462 .irq_msk = BIT(SAS_ECC_INTR_CQE_ECC_1B_OFF),
463 .msk = HGC_CQE_ECC_1B_ADDR_MSK,
464 .shift = HGC_CQE_ECC_1B_ADDR_OFF,
465 .msg = "hgc_cqe_acc1b_intr found: Ram address is 0x%08X\n",
466 .reg = HGC_CQE_ECC_ADDR,
467 },
468 {
469 .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM0_ECC_1B_OFF),
470 .msk = HGC_RXM_DFX_STATUS14_MEM0_MSK,
471 .shift = HGC_RXM_DFX_STATUS14_MEM0_OFF,
472 .msg = "rxm_mem0_acc1b_intr found: memory address is 0x%08X\n",
473 .reg = HGC_RXM_DFX_STATUS14,
474 },
475 {
476 .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM1_ECC_1B_OFF),
477 .msk = HGC_RXM_DFX_STATUS14_MEM1_MSK,
478 .shift = HGC_RXM_DFX_STATUS14_MEM1_OFF,
479 .msg = "rxm_mem1_acc1b_intr found: memory address is 0x%08X\n",
480 .reg = HGC_RXM_DFX_STATUS14,
481 },
482 {
483 .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM2_ECC_1B_OFF),
484 .msk = HGC_RXM_DFX_STATUS14_MEM2_MSK,
485 .shift = HGC_RXM_DFX_STATUS14_MEM2_OFF,
486 .msg = "rxm_mem2_acc1b_intr found: memory address is 0x%08X\n",
487 .reg = HGC_RXM_DFX_STATUS14,
488 },
489 {
490 .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM3_ECC_1B_OFF),
491 .msk = HGC_RXM_DFX_STATUS15_MEM3_MSK,
492 .shift = HGC_RXM_DFX_STATUS15_MEM3_OFF,
493 .msg = "rxm_mem3_acc1b_intr found: memory address is 0x%08X\n",
494 .reg = HGC_RXM_DFX_STATUS15,
495 },
496 };
497
498 static const struct hisi_sas_hw_error multi_bit_ecc_errors[] = {
499 {
500 .irq_msk = BIT(SAS_ECC_INTR_DQE_ECC_MB_OFF),
501 .msk = HGC_DQE_ECC_MB_ADDR_MSK,
502 .shift = HGC_DQE_ECC_MB_ADDR_OFF,
503 .msg = "hgc_dqe_accbad_intr (0x%x) found: Ram address is 0x%08X\n",
504 .reg = HGC_DQE_ECC_ADDR,
505 },
506 {
507 .irq_msk = BIT(SAS_ECC_INTR_IOST_ECC_MB_OFF),
508 .msk = HGC_IOST_ECC_MB_ADDR_MSK,
509 .shift = HGC_IOST_ECC_MB_ADDR_OFF,
510 .msg = "hgc_iost_accbad_intr (0x%x) found: Ram address is 0x%08X\n",
511 .reg = HGC_IOST_ECC_ADDR,
512 },
513 {
514 .irq_msk = BIT(SAS_ECC_INTR_ITCT_ECC_MB_OFF),
515 .msk = HGC_ITCT_ECC_MB_ADDR_MSK,
516 .shift = HGC_ITCT_ECC_MB_ADDR_OFF,
517 .msg = "hgc_itct_accbad_intr (0x%x) found: Ram address is 0x%08X\n",
518 .reg = HGC_ITCT_ECC_ADDR,
519 },
520 {
521 .irq_msk = BIT(SAS_ECC_INTR_IOSTLIST_ECC_MB_OFF),
522 .msk = HGC_LM_DFX_STATUS2_IOSTLIST_MSK,
523 .shift = HGC_LM_DFX_STATUS2_IOSTLIST_OFF,
524 .msg = "hgc_iostl_accbad_intr (0x%x) found: memory address is 0x%08X\n",
525 .reg = HGC_LM_DFX_STATUS2,
526 },
527 {
528 .irq_msk = BIT(SAS_ECC_INTR_ITCTLIST_ECC_MB_OFF),
529 .msk = HGC_LM_DFX_STATUS2_ITCTLIST_MSK,
530 .shift = HGC_LM_DFX_STATUS2_ITCTLIST_OFF,
531 .msg = "hgc_itctl_accbad_intr (0x%x) found: memory address is 0x%08X\n",
532 .reg = HGC_LM_DFX_STATUS2,
533 },
534 {
535 .irq_msk = BIT(SAS_ECC_INTR_CQE_ECC_MB_OFF),
536 .msk = HGC_CQE_ECC_MB_ADDR_MSK,
537 .shift = HGC_CQE_ECC_MB_ADDR_OFF,
538 .msg = "hgc_cqe_accbad_intr (0x%x) found: Ram address is 0x%08X\n",
539 .reg = HGC_CQE_ECC_ADDR,
540 },
541 {
542 .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM0_ECC_MB_OFF),
543 .msk = HGC_RXM_DFX_STATUS14_MEM0_MSK,
544 .shift = HGC_RXM_DFX_STATUS14_MEM0_OFF,
545 .msg = "rxm_mem0_accbad_intr (0x%x) found: memory address is 0x%08X\n",
546 .reg = HGC_RXM_DFX_STATUS14,
547 },
548 {
549 .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM1_ECC_MB_OFF),
550 .msk = HGC_RXM_DFX_STATUS14_MEM1_MSK,
551 .shift = HGC_RXM_DFX_STATUS14_MEM1_OFF,
552 .msg = "rxm_mem1_accbad_intr (0x%x) found: memory address is 0x%08X\n",
553 .reg = HGC_RXM_DFX_STATUS14,
554 },
555 {
556 .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM2_ECC_MB_OFF),
557 .msk = HGC_RXM_DFX_STATUS14_MEM2_MSK,
558 .shift = HGC_RXM_DFX_STATUS14_MEM2_OFF,
559 .msg = "rxm_mem2_accbad_intr (0x%x) found: memory address is 0x%08X\n",
560 .reg = HGC_RXM_DFX_STATUS14,
561 },
562 {
563 .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM3_ECC_MB_OFF),
564 .msk = HGC_RXM_DFX_STATUS15_MEM3_MSK,
565 .shift = HGC_RXM_DFX_STATUS15_MEM3_OFF,
566 .msg = "rxm_mem3_accbad_intr (0x%x) found: memory address is 0x%08X\n",
567 .reg = HGC_RXM_DFX_STATUS15,
568 },
569 };
570
571 enum {
572 HISI_SAS_PHY_PHY_UPDOWN,
573 HISI_SAS_PHY_CHNL_INT,
574 HISI_SAS_PHY_INT_NR
575 };
576
577 enum {
578 TRANS_TX_FAIL_BASE = 0x0, /* dw0 */
579 TRANS_RX_FAIL_BASE = 0x20, /* dw1 */
580 DMA_TX_ERR_BASE = 0x40, /* dw2 bit 15-0 */
581 SIPC_RX_ERR_BASE = 0x50, /* dw2 bit 31-16*/
582 DMA_RX_ERR_BASE = 0x60, /* dw3 */
583
584 /* trans tx*/
585 TRANS_TX_OPEN_FAIL_WITH_IT_NEXUS_LOSS = TRANS_TX_FAIL_BASE, /* 0x0 */
586 TRANS_TX_ERR_PHY_NOT_ENABLE, /* 0x1 */
587 TRANS_TX_OPEN_CNX_ERR_WRONG_DESTINATION, /* 0x2 */
588 TRANS_TX_OPEN_CNX_ERR_ZONE_VIOLATION, /* 0x3 */
589 TRANS_TX_OPEN_CNX_ERR_BY_OTHER, /* 0x4 */
590 RESERVED0, /* 0x5 */
591 TRANS_TX_OPEN_CNX_ERR_AIP_TIMEOUT, /* 0x6 */
592 TRANS_TX_OPEN_CNX_ERR_STP_RESOURCES_BUSY, /* 0x7 */
593 TRANS_TX_OPEN_CNX_ERR_PROTOCOL_NOT_SUPPORTED, /* 0x8 */
594 TRANS_TX_OPEN_CNX_ERR_CONNECTION_RATE_NOT_SUPPORTED, /* 0x9 */
595 TRANS_TX_OPEN_CNX_ERR_BAD_DESTINATION, /* 0xa */
596 TRANS_TX_OPEN_CNX_ERR_BREAK_RCVD, /* 0xb */
597 TRANS_TX_OPEN_CNX_ERR_LOW_PHY_POWER, /* 0xc */
598 TRANS_TX_OPEN_CNX_ERR_PATHWAY_BLOCKED, /* 0xd */
599 TRANS_TX_OPEN_CNX_ERR_OPEN_TIMEOUT, /* 0xe */
600 TRANS_TX_OPEN_CNX_ERR_NO_DESTINATION, /* 0xf */
601 TRANS_TX_OPEN_RETRY_ERR_THRESHOLD_REACHED, /* 0x10 */
602 TRANS_TX_ERR_FRAME_TXED, /* 0x11 */
603 TRANS_TX_ERR_WITH_BREAK_TIMEOUT, /* 0x12 */
604 TRANS_TX_ERR_WITH_BREAK_REQUEST, /* 0x13 */
605 TRANS_TX_ERR_WITH_BREAK_RECEVIED, /* 0x14 */
606 TRANS_TX_ERR_WITH_CLOSE_TIMEOUT, /* 0x15 */
607 TRANS_TX_ERR_WITH_CLOSE_NORMAL, /* 0x16 for ssp*/
608 TRANS_TX_ERR_WITH_CLOSE_PHYDISALE, /* 0x17 */
609 TRANS_TX_ERR_WITH_CLOSE_DWS_TIMEOUT, /* 0x18 */
610 TRANS_TX_ERR_WITH_CLOSE_COMINIT, /* 0x19 */
611 TRANS_TX_ERR_WITH_NAK_RECEVIED, /* 0x1a for ssp*/
612 TRANS_TX_ERR_WITH_ACK_NAK_TIMEOUT, /* 0x1b for ssp*/
613 /*IO_TX_ERR_WITH_R_ERR_RECEVIED, [> 0x1b for sata/stp<] */
614 TRANS_TX_ERR_WITH_CREDIT_TIMEOUT, /* 0x1c for ssp */
615 /*IO_RX_ERR_WITH_SATA_DEVICE_LOST 0x1c for sata/stp */
616 TRANS_TX_ERR_WITH_IPTT_CONFLICT, /* 0x1d for ssp/smp */
617 TRANS_TX_ERR_WITH_OPEN_BY_DES_OR_OTHERS, /* 0x1e */
618 /*IO_TX_ERR_WITH_SYNC_RXD, [> 0x1e <] for sata/stp */
619 TRANS_TX_ERR_WITH_WAIT_RECV_TIMEOUT, /* 0x1f for sata/stp */
620
621 /* trans rx */
622 TRANS_RX_ERR_WITH_RXFRAME_CRC_ERR = TRANS_RX_FAIL_BASE, /* 0x20 */
623 TRANS_RX_ERR_WITH_RXFIS_8B10B_DISP_ERR, /* 0x21 for sata/stp */
624 TRANS_RX_ERR_WITH_RXFRAME_HAVE_ERRPRM, /* 0x22 for ssp/smp */
625 /*IO_ERR_WITH_RXFIS_8B10B_CODE_ERR, [> 0x22 <] for sata/stp */
626 TRANS_RX_ERR_WITH_RXFIS_DECODE_ERROR, /* 0x23 for sata/stp */
627 TRANS_RX_ERR_WITH_RXFIS_CRC_ERR, /* 0x24 for sata/stp */
628 TRANS_RX_ERR_WITH_RXFRAME_LENGTH_OVERRUN, /* 0x25 for smp */
629 /*IO_ERR_WITH_RXFIS_TX SYNCP, [> 0x25 <] for sata/stp */
630 TRANS_RX_ERR_WITH_RXFIS_RX_SYNCP, /* 0x26 for sata/stp*/
631 TRANS_RX_ERR_WITH_LINK_BUF_OVERRUN, /* 0x27 */
632 TRANS_RX_ERR_WITH_BREAK_TIMEOUT, /* 0x28 */
633 TRANS_RX_ERR_WITH_BREAK_REQUEST, /* 0x29 */
634 TRANS_RX_ERR_WITH_BREAK_RECEVIED, /* 0x2a */
635 RESERVED1, /* 0x2b */
636 TRANS_RX_ERR_WITH_CLOSE_NORMAL, /* 0x2c */
637 TRANS_RX_ERR_WITH_CLOSE_PHY_DISABLE, /* 0x2d */
638 TRANS_RX_ERR_WITH_CLOSE_DWS_TIMEOUT, /* 0x2e */
639 TRANS_RX_ERR_WITH_CLOSE_COMINIT, /* 0x2f */
640 TRANS_RX_ERR_WITH_DATA_LEN0, /* 0x30 for ssp/smp */
641 TRANS_RX_ERR_WITH_BAD_HASH, /* 0x31 for ssp */
642 /*IO_RX_ERR_WITH_FIS_TOO_SHORT, [> 0x31 <] for sata/stp */
643 TRANS_RX_XRDY_WLEN_ZERO_ERR, /* 0x32 for ssp*/
644 /*IO_RX_ERR_WITH_FIS_TOO_LONG, [> 0x32 <] for sata/stp */
645 TRANS_RX_SSP_FRM_LEN_ERR, /* 0x33 for ssp */
646 /*IO_RX_ERR_WITH_SATA_DEVICE_LOST, [> 0x33 <] for sata */
647 RESERVED2, /* 0x34 */
648 RESERVED3, /* 0x35 */
649 RESERVED4, /* 0x36 */
650 RESERVED5, /* 0x37 */
651 TRANS_RX_ERR_WITH_BAD_FRM_TYPE, /* 0x38 */
652 TRANS_RX_SMP_FRM_LEN_ERR, /* 0x39 */
653 TRANS_RX_SMP_RESP_TIMEOUT_ERR, /* 0x3a */
654 RESERVED6, /* 0x3b */
655 RESERVED7, /* 0x3c */
656 RESERVED8, /* 0x3d */
657 RESERVED9, /* 0x3e */
658 TRANS_RX_R_ERR, /* 0x3f */
659
660 /* dma tx */
661 DMA_TX_DIF_CRC_ERR = DMA_TX_ERR_BASE, /* 0x40 */
662 DMA_TX_DIF_APP_ERR, /* 0x41 */
663 DMA_TX_DIF_RPP_ERR, /* 0x42 */
664 DMA_TX_DATA_SGL_OVERFLOW, /* 0x43 */
665 DMA_TX_DIF_SGL_OVERFLOW, /* 0x44 */
666 DMA_TX_UNEXP_XFER_ERR, /* 0x45 */
667 DMA_TX_UNEXP_RETRANS_ERR, /* 0x46 */
668 DMA_TX_XFER_LEN_OVERFLOW, /* 0x47 */
669 DMA_TX_XFER_OFFSET_ERR, /* 0x48 */
670 DMA_TX_RAM_ECC_ERR, /* 0x49 */
671 DMA_TX_DIF_LEN_ALIGN_ERR, /* 0x4a */
672 DMA_TX_MAX_ERR_CODE,
673
674 /* sipc rx */
675 SIPC_RX_FIS_STATUS_ERR_BIT_VLD = SIPC_RX_ERR_BASE, /* 0x50 */
676 SIPC_RX_PIO_WRSETUP_STATUS_DRQ_ERR, /* 0x51 */
677 SIPC_RX_FIS_STATUS_BSY_BIT_ERR, /* 0x52 */
678 SIPC_RX_WRSETUP_LEN_ODD_ERR, /* 0x53 */
679 SIPC_RX_WRSETUP_LEN_ZERO_ERR, /* 0x54 */
680 SIPC_RX_WRDATA_LEN_NOT_MATCH_ERR, /* 0x55 */
681 SIPC_RX_NCQ_WRSETUP_OFFSET_ERR, /* 0x56 */
682 SIPC_RX_NCQ_WRSETUP_AUTO_ACTIVE_ERR, /* 0x57 */
683 SIPC_RX_SATA_UNEXP_FIS_ERR, /* 0x58 */
684 SIPC_RX_WRSETUP_ESTATUS_ERR, /* 0x59 */
685 SIPC_RX_DATA_UNDERFLOW_ERR, /* 0x5a */
686 SIPC_RX_MAX_ERR_CODE,
687
688 /* dma rx */
689 DMA_RX_DIF_CRC_ERR = DMA_RX_ERR_BASE, /* 0x60 */
690 DMA_RX_DIF_APP_ERR, /* 0x61 */
691 DMA_RX_DIF_RPP_ERR, /* 0x62 */
692 DMA_RX_DATA_SGL_OVERFLOW, /* 0x63 */
693 DMA_RX_DIF_SGL_OVERFLOW, /* 0x64 */
694 DMA_RX_DATA_LEN_OVERFLOW, /* 0x65 */
695 DMA_RX_DATA_LEN_UNDERFLOW, /* 0x66 */
696 DMA_RX_DATA_OFFSET_ERR, /* 0x67 */
697 RESERVED10, /* 0x68 */
698 DMA_RX_SATA_FRAME_TYPE_ERR, /* 0x69 */
699 DMA_RX_RESP_BUF_OVERFLOW, /* 0x6a */
700 DMA_RX_UNEXP_RETRANS_RESP_ERR, /* 0x6b */
701 DMA_RX_UNEXP_NORM_RESP_ERR, /* 0x6c */
702 DMA_RX_UNEXP_RDFRAME_ERR, /* 0x6d */
703 DMA_RX_PIO_DATA_LEN_ERR, /* 0x6e */
704 DMA_RX_RDSETUP_STATUS_ERR, /* 0x6f */
705 DMA_RX_RDSETUP_STATUS_DRQ_ERR, /* 0x70 */
706 DMA_RX_RDSETUP_STATUS_BSY_ERR, /* 0x71 */
707 DMA_RX_RDSETUP_LEN_ODD_ERR, /* 0x72 */
708 DMA_RX_RDSETUP_LEN_ZERO_ERR, /* 0x73 */
709 DMA_RX_RDSETUP_LEN_OVER_ERR, /* 0x74 */
710 DMA_RX_RDSETUP_OFFSET_ERR, /* 0x75 */
711 DMA_RX_RDSETUP_ACTIVE_ERR, /* 0x76 */
712 DMA_RX_RDSETUP_ESTATUS_ERR, /* 0x77 */
713 DMA_RX_RAM_ECC_ERR, /* 0x78 */
714 DMA_RX_UNKNOWN_FRM_ERR, /* 0x79 */
715 DMA_RX_MAX_ERR_CODE,
716 };
717
718 #define HISI_SAS_COMMAND_ENTRIES_V2_HW 4096
719 #define HISI_MAX_SATA_SUPPORT_V2_HW (HISI_SAS_COMMAND_ENTRIES_V2_HW/64 - 1)
720
721 #define DIR_NO_DATA 0
722 #define DIR_TO_INI 1
723 #define DIR_TO_DEVICE 2
724 #define DIR_RESERVED 3
725
726 #define ERR_ON_TX_PHASE(err_phase) (err_phase == 0x2 || \
727 err_phase == 0x4 || err_phase == 0x8 ||\
728 err_phase == 0x6 || err_phase == 0xa)
729 #define ERR_ON_RX_PHASE(err_phase) (err_phase == 0x10 || \
730 err_phase == 0x20 || err_phase == 0x40)
731
732 static void link_timeout_disable_link(struct timer_list *t);
733
734 static u32 hisi_sas_read32(struct hisi_hba *hisi_hba, u32 off)
735 {
736 void __iomem *regs = hisi_hba->regs + off;
737
738 return readl(regs);
739 }
740
741 static u32 hisi_sas_read32_relaxed(struct hisi_hba *hisi_hba, u32 off)
742 {
743 void __iomem *regs = hisi_hba->regs + off;
744
745 return readl_relaxed(regs);
746 }
747
748 static void hisi_sas_write32(struct hisi_hba *hisi_hba, u32 off, u32 val)
749 {
750 void __iomem *regs = hisi_hba->regs + off;
751
752 writel(val, regs);
753 }
754
755 static void hisi_sas_phy_write32(struct hisi_hba *hisi_hba, int phy_no,
756 u32 off, u32 val)
757 {
758 void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off;
759
760 writel(val, regs);
761 }
762
763 static u32 hisi_sas_phy_read32(struct hisi_hba *hisi_hba,
764 int phy_no, u32 off)
765 {
766 void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off;
767
768 return readl(regs);
769 }
770
771 /* This function needs to be protected from pre-emption. */
772 static int
773 slot_index_alloc_quirk_v2_hw(struct hisi_hba *hisi_hba,
774 struct domain_device *device)
775 {
776 int sata_dev = dev_is_sata(device);
777 void *bitmap = hisi_hba->slot_index_tags;
778 struct hisi_sas_device *sas_dev = device->lldd_dev;
779 int sata_idx = sas_dev->sata_idx;
780 int start, end;
781 unsigned long flags;
782
783 if (!sata_dev) {
784 /*
785 * STP link SoC bug workaround: index starts from 1.
786 * additionally, we can only allocate odd IPTT(1~4095)
787 * for SAS/SMP device.
788 */
789 start = 1;
790 end = hisi_hba->slot_index_count;
791 } else {
792 if (sata_idx >= HISI_MAX_SATA_SUPPORT_V2_HW)
793 return -EINVAL;
794
795 /*
796 * For SATA device: allocate even IPTT in this interval
797 * [64*(sata_idx+1), 64*(sata_idx+2)], then each SATA device
798 * own 32 IPTTs. IPTT 0 shall not be used duing to STP link
799 * SoC bug workaround. So we ignore the first 32 even IPTTs.
800 */
801 start = 64 * (sata_idx + 1);
802 end = 64 * (sata_idx + 2);
803 }
804
805 spin_lock_irqsave(&hisi_hba->lock, flags);
806 while (1) {
807 start = find_next_zero_bit(bitmap,
808 hisi_hba->slot_index_count, start);
809 if (start >= end) {
810 spin_unlock_irqrestore(&hisi_hba->lock, flags);
811 return -SAS_QUEUE_FULL;
812 }
813 /*
814 * SAS IPTT bit0 should be 1, and SATA IPTT bit0 should be 0.
815 */
816 if (sata_dev ^ (start & 1))
817 break;
818 start++;
819 }
820
821 set_bit(start, bitmap);
822 spin_unlock_irqrestore(&hisi_hba->lock, flags);
823 return start;
824 }
825
826 static bool sata_index_alloc_v2_hw(struct hisi_hba *hisi_hba, int *idx)
827 {
828 unsigned int index;
829 struct device *dev = hisi_hba->dev;
830 void *bitmap = hisi_hba->sata_dev_bitmap;
831
832 index = find_first_zero_bit(bitmap, HISI_MAX_SATA_SUPPORT_V2_HW);
833 if (index >= HISI_MAX_SATA_SUPPORT_V2_HW) {
834 dev_warn(dev, "alloc sata index failed, index=%d\n", index);
835 return false;
836 }
837
838 set_bit(index, bitmap);
839 *idx = index;
840 return true;
841 }
842
843
844 static struct
845 hisi_sas_device *alloc_dev_quirk_v2_hw(struct domain_device *device)
846 {
847 struct hisi_hba *hisi_hba = device->port->ha->lldd_ha;
848 struct hisi_sas_device *sas_dev = NULL;
849 int i, sata_dev = dev_is_sata(device);
850 int sata_idx = -1;
851 unsigned long flags;
852
853 spin_lock_irqsave(&hisi_hba->lock, flags);
854
855 if (sata_dev)
856 if (!sata_index_alloc_v2_hw(hisi_hba, &sata_idx))
857 goto out;
858
859 for (i = 0; i < HISI_SAS_MAX_DEVICES; i++) {
860 /*
861 * SATA device id bit0 should be 0
862 */
863 if (sata_dev && (i & 1))
864 continue;
865 if (hisi_hba->devices[i].dev_type == SAS_PHY_UNUSED) {
866 int queue = i % hisi_hba->queue_count;
867 struct hisi_sas_dq *dq = &hisi_hba->dq[queue];
868
869 hisi_hba->devices[i].device_id = i;
870 sas_dev = &hisi_hba->devices[i];
871 sas_dev->dev_status = HISI_SAS_DEV_INIT;
872 sas_dev->dev_type = device->dev_type;
873 sas_dev->hisi_hba = hisi_hba;
874 sas_dev->sas_device = device;
875 sas_dev->sata_idx = sata_idx;
876 sas_dev->dq = dq;
877 spin_lock_init(&sas_dev->lock);
878 INIT_LIST_HEAD(&hisi_hba->devices[i].list);
879 break;
880 }
881 }
882
883 out:
884 spin_unlock_irqrestore(&hisi_hba->lock, flags);
885
886 return sas_dev;
887 }
888
889 static void config_phy_opt_mode_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
890 {
891 u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
892
893 cfg &= ~PHY_CFG_DC_OPT_MSK;
894 cfg |= 1 << PHY_CFG_DC_OPT_OFF;
895 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
896 }
897
898 static void config_id_frame_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
899 {
900 struct sas_identify_frame identify_frame;
901 u32 *identify_buffer;
902
903 memset(&identify_frame, 0, sizeof(identify_frame));
904 identify_frame.dev_type = SAS_END_DEVICE;
905 identify_frame.frame_type = 0;
906 identify_frame._un1 = 1;
907 identify_frame.initiator_bits = SAS_PROTOCOL_ALL;
908 identify_frame.target_bits = SAS_PROTOCOL_NONE;
909 memcpy(&identify_frame._un4_11[0], hisi_hba->sas_addr, SAS_ADDR_SIZE);
910 memcpy(&identify_frame.sas_addr[0], hisi_hba->sas_addr, SAS_ADDR_SIZE);
911 identify_frame.phy_id = phy_no;
912 identify_buffer = (u32 *)(&identify_frame);
913
914 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD0,
915 __swab32(identify_buffer[0]));
916 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD1,
917 __swab32(identify_buffer[1]));
918 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD2,
919 __swab32(identify_buffer[2]));
920 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD3,
921 __swab32(identify_buffer[3]));
922 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD4,
923 __swab32(identify_buffer[4]));
924 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD5,
925 __swab32(identify_buffer[5]));
926 }
927
928 static void setup_itct_v2_hw(struct hisi_hba *hisi_hba,
929 struct hisi_sas_device *sas_dev)
930 {
931 struct domain_device *device = sas_dev->sas_device;
932 struct device *dev = hisi_hba->dev;
933 u64 qw0, device_id = sas_dev->device_id;
934 struct hisi_sas_itct *itct = &hisi_hba->itct[device_id];
935 struct domain_device *parent_dev = device->parent;
936 struct asd_sas_port *sas_port = device->port;
937 struct hisi_sas_port *port = to_hisi_sas_port(sas_port);
938 u64 sas_addr;
939
940 memset(itct, 0, sizeof(*itct));
941
942 /* qw0 */
943 qw0 = 0;
944 switch (sas_dev->dev_type) {
945 case SAS_END_DEVICE:
946 case SAS_EDGE_EXPANDER_DEVICE:
947 case SAS_FANOUT_EXPANDER_DEVICE:
948 qw0 = HISI_SAS_DEV_TYPE_SSP << ITCT_HDR_DEV_TYPE_OFF;
949 break;
950 case SAS_SATA_DEV:
951 case SAS_SATA_PENDING:
952 if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type))
953 qw0 = HISI_SAS_DEV_TYPE_STP << ITCT_HDR_DEV_TYPE_OFF;
954 else
955 qw0 = HISI_SAS_DEV_TYPE_SATA << ITCT_HDR_DEV_TYPE_OFF;
956 break;
957 default:
958 dev_warn(dev, "setup itct: unsupported dev type (%d)\n",
959 sas_dev->dev_type);
960 }
961
962 qw0 |= ((1 << ITCT_HDR_VALID_OFF) |
963 (device->linkrate << ITCT_HDR_MCR_OFF) |
964 (1 << ITCT_HDR_VLN_OFF) |
965 (ITCT_HDR_SMP_TIMEOUT << ITCT_HDR_SMP_TIMEOUT_OFF) |
966 (1 << ITCT_HDR_AWT_CONTINUE_OFF) |
967 (port->id << ITCT_HDR_PORT_ID_OFF));
968 itct->qw0 = cpu_to_le64(qw0);
969
970 /* qw1 */
971 memcpy(&sas_addr, device->sas_addr, SAS_ADDR_SIZE);
972 itct->sas_addr = cpu_to_le64(__swab64(sas_addr));
973
974 /* qw2 */
975 if (!dev_is_sata(device))
976 itct->qw2 = cpu_to_le64((5000ULL << ITCT_HDR_INLT_OFF) |
977 (0x1ULL << ITCT_HDR_BITLT_OFF) |
978 (0x32ULL << ITCT_HDR_MCTLT_OFF) |
979 (0x1ULL << ITCT_HDR_RTOLT_OFF));
980 }
981
982 static void clear_itct_v2_hw(struct hisi_hba *hisi_hba,
983 struct hisi_sas_device *sas_dev)
984 {
985 DECLARE_COMPLETION_ONSTACK(completion);
986 u64 dev_id = sas_dev->device_id;
987 struct hisi_sas_itct *itct = &hisi_hba->itct[dev_id];
988 u32 reg_val = hisi_sas_read32(hisi_hba, ENT_INT_SRC3);
989 int i;
990
991 sas_dev->completion = &completion;
992
993 /* clear the itct interrupt state */
994 if (ENT_INT_SRC3_ITC_INT_MSK & reg_val)
995 hisi_sas_write32(hisi_hba, ENT_INT_SRC3,
996 ENT_INT_SRC3_ITC_INT_MSK);
997
998 for (i = 0; i < 2; i++) {
999 reg_val = ITCT_CLR_EN_MSK | (dev_id & ITCT_DEV_MSK);
1000 hisi_sas_write32(hisi_hba, ITCT_CLR, reg_val);
1001 wait_for_completion(sas_dev->completion);
1002
1003 memset(itct, 0, sizeof(struct hisi_sas_itct));
1004 }
1005 }
1006
1007 static void free_device_v2_hw(struct hisi_sas_device *sas_dev)
1008 {
1009 struct hisi_hba *hisi_hba = sas_dev->hisi_hba;
1010
1011 /* SoC bug workaround */
1012 if (dev_is_sata(sas_dev->sas_device))
1013 clear_bit(sas_dev->sata_idx, hisi_hba->sata_dev_bitmap);
1014 }
1015
1016 static int reset_hw_v2_hw(struct hisi_hba *hisi_hba)
1017 {
1018 int i, reset_val;
1019 u32 val;
1020 unsigned long end_time;
1021 struct device *dev = hisi_hba->dev;
1022
1023 /* The mask needs to be set depending on the number of phys */
1024 if (hisi_hba->n_phy == 9)
1025 reset_val = 0x1fffff;
1026 else
1027 reset_val = 0x7ffff;
1028
1029 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 0);
1030
1031 /* Disable all of the PHYs */
1032 for (i = 0; i < hisi_hba->n_phy; i++) {
1033 u32 phy_cfg = hisi_sas_phy_read32(hisi_hba, i, PHY_CFG);
1034
1035 phy_cfg &= ~PHY_CTRL_RESET_MSK;
1036 hisi_sas_phy_write32(hisi_hba, i, PHY_CFG, phy_cfg);
1037 }
1038 udelay(50);
1039
1040 /* Ensure DMA tx & rx idle */
1041 for (i = 0; i < hisi_hba->n_phy; i++) {
1042 u32 dma_tx_status, dma_rx_status;
1043
1044 end_time = jiffies + msecs_to_jiffies(1000);
1045
1046 while (1) {
1047 dma_tx_status = hisi_sas_phy_read32(hisi_hba, i,
1048 DMA_TX_STATUS);
1049 dma_rx_status = hisi_sas_phy_read32(hisi_hba, i,
1050 DMA_RX_STATUS);
1051
1052 if (!(dma_tx_status & DMA_TX_STATUS_BUSY_MSK) &&
1053 !(dma_rx_status & DMA_RX_STATUS_BUSY_MSK))
1054 break;
1055
1056 msleep(20);
1057 if (time_after(jiffies, end_time))
1058 return -EIO;
1059 }
1060 }
1061
1062 /* Ensure axi bus idle */
1063 end_time = jiffies + msecs_to_jiffies(1000);
1064 while (1) {
1065 u32 axi_status =
1066 hisi_sas_read32(hisi_hba, AXI_CFG);
1067
1068 if (axi_status == 0)
1069 break;
1070
1071 msleep(20);
1072 if (time_after(jiffies, end_time))
1073 return -EIO;
1074 }
1075
1076 if (ACPI_HANDLE(dev)) {
1077 acpi_status s;
1078
1079 s = acpi_evaluate_object(ACPI_HANDLE(dev), "_RST", NULL, NULL);
1080 if (ACPI_FAILURE(s)) {
1081 dev_err(dev, "Reset failed\n");
1082 return -EIO;
1083 }
1084 } else if (hisi_hba->ctrl) {
1085 /* reset and disable clock*/
1086 regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_reset_reg,
1087 reset_val);
1088 regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_clock_ena_reg + 4,
1089 reset_val);
1090 msleep(1);
1091 regmap_read(hisi_hba->ctrl, hisi_hba->ctrl_reset_sts_reg, &val);
1092 if (reset_val != (val & reset_val)) {
1093 dev_err(dev, "SAS reset fail.\n");
1094 return -EIO;
1095 }
1096
1097 /* De-reset and enable clock*/
1098 regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_reset_reg + 4,
1099 reset_val);
1100 regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_clock_ena_reg,
1101 reset_val);
1102 msleep(1);
1103 regmap_read(hisi_hba->ctrl, hisi_hba->ctrl_reset_sts_reg,
1104 &val);
1105 if (val & reset_val) {
1106 dev_err(dev, "SAS de-reset fail.\n");
1107 return -EIO;
1108 }
1109 } else {
1110 dev_err(dev, "no reset method\n");
1111 return -EINVAL;
1112 }
1113
1114 return 0;
1115 }
1116
1117 /* This function needs to be called after resetting SAS controller. */
1118 static void phys_reject_stp_links_v2_hw(struct hisi_hba *hisi_hba)
1119 {
1120 u32 cfg;
1121 int phy_no;
1122
1123 hisi_hba->reject_stp_links_msk = (1 << hisi_hba->n_phy) - 1;
1124 for (phy_no = 0; phy_no < hisi_hba->n_phy; phy_no++) {
1125 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, CON_CONTROL);
1126 if (!(cfg & CON_CONTROL_CFG_OPEN_ACC_STP_MSK))
1127 continue;
1128
1129 cfg &= ~CON_CONTROL_CFG_OPEN_ACC_STP_MSK;
1130 hisi_sas_phy_write32(hisi_hba, phy_no, CON_CONTROL, cfg);
1131 }
1132 }
1133
1134 static void phys_try_accept_stp_links_v2_hw(struct hisi_hba *hisi_hba)
1135 {
1136 int phy_no;
1137 u32 dma_tx_dfx1;
1138
1139 for (phy_no = 0; phy_no < hisi_hba->n_phy; phy_no++) {
1140 if (!(hisi_hba->reject_stp_links_msk & BIT(phy_no)))
1141 continue;
1142
1143 dma_tx_dfx1 = hisi_sas_phy_read32(hisi_hba, phy_no,
1144 DMA_TX_DFX1);
1145 if (dma_tx_dfx1 & DMA_TX_DFX1_IPTT_MSK) {
1146 u32 cfg = hisi_sas_phy_read32(hisi_hba,
1147 phy_no, CON_CONTROL);
1148
1149 cfg |= CON_CONTROL_CFG_OPEN_ACC_STP_MSK;
1150 hisi_sas_phy_write32(hisi_hba, phy_no,
1151 CON_CONTROL, cfg);
1152 clear_bit(phy_no, &hisi_hba->reject_stp_links_msk);
1153 }
1154 }
1155 }
1156
1157 static const struct signal_attenuation_s x6000 = {9200, 0, 10476};
1158 static const struct sig_atten_lu_s sig_atten_lu[] = {
1159 { &x6000, 0x3016a68 },
1160 };
1161
1162 static void init_reg_v2_hw(struct hisi_hba *hisi_hba)
1163 {
1164 struct device *dev = hisi_hba->dev;
1165 u32 sas_phy_ctrl = 0x30b9908;
1166 u32 signal[3];
1167 int i;
1168
1169 /* Global registers init */
1170
1171 /* Deal with am-max-transmissions quirk */
1172 if (device_property_present(dev, "hip06-sas-v2-quirk-amt")) {
1173 hisi_sas_write32(hisi_hba, AM_CFG_MAX_TRANS, 0x2020);
1174 hisi_sas_write32(hisi_hba, AM_CFG_SINGLE_PORT_MAX_TRANS,
1175 0x2020);
1176 } /* Else, use defaults -> do nothing */
1177
1178 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE,
1179 (u32)((1ULL << hisi_hba->queue_count) - 1));
1180 hisi_sas_write32(hisi_hba, AXI_USER1, 0xc0000000);
1181 hisi_sas_write32(hisi_hba, AXI_USER2, 0x10000);
1182 hisi_sas_write32(hisi_hba, HGC_SAS_TXFAIL_RETRY_CTRL, 0x0);
1183 hisi_sas_write32(hisi_hba, HGC_SAS_TX_OPEN_FAIL_RETRY_CTRL, 0x7FF);
1184 hisi_sas_write32(hisi_hba, OPENA_WT_CONTI_TIME, 0x1);
1185 hisi_sas_write32(hisi_hba, I_T_NEXUS_LOSS_TIME, 0x1F4);
1186 hisi_sas_write32(hisi_hba, MAX_CON_TIME_LIMIT_TIME, 0x32);
1187 hisi_sas_write32(hisi_hba, BUS_INACTIVE_LIMIT_TIME, 0x1);
1188 hisi_sas_write32(hisi_hba, CFG_AGING_TIME, 0x1);
1189 hisi_sas_write32(hisi_hba, HGC_ERR_STAT_EN, 0x1);
1190 hisi_sas_write32(hisi_hba, HGC_GET_ITV_TIME, 0x1);
1191 hisi_sas_write32(hisi_hba, INT_COAL_EN, 0xc);
1192 hisi_sas_write32(hisi_hba, OQ_INT_COAL_TIME, 0x60);
1193 hisi_sas_write32(hisi_hba, OQ_INT_COAL_CNT, 0x3);
1194 hisi_sas_write32(hisi_hba, ENT_INT_COAL_TIME, 0x1);
1195 hisi_sas_write32(hisi_hba, ENT_INT_COAL_CNT, 0x1);
1196 hisi_sas_write32(hisi_hba, OQ_INT_SRC, 0x0);
1197 hisi_sas_write32(hisi_hba, ENT_INT_SRC1, 0xffffffff);
1198 hisi_sas_write32(hisi_hba, ENT_INT_SRC2, 0xffffffff);
1199 hisi_sas_write32(hisi_hba, ENT_INT_SRC3, 0xffffffff);
1200 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1, 0x7efefefe);
1201 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK2, 0x7efefefe);
1202 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, 0x7ffe20fe);
1203 hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, 0xfff00c30);
1204 for (i = 0; i < hisi_hba->queue_count; i++)
1205 hisi_sas_write32(hisi_hba, OQ0_INT_SRC_MSK+0x4*i, 0);
1206
1207 hisi_sas_write32(hisi_hba, AXI_AHB_CLK_CFG, 1);
1208 hisi_sas_write32(hisi_hba, HYPER_STREAM_ID_EN_CFG, 1);
1209
1210 /* Get sas_phy_ctrl value to deal with TX FFE issue. */
1211 if (!device_property_read_u32_array(dev, "hisilicon,signal-attenuation",
1212 signal, ARRAY_SIZE(signal))) {
1213 for (i = 0; i < ARRAY_SIZE(sig_atten_lu); i++) {
1214 const struct sig_atten_lu_s *lookup = &sig_atten_lu[i];
1215 const struct signal_attenuation_s *att = lookup->att;
1216
1217 if ((signal[0] == att->de_emphasis) &&
1218 (signal[1] == att->preshoot) &&
1219 (signal[2] == att->boost)) {
1220 sas_phy_ctrl = lookup->sas_phy_ctrl;
1221 break;
1222 }
1223 }
1224
1225 if (i == ARRAY_SIZE(sig_atten_lu))
1226 dev_warn(dev, "unknown signal attenuation values, using default PHY ctrl config\n");
1227 }
1228
1229 for (i = 0; i < hisi_hba->n_phy; i++) {
1230 struct hisi_sas_phy *phy = &hisi_hba->phy[i];
1231 struct asd_sas_phy *sas_phy = &phy->sas_phy;
1232 u32 prog_phy_link_rate = 0x800;
1233
1234 if (!sas_phy->phy || (sas_phy->phy->maximum_linkrate <
1235 SAS_LINK_RATE_1_5_GBPS)) {
1236 prog_phy_link_rate = 0x855;
1237 } else {
1238 enum sas_linkrate max = sas_phy->phy->maximum_linkrate;
1239
1240 prog_phy_link_rate =
1241 hisi_sas_get_prog_phy_linkrate_mask(max) |
1242 0x800;
1243 }
1244 hisi_sas_phy_write32(hisi_hba, i, PROG_PHY_LINK_RATE,
1245 prog_phy_link_rate);
1246 hisi_sas_phy_write32(hisi_hba, i, SAS_PHY_CTRL, sas_phy_ctrl);
1247 hisi_sas_phy_write32(hisi_hba, i, SL_TOUT_CFG, 0x7d7d7d7d);
1248 hisi_sas_phy_write32(hisi_hba, i, SL_CONTROL, 0x0);
1249 hisi_sas_phy_write32(hisi_hba, i, TXID_AUTO, 0x2);
1250 hisi_sas_phy_write32(hisi_hba, i, DONE_RECEIVED_TIME, 0x8);
1251 hisi_sas_phy_write32(hisi_hba, i, CHL_INT0, 0xffffffff);
1252 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1, 0xffffffff);
1253 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2, 0xfff87fff);
1254 hisi_sas_phy_write32(hisi_hba, i, RXOP_CHECK_CFG_H, 0x1000);
1255 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1_MSK, 0xff857fff);
1256 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0x8ffffbfe);
1257 hisi_sas_phy_write32(hisi_hba, i, SL_CFG, 0x13f801fc);
1258 hisi_sas_phy_write32(hisi_hba, i, PHY_CTRL_RDY_MSK, 0x0);
1259 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_NOT_RDY_MSK, 0x0);
1260 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_DWS_RESET_MSK, 0x0);
1261 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_PHY_ENA_MSK, 0x0);
1262 hisi_sas_phy_write32(hisi_hba, i, SL_RX_BCAST_CHK_MSK, 0x0);
1263 hisi_sas_phy_write32(hisi_hba, i, CHL_INT_COAL_EN, 0x0);
1264 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_OOB_RESTART_MSK, 0x0);
1265 if (hisi_hba->refclk_frequency_mhz == 66)
1266 hisi_sas_phy_write32(hisi_hba, i, PHY_CTRL, 0x199B694);
1267 /* else, do nothing -> leave it how you found it */
1268 }
1269
1270 for (i = 0; i < hisi_hba->queue_count; i++) {
1271 /* Delivery queue */
1272 hisi_sas_write32(hisi_hba,
1273 DLVRY_Q_0_BASE_ADDR_HI + (i * 0x14),
1274 upper_32_bits(hisi_hba->cmd_hdr_dma[i]));
1275
1276 hisi_sas_write32(hisi_hba, DLVRY_Q_0_BASE_ADDR_LO + (i * 0x14),
1277 lower_32_bits(hisi_hba->cmd_hdr_dma[i]));
1278
1279 hisi_sas_write32(hisi_hba, DLVRY_Q_0_DEPTH + (i * 0x14),
1280 HISI_SAS_QUEUE_SLOTS);
1281
1282 /* Completion queue */
1283 hisi_sas_write32(hisi_hba, COMPL_Q_0_BASE_ADDR_HI + (i * 0x14),
1284 upper_32_bits(hisi_hba->complete_hdr_dma[i]));
1285
1286 hisi_sas_write32(hisi_hba, COMPL_Q_0_BASE_ADDR_LO + (i * 0x14),
1287 lower_32_bits(hisi_hba->complete_hdr_dma[i]));
1288
1289 hisi_sas_write32(hisi_hba, COMPL_Q_0_DEPTH + (i * 0x14),
1290 HISI_SAS_QUEUE_SLOTS);
1291 }
1292
1293 /* itct */
1294 hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_LO,
1295 lower_32_bits(hisi_hba->itct_dma));
1296
1297 hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_HI,
1298 upper_32_bits(hisi_hba->itct_dma));
1299
1300 /* iost */
1301 hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_LO,
1302 lower_32_bits(hisi_hba->iost_dma));
1303
1304 hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_HI,
1305 upper_32_bits(hisi_hba->iost_dma));
1306
1307 /* breakpoint */
1308 hisi_sas_write32(hisi_hba, IO_BROKEN_MSG_ADDR_LO,
1309 lower_32_bits(hisi_hba->breakpoint_dma));
1310
1311 hisi_sas_write32(hisi_hba, IO_BROKEN_MSG_ADDR_HI,
1312 upper_32_bits(hisi_hba->breakpoint_dma));
1313
1314 /* SATA broken msg */
1315 hisi_sas_write32(hisi_hba, IO_SATA_BROKEN_MSG_ADDR_LO,
1316 lower_32_bits(hisi_hba->sata_breakpoint_dma));
1317
1318 hisi_sas_write32(hisi_hba, IO_SATA_BROKEN_MSG_ADDR_HI,
1319 upper_32_bits(hisi_hba->sata_breakpoint_dma));
1320
1321 /* SATA initial fis */
1322 hisi_sas_write32(hisi_hba, SATA_INITI_D2H_STORE_ADDR_LO,
1323 lower_32_bits(hisi_hba->initial_fis_dma));
1324
1325 hisi_sas_write32(hisi_hba, SATA_INITI_D2H_STORE_ADDR_HI,
1326 upper_32_bits(hisi_hba->initial_fis_dma));
1327 }
1328
1329 static void link_timeout_enable_link(struct timer_list *t)
1330 {
1331 struct hisi_hba *hisi_hba = from_timer(hisi_hba, t, timer);
1332 int i, reg_val;
1333
1334 for (i = 0; i < hisi_hba->n_phy; i++) {
1335 if (hisi_hba->reject_stp_links_msk & BIT(i))
1336 continue;
1337
1338 reg_val = hisi_sas_phy_read32(hisi_hba, i, CON_CONTROL);
1339 if (!(reg_val & BIT(0))) {
1340 hisi_sas_phy_write32(hisi_hba, i,
1341 CON_CONTROL, 0x7);
1342 break;
1343 }
1344 }
1345
1346 hisi_hba->timer.function = link_timeout_disable_link;
1347 mod_timer(&hisi_hba->timer, jiffies + msecs_to_jiffies(900));
1348 }
1349
1350 static void link_timeout_disable_link(struct timer_list *t)
1351 {
1352 struct hisi_hba *hisi_hba = from_timer(hisi_hba, t, timer);
1353 int i, reg_val;
1354
1355 reg_val = hisi_sas_read32(hisi_hba, PHY_STATE);
1356 for (i = 0; i < hisi_hba->n_phy && reg_val; i++) {
1357 if (hisi_hba->reject_stp_links_msk & BIT(i))
1358 continue;
1359
1360 if (reg_val & BIT(i)) {
1361 hisi_sas_phy_write32(hisi_hba, i,
1362 CON_CONTROL, 0x6);
1363 break;
1364 }
1365 }
1366
1367 hisi_hba->timer.function = link_timeout_enable_link;
1368 mod_timer(&hisi_hba->timer, jiffies + msecs_to_jiffies(100));
1369 }
1370
1371 static void set_link_timer_quirk(struct hisi_hba *hisi_hba)
1372 {
1373 hisi_hba->timer.function = link_timeout_disable_link;
1374 hisi_hba->timer.expires = jiffies + msecs_to_jiffies(1000);
1375 add_timer(&hisi_hba->timer);
1376 }
1377
1378 static int hw_init_v2_hw(struct hisi_hba *hisi_hba)
1379 {
1380 struct device *dev = hisi_hba->dev;
1381 int rc;
1382
1383 rc = reset_hw_v2_hw(hisi_hba);
1384 if (rc) {
1385 dev_err(dev, "hisi_sas_reset_hw failed, rc=%d", rc);
1386 return rc;
1387 }
1388
1389 msleep(100);
1390 init_reg_v2_hw(hisi_hba);
1391
1392 return 0;
1393 }
1394
1395 static void enable_phy_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1396 {
1397 u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
1398
1399 cfg |= PHY_CFG_ENA_MSK;
1400 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
1401 }
1402
1403 static bool is_sata_phy_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1404 {
1405 u32 context;
1406
1407 context = hisi_sas_read32(hisi_hba, PHY_CONTEXT);
1408 if (context & (1 << phy_no))
1409 return true;
1410
1411 return false;
1412 }
1413
1414 static bool tx_fifo_is_empty_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1415 {
1416 u32 dfx_val;
1417
1418 dfx_val = hisi_sas_phy_read32(hisi_hba, phy_no, DMA_TX_DFX1);
1419
1420 if (dfx_val & BIT(16))
1421 return false;
1422
1423 return true;
1424 }
1425
1426 static bool axi_bus_is_idle_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1427 {
1428 int i, max_loop = 1000;
1429 struct device *dev = hisi_hba->dev;
1430 u32 status, axi_status, dfx_val, dfx_tx_val;
1431
1432 for (i = 0; i < max_loop; i++) {
1433 status = hisi_sas_read32_relaxed(hisi_hba,
1434 AXI_MASTER_CFG_BASE + AM_CURR_TRANS_RETURN);
1435
1436 axi_status = hisi_sas_read32(hisi_hba, AXI_CFG);
1437 dfx_val = hisi_sas_phy_read32(hisi_hba, phy_no, DMA_TX_DFX1);
1438 dfx_tx_val = hisi_sas_phy_read32(hisi_hba,
1439 phy_no, DMA_TX_FIFO_DFX0);
1440
1441 if ((status == 0x3) && (axi_status == 0x0) &&
1442 (dfx_val & BIT(20)) && (dfx_tx_val & BIT(10)))
1443 return true;
1444 udelay(10);
1445 }
1446 dev_err(dev, "bus is not idle phy%d, axi150:0x%x axi100:0x%x port204:0x%x port240:0x%x\n",
1447 phy_no, status, axi_status,
1448 dfx_val, dfx_tx_val);
1449 return false;
1450 }
1451
1452 static bool wait_io_done_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1453 {
1454 int i, max_loop = 1000;
1455 struct device *dev = hisi_hba->dev;
1456 u32 status, tx_dfx0;
1457
1458 for (i = 0; i < max_loop; i++) {
1459 status = hisi_sas_phy_read32(hisi_hba, phy_no, LINK_DFX2);
1460 status = (status & 0x3fc0) >> 6;
1461
1462 if (status != 0x1)
1463 return true;
1464
1465 tx_dfx0 = hisi_sas_phy_read32(hisi_hba, phy_no, DMA_TX_DFX0);
1466 if ((tx_dfx0 & 0x1ff) == 0x2)
1467 return true;
1468 udelay(10);
1469 }
1470 dev_err(dev, "IO not done phy%d, port264:0x%x port200:0x%x\n",
1471 phy_no, status, tx_dfx0);
1472 return false;
1473 }
1474
1475 static bool allowed_disable_phy_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1476 {
1477 if (tx_fifo_is_empty_v2_hw(hisi_hba, phy_no))
1478 return true;
1479
1480 if (!axi_bus_is_idle_v2_hw(hisi_hba, phy_no))
1481 return false;
1482
1483 if (!wait_io_done_v2_hw(hisi_hba, phy_no))
1484 return false;
1485
1486 return true;
1487 }
1488
1489
1490 static void disable_phy_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1491 {
1492 u32 cfg, axi_val, dfx0_val, txid_auto;
1493 struct device *dev = hisi_hba->dev;
1494
1495 /* Close axi bus. */
1496 axi_val = hisi_sas_read32(hisi_hba, AXI_MASTER_CFG_BASE +
1497 AM_CTRL_GLOBAL);
1498 axi_val |= 0x1;
1499 hisi_sas_write32(hisi_hba, AXI_MASTER_CFG_BASE +
1500 AM_CTRL_GLOBAL, axi_val);
1501
1502 if (is_sata_phy_v2_hw(hisi_hba, phy_no)) {
1503 if (allowed_disable_phy_v2_hw(hisi_hba, phy_no))
1504 goto do_disable;
1505
1506 /* Reset host controller. */
1507 queue_work(hisi_hba->wq, &hisi_hba->rst_work);
1508 return;
1509 }
1510
1511 dfx0_val = hisi_sas_phy_read32(hisi_hba, phy_no, PORT_DFX0);
1512 dfx0_val = (dfx0_val & 0x1fc0) >> 6;
1513 if (dfx0_val != 0x4)
1514 goto do_disable;
1515
1516 if (!tx_fifo_is_empty_v2_hw(hisi_hba, phy_no)) {
1517 dev_warn(dev, "phy%d, wait tx fifo need send break\n",
1518 phy_no);
1519 txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no,
1520 TXID_AUTO);
1521 txid_auto |= TXID_AUTO_CTB_MSK;
1522 hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO,
1523 txid_auto);
1524 }
1525
1526 do_disable:
1527 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
1528 cfg &= ~PHY_CFG_ENA_MSK;
1529 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
1530
1531 /* Open axi bus. */
1532 axi_val &= ~0x1;
1533 hisi_sas_write32(hisi_hba, AXI_MASTER_CFG_BASE +
1534 AM_CTRL_GLOBAL, axi_val);
1535 }
1536
1537 static void start_phy_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1538 {
1539 config_id_frame_v2_hw(hisi_hba, phy_no);
1540 config_phy_opt_mode_v2_hw(hisi_hba, phy_no);
1541 enable_phy_v2_hw(hisi_hba, phy_no);
1542 }
1543
1544 static void phy_hard_reset_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1545 {
1546 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1547 u32 txid_auto;
1548
1549 disable_phy_v2_hw(hisi_hba, phy_no);
1550 if (phy->identify.device_type == SAS_END_DEVICE) {
1551 txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no, TXID_AUTO);
1552 hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO,
1553 txid_auto | TX_HARDRST_MSK);
1554 }
1555 msleep(100);
1556 start_phy_v2_hw(hisi_hba, phy_no);
1557 }
1558
1559 static void phy_get_events_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1560 {
1561 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1562 struct asd_sas_phy *sas_phy = &phy->sas_phy;
1563 struct sas_phy *sphy = sas_phy->phy;
1564 u32 err4_reg_val, err6_reg_val;
1565
1566 /* loss dword syn, phy reset problem */
1567 err4_reg_val = hisi_sas_phy_read32(hisi_hba, phy_no, SAS_ERR_CNT4_REG);
1568
1569 /* disparity err, invalid dword */
1570 err6_reg_val = hisi_sas_phy_read32(hisi_hba, phy_no, SAS_ERR_CNT6_REG);
1571
1572 sphy->loss_of_dword_sync_count += (err4_reg_val >> 16) & 0xFFFF;
1573 sphy->phy_reset_problem_count += err4_reg_val & 0xFFFF;
1574 sphy->invalid_dword_count += (err6_reg_val & 0xFF0000) >> 16;
1575 sphy->running_disparity_error_count += err6_reg_val & 0xFF;
1576 }
1577
1578 static void phys_init_v2_hw(struct hisi_hba *hisi_hba)
1579 {
1580 int i;
1581
1582 for (i = 0; i < hisi_hba->n_phy; i++) {
1583 struct hisi_sas_phy *phy = &hisi_hba->phy[i];
1584 struct asd_sas_phy *sas_phy = &phy->sas_phy;
1585
1586 if (!sas_phy->phy->enabled)
1587 continue;
1588
1589 start_phy_v2_hw(hisi_hba, i);
1590 }
1591 }
1592
1593 static void sl_notify_ssp_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1594 {
1595 u32 sl_control;
1596
1597 sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
1598 sl_control |= SL_CONTROL_NOTIFY_EN_MSK;
1599 hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control);
1600 msleep(1);
1601 sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
1602 sl_control &= ~SL_CONTROL_NOTIFY_EN_MSK;
1603 hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control);
1604 }
1605
1606 static enum sas_linkrate phy_get_max_linkrate_v2_hw(void)
1607 {
1608 return SAS_LINK_RATE_12_0_GBPS;
1609 }
1610
1611 static void phy_set_linkrate_v2_hw(struct hisi_hba *hisi_hba, int phy_no,
1612 struct sas_phy_linkrates *r)
1613 {
1614 enum sas_linkrate max = r->maximum_linkrate;
1615 u32 prog_phy_link_rate = 0x800;
1616
1617 prog_phy_link_rate |= hisi_sas_get_prog_phy_linkrate_mask(max);
1618 hisi_sas_phy_write32(hisi_hba, phy_no, PROG_PHY_LINK_RATE,
1619 prog_phy_link_rate);
1620 }
1621
1622 static int get_wideport_bitmap_v2_hw(struct hisi_hba *hisi_hba, int port_id)
1623 {
1624 int i, bitmap = 0;
1625 u32 phy_port_num_ma = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA);
1626 u32 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE);
1627
1628 for (i = 0; i < (hisi_hba->n_phy < 9 ? hisi_hba->n_phy : 8); i++)
1629 if (phy_state & 1 << i)
1630 if (((phy_port_num_ma >> (i * 4)) & 0xf) == port_id)
1631 bitmap |= 1 << i;
1632
1633 if (hisi_hba->n_phy == 9) {
1634 u32 port_state = hisi_sas_read32(hisi_hba, PORT_STATE);
1635
1636 if (phy_state & 1 << 8)
1637 if (((port_state & PORT_STATE_PHY8_PORT_NUM_MSK) >>
1638 PORT_STATE_PHY8_PORT_NUM_OFF) == port_id)
1639 bitmap |= 1 << 9;
1640 }
1641
1642 return bitmap;
1643 }
1644
1645 /*
1646 * The callpath to this function and upto writing the write
1647 * queue pointer should be safe from interruption.
1648 */
1649 static int
1650 get_free_slot_v2_hw(struct hisi_hba *hisi_hba, struct hisi_sas_dq *dq)
1651 {
1652 struct device *dev = hisi_hba->dev;
1653 int queue = dq->id;
1654 u32 r, w;
1655
1656 w = dq->wr_point;
1657 r = hisi_sas_read32_relaxed(hisi_hba,
1658 DLVRY_Q_0_RD_PTR + (queue * 0x14));
1659 if (r == (w+1) % HISI_SAS_QUEUE_SLOTS) {
1660 dev_warn(dev, "full queue=%d r=%d w=%d\n",
1661 queue, r, w);
1662 return -EAGAIN;
1663 }
1664
1665 dq->wr_point = (dq->wr_point + 1) % HISI_SAS_QUEUE_SLOTS;
1666
1667 return w;
1668 }
1669
1670 /* DQ lock must be taken here */
1671 static void start_delivery_v2_hw(struct hisi_sas_dq *dq)
1672 {
1673 struct hisi_hba *hisi_hba = dq->hisi_hba;
1674 struct hisi_sas_slot *s, *s1, *s2 = NULL;
1675 int dlvry_queue = dq->id;
1676 int wp;
1677
1678 list_for_each_entry_safe(s, s1, &dq->list, delivery) {
1679 if (!s->ready)
1680 break;
1681 s2 = s;
1682 list_del(&s->delivery);
1683 }
1684
1685 if (!s2)
1686 return;
1687
1688 /*
1689 * Ensure that memories for slots built on other CPUs is observed.
1690 */
1691 smp_rmb();
1692 wp = (s2->dlvry_queue_slot + 1) % HISI_SAS_QUEUE_SLOTS;
1693
1694 hisi_sas_write32(hisi_hba, DLVRY_Q_0_WR_PTR + (dlvry_queue * 0x14), wp);
1695 }
1696
1697 static void prep_prd_sge_v2_hw(struct hisi_hba *hisi_hba,
1698 struct hisi_sas_slot *slot,
1699 struct hisi_sas_cmd_hdr *hdr,
1700 struct scatterlist *scatter,
1701 int n_elem)
1702 {
1703 struct hisi_sas_sge_page *sge_page = hisi_sas_sge_addr_mem(slot);
1704 struct scatterlist *sg;
1705 int i;
1706
1707 for_each_sg(scatter, sg, n_elem, i) {
1708 struct hisi_sas_sge *entry = &sge_page->sge[i];
1709
1710 entry->addr = cpu_to_le64(sg_dma_address(sg));
1711 entry->page_ctrl_0 = entry->page_ctrl_1 = 0;
1712 entry->data_len = cpu_to_le32(sg_dma_len(sg));
1713 entry->data_off = 0;
1714 }
1715
1716 hdr->prd_table_addr = cpu_to_le64(hisi_sas_sge_addr_dma(slot));
1717
1718 hdr->sg_len = cpu_to_le32(n_elem << CMD_HDR_DATA_SGL_LEN_OFF);
1719 }
1720
1721 static void prep_smp_v2_hw(struct hisi_hba *hisi_hba,
1722 struct hisi_sas_slot *slot)
1723 {
1724 struct sas_task *task = slot->task;
1725 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
1726 struct domain_device *device = task->dev;
1727 struct hisi_sas_port *port = slot->port;
1728 struct scatterlist *sg_req;
1729 struct hisi_sas_device *sas_dev = device->lldd_dev;
1730 dma_addr_t req_dma_addr;
1731 unsigned int req_len;
1732
1733 /* req */
1734 sg_req = &task->smp_task.smp_req;
1735 req_dma_addr = sg_dma_address(sg_req);
1736 req_len = sg_dma_len(&task->smp_task.smp_req);
1737
1738 /* create header */
1739 /* dw0 */
1740 hdr->dw0 = cpu_to_le32((port->id << CMD_HDR_PORT_OFF) |
1741 (1 << CMD_HDR_PRIORITY_OFF) | /* high pri */
1742 (2 << CMD_HDR_CMD_OFF)); /* smp */
1743
1744 /* map itct entry */
1745 hdr->dw1 = cpu_to_le32((sas_dev->device_id << CMD_HDR_DEV_ID_OFF) |
1746 (1 << CMD_HDR_FRAME_TYPE_OFF) |
1747 (DIR_NO_DATA << CMD_HDR_DIR_OFF));
1748
1749 /* dw2 */
1750 hdr->dw2 = cpu_to_le32((((req_len - 4) / 4) << CMD_HDR_CFL_OFF) |
1751 (HISI_SAS_MAX_SMP_RESP_SZ / 4 <<
1752 CMD_HDR_MRFL_OFF));
1753
1754 hdr->transfer_tags = cpu_to_le32(slot->idx << CMD_HDR_IPTT_OFF);
1755
1756 hdr->cmd_table_addr = cpu_to_le64(req_dma_addr);
1757 hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot));
1758 }
1759
1760 static void prep_ssp_v2_hw(struct hisi_hba *hisi_hba,
1761 struct hisi_sas_slot *slot)
1762 {
1763 struct sas_task *task = slot->task;
1764 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
1765 struct domain_device *device = task->dev;
1766 struct hisi_sas_device *sas_dev = device->lldd_dev;
1767 struct hisi_sas_port *port = slot->port;
1768 struct sas_ssp_task *ssp_task = &task->ssp_task;
1769 struct scsi_cmnd *scsi_cmnd = ssp_task->cmd;
1770 struct hisi_sas_tmf_task *tmf = slot->tmf;
1771 int has_data = 0, priority = !!tmf;
1772 u8 *buf_cmd;
1773 u32 dw1 = 0, dw2 = 0;
1774
1775 hdr->dw0 = cpu_to_le32((1 << CMD_HDR_RESP_REPORT_OFF) |
1776 (2 << CMD_HDR_TLR_CTRL_OFF) |
1777 (port->id << CMD_HDR_PORT_OFF) |
1778 (priority << CMD_HDR_PRIORITY_OFF) |
1779 (1 << CMD_HDR_CMD_OFF)); /* ssp */
1780
1781 dw1 = 1 << CMD_HDR_VDTL_OFF;
1782 if (tmf) {
1783 dw1 |= 2 << CMD_HDR_FRAME_TYPE_OFF;
1784 dw1 |= DIR_NO_DATA << CMD_HDR_DIR_OFF;
1785 } else {
1786 dw1 |= 1 << CMD_HDR_FRAME_TYPE_OFF;
1787 switch (scsi_cmnd->sc_data_direction) {
1788 case DMA_TO_DEVICE:
1789 has_data = 1;
1790 dw1 |= DIR_TO_DEVICE << CMD_HDR_DIR_OFF;
1791 break;
1792 case DMA_FROM_DEVICE:
1793 has_data = 1;
1794 dw1 |= DIR_TO_INI << CMD_HDR_DIR_OFF;
1795 break;
1796 default:
1797 dw1 &= ~CMD_HDR_DIR_MSK;
1798 }
1799 }
1800
1801 /* map itct entry */
1802 dw1 |= sas_dev->device_id << CMD_HDR_DEV_ID_OFF;
1803 hdr->dw1 = cpu_to_le32(dw1);
1804
1805 dw2 = (((sizeof(struct ssp_command_iu) + sizeof(struct ssp_frame_hdr)
1806 + 3) / 4) << CMD_HDR_CFL_OFF) |
1807 ((HISI_SAS_MAX_SSP_RESP_SZ / 4) << CMD_HDR_MRFL_OFF) |
1808 (2 << CMD_HDR_SG_MOD_OFF);
1809 hdr->dw2 = cpu_to_le32(dw2);
1810
1811 hdr->transfer_tags = cpu_to_le32(slot->idx);
1812
1813 if (has_data)
1814 prep_prd_sge_v2_hw(hisi_hba, slot, hdr, task->scatter,
1815 slot->n_elem);
1816
1817 hdr->data_transfer_len = cpu_to_le32(task->total_xfer_len);
1818 hdr->cmd_table_addr = cpu_to_le64(hisi_sas_cmd_hdr_addr_dma(slot));
1819 hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot));
1820
1821 buf_cmd = hisi_sas_cmd_hdr_addr_mem(slot) +
1822 sizeof(struct ssp_frame_hdr);
1823
1824 memcpy(buf_cmd, &task->ssp_task.LUN, 8);
1825 if (!tmf) {
1826 buf_cmd[9] = task->ssp_task.task_attr |
1827 (task->ssp_task.task_prio << 3);
1828 memcpy(buf_cmd + 12, task->ssp_task.cmd->cmnd,
1829 task->ssp_task.cmd->cmd_len);
1830 } else {
1831 buf_cmd[10] = tmf->tmf;
1832 switch (tmf->tmf) {
1833 case TMF_ABORT_TASK:
1834 case TMF_QUERY_TASK:
1835 buf_cmd[12] =
1836 (tmf->tag_of_task_to_be_managed >> 8) & 0xff;
1837 buf_cmd[13] =
1838 tmf->tag_of_task_to_be_managed & 0xff;
1839 break;
1840 default:
1841 break;
1842 }
1843 }
1844 }
1845
1846 #define TRANS_TX_ERR 0
1847 #define TRANS_RX_ERR 1
1848 #define DMA_TX_ERR 2
1849 #define SIPC_RX_ERR 3
1850 #define DMA_RX_ERR 4
1851
1852 #define DMA_TX_ERR_OFF 0
1853 #define DMA_TX_ERR_MSK (0xffff << DMA_TX_ERR_OFF)
1854 #define SIPC_RX_ERR_OFF 16
1855 #define SIPC_RX_ERR_MSK (0xffff << SIPC_RX_ERR_OFF)
1856
1857 static int parse_trans_tx_err_code_v2_hw(u32 err_msk)
1858 {
1859 static const u8 trans_tx_err_code_prio[] = {
1860 TRANS_TX_OPEN_FAIL_WITH_IT_NEXUS_LOSS,
1861 TRANS_TX_ERR_PHY_NOT_ENABLE,
1862 TRANS_TX_OPEN_CNX_ERR_WRONG_DESTINATION,
1863 TRANS_TX_OPEN_CNX_ERR_ZONE_VIOLATION,
1864 TRANS_TX_OPEN_CNX_ERR_BY_OTHER,
1865 RESERVED0,
1866 TRANS_TX_OPEN_CNX_ERR_AIP_TIMEOUT,
1867 TRANS_TX_OPEN_CNX_ERR_STP_RESOURCES_BUSY,
1868 TRANS_TX_OPEN_CNX_ERR_PROTOCOL_NOT_SUPPORTED,
1869 TRANS_TX_OPEN_CNX_ERR_CONNECTION_RATE_NOT_SUPPORTED,
1870 TRANS_TX_OPEN_CNX_ERR_BAD_DESTINATION,
1871 TRANS_TX_OPEN_CNX_ERR_BREAK_RCVD,
1872 TRANS_TX_OPEN_CNX_ERR_LOW_PHY_POWER,
1873 TRANS_TX_OPEN_CNX_ERR_PATHWAY_BLOCKED,
1874 TRANS_TX_OPEN_CNX_ERR_OPEN_TIMEOUT,
1875 TRANS_TX_OPEN_CNX_ERR_NO_DESTINATION,
1876 TRANS_TX_OPEN_RETRY_ERR_THRESHOLD_REACHED,
1877 TRANS_TX_ERR_WITH_CLOSE_PHYDISALE,
1878 TRANS_TX_ERR_WITH_CLOSE_DWS_TIMEOUT,
1879 TRANS_TX_ERR_WITH_CLOSE_COMINIT,
1880 TRANS_TX_ERR_WITH_BREAK_TIMEOUT,
1881 TRANS_TX_ERR_WITH_BREAK_REQUEST,
1882 TRANS_TX_ERR_WITH_BREAK_RECEVIED,
1883 TRANS_TX_ERR_WITH_CLOSE_TIMEOUT,
1884 TRANS_TX_ERR_WITH_CLOSE_NORMAL,
1885 TRANS_TX_ERR_WITH_NAK_RECEVIED,
1886 TRANS_TX_ERR_WITH_ACK_NAK_TIMEOUT,
1887 TRANS_TX_ERR_WITH_CREDIT_TIMEOUT,
1888 TRANS_TX_ERR_WITH_IPTT_CONFLICT,
1889 TRANS_TX_ERR_WITH_OPEN_BY_DES_OR_OTHERS,
1890 TRANS_TX_ERR_WITH_WAIT_RECV_TIMEOUT,
1891 };
1892 int index, i;
1893
1894 for (i = 0; i < ARRAY_SIZE(trans_tx_err_code_prio); i++) {
1895 index = trans_tx_err_code_prio[i] - TRANS_TX_FAIL_BASE;
1896 if (err_msk & (1 << index))
1897 return trans_tx_err_code_prio[i];
1898 }
1899 return -1;
1900 }
1901
1902 static int parse_trans_rx_err_code_v2_hw(u32 err_msk)
1903 {
1904 static const u8 trans_rx_err_code_prio[] = {
1905 TRANS_RX_ERR_WITH_RXFRAME_CRC_ERR,
1906 TRANS_RX_ERR_WITH_RXFIS_8B10B_DISP_ERR,
1907 TRANS_RX_ERR_WITH_RXFRAME_HAVE_ERRPRM,
1908 TRANS_RX_ERR_WITH_RXFIS_DECODE_ERROR,
1909 TRANS_RX_ERR_WITH_RXFIS_CRC_ERR,
1910 TRANS_RX_ERR_WITH_RXFRAME_LENGTH_OVERRUN,
1911 TRANS_RX_ERR_WITH_RXFIS_RX_SYNCP,
1912 TRANS_RX_ERR_WITH_LINK_BUF_OVERRUN,
1913 TRANS_RX_ERR_WITH_CLOSE_PHY_DISABLE,
1914 TRANS_RX_ERR_WITH_CLOSE_DWS_TIMEOUT,
1915 TRANS_RX_ERR_WITH_CLOSE_COMINIT,
1916 TRANS_RX_ERR_WITH_BREAK_TIMEOUT,
1917 TRANS_RX_ERR_WITH_BREAK_REQUEST,
1918 TRANS_RX_ERR_WITH_BREAK_RECEVIED,
1919 RESERVED1,
1920 TRANS_RX_ERR_WITH_CLOSE_NORMAL,
1921 TRANS_RX_ERR_WITH_DATA_LEN0,
1922 TRANS_RX_ERR_WITH_BAD_HASH,
1923 TRANS_RX_XRDY_WLEN_ZERO_ERR,
1924 TRANS_RX_SSP_FRM_LEN_ERR,
1925 RESERVED2,
1926 RESERVED3,
1927 RESERVED4,
1928 RESERVED5,
1929 TRANS_RX_ERR_WITH_BAD_FRM_TYPE,
1930 TRANS_RX_SMP_FRM_LEN_ERR,
1931 TRANS_RX_SMP_RESP_TIMEOUT_ERR,
1932 RESERVED6,
1933 RESERVED7,
1934 RESERVED8,
1935 RESERVED9,
1936 TRANS_RX_R_ERR,
1937 };
1938 int index, i;
1939
1940 for (i = 0; i < ARRAY_SIZE(trans_rx_err_code_prio); i++) {
1941 index = trans_rx_err_code_prio[i] - TRANS_RX_FAIL_BASE;
1942 if (err_msk & (1 << index))
1943 return trans_rx_err_code_prio[i];
1944 }
1945 return -1;
1946 }
1947
1948 static int parse_dma_tx_err_code_v2_hw(u32 err_msk)
1949 {
1950 static const u8 dma_tx_err_code_prio[] = {
1951 DMA_TX_UNEXP_XFER_ERR,
1952 DMA_TX_UNEXP_RETRANS_ERR,
1953 DMA_TX_XFER_LEN_OVERFLOW,
1954 DMA_TX_XFER_OFFSET_ERR,
1955 DMA_TX_RAM_ECC_ERR,
1956 DMA_TX_DIF_LEN_ALIGN_ERR,
1957 DMA_TX_DIF_CRC_ERR,
1958 DMA_TX_DIF_APP_ERR,
1959 DMA_TX_DIF_RPP_ERR,
1960 DMA_TX_DATA_SGL_OVERFLOW,
1961 DMA_TX_DIF_SGL_OVERFLOW,
1962 };
1963 int index, i;
1964
1965 for (i = 0; i < ARRAY_SIZE(dma_tx_err_code_prio); i++) {
1966 index = dma_tx_err_code_prio[i] - DMA_TX_ERR_BASE;
1967 err_msk = err_msk & DMA_TX_ERR_MSK;
1968 if (err_msk & (1 << index))
1969 return dma_tx_err_code_prio[i];
1970 }
1971 return -1;
1972 }
1973
1974 static int parse_sipc_rx_err_code_v2_hw(u32 err_msk)
1975 {
1976 static const u8 sipc_rx_err_code_prio[] = {
1977 SIPC_RX_FIS_STATUS_ERR_BIT_VLD,
1978 SIPC_RX_PIO_WRSETUP_STATUS_DRQ_ERR,
1979 SIPC_RX_FIS_STATUS_BSY_BIT_ERR,
1980 SIPC_RX_WRSETUP_LEN_ODD_ERR,
1981 SIPC_RX_WRSETUP_LEN_ZERO_ERR,
1982 SIPC_RX_WRDATA_LEN_NOT_MATCH_ERR,
1983 SIPC_RX_NCQ_WRSETUP_OFFSET_ERR,
1984 SIPC_RX_NCQ_WRSETUP_AUTO_ACTIVE_ERR,
1985 SIPC_RX_SATA_UNEXP_FIS_ERR,
1986 SIPC_RX_WRSETUP_ESTATUS_ERR,
1987 SIPC_RX_DATA_UNDERFLOW_ERR,
1988 };
1989 int index, i;
1990
1991 for (i = 0; i < ARRAY_SIZE(sipc_rx_err_code_prio); i++) {
1992 index = sipc_rx_err_code_prio[i] - SIPC_RX_ERR_BASE;
1993 err_msk = err_msk & SIPC_RX_ERR_MSK;
1994 if (err_msk & (1 << (index + 0x10)))
1995 return sipc_rx_err_code_prio[i];
1996 }
1997 return -1;
1998 }
1999
2000 static int parse_dma_rx_err_code_v2_hw(u32 err_msk)
2001 {
2002 static const u8 dma_rx_err_code_prio[] = {
2003 DMA_RX_UNKNOWN_FRM_ERR,
2004 DMA_RX_DATA_LEN_OVERFLOW,
2005 DMA_RX_DATA_LEN_UNDERFLOW,
2006 DMA_RX_DATA_OFFSET_ERR,
2007 RESERVED10,
2008 DMA_RX_SATA_FRAME_TYPE_ERR,
2009 DMA_RX_RESP_BUF_OVERFLOW,
2010 DMA_RX_UNEXP_RETRANS_RESP_ERR,
2011 DMA_RX_UNEXP_NORM_RESP_ERR,
2012 DMA_RX_UNEXP_RDFRAME_ERR,
2013 DMA_RX_PIO_DATA_LEN_ERR,
2014 DMA_RX_RDSETUP_STATUS_ERR,
2015 DMA_RX_RDSETUP_STATUS_DRQ_ERR,
2016 DMA_RX_RDSETUP_STATUS_BSY_ERR,
2017 DMA_RX_RDSETUP_LEN_ODD_ERR,
2018 DMA_RX_RDSETUP_LEN_ZERO_ERR,
2019 DMA_RX_RDSETUP_LEN_OVER_ERR,
2020 DMA_RX_RDSETUP_OFFSET_ERR,
2021 DMA_RX_RDSETUP_ACTIVE_ERR,
2022 DMA_RX_RDSETUP_ESTATUS_ERR,
2023 DMA_RX_RAM_ECC_ERR,
2024 DMA_RX_DIF_CRC_ERR,
2025 DMA_RX_DIF_APP_ERR,
2026 DMA_RX_DIF_RPP_ERR,
2027 DMA_RX_DATA_SGL_OVERFLOW,
2028 DMA_RX_DIF_SGL_OVERFLOW,
2029 };
2030 int index, i;
2031
2032 for (i = 0; i < ARRAY_SIZE(dma_rx_err_code_prio); i++) {
2033 index = dma_rx_err_code_prio[i] - DMA_RX_ERR_BASE;
2034 if (err_msk & (1 << index))
2035 return dma_rx_err_code_prio[i];
2036 }
2037 return -1;
2038 }
2039
2040 /* by default, task resp is complete */
2041 static void slot_err_v2_hw(struct hisi_hba *hisi_hba,
2042 struct sas_task *task,
2043 struct hisi_sas_slot *slot,
2044 int err_phase)
2045 {
2046 struct task_status_struct *ts = &task->task_status;
2047 struct hisi_sas_err_record_v2 *err_record =
2048 hisi_sas_status_buf_addr_mem(slot);
2049 u32 trans_tx_fail_type = le32_to_cpu(err_record->trans_tx_fail_type);
2050 u32 trans_rx_fail_type = le32_to_cpu(err_record->trans_rx_fail_type);
2051 u16 dma_tx_err_type = le16_to_cpu(err_record->dma_tx_err_type);
2052 u16 sipc_rx_err_type = le16_to_cpu(err_record->sipc_rx_err_type);
2053 u32 dma_rx_err_type = le32_to_cpu(err_record->dma_rx_err_type);
2054 int error = -1;
2055
2056 if (err_phase == 1) {
2057 /* error in TX phase, the priority of error is: DW2 > DW0 */
2058 error = parse_dma_tx_err_code_v2_hw(dma_tx_err_type);
2059 if (error == -1)
2060 error = parse_trans_tx_err_code_v2_hw(
2061 trans_tx_fail_type);
2062 } else if (err_phase == 2) {
2063 /* error in RX phase, the priority is: DW1 > DW3 > DW2 */
2064 error = parse_trans_rx_err_code_v2_hw(trans_rx_fail_type);
2065 if (error == -1) {
2066 error = parse_dma_rx_err_code_v2_hw(
2067 dma_rx_err_type);
2068 if (error == -1)
2069 error = parse_sipc_rx_err_code_v2_hw(
2070 sipc_rx_err_type);
2071 }
2072 }
2073
2074 switch (task->task_proto) {
2075 case SAS_PROTOCOL_SSP:
2076 {
2077 switch (error) {
2078 case TRANS_TX_OPEN_CNX_ERR_NO_DESTINATION:
2079 {
2080 ts->stat = SAS_OPEN_REJECT;
2081 ts->open_rej_reason = SAS_OREJ_NO_DEST;
2082 break;
2083 }
2084 case TRANS_TX_OPEN_CNX_ERR_PROTOCOL_NOT_SUPPORTED:
2085 {
2086 ts->stat = SAS_OPEN_REJECT;
2087 ts->open_rej_reason = SAS_OREJ_EPROTO;
2088 break;
2089 }
2090 case TRANS_TX_OPEN_CNX_ERR_CONNECTION_RATE_NOT_SUPPORTED:
2091 {
2092 ts->stat = SAS_OPEN_REJECT;
2093 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2094 break;
2095 }
2096 case TRANS_TX_OPEN_CNX_ERR_BAD_DESTINATION:
2097 {
2098 ts->stat = SAS_OPEN_REJECT;
2099 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2100 break;
2101 }
2102 case TRANS_TX_OPEN_CNX_ERR_WRONG_DESTINATION:
2103 {
2104 ts->stat = SAS_OPEN_REJECT;
2105 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2106 break;
2107 }
2108 case DMA_RX_UNEXP_NORM_RESP_ERR:
2109 case TRANS_TX_OPEN_CNX_ERR_ZONE_VIOLATION:
2110 case DMA_RX_RESP_BUF_OVERFLOW:
2111 {
2112 ts->stat = SAS_OPEN_REJECT;
2113 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2114 break;
2115 }
2116 case TRANS_TX_OPEN_CNX_ERR_LOW_PHY_POWER:
2117 {
2118 /* not sure */
2119 ts->stat = SAS_DEV_NO_RESPONSE;
2120 break;
2121 }
2122 case DMA_RX_DATA_LEN_OVERFLOW:
2123 {
2124 ts->stat = SAS_DATA_OVERRUN;
2125 ts->residual = 0;
2126 break;
2127 }
2128 case DMA_RX_DATA_LEN_UNDERFLOW:
2129 {
2130 ts->residual = trans_tx_fail_type;
2131 ts->stat = SAS_DATA_UNDERRUN;
2132 break;
2133 }
2134 case TRANS_TX_OPEN_FAIL_WITH_IT_NEXUS_LOSS:
2135 case TRANS_TX_ERR_PHY_NOT_ENABLE:
2136 case TRANS_TX_OPEN_CNX_ERR_BY_OTHER:
2137 case TRANS_TX_OPEN_CNX_ERR_AIP_TIMEOUT:
2138 case TRANS_TX_OPEN_CNX_ERR_BREAK_RCVD:
2139 case TRANS_TX_OPEN_CNX_ERR_PATHWAY_BLOCKED:
2140 case TRANS_TX_OPEN_CNX_ERR_OPEN_TIMEOUT:
2141 case TRANS_TX_OPEN_RETRY_ERR_THRESHOLD_REACHED:
2142 case TRANS_TX_ERR_WITH_BREAK_TIMEOUT:
2143 case TRANS_TX_ERR_WITH_BREAK_REQUEST:
2144 case TRANS_TX_ERR_WITH_BREAK_RECEVIED:
2145 case TRANS_TX_ERR_WITH_CLOSE_TIMEOUT:
2146 case TRANS_TX_ERR_WITH_CLOSE_NORMAL:
2147 case TRANS_TX_ERR_WITH_CLOSE_PHYDISALE:
2148 case TRANS_TX_ERR_WITH_CLOSE_DWS_TIMEOUT:
2149 case TRANS_TX_ERR_WITH_CLOSE_COMINIT:
2150 case TRANS_TX_ERR_WITH_NAK_RECEVIED:
2151 case TRANS_TX_ERR_WITH_ACK_NAK_TIMEOUT:
2152 case TRANS_TX_ERR_WITH_CREDIT_TIMEOUT:
2153 case TRANS_TX_ERR_WITH_IPTT_CONFLICT:
2154 case TRANS_RX_ERR_WITH_RXFRAME_CRC_ERR:
2155 case TRANS_RX_ERR_WITH_RXFIS_8B10B_DISP_ERR:
2156 case TRANS_RX_ERR_WITH_RXFRAME_HAVE_ERRPRM:
2157 case TRANS_RX_ERR_WITH_LINK_BUF_OVERRUN:
2158 case TRANS_RX_ERR_WITH_BREAK_TIMEOUT:
2159 case TRANS_RX_ERR_WITH_BREAK_REQUEST:
2160 case TRANS_RX_ERR_WITH_BREAK_RECEVIED:
2161 case TRANS_RX_ERR_WITH_CLOSE_NORMAL:
2162 case TRANS_RX_ERR_WITH_CLOSE_DWS_TIMEOUT:
2163 case TRANS_RX_ERR_WITH_CLOSE_COMINIT:
2164 case TRANS_TX_ERR_FRAME_TXED:
2165 case TRANS_RX_ERR_WITH_CLOSE_PHY_DISABLE:
2166 case TRANS_RX_ERR_WITH_DATA_LEN0:
2167 case TRANS_RX_ERR_WITH_BAD_HASH:
2168 case TRANS_RX_XRDY_WLEN_ZERO_ERR:
2169 case TRANS_RX_SSP_FRM_LEN_ERR:
2170 case TRANS_RX_ERR_WITH_BAD_FRM_TYPE:
2171 case DMA_TX_DATA_SGL_OVERFLOW:
2172 case DMA_TX_UNEXP_XFER_ERR:
2173 case DMA_TX_UNEXP_RETRANS_ERR:
2174 case DMA_TX_XFER_LEN_OVERFLOW:
2175 case DMA_TX_XFER_OFFSET_ERR:
2176 case SIPC_RX_DATA_UNDERFLOW_ERR:
2177 case DMA_RX_DATA_SGL_OVERFLOW:
2178 case DMA_RX_DATA_OFFSET_ERR:
2179 case DMA_RX_RDSETUP_LEN_ODD_ERR:
2180 case DMA_RX_RDSETUP_LEN_ZERO_ERR:
2181 case DMA_RX_RDSETUP_LEN_OVER_ERR:
2182 case DMA_RX_SATA_FRAME_TYPE_ERR:
2183 case DMA_RX_UNKNOWN_FRM_ERR:
2184 {
2185 /* This will request a retry */
2186 ts->stat = SAS_QUEUE_FULL;
2187 slot->abort = 1;
2188 break;
2189 }
2190 default:
2191 break;
2192 }
2193 }
2194 break;
2195 case SAS_PROTOCOL_SMP:
2196 ts->stat = SAM_STAT_CHECK_CONDITION;
2197 break;
2198
2199 case SAS_PROTOCOL_SATA:
2200 case SAS_PROTOCOL_STP:
2201 case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP:
2202 {
2203 switch (error) {
2204 case TRANS_TX_OPEN_CNX_ERR_NO_DESTINATION:
2205 {
2206 ts->stat = SAS_OPEN_REJECT;
2207 ts->open_rej_reason = SAS_OREJ_NO_DEST;
2208 break;
2209 }
2210 case TRANS_TX_OPEN_CNX_ERR_LOW_PHY_POWER:
2211 {
2212 ts->resp = SAS_TASK_UNDELIVERED;
2213 ts->stat = SAS_DEV_NO_RESPONSE;
2214 break;
2215 }
2216 case TRANS_TX_OPEN_CNX_ERR_PROTOCOL_NOT_SUPPORTED:
2217 {
2218 ts->stat = SAS_OPEN_REJECT;
2219 ts->open_rej_reason = SAS_OREJ_EPROTO;
2220 break;
2221 }
2222 case TRANS_TX_OPEN_CNX_ERR_CONNECTION_RATE_NOT_SUPPORTED:
2223 {
2224 ts->stat = SAS_OPEN_REJECT;
2225 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2226 break;
2227 }
2228 case TRANS_TX_OPEN_CNX_ERR_BAD_DESTINATION:
2229 {
2230 ts->stat = SAS_OPEN_REJECT;
2231 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2232 break;
2233 }
2234 case TRANS_TX_OPEN_CNX_ERR_WRONG_DESTINATION:
2235 {
2236 ts->stat = SAS_OPEN_REJECT;
2237 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2238 break;
2239 }
2240 case DMA_RX_RESP_BUF_OVERFLOW:
2241 case DMA_RX_UNEXP_NORM_RESP_ERR:
2242 case TRANS_TX_OPEN_CNX_ERR_ZONE_VIOLATION:
2243 {
2244 ts->stat = SAS_OPEN_REJECT;
2245 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2246 break;
2247 }
2248 case DMA_RX_DATA_LEN_OVERFLOW:
2249 {
2250 ts->stat = SAS_DATA_OVERRUN;
2251 ts->residual = 0;
2252 break;
2253 }
2254 case DMA_RX_DATA_LEN_UNDERFLOW:
2255 {
2256 ts->residual = trans_tx_fail_type;
2257 ts->stat = SAS_DATA_UNDERRUN;
2258 break;
2259 }
2260 case TRANS_TX_OPEN_FAIL_WITH_IT_NEXUS_LOSS:
2261 case TRANS_TX_ERR_PHY_NOT_ENABLE:
2262 case TRANS_TX_OPEN_CNX_ERR_BY_OTHER:
2263 case TRANS_TX_OPEN_CNX_ERR_AIP_TIMEOUT:
2264 case TRANS_TX_OPEN_CNX_ERR_BREAK_RCVD:
2265 case TRANS_TX_OPEN_CNX_ERR_PATHWAY_BLOCKED:
2266 case TRANS_TX_OPEN_CNX_ERR_OPEN_TIMEOUT:
2267 case TRANS_TX_OPEN_RETRY_ERR_THRESHOLD_REACHED:
2268 case TRANS_TX_ERR_WITH_BREAK_TIMEOUT:
2269 case TRANS_TX_ERR_WITH_BREAK_REQUEST:
2270 case TRANS_TX_ERR_WITH_BREAK_RECEVIED:
2271 case TRANS_TX_ERR_WITH_CLOSE_TIMEOUT:
2272 case TRANS_TX_ERR_WITH_CLOSE_NORMAL:
2273 case TRANS_TX_ERR_WITH_CLOSE_PHYDISALE:
2274 case TRANS_TX_ERR_WITH_CLOSE_DWS_TIMEOUT:
2275 case TRANS_TX_ERR_WITH_CLOSE_COMINIT:
2276 case TRANS_TX_ERR_WITH_ACK_NAK_TIMEOUT:
2277 case TRANS_TX_ERR_WITH_CREDIT_TIMEOUT:
2278 case TRANS_TX_ERR_WITH_OPEN_BY_DES_OR_OTHERS:
2279 case TRANS_TX_ERR_WITH_WAIT_RECV_TIMEOUT:
2280 case TRANS_RX_ERR_WITH_RXFRAME_HAVE_ERRPRM:
2281 case TRANS_RX_ERR_WITH_RXFIS_8B10B_DISP_ERR:
2282 case TRANS_RX_ERR_WITH_RXFIS_DECODE_ERROR:
2283 case TRANS_RX_ERR_WITH_RXFIS_CRC_ERR:
2284 case TRANS_RX_ERR_WITH_RXFRAME_LENGTH_OVERRUN:
2285 case TRANS_RX_ERR_WITH_RXFIS_RX_SYNCP:
2286 case TRANS_RX_ERR_WITH_LINK_BUF_OVERRUN:
2287 case TRANS_RX_ERR_WITH_BREAK_TIMEOUT:
2288 case TRANS_RX_ERR_WITH_BREAK_REQUEST:
2289 case TRANS_RX_ERR_WITH_BREAK_RECEVIED:
2290 case TRANS_RX_ERR_WITH_CLOSE_NORMAL:
2291 case TRANS_RX_ERR_WITH_CLOSE_PHY_DISABLE:
2292 case TRANS_RX_ERR_WITH_CLOSE_DWS_TIMEOUT:
2293 case TRANS_RX_ERR_WITH_CLOSE_COMINIT:
2294 case TRANS_RX_ERR_WITH_DATA_LEN0:
2295 case TRANS_RX_ERR_WITH_BAD_HASH:
2296 case TRANS_RX_XRDY_WLEN_ZERO_ERR:
2297 case TRANS_RX_ERR_WITH_BAD_FRM_TYPE:
2298 case DMA_TX_DATA_SGL_OVERFLOW:
2299 case DMA_TX_UNEXP_XFER_ERR:
2300 case DMA_TX_UNEXP_RETRANS_ERR:
2301 case DMA_TX_XFER_LEN_OVERFLOW:
2302 case DMA_TX_XFER_OFFSET_ERR:
2303 case SIPC_RX_FIS_STATUS_ERR_BIT_VLD:
2304 case SIPC_RX_PIO_WRSETUP_STATUS_DRQ_ERR:
2305 case SIPC_RX_FIS_STATUS_BSY_BIT_ERR:
2306 case SIPC_RX_WRSETUP_LEN_ODD_ERR:
2307 case SIPC_RX_WRSETUP_LEN_ZERO_ERR:
2308 case SIPC_RX_WRDATA_LEN_NOT_MATCH_ERR:
2309 case SIPC_RX_SATA_UNEXP_FIS_ERR:
2310 case DMA_RX_DATA_SGL_OVERFLOW:
2311 case DMA_RX_DATA_OFFSET_ERR:
2312 case DMA_RX_SATA_FRAME_TYPE_ERR:
2313 case DMA_RX_UNEXP_RDFRAME_ERR:
2314 case DMA_RX_PIO_DATA_LEN_ERR:
2315 case DMA_RX_RDSETUP_STATUS_ERR:
2316 case DMA_RX_RDSETUP_STATUS_DRQ_ERR:
2317 case DMA_RX_RDSETUP_STATUS_BSY_ERR:
2318 case DMA_RX_RDSETUP_LEN_ODD_ERR:
2319 case DMA_RX_RDSETUP_LEN_ZERO_ERR:
2320 case DMA_RX_RDSETUP_LEN_OVER_ERR:
2321 case DMA_RX_RDSETUP_OFFSET_ERR:
2322 case DMA_RX_RDSETUP_ACTIVE_ERR:
2323 case DMA_RX_RDSETUP_ESTATUS_ERR:
2324 case DMA_RX_UNKNOWN_FRM_ERR:
2325 case TRANS_RX_SSP_FRM_LEN_ERR:
2326 case TRANS_TX_OPEN_CNX_ERR_STP_RESOURCES_BUSY:
2327 {
2328 slot->abort = 1;
2329 ts->stat = SAS_PHY_DOWN;
2330 break;
2331 }
2332 default:
2333 {
2334 ts->stat = SAS_PROTO_RESPONSE;
2335 break;
2336 }
2337 }
2338 hisi_sas_sata_done(task, slot);
2339 }
2340 break;
2341 default:
2342 break;
2343 }
2344 }
2345
2346 static int
2347 slot_complete_v2_hw(struct hisi_hba *hisi_hba, struct hisi_sas_slot *slot)
2348 {
2349 struct sas_task *task = slot->task;
2350 struct hisi_sas_device *sas_dev;
2351 struct device *dev = hisi_hba->dev;
2352 struct task_status_struct *ts;
2353 struct domain_device *device;
2354 struct sas_ha_struct *ha;
2355 enum exec_status sts;
2356 struct hisi_sas_complete_v2_hdr *complete_queue =
2357 hisi_hba->complete_hdr[slot->cmplt_queue];
2358 struct hisi_sas_complete_v2_hdr *complete_hdr =
2359 &complete_queue[slot->cmplt_queue_slot];
2360 unsigned long flags;
2361 bool is_internal = slot->is_internal;
2362 u32 dw0;
2363
2364 if (unlikely(!task || !task->lldd_task || !task->dev))
2365 return -EINVAL;
2366
2367 ts = &task->task_status;
2368 device = task->dev;
2369 ha = device->port->ha;
2370 sas_dev = device->lldd_dev;
2371
2372 spin_lock_irqsave(&task->task_state_lock, flags);
2373 task->task_state_flags &=
2374 ~(SAS_TASK_STATE_PENDING | SAS_TASK_AT_INITIATOR);
2375 spin_unlock_irqrestore(&task->task_state_lock, flags);
2376
2377 memset(ts, 0, sizeof(*ts));
2378 ts->resp = SAS_TASK_COMPLETE;
2379
2380 if (unlikely(!sas_dev)) {
2381 dev_dbg(dev, "slot complete: port has no device\n");
2382 ts->stat = SAS_PHY_DOWN;
2383 goto out;
2384 }
2385
2386 /* Use SAS+TMF status codes */
2387 dw0 = le32_to_cpu(complete_hdr->dw0);
2388 switch ((dw0 & CMPLT_HDR_ABORT_STAT_MSK) >>
2389 CMPLT_HDR_ABORT_STAT_OFF) {
2390 case STAT_IO_ABORTED:
2391 /* this io has been aborted by abort command */
2392 ts->stat = SAS_ABORTED_TASK;
2393 goto out;
2394 case STAT_IO_COMPLETE:
2395 /* internal abort command complete */
2396 ts->stat = TMF_RESP_FUNC_SUCC;
2397 del_timer(&slot->internal_abort_timer);
2398 goto out;
2399 case STAT_IO_NO_DEVICE:
2400 ts->stat = TMF_RESP_FUNC_COMPLETE;
2401 del_timer(&slot->internal_abort_timer);
2402 goto out;
2403 case STAT_IO_NOT_VALID:
2404 /* abort single io, controller don't find
2405 * the io need to abort
2406 */
2407 ts->stat = TMF_RESP_FUNC_FAILED;
2408 del_timer(&slot->internal_abort_timer);
2409 goto out;
2410 default:
2411 break;
2412 }
2413
2414 if ((dw0 & CMPLT_HDR_ERX_MSK) && (!(dw0 & CMPLT_HDR_RSPNS_XFRD_MSK))) {
2415 u32 err_phase = (dw0 & CMPLT_HDR_ERR_PHASE_MSK)
2416 >> CMPLT_HDR_ERR_PHASE_OFF;
2417 u32 *error_info = hisi_sas_status_buf_addr_mem(slot);
2418
2419 /* Analyse error happens on which phase TX or RX */
2420 if (ERR_ON_TX_PHASE(err_phase))
2421 slot_err_v2_hw(hisi_hba, task, slot, 1);
2422 else if (ERR_ON_RX_PHASE(err_phase))
2423 slot_err_v2_hw(hisi_hba, task, slot, 2);
2424
2425 if (ts->stat != SAS_DATA_UNDERRUN)
2426 dev_info(dev, "erroneous completion iptt=%d task=%p dev id=%d "
2427 "CQ hdr: 0x%x 0x%x 0x%x 0x%x "
2428 "Error info: 0x%x 0x%x 0x%x 0x%x\n",
2429 slot->idx, task, sas_dev->device_id,
2430 complete_hdr->dw0, complete_hdr->dw1,
2431 complete_hdr->act, complete_hdr->dw3,
2432 error_info[0], error_info[1],
2433 error_info[2], error_info[3]);
2434
2435 if (unlikely(slot->abort))
2436 return ts->stat;
2437 goto out;
2438 }
2439
2440 switch (task->task_proto) {
2441 case SAS_PROTOCOL_SSP:
2442 {
2443 struct hisi_sas_status_buffer *status_buffer =
2444 hisi_sas_status_buf_addr_mem(slot);
2445 struct ssp_response_iu *iu = (struct ssp_response_iu *)
2446 &status_buffer->iu[0];
2447
2448 sas_ssp_task_response(dev, task, iu);
2449 break;
2450 }
2451 case SAS_PROTOCOL_SMP:
2452 {
2453 struct scatterlist *sg_resp = &task->smp_task.smp_resp;
2454 void *to;
2455
2456 ts->stat = SAM_STAT_GOOD;
2457 to = kmap_atomic(sg_page(sg_resp));
2458
2459 dma_unmap_sg(dev, &task->smp_task.smp_resp, 1,
2460 DMA_FROM_DEVICE);
2461 dma_unmap_sg(dev, &task->smp_task.smp_req, 1,
2462 DMA_TO_DEVICE);
2463 memcpy(to + sg_resp->offset,
2464 hisi_sas_status_buf_addr_mem(slot) +
2465 sizeof(struct hisi_sas_err_record),
2466 sg_dma_len(sg_resp));
2467 kunmap_atomic(to);
2468 break;
2469 }
2470 case SAS_PROTOCOL_SATA:
2471 case SAS_PROTOCOL_STP:
2472 case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP:
2473 {
2474 ts->stat = SAM_STAT_GOOD;
2475 hisi_sas_sata_done(task, slot);
2476 break;
2477 }
2478 default:
2479 ts->stat = SAM_STAT_CHECK_CONDITION;
2480 break;
2481 }
2482
2483 if (!slot->port->port_attached) {
2484 dev_warn(dev, "slot complete: port %d has removed\n",
2485 slot->port->sas_port.id);
2486 ts->stat = SAS_PHY_DOWN;
2487 }
2488
2489 out:
2490 sts = ts->stat;
2491 spin_lock_irqsave(&task->task_state_lock, flags);
2492 if (task->task_state_flags & SAS_TASK_STATE_ABORTED) {
2493 spin_unlock_irqrestore(&task->task_state_lock, flags);
2494 dev_info(dev, "slot complete: task(%p) aborted\n", task);
2495 return SAS_ABORTED_TASK;
2496 }
2497 task->task_state_flags |= SAS_TASK_STATE_DONE;
2498 spin_unlock_irqrestore(&task->task_state_lock, flags);
2499 hisi_sas_slot_task_free(hisi_hba, task, slot);
2500
2501 if (!is_internal && (task->task_proto != SAS_PROTOCOL_SMP)) {
2502 spin_lock_irqsave(&device->done_lock, flags);
2503 if (test_bit(SAS_HA_FROZEN, &ha->state)) {
2504 spin_unlock_irqrestore(&device->done_lock, flags);
2505 dev_info(dev, "slot complete: task(%p) ignored\n ",
2506 task);
2507 return sts;
2508 }
2509 spin_unlock_irqrestore(&device->done_lock, flags);
2510 }
2511
2512 if (task->task_done)
2513 task->task_done(task);
2514
2515 return sts;
2516 }
2517
2518 static void prep_ata_v2_hw(struct hisi_hba *hisi_hba,
2519 struct hisi_sas_slot *slot)
2520 {
2521 struct sas_task *task = slot->task;
2522 struct domain_device *device = task->dev;
2523 struct domain_device *parent_dev = device->parent;
2524 struct hisi_sas_device *sas_dev = device->lldd_dev;
2525 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
2526 struct asd_sas_port *sas_port = device->port;
2527 struct hisi_sas_port *port = to_hisi_sas_port(sas_port);
2528 struct hisi_sas_tmf_task *tmf = slot->tmf;
2529 u8 *buf_cmd;
2530 int has_data = 0, hdr_tag = 0;
2531 u32 dw0, dw1 = 0, dw2 = 0;
2532
2533 /* create header */
2534 /* dw0 */
2535 dw0 = port->id << CMD_HDR_PORT_OFF;
2536 if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type))
2537 dw0 |= 3 << CMD_HDR_CMD_OFF;
2538 else
2539 dw0 |= 4 << CMD_HDR_CMD_OFF;
2540
2541 if (tmf && tmf->force_phy) {
2542 dw0 |= CMD_HDR_FORCE_PHY_MSK;
2543 dw0 |= (1 << tmf->phy_id) << CMD_HDR_PHY_ID_OFF;
2544 }
2545
2546 hdr->dw0 = cpu_to_le32(dw0);
2547
2548 /* dw1 */
2549 switch (task->data_dir) {
2550 case DMA_TO_DEVICE:
2551 has_data = 1;
2552 dw1 |= DIR_TO_DEVICE << CMD_HDR_DIR_OFF;
2553 break;
2554 case DMA_FROM_DEVICE:
2555 has_data = 1;
2556 dw1 |= DIR_TO_INI << CMD_HDR_DIR_OFF;
2557 break;
2558 default:
2559 dw1 &= ~CMD_HDR_DIR_MSK;
2560 }
2561
2562 if ((task->ata_task.fis.command == ATA_CMD_DEV_RESET) &&
2563 (task->ata_task.fis.control & ATA_SRST))
2564 dw1 |= 1 << CMD_HDR_RESET_OFF;
2565
2566 dw1 |= (hisi_sas_get_ata_protocol(
2567 &task->ata_task.fis, task->data_dir))
2568 << CMD_HDR_FRAME_TYPE_OFF;
2569 dw1 |= sas_dev->device_id << CMD_HDR_DEV_ID_OFF;
2570 hdr->dw1 = cpu_to_le32(dw1);
2571
2572 /* dw2 */
2573 if (task->ata_task.use_ncq && hisi_sas_get_ncq_tag(task, &hdr_tag)) {
2574 task->ata_task.fis.sector_count |= (u8) (hdr_tag << 3);
2575 dw2 |= hdr_tag << CMD_HDR_NCQ_TAG_OFF;
2576 }
2577
2578 dw2 |= (HISI_SAS_MAX_STP_RESP_SZ / 4) << CMD_HDR_CFL_OFF |
2579 2 << CMD_HDR_SG_MOD_OFF;
2580 hdr->dw2 = cpu_to_le32(dw2);
2581
2582 /* dw3 */
2583 hdr->transfer_tags = cpu_to_le32(slot->idx);
2584
2585 if (has_data)
2586 prep_prd_sge_v2_hw(hisi_hba, slot, hdr, task->scatter,
2587 slot->n_elem);
2588
2589 hdr->data_transfer_len = cpu_to_le32(task->total_xfer_len);
2590 hdr->cmd_table_addr = cpu_to_le64(hisi_sas_cmd_hdr_addr_dma(slot));
2591 hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot));
2592
2593 buf_cmd = hisi_sas_cmd_hdr_addr_mem(slot);
2594
2595 if (likely(!task->ata_task.device_control_reg_update))
2596 task->ata_task.fis.flags |= 0x80; /* C=1: update ATA cmd reg */
2597 /* fill in command FIS */
2598 memcpy(buf_cmd, &task->ata_task.fis, sizeof(struct host_to_dev_fis));
2599 }
2600
2601 static void hisi_sas_internal_abort_quirk_timeout(struct timer_list *t)
2602 {
2603 struct hisi_sas_slot *slot = from_timer(slot, t, internal_abort_timer);
2604 struct hisi_sas_port *port = slot->port;
2605 struct asd_sas_port *asd_sas_port;
2606 struct asd_sas_phy *sas_phy;
2607
2608 if (!port)
2609 return;
2610
2611 asd_sas_port = &port->sas_port;
2612
2613 /* Kick the hardware - send break command */
2614 list_for_each_entry(sas_phy, &asd_sas_port->phy_list, port_phy_el) {
2615 struct hisi_sas_phy *phy = sas_phy->lldd_phy;
2616 struct hisi_hba *hisi_hba = phy->hisi_hba;
2617 int phy_no = sas_phy->id;
2618 u32 link_dfx2;
2619
2620 link_dfx2 = hisi_sas_phy_read32(hisi_hba, phy_no, LINK_DFX2);
2621 if ((link_dfx2 == LINK_DFX2_RCVR_HOLD_STS_MSK) ||
2622 (link_dfx2 & LINK_DFX2_SEND_HOLD_STS_MSK)) {
2623 u32 txid_auto;
2624
2625 txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no,
2626 TXID_AUTO);
2627 txid_auto |= TXID_AUTO_CTB_MSK;
2628 hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO,
2629 txid_auto);
2630 return;
2631 }
2632 }
2633 }
2634
2635 static void prep_abort_v2_hw(struct hisi_hba *hisi_hba,
2636 struct hisi_sas_slot *slot,
2637 int device_id, int abort_flag, int tag_to_abort)
2638 {
2639 struct sas_task *task = slot->task;
2640 struct domain_device *dev = task->dev;
2641 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
2642 struct hisi_sas_port *port = slot->port;
2643 struct timer_list *timer = &slot->internal_abort_timer;
2644
2645 /* setup the quirk timer */
2646 timer_setup(timer, hisi_sas_internal_abort_quirk_timeout, 0);
2647 /* Set the timeout to 10ms less than internal abort timeout */
2648 mod_timer(timer, jiffies + msecs_to_jiffies(100));
2649
2650 /* dw0 */
2651 hdr->dw0 = cpu_to_le32((5 << CMD_HDR_CMD_OFF) | /*abort*/
2652 (port->id << CMD_HDR_PORT_OFF) |
2653 (dev_is_sata(dev) <<
2654 CMD_HDR_ABORT_DEVICE_TYPE_OFF) |
2655 (abort_flag << CMD_HDR_ABORT_FLAG_OFF));
2656
2657 /* dw1 */
2658 hdr->dw1 = cpu_to_le32(device_id << CMD_HDR_DEV_ID_OFF);
2659
2660 /* dw7 */
2661 hdr->dw7 = cpu_to_le32(tag_to_abort << CMD_HDR_ABORT_IPTT_OFF);
2662 hdr->transfer_tags = cpu_to_le32(slot->idx);
2663 }
2664
2665 static int phy_up_v2_hw(int phy_no, struct hisi_hba *hisi_hba)
2666 {
2667 int i, res = IRQ_HANDLED;
2668 u32 port_id, link_rate;
2669 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
2670 struct asd_sas_phy *sas_phy = &phy->sas_phy;
2671 struct device *dev = hisi_hba->dev;
2672 u32 *frame_rcvd = (u32 *)sas_phy->frame_rcvd;
2673 struct sas_identify_frame *id = (struct sas_identify_frame *)frame_rcvd;
2674 unsigned long flags;
2675
2676 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_PHY_ENA_MSK, 1);
2677
2678 if (is_sata_phy_v2_hw(hisi_hba, phy_no))
2679 goto end;
2680
2681 del_timer(&phy->timer);
2682
2683 if (phy_no == 8) {
2684 u32 port_state = hisi_sas_read32(hisi_hba, PORT_STATE);
2685
2686 port_id = (port_state & PORT_STATE_PHY8_PORT_NUM_MSK) >>
2687 PORT_STATE_PHY8_PORT_NUM_OFF;
2688 link_rate = (port_state & PORT_STATE_PHY8_CONN_RATE_MSK) >>
2689 PORT_STATE_PHY8_CONN_RATE_OFF;
2690 } else {
2691 port_id = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA);
2692 port_id = (port_id >> (4 * phy_no)) & 0xf;
2693 link_rate = hisi_sas_read32(hisi_hba, PHY_CONN_RATE);
2694 link_rate = (link_rate >> (phy_no * 4)) & 0xf;
2695 }
2696
2697 if (port_id == 0xf) {
2698 dev_err(dev, "phyup: phy%d invalid portid\n", phy_no);
2699 res = IRQ_NONE;
2700 goto end;
2701 }
2702
2703 for (i = 0; i < 6; i++) {
2704 u32 idaf = hisi_sas_phy_read32(hisi_hba, phy_no,
2705 RX_IDAF_DWORD0 + (i * 4));
2706 frame_rcvd[i] = __swab32(idaf);
2707 }
2708
2709 sas_phy->linkrate = link_rate;
2710 sas_phy->oob_mode = SAS_OOB_MODE;
2711 memcpy(sas_phy->attached_sas_addr, &id->sas_addr, SAS_ADDR_SIZE);
2712 dev_info(dev, "phyup: phy%d link_rate=%d\n", phy_no, link_rate);
2713 phy->port_id = port_id;
2714 phy->phy_type &= ~(PORT_TYPE_SAS | PORT_TYPE_SATA);
2715 phy->phy_type |= PORT_TYPE_SAS;
2716 phy->phy_attached = 1;
2717 phy->identify.device_type = id->dev_type;
2718 phy->frame_rcvd_size = sizeof(struct sas_identify_frame);
2719 if (phy->identify.device_type == SAS_END_DEVICE)
2720 phy->identify.target_port_protocols =
2721 SAS_PROTOCOL_SSP;
2722 else if (phy->identify.device_type != SAS_PHY_UNUSED) {
2723 phy->identify.target_port_protocols =
2724 SAS_PROTOCOL_SMP;
2725 if (!timer_pending(&hisi_hba->timer))
2726 set_link_timer_quirk(hisi_hba);
2727 }
2728 hisi_sas_notify_phy_event(phy, HISI_PHYE_PHY_UP);
2729 spin_lock_irqsave(&phy->lock, flags);
2730 if (phy->reset_completion) {
2731 phy->in_reset = 0;
2732 complete(phy->reset_completion);
2733 }
2734 spin_unlock_irqrestore(&phy->lock, flags);
2735
2736 end:
2737 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0,
2738 CHL_INT0_SL_PHY_ENABLE_MSK);
2739 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_PHY_ENA_MSK, 0);
2740
2741 return res;
2742 }
2743
2744 static bool check_any_wideports_v2_hw(struct hisi_hba *hisi_hba)
2745 {
2746 u32 port_state;
2747
2748 port_state = hisi_sas_read32(hisi_hba, PORT_STATE);
2749 if (port_state & 0x1ff)
2750 return true;
2751
2752 return false;
2753 }
2754
2755 static int phy_down_v2_hw(int phy_no, struct hisi_hba *hisi_hba)
2756 {
2757 u32 phy_state, sl_ctrl, txid_auto;
2758 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
2759 struct hisi_sas_port *port = phy->port;
2760 struct device *dev = hisi_hba->dev;
2761
2762 del_timer(&phy->timer);
2763 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_NOT_RDY_MSK, 1);
2764
2765 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE);
2766 dev_info(dev, "phydown: phy%d phy_state=0x%x\n", phy_no, phy_state);
2767 hisi_sas_phy_down(hisi_hba, phy_no, (phy_state & 1 << phy_no) ? 1 : 0);
2768
2769 sl_ctrl = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
2770 hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL,
2771 sl_ctrl & ~SL_CONTROL_CTA_MSK);
2772 if (port && !get_wideport_bitmap_v2_hw(hisi_hba, port->id))
2773 if (!check_any_wideports_v2_hw(hisi_hba) &&
2774 timer_pending(&hisi_hba->timer))
2775 del_timer(&hisi_hba->timer);
2776
2777 txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no, TXID_AUTO);
2778 hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO,
2779 txid_auto | TXID_AUTO_CT3_MSK);
2780
2781 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0, CHL_INT0_NOT_RDY_MSK);
2782 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_NOT_RDY_MSK, 0);
2783
2784 return IRQ_HANDLED;
2785 }
2786
2787 static irqreturn_t int_phy_updown_v2_hw(int irq_no, void *p)
2788 {
2789 struct hisi_hba *hisi_hba = p;
2790 u32 irq_msk;
2791 int phy_no = 0;
2792 irqreturn_t res = IRQ_NONE;
2793
2794 irq_msk = (hisi_sas_read32(hisi_hba, HGC_INVLD_DQE_INFO)
2795 >> HGC_INVLD_DQE_INFO_FB_CH0_OFF) & 0x1ff;
2796 while (irq_msk) {
2797 if (irq_msk & 1) {
2798 u32 reg_value = hisi_sas_phy_read32(hisi_hba, phy_no,
2799 CHL_INT0);
2800
2801 switch (reg_value & (CHL_INT0_NOT_RDY_MSK |
2802 CHL_INT0_SL_PHY_ENABLE_MSK)) {
2803
2804 case CHL_INT0_SL_PHY_ENABLE_MSK:
2805 /* phy up */
2806 if (phy_up_v2_hw(phy_no, hisi_hba) ==
2807 IRQ_HANDLED)
2808 res = IRQ_HANDLED;
2809 break;
2810
2811 case CHL_INT0_NOT_RDY_MSK:
2812 /* phy down */
2813 if (phy_down_v2_hw(phy_no, hisi_hba) ==
2814 IRQ_HANDLED)
2815 res = IRQ_HANDLED;
2816 break;
2817
2818 case (CHL_INT0_NOT_RDY_MSK |
2819 CHL_INT0_SL_PHY_ENABLE_MSK):
2820 reg_value = hisi_sas_read32(hisi_hba,
2821 PHY_STATE);
2822 if (reg_value & BIT(phy_no)) {
2823 /* phy up */
2824 if (phy_up_v2_hw(phy_no, hisi_hba) ==
2825 IRQ_HANDLED)
2826 res = IRQ_HANDLED;
2827 } else {
2828 /* phy down */
2829 if (phy_down_v2_hw(phy_no, hisi_hba) ==
2830 IRQ_HANDLED)
2831 res = IRQ_HANDLED;
2832 }
2833 break;
2834
2835 default:
2836 break;
2837 }
2838
2839 }
2840 irq_msk >>= 1;
2841 phy_no++;
2842 }
2843
2844 return res;
2845 }
2846
2847 static void phy_bcast_v2_hw(int phy_no, struct hisi_hba *hisi_hba)
2848 {
2849 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
2850 struct asd_sas_phy *sas_phy = &phy->sas_phy;
2851 struct sas_ha_struct *sas_ha = &hisi_hba->sha;
2852 u32 bcast_status;
2853
2854 hisi_sas_phy_write32(hisi_hba, phy_no, SL_RX_BCAST_CHK_MSK, 1);
2855 bcast_status = hisi_sas_phy_read32(hisi_hba, phy_no, RX_PRIMS_STATUS);
2856 if ((bcast_status & RX_BCAST_CHG_MSK) &&
2857 !test_bit(HISI_SAS_RESET_BIT, &hisi_hba->flags))
2858 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
2859 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0,
2860 CHL_INT0_SL_RX_BCST_ACK_MSK);
2861 hisi_sas_phy_write32(hisi_hba, phy_no, SL_RX_BCAST_CHK_MSK, 0);
2862 }
2863
2864 static const struct hisi_sas_hw_error port_ecc_axi_error[] = {
2865 {
2866 .irq_msk = BIT(CHL_INT1_DMAC_TX_ECC_ERR_OFF),
2867 .msg = "dmac_tx_ecc_bad_err",
2868 },
2869 {
2870 .irq_msk = BIT(CHL_INT1_DMAC_RX_ECC_ERR_OFF),
2871 .msg = "dmac_rx_ecc_bad_err",
2872 },
2873 {
2874 .irq_msk = BIT(CHL_INT1_DMAC_TX_AXI_WR_ERR_OFF),
2875 .msg = "dma_tx_axi_wr_err",
2876 },
2877 {
2878 .irq_msk = BIT(CHL_INT1_DMAC_TX_AXI_RD_ERR_OFF),
2879 .msg = "dma_tx_axi_rd_err",
2880 },
2881 {
2882 .irq_msk = BIT(CHL_INT1_DMAC_RX_AXI_WR_ERR_OFF),
2883 .msg = "dma_rx_axi_wr_err",
2884 },
2885 {
2886 .irq_msk = BIT(CHL_INT1_DMAC_RX_AXI_RD_ERR_OFF),
2887 .msg = "dma_rx_axi_rd_err",
2888 },
2889 };
2890
2891 static irqreturn_t int_chnl_int_v2_hw(int irq_no, void *p)
2892 {
2893 struct hisi_hba *hisi_hba = p;
2894 struct device *dev = hisi_hba->dev;
2895 u32 ent_msk, ent_tmp, irq_msk;
2896 int phy_no = 0;
2897
2898 ent_msk = hisi_sas_read32(hisi_hba, ENT_INT_SRC_MSK3);
2899 ent_tmp = ent_msk;
2900 ent_msk |= ENT_INT_SRC_MSK3_ENT95_MSK_MSK;
2901 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, ent_msk);
2902
2903 irq_msk = (hisi_sas_read32(hisi_hba, HGC_INVLD_DQE_INFO) >>
2904 HGC_INVLD_DQE_INFO_FB_CH3_OFF) & 0x1ff;
2905
2906 while (irq_msk) {
2907 u32 irq_value0 = hisi_sas_phy_read32(hisi_hba, phy_no,
2908 CHL_INT0);
2909 u32 irq_value1 = hisi_sas_phy_read32(hisi_hba, phy_no,
2910 CHL_INT1);
2911 u32 irq_value2 = hisi_sas_phy_read32(hisi_hba, phy_no,
2912 CHL_INT2);
2913
2914 if ((irq_msk & (1 << phy_no)) && irq_value1) {
2915 int i;
2916
2917 for (i = 0; i < ARRAY_SIZE(port_ecc_axi_error); i++) {
2918 const struct hisi_sas_hw_error *error =
2919 &port_ecc_axi_error[i];
2920
2921 if (!(irq_value1 & error->irq_msk))
2922 continue;
2923
2924 dev_warn(dev, "%s error (phy%d 0x%x) found!\n",
2925 error->msg, phy_no, irq_value1);
2926 queue_work(hisi_hba->wq, &hisi_hba->rst_work);
2927 }
2928
2929 hisi_sas_phy_write32(hisi_hba, phy_no,
2930 CHL_INT1, irq_value1);
2931 }
2932
2933 if ((irq_msk & (1 << phy_no)) && irq_value2) {
2934 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
2935
2936 if (irq_value2 & BIT(CHL_INT2_SL_IDAF_TOUT_CONF_OFF)) {
2937 dev_warn(dev, "phy%d identify timeout\n",
2938 phy_no);
2939 hisi_sas_notify_phy_event(phy,
2940 HISI_PHYE_LINK_RESET);
2941 }
2942
2943 hisi_sas_phy_write32(hisi_hba, phy_no,
2944 CHL_INT2, irq_value2);
2945 }
2946
2947 if ((irq_msk & (1 << phy_no)) && irq_value0) {
2948 if (irq_value0 & CHL_INT0_SL_RX_BCST_ACK_MSK)
2949 phy_bcast_v2_hw(phy_no, hisi_hba);
2950
2951 if (irq_value0 & CHL_INT0_PHY_RDY_MSK)
2952 hisi_sas_phy_oob_ready(hisi_hba, phy_no);
2953
2954 hisi_sas_phy_write32(hisi_hba, phy_no,
2955 CHL_INT0, irq_value0
2956 & (~CHL_INT0_HOTPLUG_TOUT_MSK)
2957 & (~CHL_INT0_SL_PHY_ENABLE_MSK)
2958 & (~CHL_INT0_NOT_RDY_MSK));
2959 }
2960 irq_msk &= ~(1 << phy_no);
2961 phy_no++;
2962 }
2963
2964 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, ent_tmp);
2965
2966 return IRQ_HANDLED;
2967 }
2968
2969 static void
2970 one_bit_ecc_error_process_v2_hw(struct hisi_hba *hisi_hba, u32 irq_value)
2971 {
2972 struct device *dev = hisi_hba->dev;
2973 const struct hisi_sas_hw_error *ecc_error;
2974 u32 val;
2975 int i;
2976
2977 for (i = 0; i < ARRAY_SIZE(one_bit_ecc_errors); i++) {
2978 ecc_error = &one_bit_ecc_errors[i];
2979 if (irq_value & ecc_error->irq_msk) {
2980 val = hisi_sas_read32(hisi_hba, ecc_error->reg);
2981 val &= ecc_error->msk;
2982 val >>= ecc_error->shift;
2983 dev_warn(dev, ecc_error->msg, val);
2984 }
2985 }
2986 }
2987
2988 static void multi_bit_ecc_error_process_v2_hw(struct hisi_hba *hisi_hba,
2989 u32 irq_value)
2990 {
2991 struct device *dev = hisi_hba->dev;
2992 const struct hisi_sas_hw_error *ecc_error;
2993 u32 val;
2994 int i;
2995
2996 for (i = 0; i < ARRAY_SIZE(multi_bit_ecc_errors); i++) {
2997 ecc_error = &multi_bit_ecc_errors[i];
2998 if (irq_value & ecc_error->irq_msk) {
2999 val = hisi_sas_read32(hisi_hba, ecc_error->reg);
3000 val &= ecc_error->msk;
3001 val >>= ecc_error->shift;
3002 dev_err(dev, ecc_error->msg, irq_value, val);
3003 queue_work(hisi_hba->wq, &hisi_hba->rst_work);
3004 }
3005 }
3006
3007 return;
3008 }
3009
3010 static irqreturn_t fatal_ecc_int_v2_hw(int irq_no, void *p)
3011 {
3012 struct hisi_hba *hisi_hba = p;
3013 u32 irq_value, irq_msk;
3014
3015 irq_msk = hisi_sas_read32(hisi_hba, SAS_ECC_INTR_MSK);
3016 hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, irq_msk | 0xffffffff);
3017
3018 irq_value = hisi_sas_read32(hisi_hba, SAS_ECC_INTR);
3019 if (irq_value) {
3020 one_bit_ecc_error_process_v2_hw(hisi_hba, irq_value);
3021 multi_bit_ecc_error_process_v2_hw(hisi_hba, irq_value);
3022 }
3023
3024 hisi_sas_write32(hisi_hba, SAS_ECC_INTR, irq_value);
3025 hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, irq_msk);
3026
3027 return IRQ_HANDLED;
3028 }
3029
3030 static const struct hisi_sas_hw_error axi_error[] = {
3031 { .msk = BIT(0), .msg = "IOST_AXI_W_ERR" },
3032 { .msk = BIT(1), .msg = "IOST_AXI_R_ERR" },
3033 { .msk = BIT(2), .msg = "ITCT_AXI_W_ERR" },
3034 { .msk = BIT(3), .msg = "ITCT_AXI_R_ERR" },
3035 { .msk = BIT(4), .msg = "SATA_AXI_W_ERR" },
3036 { .msk = BIT(5), .msg = "SATA_AXI_R_ERR" },
3037 { .msk = BIT(6), .msg = "DQE_AXI_R_ERR" },
3038 { .msk = BIT(7), .msg = "CQE_AXI_W_ERR" },
3039 {},
3040 };
3041
3042 static const struct hisi_sas_hw_error fifo_error[] = {
3043 { .msk = BIT(8), .msg = "CQE_WINFO_FIFO" },
3044 { .msk = BIT(9), .msg = "CQE_MSG_FIFIO" },
3045 { .msk = BIT(10), .msg = "GETDQE_FIFO" },
3046 { .msk = BIT(11), .msg = "CMDP_FIFO" },
3047 { .msk = BIT(12), .msg = "AWTCTRL_FIFO" },
3048 {},
3049 };
3050
3051 static const struct hisi_sas_hw_error fatal_axi_errors[] = {
3052 {
3053 .irq_msk = BIT(ENT_INT_SRC3_WP_DEPTH_OFF),
3054 .msg = "write pointer and depth",
3055 },
3056 {
3057 .irq_msk = BIT(ENT_INT_SRC3_IPTT_SLOT_NOMATCH_OFF),
3058 .msg = "iptt no match slot",
3059 },
3060 {
3061 .irq_msk = BIT(ENT_INT_SRC3_RP_DEPTH_OFF),
3062 .msg = "read pointer and depth",
3063 },
3064 {
3065 .irq_msk = BIT(ENT_INT_SRC3_AXI_OFF),
3066 .reg = HGC_AXI_FIFO_ERR_INFO,
3067 .sub = axi_error,
3068 },
3069 {
3070 .irq_msk = BIT(ENT_INT_SRC3_FIFO_OFF),
3071 .reg = HGC_AXI_FIFO_ERR_INFO,
3072 .sub = fifo_error,
3073 },
3074 {
3075 .irq_msk = BIT(ENT_INT_SRC3_LM_OFF),
3076 .msg = "LM add/fetch list",
3077 },
3078 {
3079 .irq_msk = BIT(ENT_INT_SRC3_ABT_OFF),
3080 .msg = "SAS_HGC_ABT fetch LM list",
3081 },
3082 };
3083
3084 static irqreturn_t fatal_axi_int_v2_hw(int irq_no, void *p)
3085 {
3086 struct hisi_hba *hisi_hba = p;
3087 u32 irq_value, irq_msk, err_value;
3088 struct device *dev = hisi_hba->dev;
3089 const struct hisi_sas_hw_error *axi_error;
3090 int i;
3091
3092 irq_msk = hisi_sas_read32(hisi_hba, ENT_INT_SRC_MSK3);
3093 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, irq_msk | 0xfffffffe);
3094
3095 irq_value = hisi_sas_read32(hisi_hba, ENT_INT_SRC3);
3096
3097 for (i = 0; i < ARRAY_SIZE(fatal_axi_errors); i++) {
3098 axi_error = &fatal_axi_errors[i];
3099 if (!(irq_value & axi_error->irq_msk))
3100 continue;
3101
3102 hisi_sas_write32(hisi_hba, ENT_INT_SRC3,
3103 1 << axi_error->shift);
3104 if (axi_error->sub) {
3105 const struct hisi_sas_hw_error *sub = axi_error->sub;
3106
3107 err_value = hisi_sas_read32(hisi_hba, axi_error->reg);
3108 for (; sub->msk || sub->msg; sub++) {
3109 if (!(err_value & sub->msk))
3110 continue;
3111 dev_err(dev, "%s (0x%x) found!\n",
3112 sub->msg, irq_value);
3113 queue_work(hisi_hba->wq, &hisi_hba->rst_work);
3114 }
3115 } else {
3116 dev_err(dev, "%s (0x%x) found!\n",
3117 axi_error->msg, irq_value);
3118 queue_work(hisi_hba->wq, &hisi_hba->rst_work);
3119 }
3120 }
3121
3122 if (irq_value & BIT(ENT_INT_SRC3_ITC_INT_OFF)) {
3123 u32 reg_val = hisi_sas_read32(hisi_hba, ITCT_CLR);
3124 u32 dev_id = reg_val & ITCT_DEV_MSK;
3125 struct hisi_sas_device *sas_dev = &hisi_hba->devices[dev_id];
3126
3127 hisi_sas_write32(hisi_hba, ITCT_CLR, 0);
3128 dev_dbg(dev, "clear ITCT ok\n");
3129 complete(sas_dev->completion);
3130 }
3131
3132 hisi_sas_write32(hisi_hba, ENT_INT_SRC3, irq_value);
3133 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, irq_msk);
3134
3135 return IRQ_HANDLED;
3136 }
3137
3138 static void cq_tasklet_v2_hw(unsigned long val)
3139 {
3140 struct hisi_sas_cq *cq = (struct hisi_sas_cq *)val;
3141 struct hisi_hba *hisi_hba = cq->hisi_hba;
3142 struct hisi_sas_slot *slot;
3143 struct hisi_sas_itct *itct;
3144 struct hisi_sas_complete_v2_hdr *complete_queue;
3145 u32 rd_point = cq->rd_point, wr_point, dev_id;
3146 int queue = cq->id;
3147
3148 if (unlikely(hisi_hba->reject_stp_links_msk))
3149 phys_try_accept_stp_links_v2_hw(hisi_hba);
3150
3151 complete_queue = hisi_hba->complete_hdr[queue];
3152
3153 wr_point = hisi_sas_read32(hisi_hba, COMPL_Q_0_WR_PTR +
3154 (0x14 * queue));
3155
3156 while (rd_point != wr_point) {
3157 struct hisi_sas_complete_v2_hdr *complete_hdr;
3158 int iptt;
3159
3160 complete_hdr = &complete_queue[rd_point];
3161
3162 /* Check for NCQ completion */
3163 if (complete_hdr->act) {
3164 u32 act_tmp = le32_to_cpu(complete_hdr->act);
3165 int ncq_tag_count = ffs(act_tmp);
3166 u32 dw1 = le32_to_cpu(complete_hdr->dw1);
3167
3168 dev_id = (dw1 & CMPLT_HDR_DEV_ID_MSK) >>
3169 CMPLT_HDR_DEV_ID_OFF;
3170 itct = &hisi_hba->itct[dev_id];
3171
3172 /* The NCQ tags are held in the itct header */
3173 while (ncq_tag_count) {
3174 __le64 *_ncq_tag = &itct->qw4_15[0], __ncq_tag;
3175 u64 ncq_tag;
3176
3177 ncq_tag_count--;
3178 __ncq_tag = _ncq_tag[ncq_tag_count / 5];
3179 ncq_tag = le64_to_cpu(__ncq_tag);
3180 iptt = (ncq_tag >> (ncq_tag_count % 5) * 12) &
3181 0xfff;
3182
3183 slot = &hisi_hba->slot_info[iptt];
3184 slot->cmplt_queue_slot = rd_point;
3185 slot->cmplt_queue = queue;
3186 slot_complete_v2_hw(hisi_hba, slot);
3187
3188 act_tmp &= ~(1 << ncq_tag_count);
3189 ncq_tag_count = ffs(act_tmp);
3190 }
3191 } else {
3192 u32 dw1 = le32_to_cpu(complete_hdr->dw1);
3193
3194 iptt = dw1 & CMPLT_HDR_IPTT_MSK;
3195 slot = &hisi_hba->slot_info[iptt];
3196 slot->cmplt_queue_slot = rd_point;
3197 slot->cmplt_queue = queue;
3198 slot_complete_v2_hw(hisi_hba, slot);
3199 }
3200
3201 if (++rd_point >= HISI_SAS_QUEUE_SLOTS)
3202 rd_point = 0;
3203 }
3204
3205 /* update rd_point */
3206 cq->rd_point = rd_point;
3207 hisi_sas_write32(hisi_hba, COMPL_Q_0_RD_PTR + (0x14 * queue), rd_point);
3208 }
3209
3210 static irqreturn_t cq_interrupt_v2_hw(int irq_no, void *p)
3211 {
3212 struct hisi_sas_cq *cq = p;
3213 struct hisi_hba *hisi_hba = cq->hisi_hba;
3214 int queue = cq->id;
3215
3216 hisi_sas_write32(hisi_hba, OQ_INT_SRC, 1 << queue);
3217
3218 tasklet_schedule(&cq->tasklet);
3219
3220 return IRQ_HANDLED;
3221 }
3222
3223 static irqreturn_t sata_int_v2_hw(int irq_no, void *p)
3224 {
3225 struct hisi_sas_phy *phy = p;
3226 struct hisi_hba *hisi_hba = phy->hisi_hba;
3227 struct asd_sas_phy *sas_phy = &phy->sas_phy;
3228 struct device *dev = hisi_hba->dev;
3229 struct hisi_sas_initial_fis *initial_fis;
3230 struct dev_to_host_fis *fis;
3231 u32 ent_tmp, ent_msk, ent_int, port_id, link_rate, hard_phy_linkrate;
3232 irqreturn_t res = IRQ_HANDLED;
3233 u8 attached_sas_addr[SAS_ADDR_SIZE] = {0};
3234 unsigned long flags;
3235 int phy_no, offset;
3236
3237 del_timer(&phy->timer);
3238
3239 phy_no = sas_phy->id;
3240 initial_fis = &hisi_hba->initial_fis[phy_no];
3241 fis = &initial_fis->fis;
3242
3243 offset = 4 * (phy_no / 4);
3244 ent_msk = hisi_sas_read32(hisi_hba, ENT_INT_SRC_MSK1 + offset);
3245 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1 + offset,
3246 ent_msk | 1 << ((phy_no % 4) * 8));
3247
3248 ent_int = hisi_sas_read32(hisi_hba, ENT_INT_SRC1 + offset);
3249 ent_tmp = ent_int & (1 << (ENT_INT_SRC1_D2H_FIS_CH1_OFF *
3250 (phy_no % 4)));
3251 ent_int >>= ENT_INT_SRC1_D2H_FIS_CH1_OFF * (phy_no % 4);
3252 if ((ent_int & ENT_INT_SRC1_D2H_FIS_CH0_MSK) == 0) {
3253 dev_warn(dev, "sata int: phy%d did not receive FIS\n", phy_no);
3254 res = IRQ_NONE;
3255 goto end;
3256 }
3257
3258 /* check ERR bit of Status Register */
3259 if (fis->status & ATA_ERR) {
3260 dev_warn(dev, "sata int: phy%d FIS status: 0x%x\n", phy_no,
3261 fis->status);
3262 hisi_sas_notify_phy_event(phy, HISI_PHYE_LINK_RESET);
3263 res = IRQ_NONE;
3264 goto end;
3265 }
3266
3267 if (unlikely(phy_no == 8)) {
3268 u32 port_state = hisi_sas_read32(hisi_hba, PORT_STATE);
3269
3270 port_id = (port_state & PORT_STATE_PHY8_PORT_NUM_MSK) >>
3271 PORT_STATE_PHY8_PORT_NUM_OFF;
3272 link_rate = (port_state & PORT_STATE_PHY8_CONN_RATE_MSK) >>
3273 PORT_STATE_PHY8_CONN_RATE_OFF;
3274 } else {
3275 port_id = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA);
3276 port_id = (port_id >> (4 * phy_no)) & 0xf;
3277 link_rate = hisi_sas_read32(hisi_hba, PHY_CONN_RATE);
3278 link_rate = (link_rate >> (phy_no * 4)) & 0xf;
3279 }
3280
3281 if (port_id == 0xf) {
3282 dev_err(dev, "sata int: phy%d invalid portid\n", phy_no);
3283 res = IRQ_NONE;
3284 goto end;
3285 }
3286
3287 sas_phy->linkrate = link_rate;
3288 hard_phy_linkrate = hisi_sas_phy_read32(hisi_hba, phy_no,
3289 HARD_PHY_LINKRATE);
3290 phy->maximum_linkrate = hard_phy_linkrate & 0xf;
3291 phy->minimum_linkrate = (hard_phy_linkrate >> 4) & 0xf;
3292
3293 sas_phy->oob_mode = SATA_OOB_MODE;
3294 /* Make up some unique SAS address */
3295 attached_sas_addr[0] = 0x50;
3296 attached_sas_addr[6] = hisi_hba->shost->host_no;
3297 attached_sas_addr[7] = phy_no;
3298 memcpy(sas_phy->attached_sas_addr, attached_sas_addr, SAS_ADDR_SIZE);
3299 memcpy(sas_phy->frame_rcvd, fis, sizeof(struct dev_to_host_fis));
3300 dev_info(dev, "sata int phyup: phy%d link_rate=%d\n", phy_no, link_rate);
3301 phy->phy_type &= ~(PORT_TYPE_SAS | PORT_TYPE_SATA);
3302 phy->port_id = port_id;
3303 phy->phy_type |= PORT_TYPE_SATA;
3304 phy->phy_attached = 1;
3305 phy->identify.device_type = SAS_SATA_DEV;
3306 phy->frame_rcvd_size = sizeof(struct dev_to_host_fis);
3307 phy->identify.target_port_protocols = SAS_PROTOCOL_SATA;
3308 hisi_sas_notify_phy_event(phy, HISI_PHYE_PHY_UP);
3309
3310 spin_lock_irqsave(&phy->lock, flags);
3311 if (phy->reset_completion) {
3312 phy->in_reset = 0;
3313 complete(phy->reset_completion);
3314 }
3315 spin_unlock_irqrestore(&phy->lock, flags);
3316 end:
3317 hisi_sas_write32(hisi_hba, ENT_INT_SRC1 + offset, ent_tmp);
3318 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1 + offset, ent_msk);
3319
3320 return res;
3321 }
3322
3323 static irq_handler_t phy_interrupts[HISI_SAS_PHY_INT_NR] = {
3324 int_phy_updown_v2_hw,
3325 int_chnl_int_v2_hw,
3326 };
3327
3328 static irq_handler_t fatal_interrupts[HISI_SAS_FATAL_INT_NR] = {
3329 fatal_ecc_int_v2_hw,
3330 fatal_axi_int_v2_hw
3331 };
3332
3333 /**
3334 * There is a limitation in the hip06 chipset that we need
3335 * to map in all mbigen interrupts, even if they are not used.
3336 */
3337 static int interrupt_init_v2_hw(struct hisi_hba *hisi_hba)
3338 {
3339 struct platform_device *pdev = hisi_hba->platform_dev;
3340 struct device *dev = &pdev->dev;
3341 int irq, rc, irq_map[128];
3342 int i, phy_no, fatal_no, queue_no, k;
3343
3344 for (i = 0; i < 128; i++)
3345 irq_map[i] = platform_get_irq(pdev, i);
3346
3347 for (i = 0; i < HISI_SAS_PHY_INT_NR; i++) {
3348 irq = irq_map[i + 1]; /* Phy up/down is irq1 */
3349 rc = devm_request_irq(dev, irq, phy_interrupts[i], 0,
3350 DRV_NAME " phy", hisi_hba);
3351 if (rc) {
3352 dev_err(dev, "irq init: could not request "
3353 "phy interrupt %d, rc=%d\n",
3354 irq, rc);
3355 rc = -ENOENT;
3356 goto free_phy_int_irqs;
3357 }
3358 }
3359
3360 for (phy_no = 0; phy_no < hisi_hba->n_phy; phy_no++) {
3361 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
3362
3363 irq = irq_map[phy_no + 72];
3364 rc = devm_request_irq(dev, irq, sata_int_v2_hw, 0,
3365 DRV_NAME " sata", phy);
3366 if (rc) {
3367 dev_err(dev, "irq init: could not request "
3368 "sata interrupt %d, rc=%d\n",
3369 irq, rc);
3370 rc = -ENOENT;
3371 goto free_sata_int_irqs;
3372 }
3373 }
3374
3375 for (fatal_no = 0; fatal_no < HISI_SAS_FATAL_INT_NR; fatal_no++) {
3376 irq = irq_map[fatal_no + 81];
3377 rc = devm_request_irq(dev, irq, fatal_interrupts[fatal_no], 0,
3378 DRV_NAME " fatal", hisi_hba);
3379 if (rc) {
3380 dev_err(dev,
3381 "irq init: could not request fatal interrupt %d, rc=%d\n",
3382 irq, rc);
3383 rc = -ENOENT;
3384 goto free_fatal_int_irqs;
3385 }
3386 }
3387
3388 for (queue_no = 0; queue_no < hisi_hba->queue_count; queue_no++) {
3389 struct hisi_sas_cq *cq = &hisi_hba->cq[queue_no];
3390 struct tasklet_struct *t = &cq->tasklet;
3391
3392 irq = irq_map[queue_no + 96];
3393 rc = devm_request_irq(dev, irq, cq_interrupt_v2_hw, 0,
3394 DRV_NAME " cq", cq);
3395 if (rc) {
3396 dev_err(dev,
3397 "irq init: could not request cq interrupt %d, rc=%d\n",
3398 irq, rc);
3399 rc = -ENOENT;
3400 goto free_cq_int_irqs;
3401 }
3402 tasklet_init(t, cq_tasklet_v2_hw, (unsigned long)cq);
3403 }
3404
3405 hisi_hba->cq_nvecs = hisi_hba->queue_count;
3406
3407 return 0;
3408
3409 free_cq_int_irqs:
3410 for (k = 0; k < queue_no; k++) {
3411 struct hisi_sas_cq *cq = &hisi_hba->cq[k];
3412
3413 free_irq(irq_map[k + 96], cq);
3414 tasklet_kill(&cq->tasklet);
3415 }
3416 free_fatal_int_irqs:
3417 for (k = 0; k < fatal_no; k++)
3418 free_irq(irq_map[k + 81], hisi_hba);
3419 free_sata_int_irqs:
3420 for (k = 0; k < phy_no; k++) {
3421 struct hisi_sas_phy *phy = &hisi_hba->phy[k];
3422
3423 free_irq(irq_map[k + 72], phy);
3424 }
3425 free_phy_int_irqs:
3426 for (k = 0; k < i; k++)
3427 free_irq(irq_map[k + 1], hisi_hba);
3428 return rc;
3429 }
3430
3431 static int hisi_sas_v2_init(struct hisi_hba *hisi_hba)
3432 {
3433 int rc;
3434
3435 memset(hisi_hba->sata_dev_bitmap, 0, sizeof(hisi_hba->sata_dev_bitmap));
3436
3437 rc = hw_init_v2_hw(hisi_hba);
3438 if (rc)
3439 return rc;
3440
3441 rc = interrupt_init_v2_hw(hisi_hba);
3442 if (rc)
3443 return rc;
3444
3445 return 0;
3446 }
3447
3448 static void interrupt_disable_v2_hw(struct hisi_hba *hisi_hba)
3449 {
3450 struct platform_device *pdev = hisi_hba->platform_dev;
3451 int i;
3452
3453 for (i = 0; i < hisi_hba->queue_count; i++)
3454 hisi_sas_write32(hisi_hba, OQ0_INT_SRC_MSK + 0x4 * i, 0x1);
3455
3456 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1, 0xffffffff);
3457 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK2, 0xffffffff);
3458 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, 0xffffffff);
3459 hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, 0xffffffff);
3460
3461 for (i = 0; i < hisi_hba->n_phy; i++) {
3462 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1_MSK, 0xffffffff);
3463 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0xffffffff);
3464 }
3465
3466 for (i = 0; i < 128; i++)
3467 synchronize_irq(platform_get_irq(pdev, i));
3468 }
3469
3470
3471 static u32 get_phys_state_v2_hw(struct hisi_hba *hisi_hba)
3472 {
3473 return hisi_sas_read32(hisi_hba, PHY_STATE);
3474 }
3475
3476 static int soft_reset_v2_hw(struct hisi_hba *hisi_hba)
3477 {
3478 struct device *dev = hisi_hba->dev;
3479 int rc, cnt;
3480
3481 interrupt_disable_v2_hw(hisi_hba);
3482 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 0x0);
3483 hisi_sas_kill_tasklets(hisi_hba);
3484
3485 hisi_sas_stop_phys(hisi_hba);
3486
3487 mdelay(10);
3488
3489 hisi_sas_write32(hisi_hba, AXI_MASTER_CFG_BASE + AM_CTRL_GLOBAL, 0x1);
3490
3491 /* wait until bus idle */
3492 cnt = 0;
3493 while (1) {
3494 u32 status = hisi_sas_read32_relaxed(hisi_hba,
3495 AXI_MASTER_CFG_BASE + AM_CURR_TRANS_RETURN);
3496
3497 if (status == 0x3)
3498 break;
3499
3500 udelay(10);
3501 if (cnt++ > 10) {
3502 dev_err(dev, "wait axi bus state to idle timeout!\n");
3503 return -1;
3504 }
3505 }
3506
3507 hisi_sas_init_mem(hisi_hba);
3508
3509 rc = hw_init_v2_hw(hisi_hba);
3510 if (rc)
3511 return rc;
3512
3513 phys_reject_stp_links_v2_hw(hisi_hba);
3514
3515 return 0;
3516 }
3517
3518 static int write_gpio_v2_hw(struct hisi_hba *hisi_hba, u8 reg_type,
3519 u8 reg_index, u8 reg_count, u8 *write_data)
3520 {
3521 struct device *dev = hisi_hba->dev;
3522 int phy_no, count;
3523
3524 if (!hisi_hba->sgpio_regs)
3525 return -EOPNOTSUPP;
3526
3527 switch (reg_type) {
3528 case SAS_GPIO_REG_TX:
3529 count = reg_count * 4;
3530 count = min(count, hisi_hba->n_phy);
3531
3532 for (phy_no = 0; phy_no < count; phy_no++) {
3533 /*
3534 * GPIO_TX[n] register has the highest numbered drive
3535 * of the four in the first byte and the lowest
3536 * numbered drive in the fourth byte.
3537 * See SFF-8485 Rev. 0.7 Table 24.
3538 */
3539 void __iomem *reg_addr = hisi_hba->sgpio_regs +
3540 reg_index * 4 + phy_no;
3541 int data_idx = phy_no + 3 - (phy_no % 4) * 2;
3542
3543 writeb(write_data[data_idx], reg_addr);
3544 }
3545
3546 break;
3547 default:
3548 dev_err(dev, "write gpio: unsupported or bad reg type %d\n",
3549 reg_type);
3550 return -EINVAL;
3551 }
3552
3553 return 0;
3554 }
3555
3556 static int wait_cmds_complete_timeout_v2_hw(struct hisi_hba *hisi_hba,
3557 int delay_ms, int timeout_ms)
3558 {
3559 struct device *dev = hisi_hba->dev;
3560 int entries, entries_old = 0, time;
3561
3562 for (time = 0; time < timeout_ms; time += delay_ms) {
3563 entries = hisi_sas_read32(hisi_hba, CQE_SEND_CNT);
3564 if (entries == entries_old)
3565 break;
3566
3567 entries_old = entries;
3568 msleep(delay_ms);
3569 }
3570
3571 if (time >= timeout_ms)
3572 return -ETIMEDOUT;
3573
3574 dev_dbg(dev, "wait commands complete %dms\n", time);
3575
3576 return 0;
3577 }
3578
3579 static struct device_attribute *host_attrs_v2_hw[] = {
3580 &dev_attr_phy_event_threshold,
3581 NULL
3582 };
3583
3584 static struct scsi_host_template sht_v2_hw = {
3585 .name = DRV_NAME,
3586 .module = THIS_MODULE,
3587 .queuecommand = sas_queuecommand,
3588 .target_alloc = sas_target_alloc,
3589 .slave_configure = hisi_sas_slave_configure,
3590 .scan_finished = hisi_sas_scan_finished,
3591 .scan_start = hisi_sas_scan_start,
3592 .change_queue_depth = sas_change_queue_depth,
3593 .bios_param = sas_bios_param,
3594 .this_id = -1,
3595 .sg_tablesize = HISI_SAS_SGE_PAGE_CNT,
3596 .max_sectors = SCSI_DEFAULT_MAX_SECTORS,
3597 .eh_device_reset_handler = sas_eh_device_reset_handler,
3598 .eh_target_reset_handler = sas_eh_target_reset_handler,
3599 .target_destroy = sas_target_destroy,
3600 .ioctl = sas_ioctl,
3601 .shost_attrs = host_attrs_v2_hw,
3602 };
3603
3604 static const struct hisi_sas_hw hisi_sas_v2_hw = {
3605 .hw_init = hisi_sas_v2_init,
3606 .setup_itct = setup_itct_v2_hw,
3607 .slot_index_alloc = slot_index_alloc_quirk_v2_hw,
3608 .alloc_dev = alloc_dev_quirk_v2_hw,
3609 .sl_notify_ssp = sl_notify_ssp_v2_hw,
3610 .get_wideport_bitmap = get_wideport_bitmap_v2_hw,
3611 .clear_itct = clear_itct_v2_hw,
3612 .free_device = free_device_v2_hw,
3613 .prep_smp = prep_smp_v2_hw,
3614 .prep_ssp = prep_ssp_v2_hw,
3615 .prep_stp = prep_ata_v2_hw,
3616 .prep_abort = prep_abort_v2_hw,
3617 .get_free_slot = get_free_slot_v2_hw,
3618 .start_delivery = start_delivery_v2_hw,
3619 .slot_complete = slot_complete_v2_hw,
3620 .phys_init = phys_init_v2_hw,
3621 .phy_start = start_phy_v2_hw,
3622 .phy_disable = disable_phy_v2_hw,
3623 .phy_hard_reset = phy_hard_reset_v2_hw,
3624 .get_events = phy_get_events_v2_hw,
3625 .phy_set_linkrate = phy_set_linkrate_v2_hw,
3626 .phy_get_max_linkrate = phy_get_max_linkrate_v2_hw,
3627 .max_command_entries = HISI_SAS_COMMAND_ENTRIES_V2_HW,
3628 .complete_hdr_size = sizeof(struct hisi_sas_complete_v2_hdr),
3629 .soft_reset = soft_reset_v2_hw,
3630 .get_phys_state = get_phys_state_v2_hw,
3631 .write_gpio = write_gpio_v2_hw,
3632 .wait_cmds_complete_timeout = wait_cmds_complete_timeout_v2_hw,
3633 .sht = &sht_v2_hw,
3634 };
3635
3636 static int hisi_sas_v2_probe(struct platform_device *pdev)
3637 {
3638 /*
3639 * Check if we should defer the probe before we probe the
3640 * upper layer, as it's hard to defer later on.
3641 */
3642 int ret = platform_get_irq(pdev, 0);
3643
3644 if (ret < 0) {
3645 if (ret != -EPROBE_DEFER)
3646 dev_err(&pdev->dev, "cannot obtain irq\n");
3647 return ret;
3648 }
3649
3650 return hisi_sas_probe(pdev, &hisi_sas_v2_hw);
3651 }
3652
3653 static int hisi_sas_v2_remove(struct platform_device *pdev)
3654 {
3655 struct sas_ha_struct *sha = platform_get_drvdata(pdev);
3656 struct hisi_hba *hisi_hba = sha->lldd_ha;
3657
3658 hisi_sas_kill_tasklets(hisi_hba);
3659
3660 return hisi_sas_remove(pdev);
3661 }
3662
3663 static const struct of_device_id sas_v2_of_match[] = {
3664 { .compatible = "hisilicon,hip06-sas-v2",},
3665 { .compatible = "hisilicon,hip07-sas-v2",},
3666 {},
3667 };
3668 MODULE_DEVICE_TABLE(of, sas_v2_of_match);
3669
3670 static const struct acpi_device_id sas_v2_acpi_match[] = {
3671 { "HISI0162", 0 },
3672 { }
3673 };
3674
3675 MODULE_DEVICE_TABLE(acpi, sas_v2_acpi_match);
3676
3677 static struct platform_driver hisi_sas_v2_driver = {
3678 .probe = hisi_sas_v2_probe,
3679 .remove = hisi_sas_v2_remove,
3680 .driver = {
3681 .name = DRV_NAME,
3682 .of_match_table = sas_v2_of_match,
3683 .acpi_match_table = ACPI_PTR(sas_v2_acpi_match),
3684 },
3685 };
3686
3687 module_platform_driver(hisi_sas_v2_driver);
3688
3689 MODULE_LICENSE("GPL");
3690 MODULE_AUTHOR("John Garry <john.garry@huawei.com>");
3691 MODULE_DESCRIPTION("HISILICON SAS controller v2 hw driver");
3692 MODULE_ALIAS("platform:" DRV_NAME);
Linux with added FPC-III support