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Linux 5.1.15
[linux/fpc-iii.git] / drivers / scsi / qla2xxx / qla_sup.c
blob2a3055c799fb613039fb73718ace4fd70b23886d
1 /*
2 * QLogic Fibre Channel HBA Driver
3 * Copyright (c) 2003-2014 QLogic Corporation
4 *
5 * See LICENSE.qla2xxx for copyright and licensing details.
6 */
7 #include "qla_def.h"
8
9 #include <linux/delay.h>
10 #include <linux/slab.h>
11 #include <linux/vmalloc.h>
12 #include <linux/uaccess.h>
13
14 /*
15 * NVRAM support routines
16 */
17
18 /**
19 * qla2x00_lock_nvram_access() -
20 * @ha: HA context
21 */
22 static void
23 qla2x00_lock_nvram_access(struct qla_hw_data *ha)
24 {
25 uint16_t data;
26 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
27
28 if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha)) {
29 data = RD_REG_WORD(&reg->nvram);
30 while (data & NVR_BUSY) {
31 udelay(100);
32 data = RD_REG_WORD(&reg->nvram);
33 }
34
35 /* Lock resource */
36 WRT_REG_WORD(&reg->u.isp2300.host_semaphore, 0x1);
37 RD_REG_WORD(&reg->u.isp2300.host_semaphore);
38 udelay(5);
39 data = RD_REG_WORD(&reg->u.isp2300.host_semaphore);
40 while ((data & BIT_0) == 0) {
41 /* Lock failed */
42 udelay(100);
43 WRT_REG_WORD(&reg->u.isp2300.host_semaphore, 0x1);
44 RD_REG_WORD(&reg->u.isp2300.host_semaphore);
45 udelay(5);
46 data = RD_REG_WORD(&reg->u.isp2300.host_semaphore);
47 }
48 }
49 }
50
51 /**
52 * qla2x00_unlock_nvram_access() -
53 * @ha: HA context
54 */
55 static void
56 qla2x00_unlock_nvram_access(struct qla_hw_data *ha)
57 {
58 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
59
60 if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha)) {
61 WRT_REG_WORD(&reg->u.isp2300.host_semaphore, 0);
62 RD_REG_WORD(&reg->u.isp2300.host_semaphore);
63 }
64 }
65
66 /**
67 * qla2x00_nv_write() - Prepare for NVRAM read/write operation.
68 * @ha: HA context
69 * @data: Serial interface selector
70 */
71 static void
72 qla2x00_nv_write(struct qla_hw_data *ha, uint16_t data)
73 {
74 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
75
76 WRT_REG_WORD(&reg->nvram, data | NVR_SELECT | NVR_WRT_ENABLE);
77 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
78 NVRAM_DELAY();
79 WRT_REG_WORD(&reg->nvram, data | NVR_SELECT | NVR_CLOCK |
80 NVR_WRT_ENABLE);
81 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
82 NVRAM_DELAY();
83 WRT_REG_WORD(&reg->nvram, data | NVR_SELECT | NVR_WRT_ENABLE);
84 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
85 NVRAM_DELAY();
86 }
87
88 /**
89 * qla2x00_nvram_request() - Sends read command to NVRAM and gets data from
90 * NVRAM.
91 * @ha: HA context
92 * @nv_cmd: NVRAM command
93 *
94 * Bit definitions for NVRAM command:
95 *
96 * Bit 26 = start bit
97 * Bit 25, 24 = opcode
98 * Bit 23-16 = address
99 * Bit 15-0 = write data
100 *
101 * Returns the word read from nvram @addr.
102 */
103 static uint16_t
104 qla2x00_nvram_request(struct qla_hw_data *ha, uint32_t nv_cmd)
105 {
106 uint8_t cnt;
107 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
108 uint16_t data = 0;
109 uint16_t reg_data;
110
111 /* Send command to NVRAM. */
112 nv_cmd <<= 5;
113 for (cnt = 0; cnt < 11; cnt++) {
114 if (nv_cmd & BIT_31)
115 qla2x00_nv_write(ha, NVR_DATA_OUT);
116 else
117 qla2x00_nv_write(ha, 0);
118 nv_cmd <<= 1;
119 }
120
121 /* Read data from NVRAM. */
122 for (cnt = 0; cnt < 16; cnt++) {
123 WRT_REG_WORD(&reg->nvram, NVR_SELECT | NVR_CLOCK);
124 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
125 NVRAM_DELAY();
126 data <<= 1;
127 reg_data = RD_REG_WORD(&reg->nvram);
128 if (reg_data & NVR_DATA_IN)
129 data |= BIT_0;
130 WRT_REG_WORD(&reg->nvram, NVR_SELECT);
131 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
132 NVRAM_DELAY();
133 }
134
135 /* Deselect chip. */
136 WRT_REG_WORD(&reg->nvram, NVR_DESELECT);
137 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
138 NVRAM_DELAY();
139
140 return data;
141 }
142
143
144 /**
145 * qla2x00_get_nvram_word() - Calculates word position in NVRAM and calls the
146 * request routine to get the word from NVRAM.
147 * @ha: HA context
148 * @addr: Address in NVRAM to read
149 *
150 * Returns the word read from nvram @addr.
151 */
152 static uint16_t
153 qla2x00_get_nvram_word(struct qla_hw_data *ha, uint32_t addr)
154 {
155 uint16_t data;
156 uint32_t nv_cmd;
157
158 nv_cmd = addr << 16;
159 nv_cmd |= NV_READ_OP;
160 data = qla2x00_nvram_request(ha, nv_cmd);
161
162 return (data);
163 }
164
165 /**
166 * qla2x00_nv_deselect() - Deselect NVRAM operations.
167 * @ha: HA context
168 */
169 static void
170 qla2x00_nv_deselect(struct qla_hw_data *ha)
171 {
172 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
173
174 WRT_REG_WORD(&reg->nvram, NVR_DESELECT);
175 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
176 NVRAM_DELAY();
177 }
178
179 /**
180 * qla2x00_write_nvram_word() - Write NVRAM data.
181 * @ha: HA context
182 * @addr: Address in NVRAM to write
183 * @data: word to program
184 */
185 static void
186 qla2x00_write_nvram_word(struct qla_hw_data *ha, uint32_t addr, uint16_t data)
187 {
188 int count;
189 uint16_t word;
190 uint32_t nv_cmd, wait_cnt;
191 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
192 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
193
194 qla2x00_nv_write(ha, NVR_DATA_OUT);
195 qla2x00_nv_write(ha, 0);
196 qla2x00_nv_write(ha, 0);
197
198 for (word = 0; word < 8; word++)
199 qla2x00_nv_write(ha, NVR_DATA_OUT);
200
201 qla2x00_nv_deselect(ha);
202
203 /* Write data */
204 nv_cmd = (addr << 16) | NV_WRITE_OP;
205 nv_cmd |= data;
206 nv_cmd <<= 5;
207 for (count = 0; count < 27; count++) {
208 if (nv_cmd & BIT_31)
209 qla2x00_nv_write(ha, NVR_DATA_OUT);
210 else
211 qla2x00_nv_write(ha, 0);
212
213 nv_cmd <<= 1;
214 }
215
216 qla2x00_nv_deselect(ha);
217
218 /* Wait for NVRAM to become ready */
219 WRT_REG_WORD(&reg->nvram, NVR_SELECT);
220 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
221 wait_cnt = NVR_WAIT_CNT;
222 do {
223 if (!--wait_cnt) {
224 ql_dbg(ql_dbg_user, vha, 0x708d,
225 "NVRAM didn't go ready...\n");
226 break;
227 }
228 NVRAM_DELAY();
229 word = RD_REG_WORD(&reg->nvram);
230 } while ((word & NVR_DATA_IN) == 0);
231
232 qla2x00_nv_deselect(ha);
233
234 /* Disable writes */
235 qla2x00_nv_write(ha, NVR_DATA_OUT);
236 for (count = 0; count < 10; count++)
237 qla2x00_nv_write(ha, 0);
238
239 qla2x00_nv_deselect(ha);
240 }
241
242 static int
243 qla2x00_write_nvram_word_tmo(struct qla_hw_data *ha, uint32_t addr,
244 uint16_t data, uint32_t tmo)
245 {
246 int ret, count;
247 uint16_t word;
248 uint32_t nv_cmd;
249 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
250
251 ret = QLA_SUCCESS;
252
253 qla2x00_nv_write(ha, NVR_DATA_OUT);
254 qla2x00_nv_write(ha, 0);
255 qla2x00_nv_write(ha, 0);
256
257 for (word = 0; word < 8; word++)
258 qla2x00_nv_write(ha, NVR_DATA_OUT);
259
260 qla2x00_nv_deselect(ha);
261
262 /* Write data */
263 nv_cmd = (addr << 16) | NV_WRITE_OP;
264 nv_cmd |= data;
265 nv_cmd <<= 5;
266 for (count = 0; count < 27; count++) {
267 if (nv_cmd & BIT_31)
268 qla2x00_nv_write(ha, NVR_DATA_OUT);
269 else
270 qla2x00_nv_write(ha, 0);
271
272 nv_cmd <<= 1;
273 }
274
275 qla2x00_nv_deselect(ha);
276
277 /* Wait for NVRAM to become ready */
278 WRT_REG_WORD(&reg->nvram, NVR_SELECT);
279 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
280 do {
281 NVRAM_DELAY();
282 word = RD_REG_WORD(&reg->nvram);
283 if (!--tmo) {
284 ret = QLA_FUNCTION_FAILED;
285 break;
286 }
287 } while ((word & NVR_DATA_IN) == 0);
288
289 qla2x00_nv_deselect(ha);
290
291 /* Disable writes */
292 qla2x00_nv_write(ha, NVR_DATA_OUT);
293 for (count = 0; count < 10; count++)
294 qla2x00_nv_write(ha, 0);
295
296 qla2x00_nv_deselect(ha);
297
298 return ret;
299 }
300
301 /**
302 * qla2x00_clear_nvram_protection() -
303 * @ha: HA context
304 */
305 static int
306 qla2x00_clear_nvram_protection(struct qla_hw_data *ha)
307 {
308 int ret, stat;
309 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
310 uint32_t word, wait_cnt;
311 uint16_t wprot, wprot_old;
312 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
313
314 /* Clear NVRAM write protection. */
315 ret = QLA_FUNCTION_FAILED;
316
317 wprot_old = cpu_to_le16(qla2x00_get_nvram_word(ha, ha->nvram_base));
318 stat = qla2x00_write_nvram_word_tmo(ha, ha->nvram_base,
319 cpu_to_le16(0x1234), 100000);
320 wprot = cpu_to_le16(qla2x00_get_nvram_word(ha, ha->nvram_base));
321 if (stat != QLA_SUCCESS || wprot != 0x1234) {
322 /* Write enable. */
323 qla2x00_nv_write(ha, NVR_DATA_OUT);
324 qla2x00_nv_write(ha, 0);
325 qla2x00_nv_write(ha, 0);
326 for (word = 0; word < 8; word++)
327 qla2x00_nv_write(ha, NVR_DATA_OUT);
328
329 qla2x00_nv_deselect(ha);
330
331 /* Enable protection register. */
332 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
333 qla2x00_nv_write(ha, NVR_PR_ENABLE);
334 qla2x00_nv_write(ha, NVR_PR_ENABLE);
335 for (word = 0; word < 8; word++)
336 qla2x00_nv_write(ha, NVR_DATA_OUT | NVR_PR_ENABLE);
337
338 qla2x00_nv_deselect(ha);
339
340 /* Clear protection register (ffff is cleared). */
341 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
342 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
343 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
344 for (word = 0; word < 8; word++)
345 qla2x00_nv_write(ha, NVR_DATA_OUT | NVR_PR_ENABLE);
346
347 qla2x00_nv_deselect(ha);
348
349 /* Wait for NVRAM to become ready. */
350 WRT_REG_WORD(&reg->nvram, NVR_SELECT);
351 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
352 wait_cnt = NVR_WAIT_CNT;
353 do {
354 if (!--wait_cnt) {
355 ql_dbg(ql_dbg_user, vha, 0x708e,
356 "NVRAM didn't go ready...\n");
357 break;
358 }
359 NVRAM_DELAY();
360 word = RD_REG_WORD(&reg->nvram);
361 } while ((word & NVR_DATA_IN) == 0);
362
363 if (wait_cnt)
364 ret = QLA_SUCCESS;
365 } else
366 qla2x00_write_nvram_word(ha, ha->nvram_base, wprot_old);
367
368 return ret;
369 }
370
371 static void
372 qla2x00_set_nvram_protection(struct qla_hw_data *ha, int stat)
373 {
374 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
375 uint32_t word, wait_cnt;
376 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
377
378 if (stat != QLA_SUCCESS)
379 return;
380
381 /* Set NVRAM write protection. */
382 /* Write enable. */
383 qla2x00_nv_write(ha, NVR_DATA_OUT);
384 qla2x00_nv_write(ha, 0);
385 qla2x00_nv_write(ha, 0);
386 for (word = 0; word < 8; word++)
387 qla2x00_nv_write(ha, NVR_DATA_OUT);
388
389 qla2x00_nv_deselect(ha);
390
391 /* Enable protection register. */
392 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
393 qla2x00_nv_write(ha, NVR_PR_ENABLE);
394 qla2x00_nv_write(ha, NVR_PR_ENABLE);
395 for (word = 0; word < 8; word++)
396 qla2x00_nv_write(ha, NVR_DATA_OUT | NVR_PR_ENABLE);
397
398 qla2x00_nv_deselect(ha);
399
400 /* Enable protection register. */
401 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
402 qla2x00_nv_write(ha, NVR_PR_ENABLE);
403 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
404 for (word = 0; word < 8; word++)
405 qla2x00_nv_write(ha, NVR_PR_ENABLE);
406
407 qla2x00_nv_deselect(ha);
408
409 /* Wait for NVRAM to become ready. */
410 WRT_REG_WORD(&reg->nvram, NVR_SELECT);
411 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
412 wait_cnt = NVR_WAIT_CNT;
413 do {
414 if (!--wait_cnt) {
415 ql_dbg(ql_dbg_user, vha, 0x708f,
416 "NVRAM didn't go ready...\n");
417 break;
418 }
419 NVRAM_DELAY();
420 word = RD_REG_WORD(&reg->nvram);
421 } while ((word & NVR_DATA_IN) == 0);
422 }
423
424
425 /*****************************************************************************/
426 /* Flash Manipulation Routines */
427 /*****************************************************************************/
428
429 static inline uint32_t
430 flash_conf_addr(struct qla_hw_data *ha, uint32_t faddr)
431 {
432 return ha->flash_conf_off | faddr;
433 }
434
435 static inline uint32_t
436 flash_data_addr(struct qla_hw_data *ha, uint32_t faddr)
437 {
438 return ha->flash_data_off | faddr;
439 }
440
441 static inline uint32_t
442 nvram_conf_addr(struct qla_hw_data *ha, uint32_t naddr)
443 {
444 return ha->nvram_conf_off | naddr;
445 }
446
447 static inline uint32_t
448 nvram_data_addr(struct qla_hw_data *ha, uint32_t naddr)
449 {
450 return ha->nvram_data_off | naddr;
451 }
452
453 static uint32_t
454 qla24xx_read_flash_dword(struct qla_hw_data *ha, uint32_t addr)
455 {
456 int rval;
457 uint32_t cnt, data;
458 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
459
460 WRT_REG_DWORD(&reg->flash_addr, addr & ~FARX_DATA_FLAG);
461 /* Wait for READ cycle to complete. */
462 rval = QLA_SUCCESS;
463 for (cnt = 3000;
464 (RD_REG_DWORD(&reg->flash_addr) & FARX_DATA_FLAG) == 0 &&
465 rval == QLA_SUCCESS; cnt--) {
466 if (cnt)
467 udelay(10);
468 else
469 rval = QLA_FUNCTION_TIMEOUT;
470 cond_resched();
471 }
472
473 /* TODO: What happens if we time out? */
474 data = 0xDEADDEAD;
475 if (rval == QLA_SUCCESS)
476 data = RD_REG_DWORD(&reg->flash_data);
477
478 return data;
479 }
480
481 uint32_t *
482 qla24xx_read_flash_data(scsi_qla_host_t *vha, uint32_t *dwptr, uint32_t faddr,
483 uint32_t dwords)
484 {
485 uint32_t i;
486 struct qla_hw_data *ha = vha->hw;
487
488 /* Dword reads to flash. */
489 for (i = 0; i < dwords; i++, faddr++)
490 dwptr[i] = cpu_to_le32(qla24xx_read_flash_dword(ha,
491 flash_data_addr(ha, faddr)));
492
493 return dwptr;
494 }
495
496 static int
497 qla24xx_write_flash_dword(struct qla_hw_data *ha, uint32_t addr, uint32_t data)
498 {
499 int rval;
500 uint32_t cnt;
501 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
502
503 WRT_REG_DWORD(&reg->flash_data, data);
504 RD_REG_DWORD(&reg->flash_data); /* PCI Posting. */
505 WRT_REG_DWORD(&reg->flash_addr, addr | FARX_DATA_FLAG);
506 /* Wait for Write cycle to complete. */
507 rval = QLA_SUCCESS;
508 for (cnt = 500000; (RD_REG_DWORD(&reg->flash_addr) & FARX_DATA_FLAG) &&
509 rval == QLA_SUCCESS; cnt--) {
510 if (cnt)
511 udelay(10);
512 else
513 rval = QLA_FUNCTION_TIMEOUT;
514 cond_resched();
515 }
516 return rval;
517 }
518
519 static void
520 qla24xx_get_flash_manufacturer(struct qla_hw_data *ha, uint8_t *man_id,
521 uint8_t *flash_id)
522 {
523 uint32_t ids;
524
525 ids = qla24xx_read_flash_dword(ha, flash_conf_addr(ha, 0x03ab));
526 *man_id = LSB(ids);
527 *flash_id = MSB(ids);
528
529 /* Check if man_id and flash_id are valid. */
530 if (ids != 0xDEADDEAD && (*man_id == 0 || *flash_id == 0)) {
531 /* Read information using 0x9f opcode
532 * Device ID, Mfg ID would be read in the format:
533 * <Ext Dev Info><Device ID Part2><Device ID Part 1><Mfg ID>
534 * Example: ATMEL 0x00 01 45 1F
535 * Extract MFG and Dev ID from last two bytes.
536 */
537 ids = qla24xx_read_flash_dword(ha, flash_conf_addr(ha, 0x009f));
538 *man_id = LSB(ids);
539 *flash_id = MSB(ids);
540 }
541 }
542
543 static int
544 qla2xxx_find_flt_start(scsi_qla_host_t *vha, uint32_t *start)
545 {
546 const char *loc, *locations[] = { "DEF", "PCI" };
547 uint32_t pcihdr, pcids;
548 uint32_t *dcode;
549 uint8_t *buf, *bcode, last_image;
550 uint16_t cnt, chksum, *wptr;
551 struct qla_flt_location *fltl;
552 struct qla_hw_data *ha = vha->hw;
553 struct req_que *req = ha->req_q_map[0];
554
555 /*
556 * FLT-location structure resides after the last PCI region.
557 */
558
559 /* Begin with sane defaults. */
560 loc = locations[0];
561 *start = 0;
562 if (IS_QLA24XX_TYPE(ha))
563 *start = FA_FLASH_LAYOUT_ADDR_24;
564 else if (IS_QLA25XX(ha))
565 *start = FA_FLASH_LAYOUT_ADDR;
566 else if (IS_QLA81XX(ha))
567 *start = FA_FLASH_LAYOUT_ADDR_81;
568 else if (IS_P3P_TYPE(ha)) {
569 *start = FA_FLASH_LAYOUT_ADDR_82;
570 goto end;
571 } else if (IS_QLA83XX(ha) || IS_QLA27XX(ha)) {
572 *start = FA_FLASH_LAYOUT_ADDR_83;
573 goto end;
574 }
575 /* Begin with first PCI expansion ROM header. */
576 buf = (uint8_t *)req->ring;
577 dcode = (uint32_t *)req->ring;
578 pcihdr = 0;
579 last_image = 1;
580 do {
581 /* Verify PCI expansion ROM header. */
582 qla24xx_read_flash_data(vha, dcode, pcihdr >> 2, 0x20);
583 bcode = buf + (pcihdr % 4);
584 if (bcode[0x0] != 0x55 || bcode[0x1] != 0xaa)
585 goto end;
586
587 /* Locate PCI data structure. */
588 pcids = pcihdr + ((bcode[0x19] << 8) | bcode[0x18]);
589 qla24xx_read_flash_data(vha, dcode, pcids >> 2, 0x20);
590 bcode = buf + (pcihdr % 4);
591
592 /* Validate signature of PCI data structure. */
593 if (bcode[0x0] != 'P' || bcode[0x1] != 'C' ||
594 bcode[0x2] != 'I' || bcode[0x3] != 'R')
595 goto end;
596
597 last_image = bcode[0x15] & BIT_7;
598
599 /* Locate next PCI expansion ROM. */
600 pcihdr += ((bcode[0x11] << 8) | bcode[0x10]) * 512;
601 } while (!last_image);
602
603 /* Now verify FLT-location structure. */
604 fltl = (struct qla_flt_location *)req->ring;
605 qla24xx_read_flash_data(vha, dcode, pcihdr >> 2,
606 sizeof(struct qla_flt_location) >> 2);
607 if (fltl->sig[0] != 'Q' || fltl->sig[1] != 'F' ||
608 fltl->sig[2] != 'L' || fltl->sig[3] != 'T')
609 goto end;
610
611 wptr = (uint16_t *)req->ring;
612 cnt = sizeof(struct qla_flt_location) >> 1;
613 for (chksum = 0; cnt--; wptr++)
614 chksum += le16_to_cpu(*wptr);
615 if (chksum) {
616 ql_log(ql_log_fatal, vha, 0x0045,
617 "Inconsistent FLTL detected: checksum=0x%x.\n", chksum);
618 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x010e,
619 buf, sizeof(struct qla_flt_location));
620 return QLA_FUNCTION_FAILED;
621 }
622
623 /* Good data. Use specified location. */
624 loc = locations[1];
625 *start = (le16_to_cpu(fltl->start_hi) << 16 |
626 le16_to_cpu(fltl->start_lo)) >> 2;
627 end:
628 ql_dbg(ql_dbg_init, vha, 0x0046,
629 "FLTL[%s] = 0x%x.\n",
630 loc, *start);
631 return QLA_SUCCESS;
632 }
633
634 static void
635 qla2xxx_get_flt_info(scsi_qla_host_t *vha, uint32_t flt_addr)
636 {
637 const char *loc, *locations[] = { "DEF", "FLT" };
638 const uint32_t def_fw[] =
639 { FA_RISC_CODE_ADDR, FA_RISC_CODE_ADDR, FA_RISC_CODE_ADDR_81 };
640 const uint32_t def_boot[] =
641 { FA_BOOT_CODE_ADDR, FA_BOOT_CODE_ADDR, FA_BOOT_CODE_ADDR_81 };
642 const uint32_t def_vpd_nvram[] =
643 { FA_VPD_NVRAM_ADDR, FA_VPD_NVRAM_ADDR, FA_VPD_NVRAM_ADDR_81 };
644 const uint32_t def_vpd0[] =
645 { 0, 0, FA_VPD0_ADDR_81 };
646 const uint32_t def_vpd1[] =
647 { 0, 0, FA_VPD1_ADDR_81 };
648 const uint32_t def_nvram0[] =
649 { 0, 0, FA_NVRAM0_ADDR_81 };
650 const uint32_t def_nvram1[] =
651 { 0, 0, FA_NVRAM1_ADDR_81 };
652 const uint32_t def_fdt[] =
653 { FA_FLASH_DESCR_ADDR_24, FA_FLASH_DESCR_ADDR,
654 FA_FLASH_DESCR_ADDR_81 };
655 const uint32_t def_npiv_conf0[] =
656 { FA_NPIV_CONF0_ADDR_24, FA_NPIV_CONF0_ADDR,
657 FA_NPIV_CONF0_ADDR_81 };
658 const uint32_t def_npiv_conf1[] =
659 { FA_NPIV_CONF1_ADDR_24, FA_NPIV_CONF1_ADDR,
660 FA_NPIV_CONF1_ADDR_81 };
661 const uint32_t fcp_prio_cfg0[] =
662 { FA_FCP_PRIO0_ADDR, FA_FCP_PRIO0_ADDR_25,
663 0 };
664 const uint32_t fcp_prio_cfg1[] =
665 { FA_FCP_PRIO1_ADDR, FA_FCP_PRIO1_ADDR_25,
666 0 };
667 uint32_t def;
668 uint16_t *wptr;
669 uint16_t cnt, chksum;
670 uint32_t start;
671 struct qla_flt_header *flt;
672 struct qla_flt_region *region;
673 struct qla_hw_data *ha = vha->hw;
674 struct req_que *req = ha->req_q_map[0];
675
676 def = 0;
677 if (IS_QLA25XX(ha))
678 def = 1;
679 else if (IS_QLA81XX(ha))
680 def = 2;
681
682 /* Assign FCP prio region since older adapters may not have FLT, or
683 FCP prio region in it's FLT.
684 */
685 ha->flt_region_fcp_prio = (ha->port_no == 0) ?
686 fcp_prio_cfg0[def] : fcp_prio_cfg1[def];
687
688 ha->flt_region_flt = flt_addr;
689 wptr = (uint16_t *)req->ring;
690 flt = (struct qla_flt_header *)req->ring;
691 region = (struct qla_flt_region *)&flt[1];
692 ha->isp_ops->read_optrom(vha, (uint8_t *)req->ring,
693 flt_addr << 2, OPTROM_BURST_SIZE);
694 if (*wptr == cpu_to_le16(0xffff))
695 goto no_flash_data;
696 if (flt->version != cpu_to_le16(1)) {
697 ql_log(ql_log_warn, vha, 0x0047,
698 "Unsupported FLT detected: version=0x%x length=0x%x checksum=0x%x.\n",
699 le16_to_cpu(flt->version), le16_to_cpu(flt->length),
700 le16_to_cpu(flt->checksum));
701 goto no_flash_data;
702 }
703
704 cnt = (sizeof(struct qla_flt_header) + le16_to_cpu(flt->length)) >> 1;
705 for (chksum = 0; cnt--; wptr++)
706 chksum += le16_to_cpu(*wptr);
707 if (chksum) {
708 ql_log(ql_log_fatal, vha, 0x0048,
709 "Inconsistent FLT detected: version=0x%x length=0x%x checksum=0x%x.\n",
710 le16_to_cpu(flt->version), le16_to_cpu(flt->length),
711 le16_to_cpu(flt->checksum));
712 goto no_flash_data;
713 }
714
715 loc = locations[1];
716 cnt = le16_to_cpu(flt->length) / sizeof(struct qla_flt_region);
717 for ( ; cnt; cnt--, region++) {
718 /* Store addresses as DWORD offsets. */
719 start = le32_to_cpu(region->start) >> 2;
720 ql_dbg(ql_dbg_init, vha, 0x0049,
721 "FLT[%02x]: start=0x%x "
722 "end=0x%x size=0x%x.\n", le32_to_cpu(region->code) & 0xff,
723 start, le32_to_cpu(region->end) >> 2,
724 le32_to_cpu(region->size));
725
726 switch (le32_to_cpu(region->code) & 0xff) {
727 case FLT_REG_FCOE_FW:
728 if (!IS_QLA8031(ha))
729 break;
730 ha->flt_region_fw = start;
731 break;
732 case FLT_REG_FW:
733 if (IS_QLA8031(ha))
734 break;
735 ha->flt_region_fw = start;
736 break;
737 case FLT_REG_BOOT_CODE:
738 ha->flt_region_boot = start;
739 break;
740 case FLT_REG_VPD_0:
741 if (IS_QLA8031(ha))
742 break;
743 ha->flt_region_vpd_nvram = start;
744 if (IS_P3P_TYPE(ha))
745 break;
746 if (ha->port_no == 0)
747 ha->flt_region_vpd = start;
748 break;
749 case FLT_REG_VPD_1:
750 if (IS_P3P_TYPE(ha) || IS_QLA8031(ha))
751 break;
752 if (ha->port_no == 1)
753 ha->flt_region_vpd = start;
754 break;
755 case FLT_REG_VPD_2:
756 if (!IS_QLA27XX(ha))
757 break;
758 if (ha->port_no == 2)
759 ha->flt_region_vpd = start;
760 break;
761 case FLT_REG_VPD_3:
762 if (!IS_QLA27XX(ha))
763 break;
764 if (ha->port_no == 3)
765 ha->flt_region_vpd = start;
766 break;
767 case FLT_REG_NVRAM_0:
768 if (IS_QLA8031(ha))
769 break;
770 if (ha->port_no == 0)
771 ha->flt_region_nvram = start;
772 break;
773 case FLT_REG_NVRAM_1:
774 if (IS_QLA8031(ha))
775 break;
776 if (ha->port_no == 1)
777 ha->flt_region_nvram = start;
778 break;
779 case FLT_REG_NVRAM_2:
780 if (!IS_QLA27XX(ha))
781 break;
782 if (ha->port_no == 2)
783 ha->flt_region_nvram = start;
784 break;
785 case FLT_REG_NVRAM_3:
786 if (!IS_QLA27XX(ha))
787 break;
788 if (ha->port_no == 3)
789 ha->flt_region_nvram = start;
790 break;
791 case FLT_REG_FDT:
792 ha->flt_region_fdt = start;
793 break;
794 case FLT_REG_NPIV_CONF_0:
795 if (ha->port_no == 0)
796 ha->flt_region_npiv_conf = start;
797 break;
798 case FLT_REG_NPIV_CONF_1:
799 if (ha->port_no == 1)
800 ha->flt_region_npiv_conf = start;
801 break;
802 case FLT_REG_GOLD_FW:
803 ha->flt_region_gold_fw = start;
804 break;
805 case FLT_REG_FCP_PRIO_0:
806 if (ha->port_no == 0)
807 ha->flt_region_fcp_prio = start;
808 break;
809 case FLT_REG_FCP_PRIO_1:
810 if (ha->port_no == 1)
811 ha->flt_region_fcp_prio = start;
812 break;
813 case FLT_REG_BOOT_CODE_82XX:
814 ha->flt_region_boot = start;
815 break;
816 case FLT_REG_BOOT_CODE_8044:
817 if (IS_QLA8044(ha))
818 ha->flt_region_boot = start;
819 break;
820 case FLT_REG_FW_82XX:
821 ha->flt_region_fw = start;
822 break;
823 case FLT_REG_CNA_FW:
824 if (IS_CNA_CAPABLE(ha))
825 ha->flt_region_fw = start;
826 break;
827 case FLT_REG_GOLD_FW_82XX:
828 ha->flt_region_gold_fw = start;
829 break;
830 case FLT_REG_BOOTLOAD_82XX:
831 ha->flt_region_bootload = start;
832 break;
833 case FLT_REG_VPD_8XXX:
834 if (IS_CNA_CAPABLE(ha))
835 ha->flt_region_vpd = start;
836 break;
837 case FLT_REG_FCOE_NVRAM_0:
838 if (!(IS_QLA8031(ha) || IS_QLA8044(ha)))
839 break;
840 if (ha->port_no == 0)
841 ha->flt_region_nvram = start;
842 break;
843 case FLT_REG_FCOE_NVRAM_1:
844 if (!(IS_QLA8031(ha) || IS_QLA8044(ha)))
845 break;
846 if (ha->port_no == 1)
847 ha->flt_region_nvram = start;
848 break;
849 case FLT_REG_IMG_PRI_27XX:
850 if (IS_QLA27XX(ha))
851 ha->flt_region_img_status_pri = start;
852 break;
853 case FLT_REG_IMG_SEC_27XX:
854 if (IS_QLA27XX(ha))
855 ha->flt_region_img_status_sec = start;
856 break;
857 case FLT_REG_FW_SEC_27XX:
858 if (IS_QLA27XX(ha))
859 ha->flt_region_fw_sec = start;
860 break;
861 case FLT_REG_BOOTLOAD_SEC_27XX:
862 if (IS_QLA27XX(ha))
863 ha->flt_region_boot_sec = start;
864 break;
865 case FLT_REG_VPD_SEC_27XX_0:
866 if (IS_QLA27XX(ha))
867 ha->flt_region_vpd_sec = start;
868 break;
869 case FLT_REG_VPD_SEC_27XX_1:
870 if (IS_QLA27XX(ha))
871 ha->flt_region_vpd_sec = start;
872 break;
873 case FLT_REG_VPD_SEC_27XX_2:
874 if (IS_QLA27XX(ha))
875 ha->flt_region_vpd_sec = start;
876 break;
877 case FLT_REG_VPD_SEC_27XX_3:
878 if (IS_QLA27XX(ha))
879 ha->flt_region_vpd_sec = start;
880 break;
881 }
882 }
883 goto done;
884
885 no_flash_data:
886 /* Use hardcoded defaults. */
887 loc = locations[0];
888 ha->flt_region_fw = def_fw[def];
889 ha->flt_region_boot = def_boot[def];
890 ha->flt_region_vpd_nvram = def_vpd_nvram[def];
891 ha->flt_region_vpd = (ha->port_no == 0) ?
892 def_vpd0[def] : def_vpd1[def];
893 ha->flt_region_nvram = (ha->port_no == 0) ?
894 def_nvram0[def] : def_nvram1[def];
895 ha->flt_region_fdt = def_fdt[def];
896 ha->flt_region_npiv_conf = (ha->port_no == 0) ?
897 def_npiv_conf0[def] : def_npiv_conf1[def];
898 done:
899 ql_dbg(ql_dbg_init, vha, 0x004a,
900 "FLT[%s]: boot=0x%x fw=0x%x vpd_nvram=0x%x vpd=0x%x nvram=0x%x "
901 "fdt=0x%x flt=0x%x npiv=0x%x fcp_prif_cfg=0x%x.\n",
902 loc, ha->flt_region_boot, ha->flt_region_fw,
903 ha->flt_region_vpd_nvram, ha->flt_region_vpd, ha->flt_region_nvram,
904 ha->flt_region_fdt, ha->flt_region_flt, ha->flt_region_npiv_conf,
905 ha->flt_region_fcp_prio);
906 }
907
908 static void
909 qla2xxx_get_fdt_info(scsi_qla_host_t *vha)
910 {
911 #define FLASH_BLK_SIZE_4K 0x1000
912 #define FLASH_BLK_SIZE_32K 0x8000
913 #define FLASH_BLK_SIZE_64K 0x10000
914 const char *loc, *locations[] = { "MID", "FDT" };
915 uint16_t cnt, chksum;
916 uint16_t *wptr;
917 struct qla_fdt_layout *fdt;
918 uint8_t man_id, flash_id;
919 uint16_t mid = 0, fid = 0;
920 struct qla_hw_data *ha = vha->hw;
921 struct req_que *req = ha->req_q_map[0];
922
923 wptr = (uint16_t *)req->ring;
924 fdt = (struct qla_fdt_layout *)req->ring;
925 ha->isp_ops->read_optrom(vha, (uint8_t *)req->ring,
926 ha->flt_region_fdt << 2, OPTROM_BURST_SIZE);
927 if (*wptr == cpu_to_le16(0xffff))
928 goto no_flash_data;
929 if (fdt->sig[0] != 'Q' || fdt->sig[1] != 'L' || fdt->sig[2] != 'I' ||
930 fdt->sig[3] != 'D')
931 goto no_flash_data;
932
933 for (cnt = 0, chksum = 0; cnt < sizeof(*fdt) >> 1; cnt++, wptr++)
934 chksum += le16_to_cpu(*wptr);
935 if (chksum) {
936 ql_dbg(ql_dbg_init, vha, 0x004c,
937 "Inconsistent FDT detected:"
938 " checksum=0x%x id=%c version0x%x.\n", chksum,
939 fdt->sig[0], le16_to_cpu(fdt->version));
940 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0113,
941 (uint8_t *)fdt, sizeof(*fdt));
942 goto no_flash_data;
943 }
944
945 loc = locations[1];
946 mid = le16_to_cpu(fdt->man_id);
947 fid = le16_to_cpu(fdt->id);
948 ha->fdt_wrt_disable = fdt->wrt_disable_bits;
949 ha->fdt_wrt_enable = fdt->wrt_enable_bits;
950 ha->fdt_wrt_sts_reg_cmd = fdt->wrt_sts_reg_cmd;
951 if (IS_QLA8044(ha))
952 ha->fdt_erase_cmd = fdt->erase_cmd;
953 else
954 ha->fdt_erase_cmd =
955 flash_conf_addr(ha, 0x0300 | fdt->erase_cmd);
956 ha->fdt_block_size = le32_to_cpu(fdt->block_size);
957 if (fdt->unprotect_sec_cmd) {
958 ha->fdt_unprotect_sec_cmd = flash_conf_addr(ha, 0x0300 |
959 fdt->unprotect_sec_cmd);
960 ha->fdt_protect_sec_cmd = fdt->protect_sec_cmd ?
961 flash_conf_addr(ha, 0x0300 | fdt->protect_sec_cmd):
962 flash_conf_addr(ha, 0x0336);
963 }
964 goto done;
965 no_flash_data:
966 loc = locations[0];
967 if (IS_P3P_TYPE(ha)) {
968 ha->fdt_block_size = FLASH_BLK_SIZE_64K;
969 goto done;
970 }
971 qla24xx_get_flash_manufacturer(ha, &man_id, &flash_id);
972 mid = man_id;
973 fid = flash_id;
974 ha->fdt_wrt_disable = 0x9c;
975 ha->fdt_erase_cmd = flash_conf_addr(ha, 0x03d8);
976 switch (man_id) {
977 case 0xbf: /* STT flash. */
978 if (flash_id == 0x8e)
979 ha->fdt_block_size = FLASH_BLK_SIZE_64K;
980 else
981 ha->fdt_block_size = FLASH_BLK_SIZE_32K;
982
983 if (flash_id == 0x80)
984 ha->fdt_erase_cmd = flash_conf_addr(ha, 0x0352);
985 break;
986 case 0x13: /* ST M25P80. */
987 ha->fdt_block_size = FLASH_BLK_SIZE_64K;
988 break;
989 case 0x1f: /* Atmel 26DF081A. */
990 ha->fdt_block_size = FLASH_BLK_SIZE_4K;
991 ha->fdt_erase_cmd = flash_conf_addr(ha, 0x0320);
992 ha->fdt_unprotect_sec_cmd = flash_conf_addr(ha, 0x0339);
993 ha->fdt_protect_sec_cmd = flash_conf_addr(ha, 0x0336);
994 break;
995 default:
996 /* Default to 64 kb sector size. */
997 ha->fdt_block_size = FLASH_BLK_SIZE_64K;
998 break;
999 }
1000 done:
1001 ql_dbg(ql_dbg_init, vha, 0x004d,
1002 "FDT[%s]: (0x%x/0x%x) erase=0x%x "
1003 "pr=%x wrtd=0x%x blk=0x%x.\n",
1004 loc, mid, fid,
1005 ha->fdt_erase_cmd, ha->fdt_protect_sec_cmd,
1006 ha->fdt_wrt_disable, ha->fdt_block_size);
1007
1008 }
1009
1010 static void
1011 qla2xxx_get_idc_param(scsi_qla_host_t *vha)
1012 {
1013 #define QLA82XX_IDC_PARAM_ADDR 0x003e885c
1014 uint32_t *wptr;
1015 struct qla_hw_data *ha = vha->hw;
1016 struct req_que *req = ha->req_q_map[0];
1017
1018 if (!(IS_P3P_TYPE(ha)))
1019 return;
1020
1021 wptr = (uint32_t *)req->ring;
1022 ha->isp_ops->read_optrom(vha, (uint8_t *)req->ring,
1023 QLA82XX_IDC_PARAM_ADDR , 8);
1024
1025 if (*wptr == cpu_to_le32(0xffffffff)) {
1026 ha->fcoe_dev_init_timeout = QLA82XX_ROM_DEV_INIT_TIMEOUT;
1027 ha->fcoe_reset_timeout = QLA82XX_ROM_DRV_RESET_ACK_TIMEOUT;
1028 } else {
1029 ha->fcoe_dev_init_timeout = le32_to_cpu(*wptr);
1030 wptr++;
1031 ha->fcoe_reset_timeout = le32_to_cpu(*wptr);
1032 }
1033 ql_dbg(ql_dbg_init, vha, 0x004e,
1034 "fcoe_dev_init_timeout=%d "
1035 "fcoe_reset_timeout=%d.\n", ha->fcoe_dev_init_timeout,
1036 ha->fcoe_reset_timeout);
1037 return;
1038 }
1039
1040 int
1041 qla2xxx_get_flash_info(scsi_qla_host_t *vha)
1042 {
1043 int ret;
1044 uint32_t flt_addr;
1045 struct qla_hw_data *ha = vha->hw;
1046
1047 if (!IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha) &&
1048 !IS_CNA_CAPABLE(ha) && !IS_QLA2031(ha) && !IS_QLA27XX(ha))
1049 return QLA_SUCCESS;
1050
1051 ret = qla2xxx_find_flt_start(vha, &flt_addr);
1052 if (ret != QLA_SUCCESS)
1053 return ret;
1054
1055 qla2xxx_get_flt_info(vha, flt_addr);
1056 qla2xxx_get_fdt_info(vha);
1057 qla2xxx_get_idc_param(vha);
1058
1059 return QLA_SUCCESS;
1060 }
1061
1062 void
1063 qla2xxx_flash_npiv_conf(scsi_qla_host_t *vha)
1064 {
1065 #define NPIV_CONFIG_SIZE (16*1024)
1066 void *data;
1067 uint16_t *wptr;
1068 uint16_t cnt, chksum;
1069 int i;
1070 struct qla_npiv_header hdr;
1071 struct qla_npiv_entry *entry;
1072 struct qla_hw_data *ha = vha->hw;
1073
1074 if (!IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha) &&
1075 !IS_CNA_CAPABLE(ha) && !IS_QLA2031(ha))
1076 return;
1077
1078 if (ha->flags.nic_core_reset_hdlr_active)
1079 return;
1080
1081 if (IS_QLA8044(ha))
1082 return;
1083
1084 ha->isp_ops->read_optrom(vha, (uint8_t *)&hdr,
1085 ha->flt_region_npiv_conf << 2, sizeof(struct qla_npiv_header));
1086 if (hdr.version == cpu_to_le16(0xffff))
1087 return;
1088 if (hdr.version != cpu_to_le16(1)) {
1089 ql_dbg(ql_dbg_user, vha, 0x7090,
1090 "Unsupported NPIV-Config "
1091 "detected: version=0x%x entries=0x%x checksum=0x%x.\n",
1092 le16_to_cpu(hdr.version), le16_to_cpu(hdr.entries),
1093 le16_to_cpu(hdr.checksum));
1094 return;
1095 }
1096
1097 data = kmalloc(NPIV_CONFIG_SIZE, GFP_KERNEL);
1098 if (!data) {
1099 ql_log(ql_log_warn, vha, 0x7091,
1100 "Unable to allocate memory for data.\n");
1101 return;
1102 }
1103
1104 ha->isp_ops->read_optrom(vha, (uint8_t *)data,
1105 ha->flt_region_npiv_conf << 2, NPIV_CONFIG_SIZE);
1106
1107 cnt = (sizeof(hdr) + le16_to_cpu(hdr.entries) * sizeof(*entry)) >> 1;
1108 for (wptr = data, chksum = 0; cnt--; wptr++)
1109 chksum += le16_to_cpu(*wptr);
1110 if (chksum) {
1111 ql_dbg(ql_dbg_user, vha, 0x7092,
1112 "Inconsistent NPIV-Config "
1113 "detected: version=0x%x entries=0x%x checksum=0x%x.\n",
1114 le16_to_cpu(hdr.version), le16_to_cpu(hdr.entries),
1115 le16_to_cpu(hdr.checksum));
1116 goto done;
1117 }
1118
1119 entry = data + sizeof(struct qla_npiv_header);
1120 cnt = le16_to_cpu(hdr.entries);
1121 for (i = 0; cnt; cnt--, entry++, i++) {
1122 uint16_t flags;
1123 struct fc_vport_identifiers vid;
1124 struct fc_vport *vport;
1125
1126 memcpy(&ha->npiv_info[i], entry, sizeof(struct qla_npiv_entry));
1127
1128 flags = le16_to_cpu(entry->flags);
1129 if (flags == 0xffff)
1130 continue;
1131 if ((flags & BIT_0) == 0)
1132 continue;
1133
1134 memset(&vid, 0, sizeof(vid));
1135 vid.roles = FC_PORT_ROLE_FCP_INITIATOR;
1136 vid.vport_type = FC_PORTTYPE_NPIV;
1137 vid.disable = false;
1138 vid.port_name = wwn_to_u64(entry->port_name);
1139 vid.node_name = wwn_to_u64(entry->node_name);
1140
1141 ql_dbg(ql_dbg_user, vha, 0x7093,
1142 "NPIV[%02x]: wwpn=%llx "
1143 "wwnn=%llx vf_id=0x%x Q_qos=0x%x F_qos=0x%x.\n", cnt,
1144 (unsigned long long)vid.port_name,
1145 (unsigned long long)vid.node_name,
1146 le16_to_cpu(entry->vf_id),
1147 entry->q_qos, entry->f_qos);
1148
1149 if (i < QLA_PRECONFIG_VPORTS) {
1150 vport = fc_vport_create(vha->host, 0, &vid);
1151 if (!vport)
1152 ql_log(ql_log_warn, vha, 0x7094,
1153 "NPIV-Config Failed to create vport [%02x]: "
1154 "wwpn=%llx wwnn=%llx.\n", cnt,
1155 (unsigned long long)vid.port_name,
1156 (unsigned long long)vid.node_name);
1157 }
1158 }
1159 done:
1160 kfree(data);
1161 }
1162
1163 static int
1164 qla24xx_unprotect_flash(scsi_qla_host_t *vha)
1165 {
1166 struct qla_hw_data *ha = vha->hw;
1167 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1168
1169 if (ha->flags.fac_supported)
1170 return qla81xx_fac_do_write_enable(vha, 1);
1171
1172 /* Enable flash write. */
1173 WRT_REG_DWORD(&reg->ctrl_status,
1174 RD_REG_DWORD(&reg->ctrl_status) | CSRX_FLASH_ENABLE);
1175 RD_REG_DWORD(&reg->ctrl_status); /* PCI Posting. */
1176
1177 if (!ha->fdt_wrt_disable)
1178 goto done;
1179
1180 /* Disable flash write-protection, first clear SR protection bit */
1181 qla24xx_write_flash_dword(ha, flash_conf_addr(ha, 0x101), 0);
1182 /* Then write zero again to clear remaining SR bits.*/
1183 qla24xx_write_flash_dword(ha, flash_conf_addr(ha, 0x101), 0);
1184 done:
1185 return QLA_SUCCESS;
1186 }
1187
1188 static int
1189 qla24xx_protect_flash(scsi_qla_host_t *vha)
1190 {
1191 uint32_t cnt;
1192 struct qla_hw_data *ha = vha->hw;
1193 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1194
1195 if (ha->flags.fac_supported)
1196 return qla81xx_fac_do_write_enable(vha, 0);
1197
1198 if (!ha->fdt_wrt_disable)
1199 goto skip_wrt_protect;
1200
1201 /* Enable flash write-protection and wait for completion. */
1202 qla24xx_write_flash_dword(ha, flash_conf_addr(ha, 0x101),
1203 ha->fdt_wrt_disable);
1204 for (cnt = 300; cnt &&
1205 qla24xx_read_flash_dword(ha, flash_conf_addr(ha, 0x005)) & BIT_0;
1206 cnt--) {
1207 udelay(10);
1208 }
1209
1210 skip_wrt_protect:
1211 /* Disable flash write. */
1212 WRT_REG_DWORD(&reg->ctrl_status,
1213 RD_REG_DWORD(&reg->ctrl_status) & ~CSRX_FLASH_ENABLE);
1214 RD_REG_DWORD(&reg->ctrl_status); /* PCI Posting. */
1215
1216 return QLA_SUCCESS;
1217 }
1218
1219 static int
1220 qla24xx_erase_sector(scsi_qla_host_t *vha, uint32_t fdata)
1221 {
1222 struct qla_hw_data *ha = vha->hw;
1223 uint32_t start, finish;
1224
1225 if (ha->flags.fac_supported) {
1226 start = fdata >> 2;
1227 finish = start + (ha->fdt_block_size >> 2) - 1;
1228 return qla81xx_fac_erase_sector(vha, flash_data_addr(ha,
1229 start), flash_data_addr(ha, finish));
1230 }
1231
1232 return qla24xx_write_flash_dword(ha, ha->fdt_erase_cmd,
1233 (fdata & 0xff00) | ((fdata << 16) & 0xff0000) |
1234 ((fdata >> 16) & 0xff));
1235 }
1236
1237 static int
1238 qla24xx_write_flash_data(scsi_qla_host_t *vha, uint32_t *dwptr, uint32_t faddr,
1239 uint32_t dwords)
1240 {
1241 int ret;
1242 uint32_t liter;
1243 uint32_t sec_mask, rest_addr;
1244 uint32_t fdata;
1245 dma_addr_t optrom_dma;
1246 void *optrom = NULL;
1247 struct qla_hw_data *ha = vha->hw;
1248
1249 /* Prepare burst-capable write on supported ISPs. */
1250 if ((IS_QLA25XX(ha) || IS_QLA81XX(ha) || IS_QLA83XX(ha) ||
1251 IS_QLA27XX(ha)) &&
1252 !(faddr & 0xfff) && dwords > OPTROM_BURST_DWORDS) {
1253 optrom = dma_alloc_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE,
1254 &optrom_dma, GFP_KERNEL);
1255 if (!optrom) {
1256 ql_log(ql_log_warn, vha, 0x7095,
1257 "Unable to allocate "
1258 "memory for optrom burst write (%x KB).\n",
1259 OPTROM_BURST_SIZE / 1024);
1260 }
1261 }
1262
1263 rest_addr = (ha->fdt_block_size >> 2) - 1;
1264 sec_mask = ~rest_addr;
1265
1266 ret = qla24xx_unprotect_flash(vha);
1267 if (ret != QLA_SUCCESS) {
1268 ql_log(ql_log_warn, vha, 0x7096,
1269 "Unable to unprotect flash for update.\n");
1270 goto done;
1271 }
1272
1273 for (liter = 0; liter < dwords; liter++, faddr++, dwptr++) {
1274 fdata = (faddr & sec_mask) << 2;
1275
1276 /* Are we at the beginning of a sector? */
1277 if ((faddr & rest_addr) == 0) {
1278 /* Do sector unprotect. */
1279 if (ha->fdt_unprotect_sec_cmd)
1280 qla24xx_write_flash_dword(ha,
1281 ha->fdt_unprotect_sec_cmd,
1282 (fdata & 0xff00) | ((fdata << 16) &
1283 0xff0000) | ((fdata >> 16) & 0xff));
1284 ret = qla24xx_erase_sector(vha, fdata);
1285 if (ret != QLA_SUCCESS) {
1286 ql_dbg(ql_dbg_user, vha, 0x7007,
1287 "Unable to erase erase sector: address=%x.\n",
1288 faddr);
1289 break;
1290 }
1291 }
1292
1293 /* Go with burst-write. */
1294 if (optrom && (liter + OPTROM_BURST_DWORDS) <= dwords) {
1295 /* Copy data to DMA'ble buffer. */
1296 memcpy(optrom, dwptr, OPTROM_BURST_SIZE);
1297
1298 ret = qla2x00_load_ram(vha, optrom_dma,
1299 flash_data_addr(ha, faddr),
1300 OPTROM_BURST_DWORDS);
1301 if (ret != QLA_SUCCESS) {
1302 ql_log(ql_log_warn, vha, 0x7097,
1303 "Unable to burst-write optrom segment "
1304 "(%x/%x/%llx).\n", ret,
1305 flash_data_addr(ha, faddr),
1306 (unsigned long long)optrom_dma);
1307 ql_log(ql_log_warn, vha, 0x7098,
1308 "Reverting to slow-write.\n");
1309
1310 dma_free_coherent(&ha->pdev->dev,
1311 OPTROM_BURST_SIZE, optrom, optrom_dma);
1312 optrom = NULL;
1313 } else {
1314 liter += OPTROM_BURST_DWORDS - 1;
1315 faddr += OPTROM_BURST_DWORDS - 1;
1316 dwptr += OPTROM_BURST_DWORDS - 1;
1317 continue;
1318 }
1319 }
1320
1321 ret = qla24xx_write_flash_dword(ha,
1322 flash_data_addr(ha, faddr), cpu_to_le32(*dwptr));
1323 if (ret != QLA_SUCCESS) {
1324 ql_dbg(ql_dbg_user, vha, 0x7006,
1325 "Unable to program flash address=%x data=%x.\n",
1326 faddr, *dwptr);
1327 break;
1328 }
1329
1330 /* Do sector protect. */
1331 if (ha->fdt_unprotect_sec_cmd &&
1332 ((faddr & rest_addr) == rest_addr))
1333 qla24xx_write_flash_dword(ha,
1334 ha->fdt_protect_sec_cmd,
1335 (fdata & 0xff00) | ((fdata << 16) &
1336 0xff0000) | ((fdata >> 16) & 0xff));
1337 }
1338
1339 ret = qla24xx_protect_flash(vha);
1340 if (ret != QLA_SUCCESS)
1341 ql_log(ql_log_warn, vha, 0x7099,
1342 "Unable to protect flash after update.\n");
1343 done:
1344 if (optrom)
1345 dma_free_coherent(&ha->pdev->dev,
1346 OPTROM_BURST_SIZE, optrom, optrom_dma);
1347
1348 return ret;
1349 }
1350
1351 uint8_t *
1352 qla2x00_read_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr,
1353 uint32_t bytes)
1354 {
1355 uint32_t i;
1356 uint16_t *wptr;
1357 struct qla_hw_data *ha = vha->hw;
1358
1359 /* Word reads to NVRAM via registers. */
1360 wptr = (uint16_t *)buf;
1361 qla2x00_lock_nvram_access(ha);
1362 for (i = 0; i < bytes >> 1; i++, naddr++)
1363 wptr[i] = cpu_to_le16(qla2x00_get_nvram_word(ha,
1364 naddr));
1365 qla2x00_unlock_nvram_access(ha);
1366
1367 return buf;
1368 }
1369
1370 uint8_t *
1371 qla24xx_read_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr,
1372 uint32_t bytes)
1373 {
1374 uint32_t i;
1375 uint32_t *dwptr;
1376 struct qla_hw_data *ha = vha->hw;
1377
1378 if (IS_P3P_TYPE(ha))
1379 return buf;
1380
1381 /* Dword reads to flash. */
1382 dwptr = (uint32_t *)buf;
1383 for (i = 0; i < bytes >> 2; i++, naddr++)
1384 dwptr[i] = cpu_to_le32(qla24xx_read_flash_dword(ha,
1385 nvram_data_addr(ha, naddr)));
1386
1387 return buf;
1388 }
1389
1390 int
1391 qla2x00_write_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr,
1392 uint32_t bytes)
1393 {
1394 int ret, stat;
1395 uint32_t i;
1396 uint16_t *wptr;
1397 unsigned long flags;
1398 struct qla_hw_data *ha = vha->hw;
1399
1400 ret = QLA_SUCCESS;
1401
1402 spin_lock_irqsave(&ha->hardware_lock, flags);
1403 qla2x00_lock_nvram_access(ha);
1404
1405 /* Disable NVRAM write-protection. */
1406 stat = qla2x00_clear_nvram_protection(ha);
1407
1408 wptr = (uint16_t *)buf;
1409 for (i = 0; i < bytes >> 1; i++, naddr++) {
1410 qla2x00_write_nvram_word(ha, naddr,
1411 cpu_to_le16(*wptr));
1412 wptr++;
1413 }
1414
1415 /* Enable NVRAM write-protection. */
1416 qla2x00_set_nvram_protection(ha, stat);
1417
1418 qla2x00_unlock_nvram_access(ha);
1419 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1420
1421 return ret;
1422 }
1423
1424 int
1425 qla24xx_write_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr,
1426 uint32_t bytes)
1427 {
1428 int ret;
1429 uint32_t i;
1430 uint32_t *dwptr;
1431 struct qla_hw_data *ha = vha->hw;
1432 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1433
1434 ret = QLA_SUCCESS;
1435
1436 if (IS_P3P_TYPE(ha))
1437 return ret;
1438
1439 /* Enable flash write. */
1440 WRT_REG_DWORD(&reg->ctrl_status,
1441 RD_REG_DWORD(&reg->ctrl_status) | CSRX_FLASH_ENABLE);
1442 RD_REG_DWORD(&reg->ctrl_status); /* PCI Posting. */
1443
1444 /* Disable NVRAM write-protection. */
1445 qla24xx_write_flash_dword(ha, nvram_conf_addr(ha, 0x101), 0);
1446 qla24xx_write_flash_dword(ha, nvram_conf_addr(ha, 0x101), 0);
1447
1448 /* Dword writes to flash. */
1449 dwptr = (uint32_t *)buf;
1450 for (i = 0; i < bytes >> 2; i++, naddr++, dwptr++) {
1451 ret = qla24xx_write_flash_dword(ha,
1452 nvram_data_addr(ha, naddr), cpu_to_le32(*dwptr));
1453 if (ret != QLA_SUCCESS) {
1454 ql_dbg(ql_dbg_user, vha, 0x709a,
1455 "Unable to program nvram address=%x data=%x.\n",
1456 naddr, *dwptr);
1457 break;
1458 }
1459 }
1460
1461 /* Enable NVRAM write-protection. */
1462 qla24xx_write_flash_dword(ha, nvram_conf_addr(ha, 0x101), 0x8c);
1463
1464 /* Disable flash write. */
1465 WRT_REG_DWORD(&reg->ctrl_status,
1466 RD_REG_DWORD(&reg->ctrl_status) & ~CSRX_FLASH_ENABLE);
1467 RD_REG_DWORD(&reg->ctrl_status); /* PCI Posting. */
1468
1469 return ret;
1470 }
1471
1472 uint8_t *
1473 qla25xx_read_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr,
1474 uint32_t bytes)
1475 {
1476 uint32_t i;
1477 uint32_t *dwptr;
1478 struct qla_hw_data *ha = vha->hw;
1479
1480 /* Dword reads to flash. */
1481 dwptr = (uint32_t *)buf;
1482 for (i = 0; i < bytes >> 2; i++, naddr++)
1483 dwptr[i] = cpu_to_le32(qla24xx_read_flash_dword(ha,
1484 flash_data_addr(ha, ha->flt_region_vpd_nvram | naddr)));
1485
1486 return buf;
1487 }
1488
1489 int
1490 qla25xx_write_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr,
1491 uint32_t bytes)
1492 {
1493 struct qla_hw_data *ha = vha->hw;
1494 #define RMW_BUFFER_SIZE (64 * 1024)
1495 uint8_t *dbuf;
1496
1497 dbuf = vmalloc(RMW_BUFFER_SIZE);
1498 if (!dbuf)
1499 return QLA_MEMORY_ALLOC_FAILED;
1500 ha->isp_ops->read_optrom(vha, dbuf, ha->flt_region_vpd_nvram << 2,
1501 RMW_BUFFER_SIZE);
1502 memcpy(dbuf + (naddr << 2), buf, bytes);
1503 ha->isp_ops->write_optrom(vha, dbuf, ha->flt_region_vpd_nvram << 2,
1504 RMW_BUFFER_SIZE);
1505 vfree(dbuf);
1506
1507 return QLA_SUCCESS;
1508 }
1509
1510 static inline void
1511 qla2x00_flip_colors(struct qla_hw_data *ha, uint16_t *pflags)
1512 {
1513 if (IS_QLA2322(ha)) {
1514 /* Flip all colors. */
1515 if (ha->beacon_color_state == QLA_LED_ALL_ON) {
1516 /* Turn off. */
1517 ha->beacon_color_state = 0;
1518 *pflags = GPIO_LED_ALL_OFF;
1519 } else {
1520 /* Turn on. */
1521 ha->beacon_color_state = QLA_LED_ALL_ON;
1522 *pflags = GPIO_LED_RGA_ON;
1523 }
1524 } else {
1525 /* Flip green led only. */
1526 if (ha->beacon_color_state == QLA_LED_GRN_ON) {
1527 /* Turn off. */
1528 ha->beacon_color_state = 0;
1529 *pflags = GPIO_LED_GREEN_OFF_AMBER_OFF;
1530 } else {
1531 /* Turn on. */
1532 ha->beacon_color_state = QLA_LED_GRN_ON;
1533 *pflags = GPIO_LED_GREEN_ON_AMBER_OFF;
1534 }
1535 }
1536 }
1537
1538 #define PIO_REG(h, r) ((h)->pio_address + offsetof(struct device_reg_2xxx, r))
1539
1540 void
1541 qla2x00_beacon_blink(struct scsi_qla_host *vha)
1542 {
1543 uint16_t gpio_enable;
1544 uint16_t gpio_data;
1545 uint16_t led_color = 0;
1546 unsigned long flags;
1547 struct qla_hw_data *ha = vha->hw;
1548 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1549
1550 if (IS_P3P_TYPE(ha))
1551 return;
1552
1553 spin_lock_irqsave(&ha->hardware_lock, flags);
1554
1555 /* Save the Original GPIOE. */
1556 if (ha->pio_address) {
1557 gpio_enable = RD_REG_WORD_PIO(PIO_REG(ha, gpioe));
1558 gpio_data = RD_REG_WORD_PIO(PIO_REG(ha, gpiod));
1559 } else {
1560 gpio_enable = RD_REG_WORD(&reg->gpioe);
1561 gpio_data = RD_REG_WORD(&reg->gpiod);
1562 }
1563
1564 /* Set the modified gpio_enable values */
1565 gpio_enable |= GPIO_LED_MASK;
1566
1567 if (ha->pio_address) {
1568 WRT_REG_WORD_PIO(PIO_REG(ha, gpioe), gpio_enable);
1569 } else {
1570 WRT_REG_WORD(&reg->gpioe, gpio_enable);
1571 RD_REG_WORD(&reg->gpioe);
1572 }
1573
1574 qla2x00_flip_colors(ha, &led_color);
1575
1576 /* Clear out any previously set LED color. */
1577 gpio_data &= ~GPIO_LED_MASK;
1578
1579 /* Set the new input LED color to GPIOD. */
1580 gpio_data |= led_color;
1581
1582 /* Set the modified gpio_data values */
1583 if (ha->pio_address) {
1584 WRT_REG_WORD_PIO(PIO_REG(ha, gpiod), gpio_data);
1585 } else {
1586 WRT_REG_WORD(&reg->gpiod, gpio_data);
1587 RD_REG_WORD(&reg->gpiod);
1588 }
1589
1590 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1591 }
1592
1593 int
1594 qla2x00_beacon_on(struct scsi_qla_host *vha)
1595 {
1596 uint16_t gpio_enable;
1597 uint16_t gpio_data;
1598 unsigned long flags;
1599 struct qla_hw_data *ha = vha->hw;
1600 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1601
1602 ha->fw_options[1] &= ~FO1_SET_EMPHASIS_SWING;
1603 ha->fw_options[1] |= FO1_DISABLE_GPIO6_7;
1604
1605 if (qla2x00_set_fw_options(vha, ha->fw_options) != QLA_SUCCESS) {
1606 ql_log(ql_log_warn, vha, 0x709b,
1607 "Unable to update fw options (beacon on).\n");
1608 return QLA_FUNCTION_FAILED;
1609 }
1610
1611 /* Turn off LEDs. */
1612 spin_lock_irqsave(&ha->hardware_lock, flags);
1613 if (ha->pio_address) {
1614 gpio_enable = RD_REG_WORD_PIO(PIO_REG(ha, gpioe));
1615 gpio_data = RD_REG_WORD_PIO(PIO_REG(ha, gpiod));
1616 } else {
1617 gpio_enable = RD_REG_WORD(&reg->gpioe);
1618 gpio_data = RD_REG_WORD(&reg->gpiod);
1619 }
1620 gpio_enable |= GPIO_LED_MASK;
1621
1622 /* Set the modified gpio_enable values. */
1623 if (ha->pio_address) {
1624 WRT_REG_WORD_PIO(PIO_REG(ha, gpioe), gpio_enable);
1625 } else {
1626 WRT_REG_WORD(&reg->gpioe, gpio_enable);
1627 RD_REG_WORD(&reg->gpioe);
1628 }
1629
1630 /* Clear out previously set LED colour. */
1631 gpio_data &= ~GPIO_LED_MASK;
1632 if (ha->pio_address) {
1633 WRT_REG_WORD_PIO(PIO_REG(ha, gpiod), gpio_data);
1634 } else {
1635 WRT_REG_WORD(&reg->gpiod, gpio_data);
1636 RD_REG_WORD(&reg->gpiod);
1637 }
1638 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1639
1640 /*
1641 * Let the per HBA timer kick off the blinking process based on
1642 * the following flags. No need to do anything else now.
1643 */
1644 ha->beacon_blink_led = 1;
1645 ha->beacon_color_state = 0;
1646
1647 return QLA_SUCCESS;
1648 }
1649
1650 int
1651 qla2x00_beacon_off(struct scsi_qla_host *vha)
1652 {
1653 int rval = QLA_SUCCESS;
1654 struct qla_hw_data *ha = vha->hw;
1655
1656 ha->beacon_blink_led = 0;
1657
1658 /* Set the on flag so when it gets flipped it will be off. */
1659 if (IS_QLA2322(ha))
1660 ha->beacon_color_state = QLA_LED_ALL_ON;
1661 else
1662 ha->beacon_color_state = QLA_LED_GRN_ON;
1663
1664 ha->isp_ops->beacon_blink(vha); /* This turns green LED off */
1665
1666 ha->fw_options[1] &= ~FO1_SET_EMPHASIS_SWING;
1667 ha->fw_options[1] &= ~FO1_DISABLE_GPIO6_7;
1668
1669 rval = qla2x00_set_fw_options(vha, ha->fw_options);
1670 if (rval != QLA_SUCCESS)
1671 ql_log(ql_log_warn, vha, 0x709c,
1672 "Unable to update fw options (beacon off).\n");
1673 return rval;
1674 }
1675
1676
1677 static inline void
1678 qla24xx_flip_colors(struct qla_hw_data *ha, uint16_t *pflags)
1679 {
1680 /* Flip all colors. */
1681 if (ha->beacon_color_state == QLA_LED_ALL_ON) {
1682 /* Turn off. */
1683 ha->beacon_color_state = 0;
1684 *pflags = 0;
1685 } else {
1686 /* Turn on. */
1687 ha->beacon_color_state = QLA_LED_ALL_ON;
1688 *pflags = GPDX_LED_YELLOW_ON | GPDX_LED_AMBER_ON;
1689 }
1690 }
1691
1692 void
1693 qla24xx_beacon_blink(struct scsi_qla_host *vha)
1694 {
1695 uint16_t led_color = 0;
1696 uint32_t gpio_data;
1697 unsigned long flags;
1698 struct qla_hw_data *ha = vha->hw;
1699 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1700
1701 /* Save the Original GPIOD. */
1702 spin_lock_irqsave(&ha->hardware_lock, flags);
1703 gpio_data = RD_REG_DWORD(&reg->gpiod);
1704
1705 /* Enable the gpio_data reg for update. */
1706 gpio_data |= GPDX_LED_UPDATE_MASK;
1707
1708 WRT_REG_DWORD(&reg->gpiod, gpio_data);
1709 gpio_data = RD_REG_DWORD(&reg->gpiod);
1710
1711 /* Set the color bits. */
1712 qla24xx_flip_colors(ha, &led_color);
1713
1714 /* Clear out any previously set LED color. */
1715 gpio_data &= ~GPDX_LED_COLOR_MASK;
1716
1717 /* Set the new input LED color to GPIOD. */
1718 gpio_data |= led_color;
1719
1720 /* Set the modified gpio_data values. */
1721 WRT_REG_DWORD(&reg->gpiod, gpio_data);
1722 gpio_data = RD_REG_DWORD(&reg->gpiod);
1723 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1724 }
1725
1726 static uint32_t
1727 qla83xx_select_led_port(struct qla_hw_data *ha)
1728 {
1729 uint32_t led_select_value = 0;
1730
1731 if (!IS_QLA83XX(ha) && !IS_QLA27XX(ha))
1732 goto out;
1733
1734 if (ha->port_no == 0)
1735 led_select_value = QLA83XX_LED_PORT0;
1736 else
1737 led_select_value = QLA83XX_LED_PORT1;
1738
1739 out:
1740 return led_select_value;
1741 }
1742
1743 void
1744 qla83xx_beacon_blink(struct scsi_qla_host *vha)
1745 {
1746 uint32_t led_select_value;
1747 struct qla_hw_data *ha = vha->hw;
1748 uint16_t led_cfg[6];
1749 uint16_t orig_led_cfg[6];
1750 uint32_t led_10_value, led_43_value;
1751
1752 if (!IS_QLA83XX(ha) && !IS_QLA81XX(ha) && !IS_QLA27XX(ha))
1753 return;
1754
1755 if (!ha->beacon_blink_led)
1756 return;
1757
1758 if (IS_QLA27XX(ha)) {
1759 qla2x00_write_ram_word(vha, 0x1003, 0x40000230);
1760 qla2x00_write_ram_word(vha, 0x1004, 0x40000230);
1761 } else if (IS_QLA2031(ha)) {
1762 led_select_value = qla83xx_select_led_port(ha);
1763
1764 qla83xx_wr_reg(vha, led_select_value, 0x40000230);
1765 qla83xx_wr_reg(vha, led_select_value + 4, 0x40000230);
1766 } else if (IS_QLA8031(ha)) {
1767 led_select_value = qla83xx_select_led_port(ha);
1768
1769 qla83xx_rd_reg(vha, led_select_value, &led_10_value);
1770 qla83xx_rd_reg(vha, led_select_value + 0x10, &led_43_value);
1771 qla83xx_wr_reg(vha, led_select_value, 0x01f44000);
1772 msleep(500);
1773 qla83xx_wr_reg(vha, led_select_value, 0x400001f4);
1774 msleep(1000);
1775 qla83xx_wr_reg(vha, led_select_value, led_10_value);
1776 qla83xx_wr_reg(vha, led_select_value + 0x10, led_43_value);
1777 } else if (IS_QLA81XX(ha)) {
1778 int rval;
1779
1780 /* Save Current */
1781 rval = qla81xx_get_led_config(vha, orig_led_cfg);
1782 /* Do the blink */
1783 if (rval == QLA_SUCCESS) {
1784 if (IS_QLA81XX(ha)) {
1785 led_cfg[0] = 0x4000;
1786 led_cfg[1] = 0x2000;
1787 led_cfg[2] = 0;
1788 led_cfg[3] = 0;
1789 led_cfg[4] = 0;
1790 led_cfg[5] = 0;
1791 } else {
1792 led_cfg[0] = 0x4000;
1793 led_cfg[1] = 0x4000;
1794 led_cfg[2] = 0x4000;
1795 led_cfg[3] = 0x2000;
1796 led_cfg[4] = 0;
1797 led_cfg[5] = 0x2000;
1798 }
1799 rval = qla81xx_set_led_config(vha, led_cfg);
1800 msleep(1000);
1801 if (IS_QLA81XX(ha)) {
1802 led_cfg[0] = 0x4000;
1803 led_cfg[1] = 0x2000;
1804 led_cfg[2] = 0;
1805 } else {
1806 led_cfg[0] = 0x4000;
1807 led_cfg[1] = 0x2000;
1808 led_cfg[2] = 0x4000;
1809 led_cfg[3] = 0x4000;
1810 led_cfg[4] = 0;
1811 led_cfg[5] = 0x2000;
1812 }
1813 rval = qla81xx_set_led_config(vha, led_cfg);
1814 }
1815 /* On exit, restore original (presumes no status change) */
1816 qla81xx_set_led_config(vha, orig_led_cfg);
1817 }
1818 }
1819
1820 int
1821 qla24xx_beacon_on(struct scsi_qla_host *vha)
1822 {
1823 uint32_t gpio_data;
1824 unsigned long flags;
1825 struct qla_hw_data *ha = vha->hw;
1826 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1827
1828 if (IS_P3P_TYPE(ha))
1829 return QLA_SUCCESS;
1830
1831 if (IS_QLA8031(ha) || IS_QLA81XX(ha))
1832 goto skip_gpio; /* let blink handle it */
1833
1834 if (ha->beacon_blink_led == 0) {
1835 /* Enable firmware for update */
1836 ha->fw_options[1] |= ADD_FO1_DISABLE_GPIO_LED_CTRL;
1837
1838 if (qla2x00_set_fw_options(vha, ha->fw_options) != QLA_SUCCESS)
1839 return QLA_FUNCTION_FAILED;
1840
1841 if (qla2x00_get_fw_options(vha, ha->fw_options) !=
1842 QLA_SUCCESS) {
1843 ql_log(ql_log_warn, vha, 0x7009,
1844 "Unable to update fw options (beacon on).\n");
1845 return QLA_FUNCTION_FAILED;
1846 }
1847
1848 if (IS_QLA2031(ha) || IS_QLA27XX(ha))
1849 goto skip_gpio;
1850
1851 spin_lock_irqsave(&ha->hardware_lock, flags);
1852 gpio_data = RD_REG_DWORD(&reg->gpiod);
1853
1854 /* Enable the gpio_data reg for update. */
1855 gpio_data |= GPDX_LED_UPDATE_MASK;
1856 WRT_REG_DWORD(&reg->gpiod, gpio_data);
1857 RD_REG_DWORD(&reg->gpiod);
1858
1859 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1860 }
1861
1862 /* So all colors blink together. */
1863 ha->beacon_color_state = 0;
1864
1865 skip_gpio:
1866 /* Let the per HBA timer kick off the blinking process. */
1867 ha->beacon_blink_led = 1;
1868
1869 return QLA_SUCCESS;
1870 }
1871
1872 int
1873 qla24xx_beacon_off(struct scsi_qla_host *vha)
1874 {
1875 uint32_t gpio_data;
1876 unsigned long flags;
1877 struct qla_hw_data *ha = vha->hw;
1878 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1879
1880 if (IS_P3P_TYPE(ha))
1881 return QLA_SUCCESS;
1882
1883 if (!ha->flags.fw_started)
1884 return QLA_SUCCESS;
1885
1886 ha->beacon_blink_led = 0;
1887
1888 if (IS_QLA2031(ha) || IS_QLA27XX(ha))
1889 goto set_fw_options;
1890
1891 if (IS_QLA8031(ha) || IS_QLA81XX(ha))
1892 return QLA_SUCCESS;
1893
1894 ha->beacon_color_state = QLA_LED_ALL_ON;
1895
1896 ha->isp_ops->beacon_blink(vha); /* Will flip to all off. */
1897
1898 /* Give control back to firmware. */
1899 spin_lock_irqsave(&ha->hardware_lock, flags);
1900 gpio_data = RD_REG_DWORD(&reg->gpiod);
1901
1902 /* Disable the gpio_data reg for update. */
1903 gpio_data &= ~GPDX_LED_UPDATE_MASK;
1904 WRT_REG_DWORD(&reg->gpiod, gpio_data);
1905 RD_REG_DWORD(&reg->gpiod);
1906 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1907
1908 set_fw_options:
1909 ha->fw_options[1] &= ~ADD_FO1_DISABLE_GPIO_LED_CTRL;
1910
1911 if (qla2x00_set_fw_options(vha, ha->fw_options) != QLA_SUCCESS) {
1912 ql_log(ql_log_warn, vha, 0x704d,
1913 "Unable to update fw options (beacon on).\n");
1914 return QLA_FUNCTION_FAILED;
1915 }
1916
1917 if (qla2x00_get_fw_options(vha, ha->fw_options) != QLA_SUCCESS) {
1918 ql_log(ql_log_warn, vha, 0x704e,
1919 "Unable to update fw options (beacon on).\n");
1920 return QLA_FUNCTION_FAILED;
1921 }
1922
1923 return QLA_SUCCESS;
1924 }
1925
1926
1927 /*
1928 * Flash support routines
1929 */
1930
1931 /**
1932 * qla2x00_flash_enable() - Setup flash for reading and writing.
1933 * @ha: HA context
1934 */
1935 static void
1936 qla2x00_flash_enable(struct qla_hw_data *ha)
1937 {
1938 uint16_t data;
1939 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1940
1941 data = RD_REG_WORD(&reg->ctrl_status);
1942 data |= CSR_FLASH_ENABLE;
1943 WRT_REG_WORD(&reg->ctrl_status, data);
1944 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1945 }
1946
1947 /**
1948 * qla2x00_flash_disable() - Disable flash and allow RISC to run.
1949 * @ha: HA context
1950 */
1951 static void
1952 qla2x00_flash_disable(struct qla_hw_data *ha)
1953 {
1954 uint16_t data;
1955 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1956
1957 data = RD_REG_WORD(&reg->ctrl_status);
1958 data &= ~(CSR_FLASH_ENABLE);
1959 WRT_REG_WORD(&reg->ctrl_status, data);
1960 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1961 }
1962
1963 /**
1964 * qla2x00_read_flash_byte() - Reads a byte from flash
1965 * @ha: HA context
1966 * @addr: Address in flash to read
1967 *
1968 * A word is read from the chip, but, only the lower byte is valid.
1969 *
1970 * Returns the byte read from flash @addr.
1971 */
1972 static uint8_t
1973 qla2x00_read_flash_byte(struct qla_hw_data *ha, uint32_t addr)
1974 {
1975 uint16_t data;
1976 uint16_t bank_select;
1977 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1978
1979 bank_select = RD_REG_WORD(&reg->ctrl_status);
1980
1981 if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
1982 /* Specify 64K address range: */
1983 /* clear out Module Select and Flash Address bits [19:16]. */
1984 bank_select &= ~0xf8;
1985 bank_select |= addr >> 12 & 0xf0;
1986 bank_select |= CSR_FLASH_64K_BANK;
1987 WRT_REG_WORD(&reg->ctrl_status, bank_select);
1988 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1989
1990 WRT_REG_WORD(&reg->flash_address, (uint16_t)addr);
1991 data = RD_REG_WORD(&reg->flash_data);
1992
1993 return (uint8_t)data;
1994 }
1995
1996 /* Setup bit 16 of flash address. */
1997 if ((addr & BIT_16) && ((bank_select & CSR_FLASH_64K_BANK) == 0)) {
1998 bank_select |= CSR_FLASH_64K_BANK;
1999 WRT_REG_WORD(&reg->ctrl_status, bank_select);
2000 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
2001 } else if (((addr & BIT_16) == 0) &&
2002 (bank_select & CSR_FLASH_64K_BANK)) {
2003 bank_select &= ~(CSR_FLASH_64K_BANK);
2004 WRT_REG_WORD(&reg->ctrl_status, bank_select);
2005 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
2006 }
2007
2008 /* Always perform IO mapped accesses to the FLASH registers. */
2009 if (ha->pio_address) {
2010 uint16_t data2;
2011
2012 WRT_REG_WORD_PIO(PIO_REG(ha, flash_address), (uint16_t)addr);
2013 do {
2014 data = RD_REG_WORD_PIO(PIO_REG(ha, flash_data));
2015 barrier();
2016 cpu_relax();
2017 data2 = RD_REG_WORD_PIO(PIO_REG(ha, flash_data));
2018 } while (data != data2);
2019 } else {
2020 WRT_REG_WORD(&reg->flash_address, (uint16_t)addr);
2021 data = qla2x00_debounce_register(&reg->flash_data);
2022 }
2023
2024 return (uint8_t)data;
2025 }
2026
2027 /**
2028 * qla2x00_write_flash_byte() - Write a byte to flash
2029 * @ha: HA context
2030 * @addr: Address in flash to write
2031 * @data: Data to write
2032 */
2033 static void
2034 qla2x00_write_flash_byte(struct qla_hw_data *ha, uint32_t addr, uint8_t data)
2035 {
2036 uint16_t bank_select;
2037 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
2038
2039 bank_select = RD_REG_WORD(&reg->ctrl_status);
2040 if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
2041 /* Specify 64K address range: */
2042 /* clear out Module Select and Flash Address bits [19:16]. */
2043 bank_select &= ~0xf8;
2044 bank_select |= addr >> 12 & 0xf0;
2045 bank_select |= CSR_FLASH_64K_BANK;
2046 WRT_REG_WORD(&reg->ctrl_status, bank_select);
2047 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
2048
2049 WRT_REG_WORD(&reg->flash_address, (uint16_t)addr);
2050 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
2051 WRT_REG_WORD(&reg->flash_data, (uint16_t)data);
2052 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
2053
2054 return;
2055 }
2056
2057 /* Setup bit 16 of flash address. */
2058 if ((addr & BIT_16) && ((bank_select & CSR_FLASH_64K_BANK) == 0)) {
2059 bank_select |= CSR_FLASH_64K_BANK;
2060 WRT_REG_WORD(&reg->ctrl_status, bank_select);
2061 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
2062 } else if (((addr & BIT_16) == 0) &&
2063 (bank_select & CSR_FLASH_64K_BANK)) {
2064 bank_select &= ~(CSR_FLASH_64K_BANK);
2065 WRT_REG_WORD(&reg->ctrl_status, bank_select);
2066 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
2067 }
2068
2069 /* Always perform IO mapped accesses to the FLASH registers. */
2070 if (ha->pio_address) {
2071 WRT_REG_WORD_PIO(PIO_REG(ha, flash_address), (uint16_t)addr);
2072 WRT_REG_WORD_PIO(PIO_REG(ha, flash_data), (uint16_t)data);
2073 } else {
2074 WRT_REG_WORD(&reg->flash_address, (uint16_t)addr);
2075 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
2076 WRT_REG_WORD(&reg->flash_data, (uint16_t)data);
2077 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
2078 }
2079 }
2080
2081 /**
2082 * qla2x00_poll_flash() - Polls flash for completion.
2083 * @ha: HA context
2084 * @addr: Address in flash to poll
2085 * @poll_data: Data to be polled
2086 * @man_id: Flash manufacturer ID
2087 * @flash_id: Flash ID
2088 *
2089 * This function polls the device until bit 7 of what is read matches data
2090 * bit 7 or until data bit 5 becomes a 1. If that hapens, the flash ROM timed
2091 * out (a fatal error). The flash book recommeds reading bit 7 again after
2092 * reading bit 5 as a 1.
2093 *
2094 * Returns 0 on success, else non-zero.
2095 */
2096 static int
2097 qla2x00_poll_flash(struct qla_hw_data *ha, uint32_t addr, uint8_t poll_data,
2098 uint8_t man_id, uint8_t flash_id)
2099 {
2100 int status;
2101 uint8_t flash_data;
2102 uint32_t cnt;
2103
2104 status = 1;
2105
2106 /* Wait for 30 seconds for command to finish. */
2107 poll_data &= BIT_7;
2108 for (cnt = 3000000; cnt; cnt--) {
2109 flash_data = qla2x00_read_flash_byte(ha, addr);
2110 if ((flash_data & BIT_7) == poll_data) {
2111 status = 0;
2112 break;
2113 }
2114
2115 if (man_id != 0x40 && man_id != 0xda) {
2116 if ((flash_data & BIT_5) && cnt > 2)
2117 cnt = 2;
2118 }
2119 udelay(10);
2120 barrier();
2121 cond_resched();
2122 }
2123 return status;
2124 }
2125
2126 /**
2127 * qla2x00_program_flash_address() - Programs a flash address
2128 * @ha: HA context
2129 * @addr: Address in flash to program
2130 * @data: Data to be written in flash
2131 * @man_id: Flash manufacturer ID
2132 * @flash_id: Flash ID
2133 *
2134 * Returns 0 on success, else non-zero.
2135 */
2136 static int
2137 qla2x00_program_flash_address(struct qla_hw_data *ha, uint32_t addr,
2138 uint8_t data, uint8_t man_id, uint8_t flash_id)
2139 {
2140 /* Write Program Command Sequence. */
2141 if (IS_OEM_001(ha)) {
2142 qla2x00_write_flash_byte(ha, 0xaaa, 0xaa);
2143 qla2x00_write_flash_byte(ha, 0x555, 0x55);
2144 qla2x00_write_flash_byte(ha, 0xaaa, 0xa0);
2145 qla2x00_write_flash_byte(ha, addr, data);
2146 } else {
2147 if (man_id == 0xda && flash_id == 0xc1) {
2148 qla2x00_write_flash_byte(ha, addr, data);
2149 if (addr & 0x7e)
2150 return 0;
2151 } else {
2152 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
2153 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
2154 qla2x00_write_flash_byte(ha, 0x5555, 0xa0);
2155 qla2x00_write_flash_byte(ha, addr, data);
2156 }
2157 }
2158
2159 udelay(150);
2160
2161 /* Wait for write to complete. */
2162 return qla2x00_poll_flash(ha, addr, data, man_id, flash_id);
2163 }
2164
2165 /**
2166 * qla2x00_erase_flash() - Erase the flash.
2167 * @ha: HA context
2168 * @man_id: Flash manufacturer ID
2169 * @flash_id: Flash ID
2170 *
2171 * Returns 0 on success, else non-zero.
2172 */
2173 static int
2174 qla2x00_erase_flash(struct qla_hw_data *ha, uint8_t man_id, uint8_t flash_id)
2175 {
2176 /* Individual Sector Erase Command Sequence */
2177 if (IS_OEM_001(ha)) {
2178 qla2x00_write_flash_byte(ha, 0xaaa, 0xaa);
2179 qla2x00_write_flash_byte(ha, 0x555, 0x55);
2180 qla2x00_write_flash_byte(ha, 0xaaa, 0x80);
2181 qla2x00_write_flash_byte(ha, 0xaaa, 0xaa);
2182 qla2x00_write_flash_byte(ha, 0x555, 0x55);
2183 qla2x00_write_flash_byte(ha, 0xaaa, 0x10);
2184 } else {
2185 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
2186 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
2187 qla2x00_write_flash_byte(ha, 0x5555, 0x80);
2188 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
2189 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
2190 qla2x00_write_flash_byte(ha, 0x5555, 0x10);
2191 }
2192
2193 udelay(150);
2194
2195 /* Wait for erase to complete. */
2196 return qla2x00_poll_flash(ha, 0x00, 0x80, man_id, flash_id);
2197 }
2198
2199 /**
2200 * qla2x00_erase_flash_sector() - Erase a flash sector.
2201 * @ha: HA context
2202 * @addr: Flash sector to erase
2203 * @sec_mask: Sector address mask
2204 * @man_id: Flash manufacturer ID
2205 * @flash_id: Flash ID
2206 *
2207 * Returns 0 on success, else non-zero.
2208 */
2209 static int
2210 qla2x00_erase_flash_sector(struct qla_hw_data *ha, uint32_t addr,
2211 uint32_t sec_mask, uint8_t man_id, uint8_t flash_id)
2212 {
2213 /* Individual Sector Erase Command Sequence */
2214 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
2215 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
2216 qla2x00_write_flash_byte(ha, 0x5555, 0x80);
2217 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
2218 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
2219 if (man_id == 0x1f && flash_id == 0x13)
2220 qla2x00_write_flash_byte(ha, addr & sec_mask, 0x10);
2221 else
2222 qla2x00_write_flash_byte(ha, addr & sec_mask, 0x30);
2223
2224 udelay(150);
2225
2226 /* Wait for erase to complete. */
2227 return qla2x00_poll_flash(ha, addr, 0x80, man_id, flash_id);
2228 }
2229
2230 /**
2231 * qla2x00_get_flash_manufacturer() - Read manufacturer ID from flash chip.
2232 * @ha: host adapter
2233 * @man_id: Flash manufacturer ID
2234 * @flash_id: Flash ID
2235 */
2236 static void
2237 qla2x00_get_flash_manufacturer(struct qla_hw_data *ha, uint8_t *man_id,
2238 uint8_t *flash_id)
2239 {
2240 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
2241 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
2242 qla2x00_write_flash_byte(ha, 0x5555, 0x90);
2243 *man_id = qla2x00_read_flash_byte(ha, 0x0000);
2244 *flash_id = qla2x00_read_flash_byte(ha, 0x0001);
2245 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
2246 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
2247 qla2x00_write_flash_byte(ha, 0x5555, 0xf0);
2248 }
2249
2250 static void
2251 qla2x00_read_flash_data(struct qla_hw_data *ha, uint8_t *tmp_buf,
2252 uint32_t saddr, uint32_t length)
2253 {
2254 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
2255 uint32_t midpoint, ilength;
2256 uint8_t data;
2257
2258 midpoint = length / 2;
2259
2260 WRT_REG_WORD(&reg->nvram, 0);
2261 RD_REG_WORD(&reg->nvram);
2262 for (ilength = 0; ilength < length; saddr++, ilength++, tmp_buf++) {
2263 if (ilength == midpoint) {
2264 WRT_REG_WORD(&reg->nvram, NVR_SELECT);
2265 RD_REG_WORD(&reg->nvram);
2266 }
2267 data = qla2x00_read_flash_byte(ha, saddr);
2268 if (saddr % 100)
2269 udelay(10);
2270 *tmp_buf = data;
2271 cond_resched();
2272 }
2273 }
2274
2275 static inline void
2276 qla2x00_suspend_hba(struct scsi_qla_host *vha)
2277 {
2278 int cnt;
2279 unsigned long flags;
2280 struct qla_hw_data *ha = vha->hw;
2281 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
2282
2283 /* Suspend HBA. */
2284 scsi_block_requests(vha->host);
2285 ha->isp_ops->disable_intrs(ha);
2286 set_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
2287
2288 /* Pause RISC. */
2289 spin_lock_irqsave(&ha->hardware_lock, flags);
2290 WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
2291 RD_REG_WORD(&reg->hccr);
2292 if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
2293 for (cnt = 0; cnt < 30000; cnt++) {
2294 if ((RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) != 0)
2295 break;
2296 udelay(100);
2297 }
2298 } else {
2299 udelay(10);
2300 }
2301 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2302 }
2303
2304 static inline void
2305 qla2x00_resume_hba(struct scsi_qla_host *vha)
2306 {
2307 struct qla_hw_data *ha = vha->hw;
2308
2309 /* Resume HBA. */
2310 clear_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
2311 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
2312 qla2xxx_wake_dpc(vha);
2313 qla2x00_wait_for_chip_reset(vha);
2314 scsi_unblock_requests(vha->host);
2315 }
2316
2317 uint8_t *
2318 qla2x00_read_optrom_data(struct scsi_qla_host *vha, uint8_t *buf,
2319 uint32_t offset, uint32_t length)
2320 {
2321 uint32_t addr, midpoint;
2322 uint8_t *data;
2323 struct qla_hw_data *ha = vha->hw;
2324 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
2325
2326 /* Suspend HBA. */
2327 qla2x00_suspend_hba(vha);
2328
2329 /* Go with read. */
2330 midpoint = ha->optrom_size / 2;
2331
2332 qla2x00_flash_enable(ha);
2333 WRT_REG_WORD(&reg->nvram, 0);
2334 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
2335 for (addr = offset, data = buf; addr < length; addr++, data++) {
2336 if (addr == midpoint) {
2337 WRT_REG_WORD(&reg->nvram, NVR_SELECT);
2338 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
2339 }
2340
2341 *data = qla2x00_read_flash_byte(ha, addr);
2342 }
2343 qla2x00_flash_disable(ha);
2344
2345 /* Resume HBA. */
2346 qla2x00_resume_hba(vha);
2347
2348 return buf;
2349 }
2350
2351 int
2352 qla2x00_write_optrom_data(struct scsi_qla_host *vha, uint8_t *buf,
2353 uint32_t offset, uint32_t length)
2354 {
2355
2356 int rval;
2357 uint8_t man_id, flash_id, sec_number, data;
2358 uint16_t wd;
2359 uint32_t addr, liter, sec_mask, rest_addr;
2360 struct qla_hw_data *ha = vha->hw;
2361 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
2362
2363 /* Suspend HBA. */
2364 qla2x00_suspend_hba(vha);
2365
2366 rval = QLA_SUCCESS;
2367 sec_number = 0;
2368
2369 /* Reset ISP chip. */
2370 WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
2371 pci_read_config_word(ha->pdev, PCI_COMMAND, &wd);
2372
2373 /* Go with write. */
2374 qla2x00_flash_enable(ha);
2375 do { /* Loop once to provide quick error exit */
2376 /* Structure of flash memory based on manufacturer */
2377 if (IS_OEM_001(ha)) {
2378 /* OEM variant with special flash part. */
2379 man_id = flash_id = 0;
2380 rest_addr = 0xffff;
2381 sec_mask = 0x10000;
2382 goto update_flash;
2383 }
2384 qla2x00_get_flash_manufacturer(ha, &man_id, &flash_id);
2385 switch (man_id) {
2386 case 0x20: /* ST flash. */
2387 if (flash_id == 0xd2 || flash_id == 0xe3) {
2388 /*
2389 * ST m29w008at part - 64kb sector size with
2390 * 32kb,8kb,8kb,16kb sectors at memory address
2391 * 0xf0000.
2392 */
2393 rest_addr = 0xffff;
2394 sec_mask = 0x10000;
2395 break;
2396 }
2397 /*
2398 * ST m29w010b part - 16kb sector size
2399 * Default to 16kb sectors
2400 */
2401 rest_addr = 0x3fff;
2402 sec_mask = 0x1c000;
2403 break;
2404 case 0x40: /* Mostel flash. */
2405 /* Mostel v29c51001 part - 512 byte sector size. */
2406 rest_addr = 0x1ff;
2407 sec_mask = 0x1fe00;
2408 break;
2409 case 0xbf: /* SST flash. */
2410 /* SST39sf10 part - 4kb sector size. */
2411 rest_addr = 0xfff;
2412 sec_mask = 0x1f000;
2413 break;
2414 case 0xda: /* Winbond flash. */
2415 /* Winbond W29EE011 part - 256 byte sector size. */
2416 rest_addr = 0x7f;
2417 sec_mask = 0x1ff80;
2418 break;
2419 case 0xc2: /* Macronix flash. */
2420 /* 64k sector size. */
2421 if (flash_id == 0x38 || flash_id == 0x4f) {
2422 rest_addr = 0xffff;
2423 sec_mask = 0x10000;
2424 break;
2425 }
2426 /* Fall through... */
2427
2428 case 0x1f: /* Atmel flash. */
2429 /* 512k sector size. */
2430 if (flash_id == 0x13) {
2431 rest_addr = 0x7fffffff;
2432 sec_mask = 0x80000000;
2433 break;
2434 }
2435 /* Fall through... */
2436
2437 case 0x01: /* AMD flash. */
2438 if (flash_id == 0x38 || flash_id == 0x40 ||
2439 flash_id == 0x4f) {
2440 /* Am29LV081 part - 64kb sector size. */
2441 /* Am29LV002BT part - 64kb sector size. */
2442 rest_addr = 0xffff;
2443 sec_mask = 0x10000;
2444 break;
2445 } else if (flash_id == 0x3e) {
2446 /*
2447 * Am29LV008b part - 64kb sector size with
2448 * 32kb,8kb,8kb,16kb sector at memory address
2449 * h0xf0000.
2450 */
2451 rest_addr = 0xffff;
2452 sec_mask = 0x10000;
2453 break;
2454 } else if (flash_id == 0x20 || flash_id == 0x6e) {
2455 /*
2456 * Am29LV010 part or AM29f010 - 16kb sector
2457 * size.
2458 */
2459 rest_addr = 0x3fff;
2460 sec_mask = 0x1c000;
2461 break;
2462 } else if (flash_id == 0x6d) {
2463 /* Am29LV001 part - 8kb sector size. */
2464 rest_addr = 0x1fff;
2465 sec_mask = 0x1e000;
2466 break;
2467 }
2468 /* fall through */
2469 default:
2470 /* Default to 16 kb sector size. */
2471 rest_addr = 0x3fff;
2472 sec_mask = 0x1c000;
2473 break;
2474 }
2475
2476 update_flash:
2477 if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
2478 if (qla2x00_erase_flash(ha, man_id, flash_id)) {
2479 rval = QLA_FUNCTION_FAILED;
2480 break;
2481 }
2482 }
2483
2484 for (addr = offset, liter = 0; liter < length; liter++,
2485 addr++) {
2486 data = buf[liter];
2487 /* Are we at the beginning of a sector? */
2488 if ((addr & rest_addr) == 0) {
2489 if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
2490 if (addr >= 0x10000UL) {
2491 if (((addr >> 12) & 0xf0) &&
2492 ((man_id == 0x01 &&
2493 flash_id == 0x3e) ||
2494 (man_id == 0x20 &&
2495 flash_id == 0xd2))) {
2496 sec_number++;
2497 if (sec_number == 1) {
2498 rest_addr =
2499 0x7fff;
2500 sec_mask =
2501 0x18000;
2502 } else if (
2503 sec_number == 2 ||
2504 sec_number == 3) {
2505 rest_addr =
2506 0x1fff;
2507 sec_mask =
2508 0x1e000;
2509 } else if (
2510 sec_number == 4) {
2511 rest_addr =
2512 0x3fff;
2513 sec_mask =
2514 0x1c000;
2515 }
2516 }
2517 }
2518 } else if (addr == ha->optrom_size / 2) {
2519 WRT_REG_WORD(&reg->nvram, NVR_SELECT);
2520 RD_REG_WORD(&reg->nvram);
2521 }
2522
2523 if (flash_id == 0xda && man_id == 0xc1) {
2524 qla2x00_write_flash_byte(ha, 0x5555,
2525 0xaa);
2526 qla2x00_write_flash_byte(ha, 0x2aaa,
2527 0x55);
2528 qla2x00_write_flash_byte(ha, 0x5555,
2529 0xa0);
2530 } else if (!IS_QLA2322(ha) && !IS_QLA6322(ha)) {
2531 /* Then erase it */
2532 if (qla2x00_erase_flash_sector(ha,
2533 addr, sec_mask, man_id,
2534 flash_id)) {
2535 rval = QLA_FUNCTION_FAILED;
2536 break;
2537 }
2538 if (man_id == 0x01 && flash_id == 0x6d)
2539 sec_number++;
2540 }
2541 }
2542
2543 if (man_id == 0x01 && flash_id == 0x6d) {
2544 if (sec_number == 1 &&
2545 addr == (rest_addr - 1)) {
2546 rest_addr = 0x0fff;
2547 sec_mask = 0x1f000;
2548 } else if (sec_number == 3 && (addr & 0x7ffe)) {
2549 rest_addr = 0x3fff;
2550 sec_mask = 0x1c000;
2551 }
2552 }
2553
2554 if (qla2x00_program_flash_address(ha, addr, data,
2555 man_id, flash_id)) {
2556 rval = QLA_FUNCTION_FAILED;
2557 break;
2558 }
2559 cond_resched();
2560 }
2561 } while (0);
2562 qla2x00_flash_disable(ha);
2563
2564 /* Resume HBA. */
2565 qla2x00_resume_hba(vha);
2566
2567 return rval;
2568 }
2569
2570 uint8_t *
2571 qla24xx_read_optrom_data(struct scsi_qla_host *vha, uint8_t *buf,
2572 uint32_t offset, uint32_t length)
2573 {
2574 struct qla_hw_data *ha = vha->hw;
2575
2576 /* Suspend HBA. */
2577 scsi_block_requests(vha->host);
2578 set_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
2579
2580 /* Go with read. */
2581 qla24xx_read_flash_data(vha, (uint32_t *)buf, offset >> 2, length >> 2);
2582
2583 /* Resume HBA. */
2584 clear_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
2585 scsi_unblock_requests(vha->host);
2586
2587 return buf;
2588 }
2589
2590 int
2591 qla24xx_write_optrom_data(struct scsi_qla_host *vha, uint8_t *buf,
2592 uint32_t offset, uint32_t length)
2593 {
2594 int rval;
2595 struct qla_hw_data *ha = vha->hw;
2596
2597 /* Suspend HBA. */
2598 scsi_block_requests(vha->host);
2599 set_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
2600
2601 /* Go with write. */
2602 rval = qla24xx_write_flash_data(vha, (uint32_t *)buf, offset >> 2,
2603 length >> 2);
2604
2605 clear_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
2606 scsi_unblock_requests(vha->host);
2607
2608 return rval;
2609 }
2610
2611 uint8_t *
2612 qla25xx_read_optrom_data(struct scsi_qla_host *vha, uint8_t *buf,
2613 uint32_t offset, uint32_t length)
2614 {
2615 int rval;
2616 dma_addr_t optrom_dma;
2617 void *optrom;
2618 uint8_t *pbuf;
2619 uint32_t faddr, left, burst;
2620 struct qla_hw_data *ha = vha->hw;
2621
2622 if (IS_QLA25XX(ha) || IS_QLA81XX(ha) || IS_QLA83XX(ha) ||
2623 IS_QLA27XX(ha))
2624 goto try_fast;
2625 if (offset & 0xfff)
2626 goto slow_read;
2627 if (length < OPTROM_BURST_SIZE)
2628 goto slow_read;
2629
2630 try_fast:
2631 optrom = dma_alloc_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE,
2632 &optrom_dma, GFP_KERNEL);
2633 if (!optrom) {
2634 ql_log(ql_log_warn, vha, 0x00cc,
2635 "Unable to allocate memory for optrom burst read (%x KB).\n",
2636 OPTROM_BURST_SIZE / 1024);
2637 goto slow_read;
2638 }
2639
2640 pbuf = buf;
2641 faddr = offset >> 2;
2642 left = length >> 2;
2643 burst = OPTROM_BURST_DWORDS;
2644 while (left != 0) {
2645 if (burst > left)
2646 burst = left;
2647
2648 rval = qla2x00_dump_ram(vha, optrom_dma,
2649 flash_data_addr(ha, faddr), burst);
2650 if (rval) {
2651 ql_log(ql_log_warn, vha, 0x00f5,
2652 "Unable to burst-read optrom segment (%x/%x/%llx).\n",
2653 rval, flash_data_addr(ha, faddr),
2654 (unsigned long long)optrom_dma);
2655 ql_log(ql_log_warn, vha, 0x00f6,
2656 "Reverting to slow-read.\n");
2657
2658 dma_free_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE,
2659 optrom, optrom_dma);
2660 goto slow_read;
2661 }
2662
2663 memcpy(pbuf, optrom, burst * 4);
2664
2665 left -= burst;
2666 faddr += burst;
2667 pbuf += burst * 4;
2668 }
2669
2670 dma_free_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE, optrom,
2671 optrom_dma);
2672
2673 return buf;
2674
2675 slow_read:
2676 return qla24xx_read_optrom_data(vha, buf, offset, length);
2677 }
2678
2679 /**
2680 * qla2x00_get_fcode_version() - Determine an FCODE image's version.
2681 * @ha: HA context
2682 * @pcids: Pointer to the FCODE PCI data structure
2683 *
2684 * The process of retrieving the FCODE version information is at best
2685 * described as interesting.
2686 *
2687 * Within the first 100h bytes of the image an ASCII string is present
2688 * which contains several pieces of information including the FCODE
2689 * version. Unfortunately it seems the only reliable way to retrieve
2690 * the version is by scanning for another sentinel within the string,
2691 * the FCODE build date:
2692 *
2693 * ... 2.00.02 10/17/02 ...
2694 *
2695 * Returns QLA_SUCCESS on successful retrieval of version.
2696 */
2697 static void
2698 qla2x00_get_fcode_version(struct qla_hw_data *ha, uint32_t pcids)
2699 {
2700 int ret = QLA_FUNCTION_FAILED;
2701 uint32_t istart, iend, iter, vend;
2702 uint8_t do_next, rbyte, *vbyte;
2703
2704 memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision));
2705
2706 /* Skip the PCI data structure. */
2707 istart = pcids +
2708 ((qla2x00_read_flash_byte(ha, pcids + 0x0B) << 8) |
2709 qla2x00_read_flash_byte(ha, pcids + 0x0A));
2710 iend = istart + 0x100;
2711 do {
2712 /* Scan for the sentinel date string...eeewww. */
2713 do_next = 0;
2714 iter = istart;
2715 while ((iter < iend) && !do_next) {
2716 iter++;
2717 if (qla2x00_read_flash_byte(ha, iter) == '/') {
2718 if (qla2x00_read_flash_byte(ha, iter + 2) ==
2719 '/')
2720 do_next++;
2721 else if (qla2x00_read_flash_byte(ha,
2722 iter + 3) == '/')
2723 do_next++;
2724 }
2725 }
2726 if (!do_next)
2727 break;
2728
2729 /* Backtrack to previous ' ' (space). */
2730 do_next = 0;
2731 while ((iter > istart) && !do_next) {
2732 iter--;
2733 if (qla2x00_read_flash_byte(ha, iter) == ' ')
2734 do_next++;
2735 }
2736 if (!do_next)
2737 break;
2738
2739 /*
2740 * Mark end of version tag, and find previous ' ' (space) or
2741 * string length (recent FCODE images -- major hack ahead!!!).
2742 */
2743 vend = iter - 1;
2744 do_next = 0;
2745 while ((iter > istart) && !do_next) {
2746 iter--;
2747 rbyte = qla2x00_read_flash_byte(ha, iter);
2748 if (rbyte == ' ' || rbyte == 0xd || rbyte == 0x10)
2749 do_next++;
2750 }
2751 if (!do_next)
2752 break;
2753
2754 /* Mark beginning of version tag, and copy data. */
2755 iter++;
2756 if ((vend - iter) &&
2757 ((vend - iter) < sizeof(ha->fcode_revision))) {
2758 vbyte = ha->fcode_revision;
2759 while (iter <= vend) {
2760 *vbyte++ = qla2x00_read_flash_byte(ha, iter);
2761 iter++;
2762 }
2763 ret = QLA_SUCCESS;
2764 }
2765 } while (0);
2766
2767 if (ret != QLA_SUCCESS)
2768 memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision));
2769 }
2770
2771 int
2772 qla2x00_get_flash_version(scsi_qla_host_t *vha, void *mbuf)
2773 {
2774 int ret = QLA_SUCCESS;
2775 uint8_t code_type, last_image;
2776 uint32_t pcihdr, pcids;
2777 uint8_t *dbyte;
2778 uint16_t *dcode;
2779 struct qla_hw_data *ha = vha->hw;
2780
2781 if (!ha->pio_address || !mbuf)
2782 return QLA_FUNCTION_FAILED;
2783
2784 memset(ha->bios_revision, 0, sizeof(ha->bios_revision));
2785 memset(ha->efi_revision, 0, sizeof(ha->efi_revision));
2786 memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision));
2787 memset(ha->fw_revision, 0, sizeof(ha->fw_revision));
2788
2789 qla2x00_flash_enable(ha);
2790
2791 /* Begin with first PCI expansion ROM header. */
2792 pcihdr = 0;
2793 last_image = 1;
2794 do {
2795 /* Verify PCI expansion ROM header. */
2796 if (qla2x00_read_flash_byte(ha, pcihdr) != 0x55 ||
2797 qla2x00_read_flash_byte(ha, pcihdr + 0x01) != 0xaa) {
2798 /* No signature */
2799 ql_log(ql_log_fatal, vha, 0x0050,
2800 "No matching ROM signature.\n");
2801 ret = QLA_FUNCTION_FAILED;
2802 break;
2803 }
2804
2805 /* Locate PCI data structure. */
2806 pcids = pcihdr +
2807 ((qla2x00_read_flash_byte(ha, pcihdr + 0x19) << 8) |
2808 qla2x00_read_flash_byte(ha, pcihdr + 0x18));
2809
2810 /* Validate signature of PCI data structure. */
2811 if (qla2x00_read_flash_byte(ha, pcids) != 'P' ||
2812 qla2x00_read_flash_byte(ha, pcids + 0x1) != 'C' ||
2813 qla2x00_read_flash_byte(ha, pcids + 0x2) != 'I' ||
2814 qla2x00_read_flash_byte(ha, pcids + 0x3) != 'R') {
2815 /* Incorrect header. */
2816 ql_log(ql_log_fatal, vha, 0x0051,
2817 "PCI data struct not found pcir_adr=%x.\n", pcids);
2818 ret = QLA_FUNCTION_FAILED;
2819 break;
2820 }
2821
2822 /* Read version */
2823 code_type = qla2x00_read_flash_byte(ha, pcids + 0x14);
2824 switch (code_type) {
2825 case ROM_CODE_TYPE_BIOS:
2826 /* Intel x86, PC-AT compatible. */
2827 ha->bios_revision[0] =
2828 qla2x00_read_flash_byte(ha, pcids + 0x12);
2829 ha->bios_revision[1] =
2830 qla2x00_read_flash_byte(ha, pcids + 0x13);
2831 ql_dbg(ql_dbg_init, vha, 0x0052,
2832 "Read BIOS %d.%d.\n",
2833 ha->bios_revision[1], ha->bios_revision[0]);
2834 break;
2835 case ROM_CODE_TYPE_FCODE:
2836 /* Open Firmware standard for PCI (FCode). */
2837 /* Eeeewww... */
2838 qla2x00_get_fcode_version(ha, pcids);
2839 break;
2840 case ROM_CODE_TYPE_EFI:
2841 /* Extensible Firmware Interface (EFI). */
2842 ha->efi_revision[0] =
2843 qla2x00_read_flash_byte(ha, pcids + 0x12);
2844 ha->efi_revision[1] =
2845 qla2x00_read_flash_byte(ha, pcids + 0x13);
2846 ql_dbg(ql_dbg_init, vha, 0x0053,
2847 "Read EFI %d.%d.\n",
2848 ha->efi_revision[1], ha->efi_revision[0]);
2849 break;
2850 default:
2851 ql_log(ql_log_warn, vha, 0x0054,
2852 "Unrecognized code type %x at pcids %x.\n",
2853 code_type, pcids);
2854 break;
2855 }
2856
2857 last_image = qla2x00_read_flash_byte(ha, pcids + 0x15) & BIT_7;
2858
2859 /* Locate next PCI expansion ROM. */
2860 pcihdr += ((qla2x00_read_flash_byte(ha, pcids + 0x11) << 8) |
2861 qla2x00_read_flash_byte(ha, pcids + 0x10)) * 512;
2862 } while (!last_image);
2863
2864 if (IS_QLA2322(ha)) {
2865 /* Read firmware image information. */
2866 memset(ha->fw_revision, 0, sizeof(ha->fw_revision));
2867 dbyte = mbuf;
2868 memset(dbyte, 0, 8);
2869 dcode = (uint16_t *)dbyte;
2870
2871 qla2x00_read_flash_data(ha, dbyte, ha->flt_region_fw * 4 + 10,
2872 8);
2873 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x010a,
2874 "Dumping fw "
2875 "ver from flash:.\n");
2876 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x010b,
2877 (uint8_t *)dbyte, 8);
2878
2879 if ((dcode[0] == 0xffff && dcode[1] == 0xffff &&
2880 dcode[2] == 0xffff && dcode[3] == 0xffff) ||
2881 (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 &&
2882 dcode[3] == 0)) {
2883 ql_log(ql_log_warn, vha, 0x0057,
2884 "Unrecognized fw revision at %x.\n",
2885 ha->flt_region_fw * 4);
2886 } else {
2887 /* values are in big endian */
2888 ha->fw_revision[0] = dbyte[0] << 16 | dbyte[1];
2889 ha->fw_revision[1] = dbyte[2] << 16 | dbyte[3];
2890 ha->fw_revision[2] = dbyte[4] << 16 | dbyte[5];
2891 ql_dbg(ql_dbg_init, vha, 0x0058,
2892 "FW Version: "
2893 "%d.%d.%d.\n", ha->fw_revision[0],
2894 ha->fw_revision[1], ha->fw_revision[2]);
2895 }
2896 }
2897
2898 qla2x00_flash_disable(ha);
2899
2900 return ret;
2901 }
2902
2903 int
2904 qla82xx_get_flash_version(scsi_qla_host_t *vha, void *mbuf)
2905 {
2906 int ret = QLA_SUCCESS;
2907 uint32_t pcihdr, pcids;
2908 uint32_t *dcode;
2909 uint8_t *bcode;
2910 uint8_t code_type, last_image;
2911 struct qla_hw_data *ha = vha->hw;
2912
2913 if (!mbuf)
2914 return QLA_FUNCTION_FAILED;
2915
2916 memset(ha->bios_revision, 0, sizeof(ha->bios_revision));
2917 memset(ha->efi_revision, 0, sizeof(ha->efi_revision));
2918 memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision));
2919 memset(ha->fw_revision, 0, sizeof(ha->fw_revision));
2920
2921 dcode = mbuf;
2922
2923 /* Begin with first PCI expansion ROM header. */
2924 pcihdr = ha->flt_region_boot << 2;
2925 last_image = 1;
2926 do {
2927 /* Verify PCI expansion ROM header. */
2928 ha->isp_ops->read_optrom(vha, (uint8_t *)dcode, pcihdr,
2929 0x20 * 4);
2930 bcode = mbuf + (pcihdr % 4);
2931 if (bcode[0x0] != 0x55 || bcode[0x1] != 0xaa) {
2932 /* No signature */
2933 ql_log(ql_log_fatal, vha, 0x0154,
2934 "No matching ROM signature.\n");
2935 ret = QLA_FUNCTION_FAILED;
2936 break;
2937 }
2938
2939 /* Locate PCI data structure. */
2940 pcids = pcihdr + ((bcode[0x19] << 8) | bcode[0x18]);
2941
2942 ha->isp_ops->read_optrom(vha, (uint8_t *)dcode, pcids,
2943 0x20 * 4);
2944 bcode = mbuf + (pcihdr % 4);
2945
2946 /* Validate signature of PCI data structure. */
2947 if (bcode[0x0] != 'P' || bcode[0x1] != 'C' ||
2948 bcode[0x2] != 'I' || bcode[0x3] != 'R') {
2949 /* Incorrect header. */
2950 ql_log(ql_log_fatal, vha, 0x0155,
2951 "PCI data struct not found pcir_adr=%x.\n", pcids);
2952 ret = QLA_FUNCTION_FAILED;
2953 break;
2954 }
2955
2956 /* Read version */
2957 code_type = bcode[0x14];
2958 switch (code_type) {
2959 case ROM_CODE_TYPE_BIOS:
2960 /* Intel x86, PC-AT compatible. */
2961 ha->bios_revision[0] = bcode[0x12];
2962 ha->bios_revision[1] = bcode[0x13];
2963 ql_dbg(ql_dbg_init, vha, 0x0156,
2964 "Read BIOS %d.%d.\n",
2965 ha->bios_revision[1], ha->bios_revision[0]);
2966 break;
2967 case ROM_CODE_TYPE_FCODE:
2968 /* Open Firmware standard for PCI (FCode). */
2969 ha->fcode_revision[0] = bcode[0x12];
2970 ha->fcode_revision[1] = bcode[0x13];
2971 ql_dbg(ql_dbg_init, vha, 0x0157,
2972 "Read FCODE %d.%d.\n",
2973 ha->fcode_revision[1], ha->fcode_revision[0]);
2974 break;
2975 case ROM_CODE_TYPE_EFI:
2976 /* Extensible Firmware Interface (EFI). */
2977 ha->efi_revision[0] = bcode[0x12];
2978 ha->efi_revision[1] = bcode[0x13];
2979 ql_dbg(ql_dbg_init, vha, 0x0158,
2980 "Read EFI %d.%d.\n",
2981 ha->efi_revision[1], ha->efi_revision[0]);
2982 break;
2983 default:
2984 ql_log(ql_log_warn, vha, 0x0159,
2985 "Unrecognized code type %x at pcids %x.\n",
2986 code_type, pcids);
2987 break;
2988 }
2989
2990 last_image = bcode[0x15] & BIT_7;
2991
2992 /* Locate next PCI expansion ROM. */
2993 pcihdr += ((bcode[0x11] << 8) | bcode[0x10]) * 512;
2994 } while (!last_image);
2995
2996 /* Read firmware image information. */
2997 memset(ha->fw_revision, 0, sizeof(ha->fw_revision));
2998 dcode = mbuf;
2999 ha->isp_ops->read_optrom(vha, (uint8_t *)dcode, ha->flt_region_fw << 2,
3000 0x20);
3001 bcode = mbuf + (pcihdr % 4);
3002
3003 /* Validate signature of PCI data structure. */
3004 if (bcode[0x0] == 0x3 && bcode[0x1] == 0x0 &&
3005 bcode[0x2] == 0x40 && bcode[0x3] == 0x40) {
3006 ha->fw_revision[0] = bcode[0x4];
3007 ha->fw_revision[1] = bcode[0x5];
3008 ha->fw_revision[2] = bcode[0x6];
3009 ql_dbg(ql_dbg_init, vha, 0x0153,
3010 "Firmware revision %d.%d.%d\n",
3011 ha->fw_revision[0], ha->fw_revision[1],
3012 ha->fw_revision[2]);
3013 }
3014
3015 return ret;
3016 }
3017
3018 int
3019 qla24xx_get_flash_version(scsi_qla_host_t *vha, void *mbuf)
3020 {
3021 int ret = QLA_SUCCESS;
3022 uint32_t pcihdr, pcids;
3023 uint32_t *dcode;
3024 uint8_t *bcode;
3025 uint8_t code_type, last_image;
3026 int i;
3027 struct qla_hw_data *ha = vha->hw;
3028 uint32_t faddr = 0;
3029
3030 pcihdr = pcids = 0;
3031
3032 if (IS_P3P_TYPE(ha))
3033 return ret;
3034
3035 if (!mbuf)
3036 return QLA_FUNCTION_FAILED;
3037
3038 memset(ha->bios_revision, 0, sizeof(ha->bios_revision));
3039 memset(ha->efi_revision, 0, sizeof(ha->efi_revision));
3040 memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision));
3041 memset(ha->fw_revision, 0, sizeof(ha->fw_revision));
3042
3043 dcode = mbuf;
3044 pcihdr = ha->flt_region_boot << 2;
3045 if (IS_QLA27XX(ha) &&
3046 qla27xx_find_valid_image(vha) == QLA27XX_SECONDARY_IMAGE)
3047 pcihdr = ha->flt_region_boot_sec << 2;
3048
3049 last_image = 1;
3050 do {
3051 /* Verify PCI expansion ROM header. */
3052 qla24xx_read_flash_data(vha, dcode, pcihdr >> 2, 0x20);
3053 bcode = mbuf + (pcihdr % 4);
3054 if (bcode[0x0] != 0x55 || bcode[0x1] != 0xaa) {
3055 /* No signature */
3056 ql_log(ql_log_fatal, vha, 0x0059,
3057 "No matching ROM signature.\n");
3058 ret = QLA_FUNCTION_FAILED;
3059 break;
3060 }
3061
3062 /* Locate PCI data structure. */
3063 pcids = pcihdr + ((bcode[0x19] << 8) | bcode[0x18]);
3064
3065 qla24xx_read_flash_data(vha, dcode, pcids >> 2, 0x20);
3066 bcode = mbuf + (pcihdr % 4);
3067
3068 /* Validate signature of PCI data structure. */
3069 if (bcode[0x0] != 'P' || bcode[0x1] != 'C' ||
3070 bcode[0x2] != 'I' || bcode[0x3] != 'R') {
3071 /* Incorrect header. */
3072 ql_log(ql_log_fatal, vha, 0x005a,
3073 "PCI data struct not found pcir_adr=%x.\n", pcids);
3074 ret = QLA_FUNCTION_FAILED;
3075 break;
3076 }
3077
3078 /* Read version */
3079 code_type = bcode[0x14];
3080 switch (code_type) {
3081 case ROM_CODE_TYPE_BIOS:
3082 /* Intel x86, PC-AT compatible. */
3083 ha->bios_revision[0] = bcode[0x12];
3084 ha->bios_revision[1] = bcode[0x13];
3085 ql_dbg(ql_dbg_init, vha, 0x005b,
3086 "Read BIOS %d.%d.\n",
3087 ha->bios_revision[1], ha->bios_revision[0]);
3088 break;
3089 case ROM_CODE_TYPE_FCODE:
3090 /* Open Firmware standard for PCI (FCode). */
3091 ha->fcode_revision[0] = bcode[0x12];
3092 ha->fcode_revision[1] = bcode[0x13];
3093 ql_dbg(ql_dbg_init, vha, 0x005c,
3094 "Read FCODE %d.%d.\n",
3095 ha->fcode_revision[1], ha->fcode_revision[0]);
3096 break;
3097 case ROM_CODE_TYPE_EFI:
3098 /* Extensible Firmware Interface (EFI). */
3099 ha->efi_revision[0] = bcode[0x12];
3100 ha->efi_revision[1] = bcode[0x13];
3101 ql_dbg(ql_dbg_init, vha, 0x005d,
3102 "Read EFI %d.%d.\n",
3103 ha->efi_revision[1], ha->efi_revision[0]);
3104 break;
3105 default:
3106 ql_log(ql_log_warn, vha, 0x005e,
3107 "Unrecognized code type %x at pcids %x.\n",
3108 code_type, pcids);
3109 break;
3110 }
3111
3112 last_image = bcode[0x15] & BIT_7;
3113
3114 /* Locate next PCI expansion ROM. */
3115 pcihdr += ((bcode[0x11] << 8) | bcode[0x10]) * 512;
3116 } while (!last_image);
3117
3118 /* Read firmware image information. */
3119 memset(ha->fw_revision, 0, sizeof(ha->fw_revision));
3120 dcode = mbuf;
3121 faddr = ha->flt_region_fw;
3122 if (IS_QLA27XX(ha) &&
3123 qla27xx_find_valid_image(vha) == QLA27XX_SECONDARY_IMAGE)
3124 faddr = ha->flt_region_fw_sec;
3125
3126 qla24xx_read_flash_data(vha, dcode, faddr + 4, 4);
3127 for (i = 0; i < 4; i++)
3128 dcode[i] = be32_to_cpu(dcode[i]);
3129
3130 if ((dcode[0] == 0xffffffff && dcode[1] == 0xffffffff &&
3131 dcode[2] == 0xffffffff && dcode[3] == 0xffffffff) ||
3132 (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 &&
3133 dcode[3] == 0)) {
3134 ql_log(ql_log_warn, vha, 0x005f,
3135 "Unrecognized fw revision at %x.\n",
3136 ha->flt_region_fw * 4);
3137 } else {
3138 ha->fw_revision[0] = dcode[0];
3139 ha->fw_revision[1] = dcode[1];
3140 ha->fw_revision[2] = dcode[2];
3141 ha->fw_revision[3] = dcode[3];
3142 ql_dbg(ql_dbg_init, vha, 0x0060,
3143 "Firmware revision %d.%d.%d (%x).\n",
3144 ha->fw_revision[0], ha->fw_revision[1],
3145 ha->fw_revision[2], ha->fw_revision[3]);
3146 }
3147
3148 /* Check for golden firmware and get version if available */
3149 if (!IS_QLA81XX(ha)) {
3150 /* Golden firmware is not present in non 81XX adapters */
3151 return ret;
3152 }
3153
3154 memset(ha->gold_fw_version, 0, sizeof(ha->gold_fw_version));
3155 dcode = mbuf;
3156 ha->isp_ops->read_optrom(vha, (uint8_t *)dcode,
3157 ha->flt_region_gold_fw << 2, 32);
3158
3159 if (dcode[4] == 0xFFFFFFFF && dcode[5] == 0xFFFFFFFF &&
3160 dcode[6] == 0xFFFFFFFF && dcode[7] == 0xFFFFFFFF) {
3161 ql_log(ql_log_warn, vha, 0x0056,
3162 "Unrecognized golden fw at 0x%x.\n",
3163 ha->flt_region_gold_fw * 4);
3164 return ret;
3165 }
3166
3167 for (i = 4; i < 8; i++)
3168 ha->gold_fw_version[i-4] = be32_to_cpu(dcode[i]);
3169
3170 return ret;
3171 }
3172
3173 static int
3174 qla2xxx_is_vpd_valid(uint8_t *pos, uint8_t *end)
3175 {
3176 if (pos >= end || *pos != 0x82)
3177 return 0;
3178
3179 pos += 3 + pos[1];
3180 if (pos >= end || *pos != 0x90)
3181 return 0;
3182
3183 pos += 3 + pos[1];
3184 if (pos >= end || *pos != 0x78)
3185 return 0;
3186
3187 return 1;
3188 }
3189
3190 int
3191 qla2xxx_get_vpd_field(scsi_qla_host_t *vha, char *key, char *str, size_t size)
3192 {
3193 struct qla_hw_data *ha = vha->hw;
3194 uint8_t *pos = ha->vpd;
3195 uint8_t *end = pos + ha->vpd_size;
3196 int len = 0;
3197
3198 if (!IS_FWI2_CAPABLE(ha) || !qla2xxx_is_vpd_valid(pos, end))
3199 return 0;
3200
3201 while (pos < end && *pos != 0x78) {
3202 len = (*pos == 0x82) ? pos[1] : pos[2];
3203
3204 if (!strncmp(pos, key, strlen(key)))
3205 break;
3206
3207 if (*pos != 0x90 && *pos != 0x91)
3208 pos += len;
3209
3210 pos += 3;
3211 }
3212
3213 if (pos < end - len && *pos != 0x78)
3214 return scnprintf(str, size, "%.*s", len, pos + 3);
3215
3216 return 0;
3217 }
3218
3219 int
3220 qla24xx_read_fcp_prio_cfg(scsi_qla_host_t *vha)
3221 {
3222 int len, max_len;
3223 uint32_t fcp_prio_addr;
3224 struct qla_hw_data *ha = vha->hw;
3225
3226 if (!ha->fcp_prio_cfg) {
3227 ha->fcp_prio_cfg = vmalloc(FCP_PRIO_CFG_SIZE);
3228 if (!ha->fcp_prio_cfg) {
3229 ql_log(ql_log_warn, vha, 0x00d5,
3230 "Unable to allocate memory for fcp priority data (%x).\n",
3231 FCP_PRIO_CFG_SIZE);
3232 return QLA_FUNCTION_FAILED;
3233 }
3234 }
3235 memset(ha->fcp_prio_cfg, 0, FCP_PRIO_CFG_SIZE);
3236
3237 fcp_prio_addr = ha->flt_region_fcp_prio;
3238
3239 /* first read the fcp priority data header from flash */
3240 ha->isp_ops->read_optrom(vha, (uint8_t *)ha->fcp_prio_cfg,
3241 fcp_prio_addr << 2, FCP_PRIO_CFG_HDR_SIZE);
3242
3243 if (!qla24xx_fcp_prio_cfg_valid(vha, ha->fcp_prio_cfg, 0))
3244 goto fail;
3245
3246 /* read remaining FCP CMD config data from flash */
3247 fcp_prio_addr += (FCP_PRIO_CFG_HDR_SIZE >> 2);
3248 len = ha->fcp_prio_cfg->num_entries * FCP_PRIO_CFG_ENTRY_SIZE;
3249 max_len = FCP_PRIO_CFG_SIZE - FCP_PRIO_CFG_HDR_SIZE;
3250
3251 ha->isp_ops->read_optrom(vha, (uint8_t *)&ha->fcp_prio_cfg->entry[0],
3252 fcp_prio_addr << 2, (len < max_len ? len : max_len));
3253
3254 /* revalidate the entire FCP priority config data, including entries */
3255 if (!qla24xx_fcp_prio_cfg_valid(vha, ha->fcp_prio_cfg, 1))
3256 goto fail;
3257
3258 ha->flags.fcp_prio_enabled = 1;
3259 return QLA_SUCCESS;
3260 fail:
3261 vfree(ha->fcp_prio_cfg);
3262 ha->fcp_prio_cfg = NULL;
3263 return QLA_FUNCTION_FAILED;
3264 }
Linux with added FPC-III support