drivers/scsi/ufs/ufshci.h

   1 /*
   2  * Universal Flash Storage Host controller driver
   3  *
   4  * This code is based on drivers/scsi/ufs/ufshci.h
   5  * Copyright (C) 2011-2013 Samsung India Software Operations
   6  *
   7  * Authors:
   8  *      Santosh Yaraganavi <santosh.sy@samsung.com>
   9  *      Vinayak Holikatti <h.vinayak@samsung.com>
  10  *
  11  * This program is free software; you can redistribute it and/or
  12  * modify it under the terms of the GNU General Public License
  13  * as published by the Free Software Foundation; either version 2
  14  * of the License, or (at your option) any later version.
  15  * See the COPYING file in the top-level directory or visit
  16  * <http://www.gnu.org/licenses/gpl-2.0.html>
  17  *
  18  * This program is distributed in the hope that it will be useful,
  19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  21  * GNU General Public License for more details.
  22  *
  23  * This program is provided "AS IS" and "WITH ALL FAULTS" and
  24  * without warranty of any kind. You are solely responsible for
  25  * determining the appropriateness of using and distributing
  26  * the program and assume all risks associated with your exercise
  27  * of rights with respect to the program, including but not limited
  28  * to infringement of third party rights, the risks and costs of
  29  * program errors, damage to or loss of data, programs or equipment,
  30  * and unavailability or interruption of operations. Under no
  31  * circumstances will the contributor of this Program be liable for
  32  * any damages of any kind arising from your use or distribution of
  33  * this program.
  34  */
  35
  36 #ifndef _UFSHCI_H
  37 #define _UFSHCI_H
  38
  39 enum {
  40         TASK_REQ_UPIU_SIZE_DWORDS       = 8,
  41         TASK_RSP_UPIU_SIZE_DWORDS       = 8,
  42         ALIGNED_UPIU_SIZE               = 512,
  43 };
  44
  45 /* UFSHCI Registers */
  46 enum {
  47         REG_CONTROLLER_CAPABILITIES             = 0x00,
  48         REG_UFS_VERSION                         = 0x08,
  49         REG_CONTROLLER_DEV_ID                   = 0x10,
  50         REG_CONTROLLER_PROD_ID                  = 0x14,
  51         REG_AUTO_HIBERNATE_IDLE_TIMER           = 0x18,
  52         REG_INTERRUPT_STATUS                    = 0x20,
  53         REG_INTERRUPT_ENABLE                    = 0x24,
  54         REG_CONTROLLER_STATUS                   = 0x30,
  55         REG_CONTROLLER_ENABLE                   = 0x34,
  56         REG_UIC_ERROR_CODE_PHY_ADAPTER_LAYER    = 0x38,
  57         REG_UIC_ERROR_CODE_DATA_LINK_LAYER      = 0x3C,
  58         REG_UIC_ERROR_CODE_NETWORK_LAYER        = 0x40,
  59         REG_UIC_ERROR_CODE_TRANSPORT_LAYER      = 0x44,
  60         REG_UIC_ERROR_CODE_DME                  = 0x48,
  61         REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL    = 0x4C,
  62         REG_UTP_TRANSFER_REQ_LIST_BASE_L        = 0x50,
  63         REG_UTP_TRANSFER_REQ_LIST_BASE_H        = 0x54,
  64         REG_UTP_TRANSFER_REQ_DOOR_BELL          = 0x58,
  65         REG_UTP_TRANSFER_REQ_LIST_CLEAR         = 0x5C,
  66         REG_UTP_TRANSFER_REQ_LIST_RUN_STOP      = 0x60,
  67         REG_UTP_TASK_REQ_LIST_BASE_L            = 0x70,
  68         REG_UTP_TASK_REQ_LIST_BASE_H            = 0x74,
  69         REG_UTP_TASK_REQ_DOOR_BELL              = 0x78,
  70         REG_UTP_TASK_REQ_LIST_CLEAR             = 0x7C,
  71         REG_UTP_TASK_REQ_LIST_RUN_STOP          = 0x80,
  72         REG_UIC_COMMAND                         = 0x90,
  73         REG_UIC_COMMAND_ARG_1                   = 0x94,
  74         REG_UIC_COMMAND_ARG_2                   = 0x98,
  75         REG_UIC_COMMAND_ARG_3                   = 0x9C,
  76
  77         UFSHCI_REG_SPACE_SIZE                   = 0xA0,
  78
  79         REG_UFS_CCAP                            = 0x100,
  80         REG_UFS_CRYPTOCAP                       = 0x104,
  81
  82         UFSHCI_CRYPTO_REG_SPACE_SIZE            = 0x400,
  83 };
  84
  85 /* Controller capability masks */
  86 enum {
  87         MASK_TRANSFER_REQUESTS_SLOTS            = 0x0000001F,
  88         MASK_TASK_MANAGEMENT_REQUEST_SLOTS      = 0x00070000,
  89         MASK_AUTO_HIBERN8_SUPPORT               = 0x00800000,
  90         MASK_64_ADDRESSING_SUPPORT              = 0x01000000,
  91         MASK_OUT_OF_ORDER_DATA_DELIVERY_SUPPORT = 0x02000000,
  92         MASK_UIC_DME_TEST_MODE_SUPPORT          = 0x04000000,
  93 };
  94
  95 #define UFS_MASK(mask, offset)          ((mask) << (offset))
  96
  97 /* UFS Version 08h */
  98 #define MINOR_VERSION_NUM_MASK          UFS_MASK(0xFFFF, 0)
  99 #define MAJOR_VERSION_NUM_MASK          UFS_MASK(0xFFFF, 16)
 100
 101 /* Controller UFSHCI version */
 102 enum {
 103         UFSHCI_VERSION_10 = 0x00010000, /* 1.0 */
 104         UFSHCI_VERSION_11 = 0x00010100, /* 1.1 */
 105         UFSHCI_VERSION_20 = 0x00000200, /* 2.0 */
 106         UFSHCI_VERSION_21 = 0x00000210, /* 2.1 */
 107 };
 108
 109 /*
 110  * HCDDID - Host Controller Identification Descriptor
 111  *        - Device ID and Device Class 10h
 112  */
 113 #define DEVICE_CLASS    UFS_MASK(0xFFFF, 0)
 114 #define DEVICE_ID       UFS_MASK(0xFF, 24)
 115
 116 /*
 117  * HCPMID - Host Controller Identification Descriptor
 118  *        - Product/Manufacturer ID  14h
 119  */
 120 #define MANUFACTURE_ID_MASK     UFS_MASK(0xFFFF, 0)
 121 #define PRODUCT_ID_MASK         UFS_MASK(0xFFFF, 16)
 122
 123 /* AHIT - Auto-Hibernate Idle Timer */
 124 #define UFSHCI_AHIBERN8_TIMER_MASK              GENMASK(9, 0)
 125 #define UFSHCI_AHIBERN8_SCALE_MASK              GENMASK(12, 10)
 126 #define UFSHCI_AHIBERN8_SCALE_FACTOR            10
 127 #define UFSHCI_AHIBERN8_MAX                     (1023 * 100000)
 128
 129 /*
 130  * IS - Interrupt Status - 20h
 131  */
 132 #define UTP_TRANSFER_REQ_COMPL                  0x1
 133 #define UIC_DME_END_PT_RESET                    0x2
 134 #define UIC_ERROR                               0x4
 135 #define UIC_TEST_MODE                           0x8
 136 #define UIC_POWER_MODE                          0x10
 137 #define UIC_HIBERNATE_EXIT                      0x20
 138 #define UIC_HIBERNATE_ENTER                     0x40
 139 #define UIC_LINK_LOST                           0x80
 140 #define UIC_LINK_STARTUP                        0x100
 141 #define UTP_TASK_REQ_COMPL                      0x200
 142 #define UIC_COMMAND_COMPL                       0x400
 143 #define DEVICE_FATAL_ERROR                      0x800
 144 #define CONTROLLER_FATAL_ERROR                  0x10000
 145 #define SYSTEM_BUS_FATAL_ERROR                  0x20000
 146
 147 #define UFSHCD_UIC_PWR_MASK     (UIC_HIBERNATE_ENTER |\
 148                                 UIC_HIBERNATE_EXIT |\
 149                                 UIC_POWER_MODE)
 150
 151 #define UFSHCD_UIC_MASK         (UIC_COMMAND_COMPL | UFSHCD_UIC_PWR_MASK)
 152
 153 #define UFSHCD_ERROR_MASK       (UIC_ERROR |\
 154                                 DEVICE_FATAL_ERROR |\
 155                                 CONTROLLER_FATAL_ERROR |\
 156                                 SYSTEM_BUS_FATAL_ERROR)
 157
 158 #define INT_FATAL_ERRORS        (DEVICE_FATAL_ERROR |\
 159                                 CONTROLLER_FATAL_ERROR |\
 160                                 SYSTEM_BUS_FATAL_ERROR)
 161
 162 /* HCS - Host Controller Status 30h */
 163 #define DEVICE_PRESENT                          0x1
 164 #define UTP_TRANSFER_REQ_LIST_READY             0x2
 165 #define UTP_TASK_REQ_LIST_READY                 0x4
 166 #define UIC_COMMAND_READY                       0x8
 167 #define HOST_ERROR_INDICATOR                    0x10
 168 #define DEVICE_ERROR_INDICATOR                  0x20
 169 #define UIC_POWER_MODE_CHANGE_REQ_STATUS_MASK   UFS_MASK(0x7, 8)
 170
 171 #define UFSHCD_STATUS_READY     (UTP_TRANSFER_REQ_LIST_READY |\
 172                                 UTP_TASK_REQ_LIST_READY |\
 173                                 UIC_COMMAND_READY)
 174
 175 enum {
 176         PWR_OK          = 0x0,
 177         PWR_LOCAL       = 0x01,
 178         PWR_REMOTE      = 0x02,
 179         PWR_BUSY        = 0x03,
 180         PWR_ERROR_CAP   = 0x04,
 181         PWR_FATAL_ERROR = 0x05,
 182 };
 183
 184 /* HCE - Host Controller Enable 34h */
 185 #define CONTROLLER_ENABLE       0x1
 186 #define CONTROLLER_DISABLE      0x0
 187 #define CRYPTO_GENERAL_ENABLE   0x2
 188
 189 /* UECPA - Host UIC Error Code PHY Adapter Layer 38h */
 190 #define UIC_PHY_ADAPTER_LAYER_ERROR                     0x80000000
 191 #define UIC_PHY_ADAPTER_LAYER_ERROR_CODE_MASK           0x1F
 192 #define UIC_PHY_ADAPTER_LAYER_LANE_ERR_MASK             0xF
 193
 194 /* UECDL - Host UIC Error Code Data Link Layer 3Ch */
 195 #define UIC_DATA_LINK_LAYER_ERROR               0x80000000
 196 #define UIC_DATA_LINK_LAYER_ERROR_CODE_MASK     0x7FFF
 197 #define UIC_DATA_LINK_LAYER_ERROR_TCX_REP_TIMER_EXP     0x2
 198 #define UIC_DATA_LINK_LAYER_ERROR_AFCX_REQ_TIMER_EXP    0x4
 199 #define UIC_DATA_LINK_LAYER_ERROR_FCX_PRO_TIMER_EXP     0x8
 200 #define UIC_DATA_LINK_LAYER_ERROR_RX_BUF_OF     0x20
 201 #define UIC_DATA_LINK_LAYER_ERROR_PA_INIT       0x2000
 202 #define UIC_DATA_LINK_LAYER_ERROR_NAC_RECEIVED  0x0001
 203 #define UIC_DATA_LINK_LAYER_ERROR_TCx_REPLAY_TIMEOUT 0x0002
 204
 205 /* UECN - Host UIC Error Code Network Layer 40h */
 206 #define UIC_NETWORK_LAYER_ERROR                 0x80000000
 207 #define UIC_NETWORK_LAYER_ERROR_CODE_MASK       0x7
 208 #define UIC_NETWORK_UNSUPPORTED_HEADER_TYPE     0x1
 209 #define UIC_NETWORK_BAD_DEVICEID_ENC            0x2
 210 #define UIC_NETWORK_LHDR_TRAP_PACKET_DROPPING   0x4
 211
 212 /* UECT - Host UIC Error Code Transport Layer 44h */
 213 #define UIC_TRANSPORT_LAYER_ERROR               0x80000000
 214 #define UIC_TRANSPORT_LAYER_ERROR_CODE_MASK     0x7F
 215 #define UIC_TRANSPORT_UNSUPPORTED_HEADER_TYPE   0x1
 216 #define UIC_TRANSPORT_UNKNOWN_CPORTID           0x2
 217 #define UIC_TRANSPORT_NO_CONNECTION_RX          0x4
 218 #define UIC_TRANSPORT_CONTROLLED_SEGMENT_DROPPING       0x8
 219 #define UIC_TRANSPORT_BAD_TC                    0x10
 220 #define UIC_TRANSPORT_E2E_CREDIT_OVERFOW        0x20
 221 #define UIC_TRANSPORT_SAFETY_VALUE_DROPPING     0x40
 222
 223 /* UECDME - Host UIC Error Code DME 48h */
 224 #define UIC_DME_ERROR                   0x80000000
 225 #define UIC_DME_ERROR_CODE_MASK         0x1
 226
 227 /* UTRIACR - Interrupt Aggregation control register - 0x4Ch */
 228 #define INT_AGGR_TIMEOUT_VAL_MASK               0xFF
 229 #define INT_AGGR_COUNTER_THRESHOLD_MASK         UFS_MASK(0x1F, 8)
 230 #define INT_AGGR_COUNTER_AND_TIMER_RESET        0x10000
 231 #define INT_AGGR_STATUS_BIT                     0x100000
 232 #define INT_AGGR_PARAM_WRITE                    0x1000000
 233 #define INT_AGGR_ENABLE                         0x80000000
 234
 235 /* UTRLRSR - UTP Transfer Request Run-Stop Register 60h */
 236 #define UTP_TRANSFER_REQ_LIST_RUN_STOP_BIT      0x1
 237
 238 /* UTMRLRSR - UTP Task Management Request Run-Stop Register 80h */
 239 #define UTP_TASK_REQ_LIST_RUN_STOP_BIT          0x1
 240
 241 /* UICCMD - UIC Command */
 242 #define COMMAND_OPCODE_MASK             0xFF
 243 #define GEN_SELECTOR_INDEX_MASK         0xFFFF
 244
 245 #define MIB_ATTRIBUTE_MASK              UFS_MASK(0xFFFF, 16)
 246 #define RESET_LEVEL                     0xFF
 247
 248 #define ATTR_SET_TYPE_MASK              UFS_MASK(0xFF, 16)
 249 #define CONFIG_RESULT_CODE_MASK         0xFF
 250 #define GENERIC_ERROR_CODE_MASK         0xFF
 251
 252 /* GenSelectorIndex calculation macros for M-PHY attributes */
 253 #define UIC_ARG_MPHY_TX_GEN_SEL_INDEX(lane) (lane)
 254 #define UIC_ARG_MPHY_RX_GEN_SEL_INDEX(lane) (PA_MAXDATALANES + (lane))
 255
 256 #define UIC_ARG_MIB_SEL(attr, sel)      ((((attr) & 0xFFFF) << 16) |\
 257                                          ((sel) & 0xFFFF))
 258 #define UIC_ARG_MIB(attr)               UIC_ARG_MIB_SEL(attr, 0)
 259 #define UIC_ARG_ATTR_TYPE(t)            (((t) & 0xFF) << 16)
 260 #define UIC_GET_ATTR_ID(v)              (((v) >> 16) & 0xFFFF)
 261
 262 /* Link Status*/
 263 enum link_status {
 264         UFSHCD_LINK_IS_DOWN     = 1,
 265         UFSHCD_LINK_IS_UP       = 2,
 266 };
 267
 268 /* UIC Commands */
 269 enum uic_cmd_dme {
 270         UIC_CMD_DME_GET                 = 0x01,
 271         UIC_CMD_DME_SET                 = 0x02,
 272         UIC_CMD_DME_PEER_GET            = 0x03,
 273         UIC_CMD_DME_PEER_SET            = 0x04,
 274         UIC_CMD_DME_POWERON             = 0x10,
 275         UIC_CMD_DME_POWEROFF            = 0x11,
 276         UIC_CMD_DME_ENABLE              = 0x12,
 277         UIC_CMD_DME_RESET               = 0x14,
 278         UIC_CMD_DME_END_PT_RST          = 0x15,
 279         UIC_CMD_DME_LINK_STARTUP        = 0x16,
 280         UIC_CMD_DME_HIBER_ENTER         = 0x17,
 281         UIC_CMD_DME_HIBER_EXIT          = 0x18,
 282         UIC_CMD_DME_TEST_MODE           = 0x1A,
 283 };
 284
 285 /* UIC Config result code / Generic error code */
 286 enum {
 287         UIC_CMD_RESULT_SUCCESS                  = 0x00,
 288         UIC_CMD_RESULT_INVALID_ATTR             = 0x01,
 289         UIC_CMD_RESULT_FAILURE                  = 0x01,
 290         UIC_CMD_RESULT_INVALID_ATTR_VALUE       = 0x02,
 291         UIC_CMD_RESULT_READ_ONLY_ATTR           = 0x03,
 292         UIC_CMD_RESULT_WRITE_ONLY_ATTR          = 0x04,
 293         UIC_CMD_RESULT_BAD_INDEX                = 0x05,
 294         UIC_CMD_RESULT_LOCKED_ATTR              = 0x06,
 295         UIC_CMD_RESULT_BAD_TEST_FEATURE_INDEX   = 0x07,
 296         UIC_CMD_RESULT_PEER_COMM_FAILURE        = 0x08,
 297         UIC_CMD_RESULT_BUSY                     = 0x09,
 298         UIC_CMD_RESULT_DME_FAILURE              = 0x0A,
 299 };
 300
 301 #define MASK_UIC_COMMAND_RESULT                 0xFF
 302
 303 #define INT_AGGR_COUNTER_THLD_VAL(c)    (((c) & 0x1F) << 8)
 304 #define INT_AGGR_TIMEOUT_VAL(t)         (((t) & 0xFF) << 0)
 305
 306 /* Interrupt disable masks */
 307 enum {
 308         /* Interrupt disable mask for UFSHCI v1.0 */
 309         INTERRUPT_MASK_ALL_VER_10       = 0x30FFF,
 310         INTERRUPT_MASK_RW_VER_10        = 0x30000,
 311
 312         /* Interrupt disable mask for UFSHCI v1.1 */
 313         INTERRUPT_MASK_ALL_VER_11       = 0x31FFF,
 314
 315         /* Interrupt disable mask for UFSHCI v2.1 */
 316         INTERRUPT_MASK_ALL_VER_21       = 0x71FFF,
 317 };
 318
 319 /*
 320  * Request Descriptor Definitions
 321  */
 322
 323 /* Transfer request command type */
 324 enum {
 325         UTP_CMD_TYPE_SCSI               = 0x0,
 326         UTP_CMD_TYPE_UFS                = 0x1,
 327         UTP_CMD_TYPE_DEV_MANAGE         = 0x2,
 328 };
 329
 330 /* To accommodate UFS2.0 required Command type */
 331 enum {
 332         UTP_CMD_TYPE_UFS_STORAGE        = 0x1,
 333 };
 334
 335 enum {
 336         UTP_SCSI_COMMAND                = 0x00000000,
 337         UTP_NATIVE_UFS_COMMAND          = 0x10000000,
 338         UTP_DEVICE_MANAGEMENT_FUNCTION  = 0x20000000,
 339         UTP_REQ_DESC_INT_CMD            = 0x01000000,
 340 };
 341
 342 /* UTP Transfer Request Data Direction (DD) */
 343 enum {
 344         UTP_NO_DATA_TRANSFER    = 0x00000000,
 345         UTP_HOST_TO_DEVICE      = 0x02000000,
 346         UTP_DEVICE_TO_HOST      = 0x04000000,
 347 };
 348
 349 /* Overall command status values */
 350 enum {
 351         OCS_SUCCESS                     = 0x0,
 352         OCS_INVALID_CMD_TABLE_ATTR      = 0x1,
 353         OCS_INVALID_PRDT_ATTR           = 0x2,
 354         OCS_MISMATCH_DATA_BUF_SIZE      = 0x3,
 355         OCS_MISMATCH_RESP_UPIU_SIZE     = 0x4,
 356         OCS_PEER_COMM_FAILURE           = 0x5,
 357         OCS_ABORTED                     = 0x6,
 358         OCS_FATAL_ERROR                 = 0x7,
 359         OCS_INVALID_COMMAND_STATUS      = 0x0F,
 360         MASK_OCS                        = 0x0F,
 361 };
 362
 363 /* The maximum length of the data byte count field in the PRDT is 256KB */
 364 #define PRDT_DATA_BYTE_COUNT_MAX        (256 * 1024)
 365 /* The granularity of the data byte count field in the PRDT is 32-bit */
 366 #define PRDT_DATA_BYTE_COUNT_PAD        4
 367
 368 /**
 369  * struct ufshcd_sg_entry - UFSHCI PRD Entry
 370  * @base_addr: Lower 32bit physical address DW-0
 371  * @upper_addr: Upper 32bit physical address DW-1
 372  * @reserved: Reserved for future use DW-2
 373  * @size: size of physical segment DW-3
 374  */
 375 struct ufshcd_sg_entry {
 376         __le32    base_addr;
 377         __le32    upper_addr;
 378         __le32    reserved;
 379         __le32    size;
 380 };
 381
 382 /**
 383  * struct utp_transfer_cmd_desc - UFS Command Descriptor structure
 384  * @command_upiu: Command UPIU Frame address
 385  * @response_upiu: Response UPIU Frame address
 386  * @prd_table: Physical Region Descriptor
 387  */
 388 struct utp_transfer_cmd_desc {
 389         u8 command_upiu[ALIGNED_UPIU_SIZE];
 390         u8 response_upiu[ALIGNED_UPIU_SIZE];
 391         struct ufshcd_sg_entry    prd_table[SG_ALL];
 392 };
 393
 394 /**
 395  * struct request_desc_header - Descriptor Header common to both UTRD and UTMRD
 396  * @dword0: Descriptor Header DW0
 397  * @dword1: Descriptor Header DW1
 398  * @dword2: Descriptor Header DW2
 399  * @dword3: Descriptor Header DW3
 400  */
 401 struct request_desc_header {
 402         __le32 dword_0;
 403         __le32 dword_1;
 404         __le32 dword_2;
 405         __le32 dword_3;
 406 };
 407
 408 /**
 409  * struct utp_transfer_req_desc - UTRD structure
 410  * @header: UTRD header DW-0 to DW-3
 411  * @command_desc_base_addr_lo: UCD base address low DW-4
 412  * @command_desc_base_addr_hi: UCD base address high DW-5
 413  * @response_upiu_length: response UPIU length DW-6
 414  * @response_upiu_offset: response UPIU offset DW-6
 415  * @prd_table_length: Physical region descriptor length DW-7
 416  * @prd_table_offset: Physical region descriptor offset DW-7
 417  */
 418 struct utp_transfer_req_desc {
 419
 420         /* DW 0-3 */
 421         struct request_desc_header header;
 422
 423         /* DW 4-5*/
 424         __le32  command_desc_base_addr_lo;
 425         __le32  command_desc_base_addr_hi;
 426
 427         /* DW 6 */
 428         __le16  response_upiu_length;
 429         __le16  response_upiu_offset;
 430
 431         /* DW 7 */
 432         __le16  prd_table_length;
 433         __le16  prd_table_offset;
 434 };
 435
 436 /*
 437  * UTMRD structure.
 438  */
 439 struct utp_task_req_desc {
 440         /* DW 0-3 */
 441         struct request_desc_header header;
 442
 443         /* DW 4-11 - Task request UPIU structure */
 444         struct utp_upiu_header  req_header;
 445         __be32                  input_param1;
 446         __be32                  input_param2;
 447         __be32                  input_param3;
 448         __be32                  __reserved1[2];
 449
 450         /* DW 12-19 - Task Management Response UPIU structure */
 451         struct utp_upiu_header  rsp_header;
 452         __be32                  output_param1;
 453         __be32                  output_param2;
 454         __be32                  __reserved2[3];
 455 };
 456
 457 #endif /* End of Header */