drivers/spi/spi-fsl-lpspi.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 //
   3 // Freescale i.MX7ULP LPSPI driver
   4 //
   5 // Copyright 2016 Freescale Semiconductor, Inc.
   6 // Copyright 2018 NXP Semiconductors
   7
   8 #include <linux/clk.h>
   9 #include <linux/completion.h>
  10 #include <linux/delay.h>
  11 #include <linux/err.h>
  12 #include <linux/interrupt.h>
  13 #include <linux/io.h>
  14 #include <linux/irq.h>
  15 #include <linux/kernel.h>
  16 #include <linux/module.h>
  17 #include <linux/of.h>
  18 #include <linux/of_device.h>
  19 #include <linux/platform_device.h>
  20 #include <linux/slab.h>
  21 #include <linux/spi/spi.h>
  22 #include <linux/spi/spi_bitbang.h>
  23 #include <linux/types.h>
  24
  25 #define DRIVER_NAME "fsl_lpspi"
  26
  27 /* i.MX7ULP LPSPI registers */
  28 #define IMX7ULP_VERID   0x0
  29 #define IMX7ULP_PARAM   0x4
  30 #define IMX7ULP_CR      0x10
  31 #define IMX7ULP_SR      0x14
  32 #define IMX7ULP_IER     0x18
  33 #define IMX7ULP_DER     0x1c
  34 #define IMX7ULP_CFGR0   0x20
  35 #define IMX7ULP_CFGR1   0x24
  36 #define IMX7ULP_DMR0    0x30
  37 #define IMX7ULP_DMR1    0x34
  38 #define IMX7ULP_CCR     0x40
  39 #define IMX7ULP_FCR     0x58
  40 #define IMX7ULP_FSR     0x5c
  41 #define IMX7ULP_TCR     0x60
  42 #define IMX7ULP_TDR     0x64
  43 #define IMX7ULP_RSR     0x70
  44 #define IMX7ULP_RDR     0x74
  45
  46 /* General control register field define */
  47 #define CR_RRF          BIT(9)
  48 #define CR_RTF          BIT(8)
  49 #define CR_RST          BIT(1)
  50 #define CR_MEN          BIT(0)
  51 #define SR_MBF          BIT(24)
  52 #define SR_TCF          BIT(10)
  53 #define SR_FCF          BIT(9)
  54 #define SR_RDF          BIT(1)
  55 #define SR_TDF          BIT(0)
  56 #define IER_TCIE        BIT(10)
  57 #define IER_FCIE        BIT(9)
  58 #define IER_RDIE        BIT(1)
  59 #define IER_TDIE        BIT(0)
  60 #define CFGR1_PCSCFG    BIT(27)
  61 #define CFGR1_PINCFG    (BIT(24)|BIT(25))
  62 #define CFGR1_PCSPOL    BIT(8)
  63 #define CFGR1_NOSTALL   BIT(3)
  64 #define CFGR1_MASTER    BIT(0)
  65 #define FSR_RXCOUNT     (BIT(16)|BIT(17)|BIT(18))
  66 #define RSR_RXEMPTY     BIT(1)
  67 #define TCR_CPOL        BIT(31)
  68 #define TCR_CPHA        BIT(30)
  69 #define TCR_CONT        BIT(21)
  70 #define TCR_CONTC       BIT(20)
  71 #define TCR_RXMSK       BIT(19)
  72 #define TCR_TXMSK       BIT(18)
  73
  74 static int clkdivs[] = {1, 2, 4, 8, 16, 32, 64, 128};
  75
  76 struct lpspi_config {
  77         u8 bpw;
  78         u8 chip_select;
  79         u8 prescale;
  80         u16 mode;
  81         u32 speed_hz;
  82 };
  83
  84 struct fsl_lpspi_data {
  85         struct device *dev;
  86         void __iomem *base;
  87         struct clk *clk;
  88         bool is_slave;
  89
  90         void *rx_buf;
  91         const void *tx_buf;
  92         void (*tx)(struct fsl_lpspi_data *);
  93         void (*rx)(struct fsl_lpspi_data *);
  94
  95         u32 remain;
  96         u8 watermark;
  97         u8 txfifosize;
  98         u8 rxfifosize;
  99
 100         struct lpspi_config config;
 101         struct completion xfer_done;
 102
 103         bool slave_aborted;
 104 };
 105
 106 static const struct of_device_id fsl_lpspi_dt_ids[] = {
 107         { .compatible = "fsl,imx7ulp-spi", },
 108         { /* sentinel */ }
 109 };
 110 MODULE_DEVICE_TABLE(of, fsl_lpspi_dt_ids);
 111
 112 #define LPSPI_BUF_RX(type)                                              \
 113 static void fsl_lpspi_buf_rx_##type(struct fsl_lpspi_data *fsl_lpspi)   \
 114 {                                                                       \
 115         unsigned int val = readl(fsl_lpspi->base + IMX7ULP_RDR);        \
 116                                                                         \
 117         if (fsl_lpspi->rx_buf) {                                        \
 118                 *(type *)fsl_lpspi->rx_buf = val;                       \
 119                 fsl_lpspi->rx_buf += sizeof(type);                      \
 120         }                                                               \
 121 }
 122
 123 #define LPSPI_BUF_TX(type)                                              \
 124 static void fsl_lpspi_buf_tx_##type(struct fsl_lpspi_data *fsl_lpspi)   \
 125 {                                                                       \
 126         type val = 0;                                                   \
 127                                                                         \
 128         if (fsl_lpspi->tx_buf) {                                        \
 129                 val = *(type *)fsl_lpspi->tx_buf;                       \
 130                 fsl_lpspi->tx_buf += sizeof(type);                      \
 131         }                                                               \
 132                                                                         \
 133         fsl_lpspi->remain -= sizeof(type);                              \
 134         writel(val, fsl_lpspi->base + IMX7ULP_TDR);                     \
 135 }
 136
 137 LPSPI_BUF_RX(u8)
 138 LPSPI_BUF_TX(u8)
 139 LPSPI_BUF_RX(u16)
 140 LPSPI_BUF_TX(u16)
 141 LPSPI_BUF_RX(u32)
 142 LPSPI_BUF_TX(u32)
 143
 144 static void fsl_lpspi_intctrl(struct fsl_lpspi_data *fsl_lpspi,
 145                               unsigned int enable)
 146 {
 147         writel(enable, fsl_lpspi->base + IMX7ULP_IER);
 148 }
 149
 150 static int lpspi_prepare_xfer_hardware(struct spi_controller *controller)
 151 {
 152         struct fsl_lpspi_data *fsl_lpspi =
 153                                 spi_controller_get_devdata(controller);
 154
 155         return clk_prepare_enable(fsl_lpspi->clk);
 156 }
 157
 158 static int lpspi_unprepare_xfer_hardware(struct spi_controller *controller)
 159 {
 160         struct fsl_lpspi_data *fsl_lpspi =
 161                                 spi_controller_get_devdata(controller);
 162
 163         clk_disable_unprepare(fsl_lpspi->clk);
 164
 165         return 0;
 166 }
 167
 168 static void fsl_lpspi_write_tx_fifo(struct fsl_lpspi_data *fsl_lpspi)
 169 {
 170         u8 txfifo_cnt;
 171         u32 temp;
 172
 173         txfifo_cnt = readl(fsl_lpspi->base + IMX7ULP_FSR) & 0xff;
 174
 175         while (txfifo_cnt < fsl_lpspi->txfifosize) {
 176                 if (!fsl_lpspi->remain)
 177                         break;
 178                 fsl_lpspi->tx(fsl_lpspi);
 179                 txfifo_cnt++;
 180         }
 181
 182         if (txfifo_cnt < fsl_lpspi->txfifosize) {
 183                 if (!fsl_lpspi->is_slave) {
 184                         temp = readl(fsl_lpspi->base + IMX7ULP_TCR);
 185                         temp &= ~TCR_CONTC;
 186                         writel(temp, fsl_lpspi->base + IMX7ULP_TCR);
 187                 }
 188
 189                 fsl_lpspi_intctrl(fsl_lpspi, IER_FCIE);
 190         } else
 191                 fsl_lpspi_intctrl(fsl_lpspi, IER_TDIE);
 192 }
 193
 194 static void fsl_lpspi_read_rx_fifo(struct fsl_lpspi_data *fsl_lpspi)
 195 {
 196         while (!(readl(fsl_lpspi->base + IMX7ULP_RSR) & RSR_RXEMPTY))
 197                 fsl_lpspi->rx(fsl_lpspi);
 198 }
 199
 200 static void fsl_lpspi_set_cmd(struct fsl_lpspi_data *fsl_lpspi,
 201                               bool is_first_xfer)
 202 {
 203         u32 temp = 0;
 204
 205         temp |= fsl_lpspi->config.bpw - 1;
 206         temp |= (fsl_lpspi->config.mode & 0x3) << 30;
 207         if (!fsl_lpspi->is_slave) {
 208                 temp |= fsl_lpspi->config.prescale << 27;
 209                 temp |= (fsl_lpspi->config.chip_select & 0x3) << 24;
 210
 211                 /*
 212                  * Set TCR_CONT will keep SS asserted after current transfer.
 213                  * For the first transfer, clear TCR_CONTC to assert SS.
 214                  * For subsequent transfer, set TCR_CONTC to keep SS asserted.
 215                  */
 216                 temp |= TCR_CONT;
 217                 if (is_first_xfer)
 218                         temp &= ~TCR_CONTC;
 219                 else
 220                         temp |= TCR_CONTC;
 221         }
 222         writel(temp, fsl_lpspi->base + IMX7ULP_TCR);
 223
 224         dev_dbg(fsl_lpspi->dev, "TCR=0x%x\n", temp);
 225 }
 226
 227 static void fsl_lpspi_set_watermark(struct fsl_lpspi_data *fsl_lpspi)
 228 {
 229         u32 temp;
 230
 231         temp = fsl_lpspi->watermark >> 1 | (fsl_lpspi->watermark >> 1) << 16;
 232
 233         writel(temp, fsl_lpspi->base + IMX7ULP_FCR);
 234
 235         dev_dbg(fsl_lpspi->dev, "FCR=0x%x\n", temp);
 236 }
 237
 238 static int fsl_lpspi_set_bitrate(struct fsl_lpspi_data *fsl_lpspi)
 239 {
 240         struct lpspi_config config = fsl_lpspi->config;
 241         unsigned int perclk_rate, scldiv;
 242         u8 prescale;
 243
 244         perclk_rate = clk_get_rate(fsl_lpspi->clk);
 245         for (prescale = 0; prescale < 8; prescale++) {
 246                 scldiv = perclk_rate /
 247                          (clkdivs[prescale] * config.speed_hz) - 2;
 248                 if (scldiv < 256) {
 249                         fsl_lpspi->config.prescale = prescale;
 250                         break;
 251                 }
 252         }
 253
 254         if (prescale == 8 && scldiv >= 256)
 255                 return -EINVAL;
 256
 257         writel(scldiv | (scldiv << 8) | ((scldiv >> 1) << 16),
 258                                         fsl_lpspi->base + IMX7ULP_CCR);
 259
 260         dev_dbg(fsl_lpspi->dev, "perclk=%d, speed=%d, prescale =%d, scldiv=%d\n",
 261                 perclk_rate, config.speed_hz, prescale, scldiv);
 262
 263         return 0;
 264 }
 265
 266 static int fsl_lpspi_config(struct fsl_lpspi_data *fsl_lpspi)
 267 {
 268         u32 temp;
 269         int ret;
 270
 271         if (!fsl_lpspi->is_slave) {
 272                 ret = fsl_lpspi_set_bitrate(fsl_lpspi);
 273                 if (ret)
 274                         return ret;
 275         }
 276
 277         fsl_lpspi_set_watermark(fsl_lpspi);
 278
 279         if (!fsl_lpspi->is_slave)
 280                 temp = CFGR1_MASTER;
 281         else
 282                 temp = CFGR1_PINCFG;
 283         if (fsl_lpspi->config.mode & SPI_CS_HIGH)
 284                 temp |= CFGR1_PCSPOL;
 285         writel(temp, fsl_lpspi->base + IMX7ULP_CFGR1);
 286
 287         temp = readl(fsl_lpspi->base + IMX7ULP_CR);
 288         temp |= CR_RRF | CR_RTF | CR_MEN;
 289         writel(temp, fsl_lpspi->base + IMX7ULP_CR);
 290
 291         return 0;
 292 }
 293
 294 static void fsl_lpspi_setup_transfer(struct spi_device *spi,
 295                                      struct spi_transfer *t)
 296 {
 297         struct fsl_lpspi_data *fsl_lpspi =
 298                                 spi_controller_get_devdata(spi->controller);
 299
 300         fsl_lpspi->config.mode = spi->mode;
 301         fsl_lpspi->config.bpw = t ? t->bits_per_word : spi->bits_per_word;
 302         fsl_lpspi->config.speed_hz = t ? t->speed_hz : spi->max_speed_hz;
 303         fsl_lpspi->config.chip_select = spi->chip_select;
 304
 305         if (!fsl_lpspi->config.speed_hz)
 306                 fsl_lpspi->config.speed_hz = spi->max_speed_hz;
 307         if (!fsl_lpspi->config.bpw)
 308                 fsl_lpspi->config.bpw = spi->bits_per_word;
 309
 310         /* Initialize the functions for transfer */
 311         if (fsl_lpspi->config.bpw <= 8) {
 312                 fsl_lpspi->rx = fsl_lpspi_buf_rx_u8;
 313                 fsl_lpspi->tx = fsl_lpspi_buf_tx_u8;
 314         } else if (fsl_lpspi->config.bpw <= 16) {
 315                 fsl_lpspi->rx = fsl_lpspi_buf_rx_u16;
 316                 fsl_lpspi->tx = fsl_lpspi_buf_tx_u16;
 317         } else {
 318                 fsl_lpspi->rx = fsl_lpspi_buf_rx_u32;
 319                 fsl_lpspi->tx = fsl_lpspi_buf_tx_u32;
 320         }
 321
 322         if (t->len <= fsl_lpspi->txfifosize)
 323                 fsl_lpspi->watermark = t->len;
 324         else
 325                 fsl_lpspi->watermark = fsl_lpspi->txfifosize;
 326
 327         fsl_lpspi_config(fsl_lpspi);
 328 }
 329
 330 static int fsl_lpspi_slave_abort(struct spi_controller *controller)
 331 {
 332         struct fsl_lpspi_data *fsl_lpspi =
 333                                 spi_controller_get_devdata(controller);
 334
 335         fsl_lpspi->slave_aborted = true;
 336         complete(&fsl_lpspi->xfer_done);
 337         return 0;
 338 }
 339
 340 static int fsl_lpspi_wait_for_completion(struct spi_controller *controller)
 341 {
 342         struct fsl_lpspi_data *fsl_lpspi =
 343                                 spi_controller_get_devdata(controller);
 344
 345         if (fsl_lpspi->is_slave) {
 346                 if (wait_for_completion_interruptible(&fsl_lpspi->xfer_done) ||
 347                         fsl_lpspi->slave_aborted) {
 348                         dev_dbg(fsl_lpspi->dev, "interrupted\n");
 349                         return -EINTR;
 350                 }
 351         } else {
 352                 if (!wait_for_completion_timeout(&fsl_lpspi->xfer_done, HZ)) {
 353                         dev_dbg(fsl_lpspi->dev, "wait for completion timeout\n");
 354                         return -ETIMEDOUT;
 355                 }
 356         }
 357
 358         return 0;
 359 }
 360
 361 static int fsl_lpspi_reset(struct fsl_lpspi_data *fsl_lpspi)
 362 {
 363         u32 temp;
 364
 365         /* Disable all interrupt */
 366         fsl_lpspi_intctrl(fsl_lpspi, 0);
 367
 368         /* W1C for all flags in SR */
 369         temp = 0x3F << 8;
 370         writel(temp, fsl_lpspi->base + IMX7ULP_SR);
 371
 372         /* Clear FIFO and disable module */
 373         temp = CR_RRF | CR_RTF;
 374         writel(temp, fsl_lpspi->base + IMX7ULP_CR);
 375
 376         return 0;
 377 }
 378
 379 static int fsl_lpspi_transfer_one(struct spi_controller *controller,
 380                                   struct spi_device *spi,
 381                                   struct spi_transfer *t)
 382 {
 383         struct fsl_lpspi_data *fsl_lpspi =
 384                                 spi_controller_get_devdata(controller);
 385         int ret;
 386
 387         fsl_lpspi->tx_buf = t->tx_buf;
 388         fsl_lpspi->rx_buf = t->rx_buf;
 389         fsl_lpspi->remain = t->len;
 390
 391         reinit_completion(&fsl_lpspi->xfer_done);
 392         fsl_lpspi->slave_aborted = false;
 393
 394         fsl_lpspi_write_tx_fifo(fsl_lpspi);
 395
 396         ret = fsl_lpspi_wait_for_completion(controller);
 397         if (ret)
 398                 return ret;
 399
 400         fsl_lpspi_reset(fsl_lpspi);
 401
 402         return 0;
 403 }
 404
 405 static int fsl_lpspi_transfer_one_msg(struct spi_controller *controller,
 406                                       struct spi_message *msg)
 407 {
 408         struct fsl_lpspi_data *fsl_lpspi =
 409                                 spi_controller_get_devdata(controller);
 410         struct spi_device *spi = msg->spi;
 411         struct spi_transfer *xfer;
 412         bool is_first_xfer = true;
 413         int ret = 0;
 414
 415         msg->status = 0;
 416         msg->actual_length = 0;
 417
 418         list_for_each_entry(xfer, &msg->transfers, transfer_list) {
 419                 fsl_lpspi_setup_transfer(spi, xfer);
 420                 fsl_lpspi_set_cmd(fsl_lpspi, is_first_xfer);
 421
 422                 is_first_xfer = false;
 423
 424                 ret = fsl_lpspi_transfer_one(controller, spi, xfer);
 425                 if (ret < 0)
 426                         goto complete;
 427
 428                 msg->actual_length += xfer->len;
 429         }
 430
 431 complete:
 432         msg->status = ret;
 433         spi_finalize_current_message(controller);
 434
 435         return ret;
 436 }
 437
 438 static irqreturn_t fsl_lpspi_isr(int irq, void *dev_id)
 439 {
 440         u32 temp_SR, temp_IER;
 441         struct fsl_lpspi_data *fsl_lpspi = dev_id;
 442
 443         temp_IER = readl(fsl_lpspi->base + IMX7ULP_IER);
 444         fsl_lpspi_intctrl(fsl_lpspi, 0);
 445         temp_SR = readl(fsl_lpspi->base + IMX7ULP_SR);
 446
 447         fsl_lpspi_read_rx_fifo(fsl_lpspi);
 448
 449         if ((temp_SR & SR_TDF) && (temp_IER & IER_TDIE)) {
 450                 fsl_lpspi_write_tx_fifo(fsl_lpspi);
 451                 return IRQ_HANDLED;
 452         }
 453
 454         if (temp_SR & SR_MBF ||
 455             readl(fsl_lpspi->base + IMX7ULP_FSR) & FSR_RXCOUNT) {
 456                 writel(SR_FCF, fsl_lpspi->base + IMX7ULP_SR);
 457                 fsl_lpspi_intctrl(fsl_lpspi, IER_FCIE);
 458                 return IRQ_HANDLED;
 459         }
 460
 461         if (temp_SR & SR_FCF && (temp_IER & IER_FCIE)) {
 462                 writel(SR_FCF, fsl_lpspi->base + IMX7ULP_SR);
 463                         complete(&fsl_lpspi->xfer_done);
 464                 return IRQ_HANDLED;
 465         }
 466
 467         return IRQ_NONE;
 468 }
 469
 470 static int fsl_lpspi_probe(struct platform_device *pdev)
 471 {
 472         struct fsl_lpspi_data *fsl_lpspi;
 473         struct spi_controller *controller;
 474         struct resource *res;
 475         int ret, irq;
 476         u32 temp;
 477
 478         if (of_property_read_bool((&pdev->dev)->of_node, "spi-slave"))
 479                 controller = spi_alloc_slave(&pdev->dev,
 480                                         sizeof(struct fsl_lpspi_data));
 481         else
 482                 controller = spi_alloc_master(&pdev->dev,
 483                                         sizeof(struct fsl_lpspi_data));
 484
 485         if (!controller)
 486                 return -ENOMEM;
 487
 488         platform_set_drvdata(pdev, controller);
 489
 490         controller->bits_per_word_mask = SPI_BPW_RANGE_MASK(8, 32);
 491         controller->bus_num = pdev->id;
 492
 493         fsl_lpspi = spi_controller_get_devdata(controller);
 494         fsl_lpspi->dev = &pdev->dev;
 495         fsl_lpspi->is_slave = of_property_read_bool((&pdev->dev)->of_node,
 496                                                     "spi-slave");
 497
 498         controller->transfer_one_message = fsl_lpspi_transfer_one_msg;
 499         controller->prepare_transfer_hardware = lpspi_prepare_xfer_hardware;
 500         controller->unprepare_transfer_hardware = lpspi_unprepare_xfer_hardware;
 501         controller->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
 502         controller->flags = SPI_MASTER_MUST_RX | SPI_MASTER_MUST_TX;
 503         controller->dev.of_node = pdev->dev.of_node;
 504         controller->bus_num = pdev->id;
 505         controller->slave_abort = fsl_lpspi_slave_abort;
 506
 507         init_completion(&fsl_lpspi->xfer_done);
 508
 509         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 510         fsl_lpspi->base = devm_ioremap_resource(&pdev->dev, res);
 511         if (IS_ERR(fsl_lpspi->base)) {
 512                 ret = PTR_ERR(fsl_lpspi->base);
 513                 goto out_controller_put;
 514         }
 515
 516         irq = platform_get_irq(pdev, 0);
 517         if (irq < 0) {
 518                 ret = irq;
 519                 goto out_controller_put;
 520         }
 521
 522         ret = devm_request_irq(&pdev->dev, irq, fsl_lpspi_isr, 0,
 523                                dev_name(&pdev->dev), fsl_lpspi);
 524         if (ret) {
 525                 dev_err(&pdev->dev, "can't get irq%d: %d\n", irq, ret);
 526                 goto out_controller_put;
 527         }
 528
 529         fsl_lpspi->clk = devm_clk_get(&pdev->dev, "ipg");
 530         if (IS_ERR(fsl_lpspi->clk)) {
 531                 ret = PTR_ERR(fsl_lpspi->clk);
 532                 goto out_controller_put;
 533         }
 534
 535         ret = clk_prepare_enable(fsl_lpspi->clk);
 536         if (ret) {
 537                 dev_err(&pdev->dev, "can't enable lpspi clock, ret=%d\n", ret);
 538                 goto out_controller_put;
 539         }
 540
 541         temp = readl(fsl_lpspi->base + IMX7ULP_PARAM);
 542         fsl_lpspi->txfifosize = 1 << (temp & 0x0f);
 543         fsl_lpspi->rxfifosize = 1 << ((temp >> 8) & 0x0f);
 544
 545         clk_disable_unprepare(fsl_lpspi->clk);
 546
 547         ret = devm_spi_register_controller(&pdev->dev, controller);
 548         if (ret < 0) {
 549                 dev_err(&pdev->dev, "spi_register_controller error.\n");
 550                 goto out_controller_put;
 551         }
 552
 553         return 0;
 554
 555 out_controller_put:
 556         spi_controller_put(controller);
 557
 558         return ret;
 559 }
 560
 561 static int fsl_lpspi_remove(struct platform_device *pdev)
 562 {
 563         struct spi_controller *controller = platform_get_drvdata(pdev);
 564         struct fsl_lpspi_data *fsl_lpspi =
 565                                 spi_controller_get_devdata(controller);
 566
 567         clk_disable_unprepare(fsl_lpspi->clk);
 568
 569         return 0;
 570 }
 571
 572 static struct platform_driver fsl_lpspi_driver = {
 573         .driver = {
 574                 .name = DRIVER_NAME,
 575                 .of_match_table = fsl_lpspi_dt_ids,
 576         },
 577         .probe = fsl_lpspi_probe,
 578         .remove = fsl_lpspi_remove,
 579 };
 580 module_platform_driver(fsl_lpspi_driver);
 581
 582 MODULE_DESCRIPTION("LPSPI Controller driver");
 583 MODULE_AUTHOR("Gao Pan <pandy.gao@nxp.com>");
 584 MODULE_LICENSE("GPL");