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Linux 5.1.15
[linux/fpc-iii.git] / drivers / spi / spi-rspi.c
blob5d35a82945cd1c43d90cc4a81cf2c94727532dda
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * SH RSPI driver
4 *
5 * Copyright (C) 2012, 2013 Renesas Solutions Corp.
6 * Copyright (C) 2014 Glider bvba
7 *
8 * Based on spi-sh.c:
9 * Copyright (C) 2011 Renesas Solutions Corp.
10 */
11
12 #include <linux/module.h>
13 #include <linux/kernel.h>
14 #include <linux/sched.h>
15 #include <linux/errno.h>
16 #include <linux/interrupt.h>
17 #include <linux/platform_device.h>
18 #include <linux/io.h>
19 #include <linux/clk.h>
20 #include <linux/dmaengine.h>
21 #include <linux/dma-mapping.h>
22 #include <linux/of_device.h>
23 #include <linux/pm_runtime.h>
24 #include <linux/sh_dma.h>
25 #include <linux/spi/spi.h>
26 #include <linux/spi/rspi.h>
27
28 #define RSPI_SPCR 0x00 /* Control Register */
29 #define RSPI_SSLP 0x01 /* Slave Select Polarity Register */
30 #define RSPI_SPPCR 0x02 /* Pin Control Register */
31 #define RSPI_SPSR 0x03 /* Status Register */
32 #define RSPI_SPDR 0x04 /* Data Register */
33 #define RSPI_SPSCR 0x08 /* Sequence Control Register */
34 #define RSPI_SPSSR 0x09 /* Sequence Status Register */
35 #define RSPI_SPBR 0x0a /* Bit Rate Register */
36 #define RSPI_SPDCR 0x0b /* Data Control Register */
37 #define RSPI_SPCKD 0x0c /* Clock Delay Register */
38 #define RSPI_SSLND 0x0d /* Slave Select Negation Delay Register */
39 #define RSPI_SPND 0x0e /* Next-Access Delay Register */
40 #define RSPI_SPCR2 0x0f /* Control Register 2 (SH only) */
41 #define RSPI_SPCMD0 0x10 /* Command Register 0 */
42 #define RSPI_SPCMD1 0x12 /* Command Register 1 */
43 #define RSPI_SPCMD2 0x14 /* Command Register 2 */
44 #define RSPI_SPCMD3 0x16 /* Command Register 3 */
45 #define RSPI_SPCMD4 0x18 /* Command Register 4 */
46 #define RSPI_SPCMD5 0x1a /* Command Register 5 */
47 #define RSPI_SPCMD6 0x1c /* Command Register 6 */
48 #define RSPI_SPCMD7 0x1e /* Command Register 7 */
49 #define RSPI_SPCMD(i) (RSPI_SPCMD0 + (i) * 2)
50 #define RSPI_NUM_SPCMD 8
51 #define RSPI_RZ_NUM_SPCMD 4
52 #define QSPI_NUM_SPCMD 4
53
54 /* RSPI on RZ only */
55 #define RSPI_SPBFCR 0x20 /* Buffer Control Register */
56 #define RSPI_SPBFDR 0x22 /* Buffer Data Count Setting Register */
57
58 /* QSPI only */
59 #define QSPI_SPBFCR 0x18 /* Buffer Control Register */
60 #define QSPI_SPBDCR 0x1a /* Buffer Data Count Register */
61 #define QSPI_SPBMUL0 0x1c /* Transfer Data Length Multiplier Setting Register 0 */
62 #define QSPI_SPBMUL1 0x20 /* Transfer Data Length Multiplier Setting Register 1 */
63 #define QSPI_SPBMUL2 0x24 /* Transfer Data Length Multiplier Setting Register 2 */
64 #define QSPI_SPBMUL3 0x28 /* Transfer Data Length Multiplier Setting Register 3 */
65 #define QSPI_SPBMUL(i) (QSPI_SPBMUL0 + (i) * 4)
66
67 /* SPCR - Control Register */
68 #define SPCR_SPRIE 0x80 /* Receive Interrupt Enable */
69 #define SPCR_SPE 0x40 /* Function Enable */
70 #define SPCR_SPTIE 0x20 /* Transmit Interrupt Enable */
71 #define SPCR_SPEIE 0x10 /* Error Interrupt Enable */
72 #define SPCR_MSTR 0x08 /* Master/Slave Mode Select */
73 #define SPCR_MODFEN 0x04 /* Mode Fault Error Detection Enable */
74 /* RSPI on SH only */
75 #define SPCR_TXMD 0x02 /* TX Only Mode (vs. Full Duplex) */
76 #define SPCR_SPMS 0x01 /* 3-wire Mode (vs. 4-wire) */
77 /* QSPI on R-Car Gen2 only */
78 #define SPCR_WSWAP 0x02 /* Word Swap of read-data for DMAC */
79 #define SPCR_BSWAP 0x01 /* Byte Swap of read-data for DMAC */
80
81 /* SSLP - Slave Select Polarity Register */
82 #define SSLP_SSL1P 0x02 /* SSL1 Signal Polarity Setting */
83 #define SSLP_SSL0P 0x01 /* SSL0 Signal Polarity Setting */
84
85 /* SPPCR - Pin Control Register */
86 #define SPPCR_MOIFE 0x20 /* MOSI Idle Value Fixing Enable */
87 #define SPPCR_MOIFV 0x10 /* MOSI Idle Fixed Value */
88 #define SPPCR_SPOM 0x04
89 #define SPPCR_SPLP2 0x02 /* Loopback Mode 2 (non-inverting) */
90 #define SPPCR_SPLP 0x01 /* Loopback Mode (inverting) */
91
92 #define SPPCR_IO3FV 0x04 /* Single-/Dual-SPI Mode IO3 Output Fixed Value */
93 #define SPPCR_IO2FV 0x04 /* Single-/Dual-SPI Mode IO2 Output Fixed Value */
94
95 /* SPSR - Status Register */
96 #define SPSR_SPRF 0x80 /* Receive Buffer Full Flag */
97 #define SPSR_TEND 0x40 /* Transmit End */
98 #define SPSR_SPTEF 0x20 /* Transmit Buffer Empty Flag */
99 #define SPSR_PERF 0x08 /* Parity Error Flag */
100 #define SPSR_MODF 0x04 /* Mode Fault Error Flag */
101 #define SPSR_IDLNF 0x02 /* RSPI Idle Flag */
102 #define SPSR_OVRF 0x01 /* Overrun Error Flag (RSPI only) */
103
104 /* SPSCR - Sequence Control Register */
105 #define SPSCR_SPSLN_MASK 0x07 /* Sequence Length Specification */
106
107 /* SPSSR - Sequence Status Register */
108 #define SPSSR_SPECM_MASK 0x70 /* Command Error Mask */
109 #define SPSSR_SPCP_MASK 0x07 /* Command Pointer Mask */
110
111 /* SPDCR - Data Control Register */
112 #define SPDCR_TXDMY 0x80 /* Dummy Data Transmission Enable */
113 #define SPDCR_SPLW1 0x40 /* Access Width Specification (RZ) */
114 #define SPDCR_SPLW0 0x20 /* Access Width Specification (RZ) */
115 #define SPDCR_SPLLWORD (SPDCR_SPLW1 | SPDCR_SPLW0)
116 #define SPDCR_SPLWORD SPDCR_SPLW1
117 #define SPDCR_SPLBYTE SPDCR_SPLW0
118 #define SPDCR_SPLW 0x20 /* Access Width Specification (SH) */
119 #define SPDCR_SPRDTD 0x10 /* Receive Transmit Data Select (SH) */
120 #define SPDCR_SLSEL1 0x08
121 #define SPDCR_SLSEL0 0x04
122 #define SPDCR_SLSEL_MASK 0x0c /* SSL1 Output Select (SH) */
123 #define SPDCR_SPFC1 0x02
124 #define SPDCR_SPFC0 0x01
125 #define SPDCR_SPFC_MASK 0x03 /* Frame Count Setting (1-4) (SH) */
126
127 /* SPCKD - Clock Delay Register */
128 #define SPCKD_SCKDL_MASK 0x07 /* Clock Delay Setting (1-8) */
129
130 /* SSLND - Slave Select Negation Delay Register */
131 #define SSLND_SLNDL_MASK 0x07 /* SSL Negation Delay Setting (1-8) */
132
133 /* SPND - Next-Access Delay Register */
134 #define SPND_SPNDL_MASK 0x07 /* Next-Access Delay Setting (1-8) */
135
136 /* SPCR2 - Control Register 2 */
137 #define SPCR2_PTE 0x08 /* Parity Self-Test Enable */
138 #define SPCR2_SPIE 0x04 /* Idle Interrupt Enable */
139 #define SPCR2_SPOE 0x02 /* Odd Parity Enable (vs. Even) */
140 #define SPCR2_SPPE 0x01 /* Parity Enable */
141
142 /* SPCMDn - Command Registers */
143 #define SPCMD_SCKDEN 0x8000 /* Clock Delay Setting Enable */
144 #define SPCMD_SLNDEN 0x4000 /* SSL Negation Delay Setting Enable */
145 #define SPCMD_SPNDEN 0x2000 /* Next-Access Delay Enable */
146 #define SPCMD_LSBF 0x1000 /* LSB First */
147 #define SPCMD_SPB_MASK 0x0f00 /* Data Length Setting */
148 #define SPCMD_SPB_8_TO_16(bit) (((bit - 1) << 8) & SPCMD_SPB_MASK)
149 #define SPCMD_SPB_8BIT 0x0000 /* QSPI only */
150 #define SPCMD_SPB_16BIT 0x0100
151 #define SPCMD_SPB_20BIT 0x0000
152 #define SPCMD_SPB_24BIT 0x0100
153 #define SPCMD_SPB_32BIT 0x0200
154 #define SPCMD_SSLKP 0x0080 /* SSL Signal Level Keeping */
155 #define SPCMD_SPIMOD_MASK 0x0060 /* SPI Operating Mode (QSPI only) */
156 #define SPCMD_SPIMOD1 0x0040
157 #define SPCMD_SPIMOD0 0x0020
158 #define SPCMD_SPIMOD_SINGLE 0
159 #define SPCMD_SPIMOD_DUAL SPCMD_SPIMOD0
160 #define SPCMD_SPIMOD_QUAD SPCMD_SPIMOD1
161 #define SPCMD_SPRW 0x0010 /* SPI Read/Write Access (Dual/Quad) */
162 #define SPCMD_SSLA_MASK 0x0030 /* SSL Assert Signal Setting (RSPI) */
163 #define SPCMD_BRDV_MASK 0x000c /* Bit Rate Division Setting */
164 #define SPCMD_CPOL 0x0002 /* Clock Polarity Setting */
165 #define SPCMD_CPHA 0x0001 /* Clock Phase Setting */
166
167 /* SPBFCR - Buffer Control Register */
168 #define SPBFCR_TXRST 0x80 /* Transmit Buffer Data Reset */
169 #define SPBFCR_RXRST 0x40 /* Receive Buffer Data Reset */
170 #define SPBFCR_TXTRG_MASK 0x30 /* Transmit Buffer Data Triggering Number */
171 #define SPBFCR_RXTRG_MASK 0x07 /* Receive Buffer Data Triggering Number */
172 /* QSPI on R-Car Gen2 */
173 #define SPBFCR_TXTRG_1B 0x00 /* 31 bytes (1 byte available) */
174 #define SPBFCR_TXTRG_32B 0x30 /* 0 byte (32 bytes available) */
175 #define SPBFCR_RXTRG_1B 0x00 /* 1 byte (31 bytes available) */
176 #define SPBFCR_RXTRG_32B 0x07 /* 32 bytes (0 byte available) */
177
178 #define QSPI_BUFFER_SIZE 32u
179
180 struct rspi_data {
181 void __iomem *addr;
182 u32 max_speed_hz;
183 struct spi_controller *ctlr;
184 wait_queue_head_t wait;
185 struct clk *clk;
186 u16 spcmd;
187 u8 spsr;
188 u8 sppcr;
189 int rx_irq, tx_irq;
190 const struct spi_ops *ops;
191
192 unsigned dma_callbacked:1;
193 unsigned byte_access:1;
194 };
195
196 static void rspi_write8(const struct rspi_data *rspi, u8 data, u16 offset)
197 {
198 iowrite8(data, rspi->addr + offset);
199 }
200
201 static void rspi_write16(const struct rspi_data *rspi, u16 data, u16 offset)
202 {
203 iowrite16(data, rspi->addr + offset);
204 }
205
206 static void rspi_write32(const struct rspi_data *rspi, u32 data, u16 offset)
207 {
208 iowrite32(data, rspi->addr + offset);
209 }
210
211 static u8 rspi_read8(const struct rspi_data *rspi, u16 offset)
212 {
213 return ioread8(rspi->addr + offset);
214 }
215
216 static u16 rspi_read16(const struct rspi_data *rspi, u16 offset)
217 {
218 return ioread16(rspi->addr + offset);
219 }
220
221 static void rspi_write_data(const struct rspi_data *rspi, u16 data)
222 {
223 if (rspi->byte_access)
224 rspi_write8(rspi, data, RSPI_SPDR);
225 else /* 16 bit */
226 rspi_write16(rspi, data, RSPI_SPDR);
227 }
228
229 static u16 rspi_read_data(const struct rspi_data *rspi)
230 {
231 if (rspi->byte_access)
232 return rspi_read8(rspi, RSPI_SPDR);
233 else /* 16 bit */
234 return rspi_read16(rspi, RSPI_SPDR);
235 }
236
237 /* optional functions */
238 struct spi_ops {
239 int (*set_config_register)(struct rspi_data *rspi, int access_size);
240 int (*transfer_one)(struct spi_controller *ctlr,
241 struct spi_device *spi, struct spi_transfer *xfer);
242 u16 mode_bits;
243 u16 flags;
244 u16 fifo_size;
245 };
246
247 /*
248 * functions for RSPI on legacy SH
249 */
250 static int rspi_set_config_register(struct rspi_data *rspi, int access_size)
251 {
252 int spbr;
253
254 /* Sets output mode, MOSI signal, and (optionally) loopback */
255 rspi_write8(rspi, rspi->sppcr, RSPI_SPPCR);
256
257 /* Sets transfer bit rate */
258 spbr = DIV_ROUND_UP(clk_get_rate(rspi->clk),
259 2 * rspi->max_speed_hz) - 1;
260 rspi_write8(rspi, clamp(spbr, 0, 255), RSPI_SPBR);
261
262 /* Disable dummy transmission, set 16-bit word access, 1 frame */
263 rspi_write8(rspi, 0, RSPI_SPDCR);
264 rspi->byte_access = 0;
265
266 /* Sets RSPCK, SSL, next-access delay value */
267 rspi_write8(rspi, 0x00, RSPI_SPCKD);
268 rspi_write8(rspi, 0x00, RSPI_SSLND);
269 rspi_write8(rspi, 0x00, RSPI_SPND);
270
271 /* Sets parity, interrupt mask */
272 rspi_write8(rspi, 0x00, RSPI_SPCR2);
273
274 /* Resets sequencer */
275 rspi_write8(rspi, 0, RSPI_SPSCR);
276 rspi->spcmd |= SPCMD_SPB_8_TO_16(access_size);
277 rspi_write16(rspi, rspi->spcmd, RSPI_SPCMD0);
278
279 /* Sets RSPI mode */
280 rspi_write8(rspi, SPCR_MSTR, RSPI_SPCR);
281
282 return 0;
283 }
284
285 /*
286 * functions for RSPI on RZ
287 */
288 static int rspi_rz_set_config_register(struct rspi_data *rspi, int access_size)
289 {
290 int spbr;
291 int div = 0;
292 unsigned long clksrc;
293
294 /* Sets output mode, MOSI signal, and (optionally) loopback */
295 rspi_write8(rspi, rspi->sppcr, RSPI_SPPCR);
296
297 clksrc = clk_get_rate(rspi->clk);
298 while (div < 3) {
299 if (rspi->max_speed_hz >= clksrc/4) /* 4=(CLK/2)/2 */
300 break;
301 div++;
302 clksrc /= 2;
303 }
304
305 /* Sets transfer bit rate */
306 spbr = DIV_ROUND_UP(clksrc, 2 * rspi->max_speed_hz) - 1;
307 rspi_write8(rspi, clamp(spbr, 0, 255), RSPI_SPBR);
308 rspi->spcmd |= div << 2;
309
310 /* Disable dummy transmission, set byte access */
311 rspi_write8(rspi, SPDCR_SPLBYTE, RSPI_SPDCR);
312 rspi->byte_access = 1;
313
314 /* Sets RSPCK, SSL, next-access delay value */
315 rspi_write8(rspi, 0x00, RSPI_SPCKD);
316 rspi_write8(rspi, 0x00, RSPI_SSLND);
317 rspi_write8(rspi, 0x00, RSPI_SPND);
318
319 /* Resets sequencer */
320 rspi_write8(rspi, 0, RSPI_SPSCR);
321 rspi->spcmd |= SPCMD_SPB_8_TO_16(access_size);
322 rspi_write16(rspi, rspi->spcmd, RSPI_SPCMD0);
323
324 /* Sets RSPI mode */
325 rspi_write8(rspi, SPCR_MSTR, RSPI_SPCR);
326
327 return 0;
328 }
329
330 /*
331 * functions for QSPI
332 */
333 static int qspi_set_config_register(struct rspi_data *rspi, int access_size)
334 {
335 int spbr;
336
337 /* Sets output mode, MOSI signal, and (optionally) loopback */
338 rspi_write8(rspi, rspi->sppcr, RSPI_SPPCR);
339
340 /* Sets transfer bit rate */
341 spbr = DIV_ROUND_UP(clk_get_rate(rspi->clk), 2 * rspi->max_speed_hz);
342 rspi_write8(rspi, clamp(spbr, 0, 255), RSPI_SPBR);
343
344 /* Disable dummy transmission, set byte access */
345 rspi_write8(rspi, 0, RSPI_SPDCR);
346 rspi->byte_access = 1;
347
348 /* Sets RSPCK, SSL, next-access delay value */
349 rspi_write8(rspi, 0x00, RSPI_SPCKD);
350 rspi_write8(rspi, 0x00, RSPI_SSLND);
351 rspi_write8(rspi, 0x00, RSPI_SPND);
352
353 /* Data Length Setting */
354 if (access_size == 8)
355 rspi->spcmd |= SPCMD_SPB_8BIT;
356 else if (access_size == 16)
357 rspi->spcmd |= SPCMD_SPB_16BIT;
358 else
359 rspi->spcmd |= SPCMD_SPB_32BIT;
360
361 rspi->spcmd |= SPCMD_SCKDEN | SPCMD_SLNDEN | SPCMD_SPNDEN;
362
363 /* Resets transfer data length */
364 rspi_write32(rspi, 0, QSPI_SPBMUL0);
365
366 /* Resets transmit and receive buffer */
367 rspi_write8(rspi, SPBFCR_TXRST | SPBFCR_RXRST, QSPI_SPBFCR);
368 /* Sets buffer to allow normal operation */
369 rspi_write8(rspi, 0x00, QSPI_SPBFCR);
370
371 /* Resets sequencer */
372 rspi_write8(rspi, 0, RSPI_SPSCR);
373 rspi_write16(rspi, rspi->spcmd, RSPI_SPCMD0);
374
375 /* Sets RSPI mode */
376 rspi_write8(rspi, SPCR_MSTR, RSPI_SPCR);
377
378 return 0;
379 }
380
381 static void qspi_update(const struct rspi_data *rspi, u8 mask, u8 val, u8 reg)
382 {
383 u8 data;
384
385 data = rspi_read8(rspi, reg);
386 data &= ~mask;
387 data |= (val & mask);
388 rspi_write8(rspi, data, reg);
389 }
390
391 static unsigned int qspi_set_send_trigger(struct rspi_data *rspi,
392 unsigned int len)
393 {
394 unsigned int n;
395
396 n = min(len, QSPI_BUFFER_SIZE);
397
398 if (len >= QSPI_BUFFER_SIZE) {
399 /* sets triggering number to 32 bytes */
400 qspi_update(rspi, SPBFCR_TXTRG_MASK,
401 SPBFCR_TXTRG_32B, QSPI_SPBFCR);
402 } else {
403 /* sets triggering number to 1 byte */
404 qspi_update(rspi, SPBFCR_TXTRG_MASK,
405 SPBFCR_TXTRG_1B, QSPI_SPBFCR);
406 }
407
408 return n;
409 }
410
411 static int qspi_set_receive_trigger(struct rspi_data *rspi, unsigned int len)
412 {
413 unsigned int n;
414
415 n = min(len, QSPI_BUFFER_SIZE);
416
417 if (len >= QSPI_BUFFER_SIZE) {
418 /* sets triggering number to 32 bytes */
419 qspi_update(rspi, SPBFCR_RXTRG_MASK,
420 SPBFCR_RXTRG_32B, QSPI_SPBFCR);
421 } else {
422 /* sets triggering number to 1 byte */
423 qspi_update(rspi, SPBFCR_RXTRG_MASK,
424 SPBFCR_RXTRG_1B, QSPI_SPBFCR);
425 }
426 return n;
427 }
428
429 #define set_config_register(spi, n) spi->ops->set_config_register(spi, n)
430
431 static void rspi_enable_irq(const struct rspi_data *rspi, u8 enable)
432 {
433 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) | enable, RSPI_SPCR);
434 }
435
436 static void rspi_disable_irq(const struct rspi_data *rspi, u8 disable)
437 {
438 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) & ~disable, RSPI_SPCR);
439 }
440
441 static int rspi_wait_for_interrupt(struct rspi_data *rspi, u8 wait_mask,
442 u8 enable_bit)
443 {
444 int ret;
445
446 rspi->spsr = rspi_read8(rspi, RSPI_SPSR);
447 if (rspi->spsr & wait_mask)
448 return 0;
449
450 rspi_enable_irq(rspi, enable_bit);
451 ret = wait_event_timeout(rspi->wait, rspi->spsr & wait_mask, HZ);
452 if (ret == 0 && !(rspi->spsr & wait_mask))
453 return -ETIMEDOUT;
454
455 return 0;
456 }
457
458 static inline int rspi_wait_for_tx_empty(struct rspi_data *rspi)
459 {
460 return rspi_wait_for_interrupt(rspi, SPSR_SPTEF, SPCR_SPTIE);
461 }
462
463 static inline int rspi_wait_for_rx_full(struct rspi_data *rspi)
464 {
465 return rspi_wait_for_interrupt(rspi, SPSR_SPRF, SPCR_SPRIE);
466 }
467
468 static int rspi_data_out(struct rspi_data *rspi, u8 data)
469 {
470 int error = rspi_wait_for_tx_empty(rspi);
471 if (error < 0) {
472 dev_err(&rspi->ctlr->dev, "transmit timeout\n");
473 return error;
474 }
475 rspi_write_data(rspi, data);
476 return 0;
477 }
478
479 static int rspi_data_in(struct rspi_data *rspi)
480 {
481 int error;
482 u8 data;
483
484 error = rspi_wait_for_rx_full(rspi);
485 if (error < 0) {
486 dev_err(&rspi->ctlr->dev, "receive timeout\n");
487 return error;
488 }
489 data = rspi_read_data(rspi);
490 return data;
491 }
492
493 static int rspi_pio_transfer(struct rspi_data *rspi, const u8 *tx, u8 *rx,
494 unsigned int n)
495 {
496 while (n-- > 0) {
497 if (tx) {
498 int ret = rspi_data_out(rspi, *tx++);
499 if (ret < 0)
500 return ret;
501 }
502 if (rx) {
503 int ret = rspi_data_in(rspi);
504 if (ret < 0)
505 return ret;
506 *rx++ = ret;
507 }
508 }
509
510 return 0;
511 }
512
513 static void rspi_dma_complete(void *arg)
514 {
515 struct rspi_data *rspi = arg;
516
517 rspi->dma_callbacked = 1;
518 wake_up_interruptible(&rspi->wait);
519 }
520
521 static int rspi_dma_transfer(struct rspi_data *rspi, struct sg_table *tx,
522 struct sg_table *rx)
523 {
524 struct dma_async_tx_descriptor *desc_tx = NULL, *desc_rx = NULL;
525 u8 irq_mask = 0;
526 unsigned int other_irq = 0;
527 dma_cookie_t cookie;
528 int ret;
529
530 /* First prepare and submit the DMA request(s), as this may fail */
531 if (rx) {
532 desc_rx = dmaengine_prep_slave_sg(rspi->ctlr->dma_rx, rx->sgl,
533 rx->nents, DMA_DEV_TO_MEM,
534 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
535 if (!desc_rx) {
536 ret = -EAGAIN;
537 goto no_dma_rx;
538 }
539
540 desc_rx->callback = rspi_dma_complete;
541 desc_rx->callback_param = rspi;
542 cookie = dmaengine_submit(desc_rx);
543 if (dma_submit_error(cookie)) {
544 ret = cookie;
545 goto no_dma_rx;
546 }
547
548 irq_mask |= SPCR_SPRIE;
549 }
550
551 if (tx) {
552 desc_tx = dmaengine_prep_slave_sg(rspi->ctlr->dma_tx, tx->sgl,
553 tx->nents, DMA_MEM_TO_DEV,
554 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
555 if (!desc_tx) {
556 ret = -EAGAIN;
557 goto no_dma_tx;
558 }
559
560 if (rx) {
561 /* No callback */
562 desc_tx->callback = NULL;
563 } else {
564 desc_tx->callback = rspi_dma_complete;
565 desc_tx->callback_param = rspi;
566 }
567 cookie = dmaengine_submit(desc_tx);
568 if (dma_submit_error(cookie)) {
569 ret = cookie;
570 goto no_dma_tx;
571 }
572
573 irq_mask |= SPCR_SPTIE;
574 }
575
576 /*
577 * DMAC needs SPxIE, but if SPxIE is set, the IRQ routine will be
578 * called. So, this driver disables the IRQ while DMA transfer.
579 */
580 if (tx)
581 disable_irq(other_irq = rspi->tx_irq);
582 if (rx && rspi->rx_irq != other_irq)
583 disable_irq(rspi->rx_irq);
584
585 rspi_enable_irq(rspi, irq_mask);
586 rspi->dma_callbacked = 0;
587
588 /* Now start DMA */
589 if (rx)
590 dma_async_issue_pending(rspi->ctlr->dma_rx);
591 if (tx)
592 dma_async_issue_pending(rspi->ctlr->dma_tx);
593
594 ret = wait_event_interruptible_timeout(rspi->wait,
595 rspi->dma_callbacked, HZ);
596 if (ret > 0 && rspi->dma_callbacked) {
597 ret = 0;
598 } else {
599 if (!ret) {
600 dev_err(&rspi->ctlr->dev, "DMA timeout\n");
601 ret = -ETIMEDOUT;
602 }
603 if (tx)
604 dmaengine_terminate_all(rspi->ctlr->dma_tx);
605 if (rx)
606 dmaengine_terminate_all(rspi->ctlr->dma_rx);
607 }
608
609 rspi_disable_irq(rspi, irq_mask);
610
611 if (tx)
612 enable_irq(rspi->tx_irq);
613 if (rx && rspi->rx_irq != other_irq)
614 enable_irq(rspi->rx_irq);
615
616 return ret;
617
618 no_dma_tx:
619 if (rx)
620 dmaengine_terminate_all(rspi->ctlr->dma_rx);
621 no_dma_rx:
622 if (ret == -EAGAIN) {
623 pr_warn_once("%s %s: DMA not available, falling back to PIO\n",
624 dev_driver_string(&rspi->ctlr->dev),
625 dev_name(&rspi->ctlr->dev));
626 }
627 return ret;
628 }
629
630 static void rspi_receive_init(const struct rspi_data *rspi)
631 {
632 u8 spsr;
633
634 spsr = rspi_read8(rspi, RSPI_SPSR);
635 if (spsr & SPSR_SPRF)
636 rspi_read_data(rspi); /* dummy read */
637 if (spsr & SPSR_OVRF)
638 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPSR) & ~SPSR_OVRF,
639 RSPI_SPSR);
640 }
641
642 static void rspi_rz_receive_init(const struct rspi_data *rspi)
643 {
644 rspi_receive_init(rspi);
645 rspi_write8(rspi, SPBFCR_TXRST | SPBFCR_RXRST, RSPI_SPBFCR);
646 rspi_write8(rspi, 0, RSPI_SPBFCR);
647 }
648
649 static void qspi_receive_init(const struct rspi_data *rspi)
650 {
651 u8 spsr;
652
653 spsr = rspi_read8(rspi, RSPI_SPSR);
654 if (spsr & SPSR_SPRF)
655 rspi_read_data(rspi); /* dummy read */
656 rspi_write8(rspi, SPBFCR_TXRST | SPBFCR_RXRST, QSPI_SPBFCR);
657 rspi_write8(rspi, 0, QSPI_SPBFCR);
658 }
659
660 static bool __rspi_can_dma(const struct rspi_data *rspi,
661 const struct spi_transfer *xfer)
662 {
663 return xfer->len > rspi->ops->fifo_size;
664 }
665
666 static bool rspi_can_dma(struct spi_controller *ctlr, struct spi_device *spi,
667 struct spi_transfer *xfer)
668 {
669 struct rspi_data *rspi = spi_controller_get_devdata(ctlr);
670
671 return __rspi_can_dma(rspi, xfer);
672 }
673
674 static int rspi_dma_check_then_transfer(struct rspi_data *rspi,
675 struct spi_transfer *xfer)
676 {
677 if (!rspi->ctlr->can_dma || !__rspi_can_dma(rspi, xfer))
678 return -EAGAIN;
679
680 /* rx_buf can be NULL on RSPI on SH in TX-only Mode */
681 return rspi_dma_transfer(rspi, &xfer->tx_sg,
682 xfer->rx_buf ? &xfer->rx_sg : NULL);
683 }
684
685 static int rspi_common_transfer(struct rspi_data *rspi,
686 struct spi_transfer *xfer)
687 {
688 int ret;
689
690 ret = rspi_dma_check_then_transfer(rspi, xfer);
691 if (ret != -EAGAIN)
692 return ret;
693
694 ret = rspi_pio_transfer(rspi, xfer->tx_buf, xfer->rx_buf, xfer->len);
695 if (ret < 0)
696 return ret;
697
698 /* Wait for the last transmission */
699 rspi_wait_for_tx_empty(rspi);
700
701 return 0;
702 }
703
704 static int rspi_transfer_one(struct spi_controller *ctlr,
705 struct spi_device *spi, struct spi_transfer *xfer)
706 {
707 struct rspi_data *rspi = spi_controller_get_devdata(ctlr);
708 u8 spcr;
709
710 spcr = rspi_read8(rspi, RSPI_SPCR);
711 if (xfer->rx_buf) {
712 rspi_receive_init(rspi);
713 spcr &= ~SPCR_TXMD;
714 } else {
715 spcr |= SPCR_TXMD;
716 }
717 rspi_write8(rspi, spcr, RSPI_SPCR);
718
719 return rspi_common_transfer(rspi, xfer);
720 }
721
722 static int rspi_rz_transfer_one(struct spi_controller *ctlr,
723 struct spi_device *spi,
724 struct spi_transfer *xfer)
725 {
726 struct rspi_data *rspi = spi_controller_get_devdata(ctlr);
727
728 rspi_rz_receive_init(rspi);
729
730 return rspi_common_transfer(rspi, xfer);
731 }
732
733 static int qspi_trigger_transfer_out_in(struct rspi_data *rspi, const u8 *tx,
734 u8 *rx, unsigned int len)
735 {
736 unsigned int i, n;
737 int ret;
738
739 while (len > 0) {
740 n = qspi_set_send_trigger(rspi, len);
741 qspi_set_receive_trigger(rspi, len);
742 if (n == QSPI_BUFFER_SIZE) {
743 ret = rspi_wait_for_tx_empty(rspi);
744 if (ret < 0) {
745 dev_err(&rspi->ctlr->dev, "transmit timeout\n");
746 return ret;
747 }
748 for (i = 0; i < n; i++)
749 rspi_write_data(rspi, *tx++);
750
751 ret = rspi_wait_for_rx_full(rspi);
752 if (ret < 0) {
753 dev_err(&rspi->ctlr->dev, "receive timeout\n");
754 return ret;
755 }
756 for (i = 0; i < n; i++)
757 *rx++ = rspi_read_data(rspi);
758 } else {
759 ret = rspi_pio_transfer(rspi, tx, rx, n);
760 if (ret < 0)
761 return ret;
762 }
763 len -= n;
764 }
765
766 return 0;
767 }
768
769 static int qspi_transfer_out_in(struct rspi_data *rspi,
770 struct spi_transfer *xfer)
771 {
772 int ret;
773
774 qspi_receive_init(rspi);
775
776 ret = rspi_dma_check_then_transfer(rspi, xfer);
777 if (ret != -EAGAIN)
778 return ret;
779
780 return qspi_trigger_transfer_out_in(rspi, xfer->tx_buf,
781 xfer->rx_buf, xfer->len);
782 }
783
784 static int qspi_transfer_out(struct rspi_data *rspi, struct spi_transfer *xfer)
785 {
786 const u8 *tx = xfer->tx_buf;
787 unsigned int n = xfer->len;
788 unsigned int i, len;
789 int ret;
790
791 if (rspi->ctlr->can_dma && __rspi_can_dma(rspi, xfer)) {
792 ret = rspi_dma_transfer(rspi, &xfer->tx_sg, NULL);
793 if (ret != -EAGAIN)
794 return ret;
795 }
796
797 while (n > 0) {
798 len = qspi_set_send_trigger(rspi, n);
799 if (len == QSPI_BUFFER_SIZE) {
800 ret = rspi_wait_for_tx_empty(rspi);
801 if (ret < 0) {
802 dev_err(&rspi->ctlr->dev, "transmit timeout\n");
803 return ret;
804 }
805 for (i = 0; i < len; i++)
806 rspi_write_data(rspi, *tx++);
807 } else {
808 ret = rspi_pio_transfer(rspi, tx, NULL, len);
809 if (ret < 0)
810 return ret;
811 }
812 n -= len;
813 }
814
815 /* Wait for the last transmission */
816 rspi_wait_for_tx_empty(rspi);
817
818 return 0;
819 }
820
821 static int qspi_transfer_in(struct rspi_data *rspi, struct spi_transfer *xfer)
822 {
823 u8 *rx = xfer->rx_buf;
824 unsigned int n = xfer->len;
825 unsigned int i, len;
826 int ret;
827
828 if (rspi->ctlr->can_dma && __rspi_can_dma(rspi, xfer)) {
829 int ret = rspi_dma_transfer(rspi, NULL, &xfer->rx_sg);
830 if (ret != -EAGAIN)
831 return ret;
832 }
833
834 while (n > 0) {
835 len = qspi_set_receive_trigger(rspi, n);
836 if (len == QSPI_BUFFER_SIZE) {
837 ret = rspi_wait_for_rx_full(rspi);
838 if (ret < 0) {
839 dev_err(&rspi->ctlr->dev, "receive timeout\n");
840 return ret;
841 }
842 for (i = 0; i < len; i++)
843 *rx++ = rspi_read_data(rspi);
844 } else {
845 ret = rspi_pio_transfer(rspi, NULL, rx, len);
846 if (ret < 0)
847 return ret;
848 }
849 n -= len;
850 }
851
852 return 0;
853 }
854
855 static int qspi_transfer_one(struct spi_controller *ctlr,
856 struct spi_device *spi, struct spi_transfer *xfer)
857 {
858 struct rspi_data *rspi = spi_controller_get_devdata(ctlr);
859
860 if (spi->mode & SPI_LOOP) {
861 return qspi_transfer_out_in(rspi, xfer);
862 } else if (xfer->tx_nbits > SPI_NBITS_SINGLE) {
863 /* Quad or Dual SPI Write */
864 return qspi_transfer_out(rspi, xfer);
865 } else if (xfer->rx_nbits > SPI_NBITS_SINGLE) {
866 /* Quad or Dual SPI Read */
867 return qspi_transfer_in(rspi, xfer);
868 } else {
869 /* Single SPI Transfer */
870 return qspi_transfer_out_in(rspi, xfer);
871 }
872 }
873
874 static int rspi_setup(struct spi_device *spi)
875 {
876 struct rspi_data *rspi = spi_controller_get_devdata(spi->controller);
877
878 rspi->max_speed_hz = spi->max_speed_hz;
879
880 rspi->spcmd = SPCMD_SSLKP;
881 if (spi->mode & SPI_CPOL)
882 rspi->spcmd |= SPCMD_CPOL;
883 if (spi->mode & SPI_CPHA)
884 rspi->spcmd |= SPCMD_CPHA;
885
886 /* CMOS output mode and MOSI signal from previous transfer */
887 rspi->sppcr = 0;
888 if (spi->mode & SPI_LOOP)
889 rspi->sppcr |= SPPCR_SPLP;
890
891 set_config_register(rspi, 8);
892
893 return 0;
894 }
895
896 static u16 qspi_transfer_mode(const struct spi_transfer *xfer)
897 {
898 if (xfer->tx_buf)
899 switch (xfer->tx_nbits) {
900 case SPI_NBITS_QUAD:
901 return SPCMD_SPIMOD_QUAD;
902 case SPI_NBITS_DUAL:
903 return SPCMD_SPIMOD_DUAL;
904 default:
905 return 0;
906 }
907 if (xfer->rx_buf)
908 switch (xfer->rx_nbits) {
909 case SPI_NBITS_QUAD:
910 return SPCMD_SPIMOD_QUAD | SPCMD_SPRW;
911 case SPI_NBITS_DUAL:
912 return SPCMD_SPIMOD_DUAL | SPCMD_SPRW;
913 default:
914 return 0;
915 }
916
917 return 0;
918 }
919
920 static int qspi_setup_sequencer(struct rspi_data *rspi,
921 const struct spi_message *msg)
922 {
923 const struct spi_transfer *xfer;
924 unsigned int i = 0, len = 0;
925 u16 current_mode = 0xffff, mode;
926
927 list_for_each_entry(xfer, &msg->transfers, transfer_list) {
928 mode = qspi_transfer_mode(xfer);
929 if (mode == current_mode) {
930 len += xfer->len;
931 continue;
932 }
933
934 /* Transfer mode change */
935 if (i) {
936 /* Set transfer data length of previous transfer */
937 rspi_write32(rspi, len, QSPI_SPBMUL(i - 1));
938 }
939
940 if (i >= QSPI_NUM_SPCMD) {
941 dev_err(&msg->spi->dev,
942 "Too many different transfer modes");
943 return -EINVAL;
944 }
945
946 /* Program transfer mode for this transfer */
947 rspi_write16(rspi, rspi->spcmd | mode, RSPI_SPCMD(i));
948 current_mode = mode;
949 len = xfer->len;
950 i++;
951 }
952 if (i) {
953 /* Set final transfer data length and sequence length */
954 rspi_write32(rspi, len, QSPI_SPBMUL(i - 1));
955 rspi_write8(rspi, i - 1, RSPI_SPSCR);
956 }
957
958 return 0;
959 }
960
961 static int rspi_prepare_message(struct spi_controller *ctlr,
962 struct spi_message *msg)
963 {
964 struct rspi_data *rspi = spi_controller_get_devdata(ctlr);
965 int ret;
966
967 if (msg->spi->mode &
968 (SPI_TX_DUAL | SPI_TX_QUAD | SPI_RX_DUAL | SPI_RX_QUAD)) {
969 /* Setup sequencer for messages with multiple transfer modes */
970 ret = qspi_setup_sequencer(rspi, msg);
971 if (ret < 0)
972 return ret;
973 }
974
975 /* Enable SPI function in master mode */
976 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) | SPCR_SPE, RSPI_SPCR);
977 return 0;
978 }
979
980 static int rspi_unprepare_message(struct spi_controller *ctlr,
981 struct spi_message *msg)
982 {
983 struct rspi_data *rspi = spi_controller_get_devdata(ctlr);
984
985 /* Disable SPI function */
986 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) & ~SPCR_SPE, RSPI_SPCR);
987
988 /* Reset sequencer for Single SPI Transfers */
989 rspi_write16(rspi, rspi->spcmd, RSPI_SPCMD0);
990 rspi_write8(rspi, 0, RSPI_SPSCR);
991 return 0;
992 }
993
994 static irqreturn_t rspi_irq_mux(int irq, void *_sr)
995 {
996 struct rspi_data *rspi = _sr;
997 u8 spsr;
998 irqreturn_t ret = IRQ_NONE;
999 u8 disable_irq = 0;
1000
1001 rspi->spsr = spsr = rspi_read8(rspi, RSPI_SPSR);
1002 if (spsr & SPSR_SPRF)
1003 disable_irq |= SPCR_SPRIE;
1004 if (spsr & SPSR_SPTEF)
1005 disable_irq |= SPCR_SPTIE;
1006
1007 if (disable_irq) {
1008 ret = IRQ_HANDLED;
1009 rspi_disable_irq(rspi, disable_irq);
1010 wake_up(&rspi->wait);
1011 }
1012
1013 return ret;
1014 }
1015
1016 static irqreturn_t rspi_irq_rx(int irq, void *_sr)
1017 {
1018 struct rspi_data *rspi = _sr;
1019 u8 spsr;
1020
1021 rspi->spsr = spsr = rspi_read8(rspi, RSPI_SPSR);
1022 if (spsr & SPSR_SPRF) {
1023 rspi_disable_irq(rspi, SPCR_SPRIE);
1024 wake_up(&rspi->wait);
1025 return IRQ_HANDLED;
1026 }
1027
1028 return 0;
1029 }
1030
1031 static irqreturn_t rspi_irq_tx(int irq, void *_sr)
1032 {
1033 struct rspi_data *rspi = _sr;
1034 u8 spsr;
1035
1036 rspi->spsr = spsr = rspi_read8(rspi, RSPI_SPSR);
1037 if (spsr & SPSR_SPTEF) {
1038 rspi_disable_irq(rspi, SPCR_SPTIE);
1039 wake_up(&rspi->wait);
1040 return IRQ_HANDLED;
1041 }
1042
1043 return 0;
1044 }
1045
1046 static struct dma_chan *rspi_request_dma_chan(struct device *dev,
1047 enum dma_transfer_direction dir,
1048 unsigned int id,
1049 dma_addr_t port_addr)
1050 {
1051 dma_cap_mask_t mask;
1052 struct dma_chan *chan;
1053 struct dma_slave_config cfg;
1054 int ret;
1055
1056 dma_cap_zero(mask);
1057 dma_cap_set(DMA_SLAVE, mask);
1058
1059 chan = dma_request_slave_channel_compat(mask, shdma_chan_filter,
1060 (void *)(unsigned long)id, dev,
1061 dir == DMA_MEM_TO_DEV ? "tx" : "rx");
1062 if (!chan) {
1063 dev_warn(dev, "dma_request_slave_channel_compat failed\n");
1064 return NULL;
1065 }
1066
1067 memset(&cfg, 0, sizeof(cfg));
1068 cfg.direction = dir;
1069 if (dir == DMA_MEM_TO_DEV) {
1070 cfg.dst_addr = port_addr;
1071 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1072 } else {
1073 cfg.src_addr = port_addr;
1074 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1075 }
1076
1077 ret = dmaengine_slave_config(chan, &cfg);
1078 if (ret) {
1079 dev_warn(dev, "dmaengine_slave_config failed %d\n", ret);
1080 dma_release_channel(chan);
1081 return NULL;
1082 }
1083
1084 return chan;
1085 }
1086
1087 static int rspi_request_dma(struct device *dev, struct spi_controller *ctlr,
1088 const struct resource *res)
1089 {
1090 const struct rspi_plat_data *rspi_pd = dev_get_platdata(dev);
1091 unsigned int dma_tx_id, dma_rx_id;
1092
1093 if (dev->of_node) {
1094 /* In the OF case we will get the slave IDs from the DT */
1095 dma_tx_id = 0;
1096 dma_rx_id = 0;
1097 } else if (rspi_pd && rspi_pd->dma_tx_id && rspi_pd->dma_rx_id) {
1098 dma_tx_id = rspi_pd->dma_tx_id;
1099 dma_rx_id = rspi_pd->dma_rx_id;
1100 } else {
1101 /* The driver assumes no error. */
1102 return 0;
1103 }
1104
1105 ctlr->dma_tx = rspi_request_dma_chan(dev, DMA_MEM_TO_DEV, dma_tx_id,
1106 res->start + RSPI_SPDR);
1107 if (!ctlr->dma_tx)
1108 return -ENODEV;
1109
1110 ctlr->dma_rx = rspi_request_dma_chan(dev, DMA_DEV_TO_MEM, dma_rx_id,
1111 res->start + RSPI_SPDR);
1112 if (!ctlr->dma_rx) {
1113 dma_release_channel(ctlr->dma_tx);
1114 ctlr->dma_tx = NULL;
1115 return -ENODEV;
1116 }
1117
1118 ctlr->can_dma = rspi_can_dma;
1119 dev_info(dev, "DMA available");
1120 return 0;
1121 }
1122
1123 static void rspi_release_dma(struct spi_controller *ctlr)
1124 {
1125 if (ctlr->dma_tx)
1126 dma_release_channel(ctlr->dma_tx);
1127 if (ctlr->dma_rx)
1128 dma_release_channel(ctlr->dma_rx);
1129 }
1130
1131 static int rspi_remove(struct platform_device *pdev)
1132 {
1133 struct rspi_data *rspi = platform_get_drvdata(pdev);
1134
1135 rspi_release_dma(rspi->ctlr);
1136 pm_runtime_disable(&pdev->dev);
1137
1138 return 0;
1139 }
1140
1141 static const struct spi_ops rspi_ops = {
1142 .set_config_register = rspi_set_config_register,
1143 .transfer_one = rspi_transfer_one,
1144 .mode_bits = SPI_CPHA | SPI_CPOL | SPI_LOOP,
1145 .flags = SPI_CONTROLLER_MUST_TX,
1146 .fifo_size = 8,
1147 };
1148
1149 static const struct spi_ops rspi_rz_ops = {
1150 .set_config_register = rspi_rz_set_config_register,
1151 .transfer_one = rspi_rz_transfer_one,
1152 .mode_bits = SPI_CPHA | SPI_CPOL | SPI_LOOP,
1153 .flags = SPI_CONTROLLER_MUST_RX | SPI_CONTROLLER_MUST_TX,
1154 .fifo_size = 8, /* 8 for TX, 32 for RX */
1155 };
1156
1157 static const struct spi_ops qspi_ops = {
1158 .set_config_register = qspi_set_config_register,
1159 .transfer_one = qspi_transfer_one,
1160 .mode_bits = SPI_CPHA | SPI_CPOL | SPI_LOOP |
1161 SPI_TX_DUAL | SPI_TX_QUAD |
1162 SPI_RX_DUAL | SPI_RX_QUAD,
1163 .flags = SPI_CONTROLLER_MUST_RX | SPI_CONTROLLER_MUST_TX,
1164 .fifo_size = 32,
1165 };
1166
1167 #ifdef CONFIG_OF
1168 static const struct of_device_id rspi_of_match[] = {
1169 /* RSPI on legacy SH */
1170 { .compatible = "renesas,rspi", .data = &rspi_ops },
1171 /* RSPI on RZ/A1H */
1172 { .compatible = "renesas,rspi-rz", .data = &rspi_rz_ops },
1173 /* QSPI on R-Car Gen2 */
1174 { .compatible = "renesas,qspi", .data = &qspi_ops },
1175 { /* sentinel */ }
1176 };
1177
1178 MODULE_DEVICE_TABLE(of, rspi_of_match);
1179
1180 static int rspi_parse_dt(struct device *dev, struct spi_controller *ctlr)
1181 {
1182 u32 num_cs;
1183 int error;
1184
1185 /* Parse DT properties */
1186 error = of_property_read_u32(dev->of_node, "num-cs", &num_cs);
1187 if (error) {
1188 dev_err(dev, "of_property_read_u32 num-cs failed %d\n", error);
1189 return error;
1190 }
1191
1192 ctlr->num_chipselect = num_cs;
1193 return 0;
1194 }
1195 #else
1196 #define rspi_of_match NULL
1197 static inline int rspi_parse_dt(struct device *dev, struct spi_controller *ctlr)
1198 {
1199 return -EINVAL;
1200 }
1201 #endif /* CONFIG_OF */
1202
1203 static int rspi_request_irq(struct device *dev, unsigned int irq,
1204 irq_handler_t handler, const char *suffix,
1205 void *dev_id)
1206 {
1207 const char *name = devm_kasprintf(dev, GFP_KERNEL, "%s:%s",
1208 dev_name(dev), suffix);
1209 if (!name)
1210 return -ENOMEM;
1211
1212 return devm_request_irq(dev, irq, handler, 0, name, dev_id);
1213 }
1214
1215 static int rspi_probe(struct platform_device *pdev)
1216 {
1217 struct resource *res;
1218 struct spi_controller *ctlr;
1219 struct rspi_data *rspi;
1220 int ret;
1221 const struct rspi_plat_data *rspi_pd;
1222 const struct spi_ops *ops;
1223
1224 ctlr = spi_alloc_master(&pdev->dev, sizeof(struct rspi_data));
1225 if (ctlr == NULL)
1226 return -ENOMEM;
1227
1228 ops = of_device_get_match_data(&pdev->dev);
1229 if (ops) {
1230 ret = rspi_parse_dt(&pdev->dev, ctlr);
1231 if (ret)
1232 goto error1;
1233 } else {
1234 ops = (struct spi_ops *)pdev->id_entry->driver_data;
1235 rspi_pd = dev_get_platdata(&pdev->dev);
1236 if (rspi_pd && rspi_pd->num_chipselect)
1237 ctlr->num_chipselect = rspi_pd->num_chipselect;
1238 else
1239 ctlr->num_chipselect = 2; /* default */
1240 }
1241
1242 /* ops parameter check */
1243 if (!ops->set_config_register) {
1244 dev_err(&pdev->dev, "there is no set_config_register\n");
1245 ret = -ENODEV;
1246 goto error1;
1247 }
1248
1249 rspi = spi_controller_get_devdata(ctlr);
1250 platform_set_drvdata(pdev, rspi);
1251 rspi->ops = ops;
1252 rspi->ctlr = ctlr;
1253
1254 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1255 rspi->addr = devm_ioremap_resource(&pdev->dev, res);
1256 if (IS_ERR(rspi->addr)) {
1257 ret = PTR_ERR(rspi->addr);
1258 goto error1;
1259 }
1260
1261 rspi->clk = devm_clk_get(&pdev->dev, NULL);
1262 if (IS_ERR(rspi->clk)) {
1263 dev_err(&pdev->dev, "cannot get clock\n");
1264 ret = PTR_ERR(rspi->clk);
1265 goto error1;
1266 }
1267
1268 pm_runtime_enable(&pdev->dev);
1269
1270 init_waitqueue_head(&rspi->wait);
1271
1272 ctlr->bus_num = pdev->id;
1273 ctlr->setup = rspi_setup;
1274 ctlr->auto_runtime_pm = true;
1275 ctlr->transfer_one = ops->transfer_one;
1276 ctlr->prepare_message = rspi_prepare_message;
1277 ctlr->unprepare_message = rspi_unprepare_message;
1278 ctlr->mode_bits = ops->mode_bits;
1279 ctlr->flags = ops->flags;
1280 ctlr->dev.of_node = pdev->dev.of_node;
1281
1282 ret = platform_get_irq_byname(pdev, "rx");
1283 if (ret < 0) {
1284 ret = platform_get_irq_byname(pdev, "mux");
1285 if (ret < 0)
1286 ret = platform_get_irq(pdev, 0);
1287 if (ret >= 0)
1288 rspi->rx_irq = rspi->tx_irq = ret;
1289 } else {
1290 rspi->rx_irq = ret;
1291 ret = platform_get_irq_byname(pdev, "tx");
1292 if (ret >= 0)
1293 rspi->tx_irq = ret;
1294 }
1295 if (ret < 0) {
1296 dev_err(&pdev->dev, "platform_get_irq error\n");
1297 goto error2;
1298 }
1299
1300 if (rspi->rx_irq == rspi->tx_irq) {
1301 /* Single multiplexed interrupt */
1302 ret = rspi_request_irq(&pdev->dev, rspi->rx_irq, rspi_irq_mux,
1303 "mux", rspi);
1304 } else {
1305 /* Multi-interrupt mode, only SPRI and SPTI are used */
1306 ret = rspi_request_irq(&pdev->dev, rspi->rx_irq, rspi_irq_rx,
1307 "rx", rspi);
1308 if (!ret)
1309 ret = rspi_request_irq(&pdev->dev, rspi->tx_irq,
1310 rspi_irq_tx, "tx", rspi);
1311 }
1312 if (ret < 0) {
1313 dev_err(&pdev->dev, "request_irq error\n");
1314 goto error2;
1315 }
1316
1317 ret = rspi_request_dma(&pdev->dev, ctlr, res);
1318 if (ret < 0)
1319 dev_warn(&pdev->dev, "DMA not available, using PIO\n");
1320
1321 ret = devm_spi_register_controller(&pdev->dev, ctlr);
1322 if (ret < 0) {
1323 dev_err(&pdev->dev, "devm_spi_register_controller error.\n");
1324 goto error3;
1325 }
1326
1327 dev_info(&pdev->dev, "probed\n");
1328
1329 return 0;
1330
1331 error3:
1332 rspi_release_dma(ctlr);
1333 error2:
1334 pm_runtime_disable(&pdev->dev);
1335 error1:
1336 spi_controller_put(ctlr);
1337
1338 return ret;
1339 }
1340
1341 static const struct platform_device_id spi_driver_ids[] = {
1342 { "rspi", (kernel_ulong_t)&rspi_ops },
1343 { "rspi-rz", (kernel_ulong_t)&rspi_rz_ops },
1344 { "qspi", (kernel_ulong_t)&qspi_ops },
1345 {},
1346 };
1347
1348 MODULE_DEVICE_TABLE(platform, spi_driver_ids);
1349
1350 #ifdef CONFIG_PM_SLEEP
1351 static int rspi_suspend(struct device *dev)
1352 {
1353 struct rspi_data *rspi = dev_get_drvdata(dev);
1354
1355 return spi_controller_suspend(rspi->ctlr);
1356 }
1357
1358 static int rspi_resume(struct device *dev)
1359 {
1360 struct rspi_data *rspi = dev_get_drvdata(dev);
1361
1362 return spi_controller_resume(rspi->ctlr);
1363 }
1364
1365 static SIMPLE_DEV_PM_OPS(rspi_pm_ops, rspi_suspend, rspi_resume);
1366 #define DEV_PM_OPS &rspi_pm_ops
1367 #else
1368 #define DEV_PM_OPS NULL
1369 #endif /* CONFIG_PM_SLEEP */
1370
1371 static struct platform_driver rspi_driver = {
1372 .probe = rspi_probe,
1373 .remove = rspi_remove,
1374 .id_table = spi_driver_ids,
1375 .driver = {
1376 .name = "renesas_spi",
1377 .pm = DEV_PM_OPS,
1378 .of_match_table = of_match_ptr(rspi_of_match),
1379 },
1380 };
1381 module_platform_driver(rspi_driver);
1382
1383 MODULE_DESCRIPTION("Renesas RSPI bus driver");
1384 MODULE_LICENSE("GPL v2");
1385 MODULE_AUTHOR("Yoshihiro Shimoda");
1386 MODULE_ALIAS("platform:rspi");
Linux with added FPC-III support