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Linux 5.1.15
[linux/fpc-iii.git] / drivers / spi / spi-topcliff-pch.c
blob8a5966963834c3baf2fd36f37e204675a0a72b56
1 /*
2 * SPI bus driver for the Topcliff PCH used by Intel SoCs
3 *
4 * Copyright (C) 2011 LAPIS Semiconductor Co., Ltd.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16 #include <linux/delay.h>
17 #include <linux/pci.h>
18 #include <linux/wait.h>
19 #include <linux/spi/spi.h>
20 #include <linux/interrupt.h>
21 #include <linux/sched.h>
22 #include <linux/spi/spidev.h>
23 #include <linux/module.h>
24 #include <linux/device.h>
25 #include <linux/platform_device.h>
26
27 #include <linux/dmaengine.h>
28 #include <linux/pch_dma.h>
29
30 /* Register offsets */
31 #define PCH_SPCR 0x00 /* SPI control register */
32 #define PCH_SPBRR 0x04 /* SPI baud rate register */
33 #define PCH_SPSR 0x08 /* SPI status register */
34 #define PCH_SPDWR 0x0C /* SPI write data register */
35 #define PCH_SPDRR 0x10 /* SPI read data register */
36 #define PCH_SSNXCR 0x18 /* SSN Expand Control Register */
37 #define PCH_SRST 0x1C /* SPI reset register */
38 #define PCH_ADDRESS_SIZE 0x20
39
40 #define PCH_SPSR_TFD 0x000007C0
41 #define PCH_SPSR_RFD 0x0000F800
42
43 #define PCH_READABLE(x) (((x) & PCH_SPSR_RFD)>>11)
44 #define PCH_WRITABLE(x) (((x) & PCH_SPSR_TFD)>>6)
45
46 #define PCH_RX_THOLD 7
47 #define PCH_RX_THOLD_MAX 15
48
49 #define PCH_TX_THOLD 2
50
51 #define PCH_MAX_BAUDRATE 5000000
52 #define PCH_MAX_FIFO_DEPTH 16
53
54 #define STATUS_RUNNING 1
55 #define STATUS_EXITING 2
56 #define PCH_SLEEP_TIME 10
57
58 #define SSN_LOW 0x02U
59 #define SSN_HIGH 0x03U
60 #define SSN_NO_CONTROL 0x00U
61 #define PCH_MAX_CS 0xFF
62 #define PCI_DEVICE_ID_GE_SPI 0x8816
63
64 #define SPCR_SPE_BIT (1 << 0)
65 #define SPCR_MSTR_BIT (1 << 1)
66 #define SPCR_LSBF_BIT (1 << 4)
67 #define SPCR_CPHA_BIT (1 << 5)
68 #define SPCR_CPOL_BIT (1 << 6)
69 #define SPCR_TFIE_BIT (1 << 8)
70 #define SPCR_RFIE_BIT (1 << 9)
71 #define SPCR_FIE_BIT (1 << 10)
72 #define SPCR_ORIE_BIT (1 << 11)
73 #define SPCR_MDFIE_BIT (1 << 12)
74 #define SPCR_FICLR_BIT (1 << 24)
75 #define SPSR_TFI_BIT (1 << 0)
76 #define SPSR_RFI_BIT (1 << 1)
77 #define SPSR_FI_BIT (1 << 2)
78 #define SPSR_ORF_BIT (1 << 3)
79 #define SPBRR_SIZE_BIT (1 << 10)
80
81 #define PCH_ALL (SPCR_TFIE_BIT|SPCR_RFIE_BIT|SPCR_FIE_BIT|\
82 SPCR_ORIE_BIT|SPCR_MDFIE_BIT)
83
84 #define SPCR_RFIC_FIELD 20
85 #define SPCR_TFIC_FIELD 16
86
87 #define MASK_SPBRR_SPBR_BITS ((1 << 10) - 1)
88 #define MASK_RFIC_SPCR_BITS (0xf << SPCR_RFIC_FIELD)
89 #define MASK_TFIC_SPCR_BITS (0xf << SPCR_TFIC_FIELD)
90
91 #define PCH_CLOCK_HZ 50000000
92 #define PCH_MAX_SPBR 1023
93
94 /* Definition for ML7213/ML7223/ML7831 by LAPIS Semiconductor */
95 #define PCI_DEVICE_ID_ML7213_SPI 0x802c
96 #define PCI_DEVICE_ID_ML7223_SPI 0x800F
97 #define PCI_DEVICE_ID_ML7831_SPI 0x8816
98
99 /*
100 * Set the number of SPI instance max
101 * Intel EG20T PCH : 1ch
102 * LAPIS Semiconductor ML7213 IOH : 2ch
103 * LAPIS Semiconductor ML7223 IOH : 1ch
104 * LAPIS Semiconductor ML7831 IOH : 1ch
105 */
106 #define PCH_SPI_MAX_DEV 2
107
108 #define PCH_BUF_SIZE 4096
109 #define PCH_DMA_TRANS_SIZE 12
110
111 static int use_dma = 1;
112
113 struct pch_spi_dma_ctrl {
114 struct dma_async_tx_descriptor *desc_tx;
115 struct dma_async_tx_descriptor *desc_rx;
116 struct pch_dma_slave param_tx;
117 struct pch_dma_slave param_rx;
118 struct dma_chan *chan_tx;
119 struct dma_chan *chan_rx;
120 struct scatterlist *sg_tx_p;
121 struct scatterlist *sg_rx_p;
122 struct scatterlist sg_tx;
123 struct scatterlist sg_rx;
124 int nent;
125 void *tx_buf_virt;
126 void *rx_buf_virt;
127 dma_addr_t tx_buf_dma;
128 dma_addr_t rx_buf_dma;
129 };
130 /**
131 * struct pch_spi_data - Holds the SPI channel specific details
132 * @io_remap_addr: The remapped PCI base address
133 * @master: Pointer to the SPI master structure
134 * @work: Reference to work queue handler
135 * @wait: Wait queue for waking up upon receiving an
136 * interrupt.
137 * @transfer_complete: Status of SPI Transfer
138 * @bcurrent_msg_processing: Status flag for message processing
139 * @lock: Lock for protecting this structure
140 * @queue: SPI Message queue
141 * @status: Status of the SPI driver
142 * @bpw_len: Length of data to be transferred in bits per
143 * word
144 * @transfer_active: Flag showing active transfer
145 * @tx_index: Transmit data count; for bookkeeping during
146 * transfer
147 * @rx_index: Receive data count; for bookkeeping during
148 * transfer
149 * @tx_buff: Buffer for data to be transmitted
150 * @rx_index: Buffer for Received data
151 * @n_curnt_chip: The chip number that this SPI driver currently
152 * operates on
153 * @current_chip: Reference to the current chip that this SPI
154 * driver currently operates on
155 * @current_msg: The current message that this SPI driver is
156 * handling
157 * @cur_trans: The current transfer that this SPI driver is
158 * handling
159 * @board_dat: Reference to the SPI device data structure
160 * @plat_dev: platform_device structure
161 * @ch: SPI channel number
162 * @irq_reg_sts: Status of IRQ registration
163 */
164 struct pch_spi_data {
165 void __iomem *io_remap_addr;
166 unsigned long io_base_addr;
167 struct spi_master *master;
168 struct work_struct work;
169 wait_queue_head_t wait;
170 u8 transfer_complete;
171 u8 bcurrent_msg_processing;
172 spinlock_t lock;
173 struct list_head queue;
174 u8 status;
175 u32 bpw_len;
176 u8 transfer_active;
177 u32 tx_index;
178 u32 rx_index;
179 u16 *pkt_tx_buff;
180 u16 *pkt_rx_buff;
181 u8 n_curnt_chip;
182 struct spi_device *current_chip;
183 struct spi_message *current_msg;
184 struct spi_transfer *cur_trans;
185 struct pch_spi_board_data *board_dat;
186 struct platform_device *plat_dev;
187 int ch;
188 struct pch_spi_dma_ctrl dma;
189 int use_dma;
190 u8 irq_reg_sts;
191 int save_total_len;
192 };
193
194 /**
195 * struct pch_spi_board_data - Holds the SPI device specific details
196 * @pdev: Pointer to the PCI device
197 * @suspend_sts: Status of suspend
198 * @num: The number of SPI device instance
199 */
200 struct pch_spi_board_data {
201 struct pci_dev *pdev;
202 u8 suspend_sts;
203 int num;
204 };
205
206 struct pch_pd_dev_save {
207 int num;
208 struct platform_device *pd_save[PCH_SPI_MAX_DEV];
209 struct pch_spi_board_data *board_dat;
210 };
211
212 static const struct pci_device_id pch_spi_pcidev_id[] = {
213 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_GE_SPI), 1, },
214 { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7213_SPI), 2, },
215 { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7223_SPI), 1, },
216 { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7831_SPI), 1, },
217 { }
218 };
219
220 /**
221 * pch_spi_writereg() - Performs register writes
222 * @master: Pointer to struct spi_master.
223 * @idx: Register offset.
224 * @val: Value to be written to register.
225 */
226 static inline void pch_spi_writereg(struct spi_master *master, int idx, u32 val)
227 {
228 struct pch_spi_data *data = spi_master_get_devdata(master);
229 iowrite32(val, (data->io_remap_addr + idx));
230 }
231
232 /**
233 * pch_spi_readreg() - Performs register reads
234 * @master: Pointer to struct spi_master.
235 * @idx: Register offset.
236 */
237 static inline u32 pch_spi_readreg(struct spi_master *master, int idx)
238 {
239 struct pch_spi_data *data = spi_master_get_devdata(master);
240 return ioread32(data->io_remap_addr + idx);
241 }
242
243 static inline void pch_spi_setclr_reg(struct spi_master *master, int idx,
244 u32 set, u32 clr)
245 {
246 u32 tmp = pch_spi_readreg(master, idx);
247 tmp = (tmp & ~clr) | set;
248 pch_spi_writereg(master, idx, tmp);
249 }
250
251 static void pch_spi_set_master_mode(struct spi_master *master)
252 {
253 pch_spi_setclr_reg(master, PCH_SPCR, SPCR_MSTR_BIT, 0);
254 }
255
256 /**
257 * pch_spi_clear_fifo() - Clears the Transmit and Receive FIFOs
258 * @master: Pointer to struct spi_master.
259 */
260 static void pch_spi_clear_fifo(struct spi_master *master)
261 {
262 pch_spi_setclr_reg(master, PCH_SPCR, SPCR_FICLR_BIT, 0);
263 pch_spi_setclr_reg(master, PCH_SPCR, 0, SPCR_FICLR_BIT);
264 }
265
266 static void pch_spi_handler_sub(struct pch_spi_data *data, u32 reg_spsr_val,
267 void __iomem *io_remap_addr)
268 {
269 u32 n_read, tx_index, rx_index, bpw_len;
270 u16 *pkt_rx_buffer, *pkt_tx_buff;
271 int read_cnt;
272 u32 reg_spcr_val;
273 void __iomem *spsr;
274 void __iomem *spdrr;
275 void __iomem *spdwr;
276
277 spsr = io_remap_addr + PCH_SPSR;
278 iowrite32(reg_spsr_val, spsr);
279
280 if (data->transfer_active) {
281 rx_index = data->rx_index;
282 tx_index = data->tx_index;
283 bpw_len = data->bpw_len;
284 pkt_rx_buffer = data->pkt_rx_buff;
285 pkt_tx_buff = data->pkt_tx_buff;
286
287 spdrr = io_remap_addr + PCH_SPDRR;
288 spdwr = io_remap_addr + PCH_SPDWR;
289
290 n_read = PCH_READABLE(reg_spsr_val);
291
292 for (read_cnt = 0; (read_cnt < n_read); read_cnt++) {
293 pkt_rx_buffer[rx_index++] = ioread32(spdrr);
294 if (tx_index < bpw_len)
295 iowrite32(pkt_tx_buff[tx_index++], spdwr);
296 }
297
298 /* disable RFI if not needed */
299 if ((bpw_len - rx_index) <= PCH_MAX_FIFO_DEPTH) {
300 reg_spcr_val = ioread32(io_remap_addr + PCH_SPCR);
301 reg_spcr_val &= ~SPCR_RFIE_BIT; /* disable RFI */
302
303 /* reset rx threshold */
304 reg_spcr_val &= ~MASK_RFIC_SPCR_BITS;
305 reg_spcr_val |= (PCH_RX_THOLD_MAX << SPCR_RFIC_FIELD);
306
307 iowrite32(reg_spcr_val, (io_remap_addr + PCH_SPCR));
308 }
309
310 /* update counts */
311 data->tx_index = tx_index;
312 data->rx_index = rx_index;
313
314 /* if transfer complete interrupt */
315 if (reg_spsr_val & SPSR_FI_BIT) {
316 if ((tx_index == bpw_len) && (rx_index == tx_index)) {
317 /* disable interrupts */
318 pch_spi_setclr_reg(data->master, PCH_SPCR, 0,
319 PCH_ALL);
320
321 /* transfer is completed;
322 inform pch_spi_process_messages */
323 data->transfer_complete = true;
324 data->transfer_active = false;
325 wake_up(&data->wait);
326 } else {
327 dev_vdbg(&data->master->dev,
328 "%s : Transfer is not completed",
329 __func__);
330 }
331 }
332 }
333 }
334
335 /**
336 * pch_spi_handler() - Interrupt handler
337 * @irq: The interrupt number.
338 * @dev_id: Pointer to struct pch_spi_board_data.
339 */
340 static irqreturn_t pch_spi_handler(int irq, void *dev_id)
341 {
342 u32 reg_spsr_val;
343 void __iomem *spsr;
344 void __iomem *io_remap_addr;
345 irqreturn_t ret = IRQ_NONE;
346 struct pch_spi_data *data = dev_id;
347 struct pch_spi_board_data *board_dat = data->board_dat;
348
349 if (board_dat->suspend_sts) {
350 dev_dbg(&board_dat->pdev->dev,
351 "%s returning due to suspend\n", __func__);
352 return IRQ_NONE;
353 }
354
355 io_remap_addr = data->io_remap_addr;
356 spsr = io_remap_addr + PCH_SPSR;
357
358 reg_spsr_val = ioread32(spsr);
359
360 if (reg_spsr_val & SPSR_ORF_BIT) {
361 dev_err(&board_dat->pdev->dev, "%s Over run error\n", __func__);
362 if (data->current_msg->complete) {
363 data->transfer_complete = true;
364 data->current_msg->status = -EIO;
365 data->current_msg->complete(data->current_msg->context);
366 data->bcurrent_msg_processing = false;
367 data->current_msg = NULL;
368 data->cur_trans = NULL;
369 }
370 }
371
372 if (data->use_dma)
373 return IRQ_NONE;
374
375 /* Check if the interrupt is for SPI device */
376 if (reg_spsr_val & (SPSR_FI_BIT | SPSR_RFI_BIT)) {
377 pch_spi_handler_sub(data, reg_spsr_val, io_remap_addr);
378 ret = IRQ_HANDLED;
379 }
380
381 dev_dbg(&board_dat->pdev->dev, "%s EXIT return value=%d\n",
382 __func__, ret);
383
384 return ret;
385 }
386
387 /**
388 * pch_spi_set_baud_rate() - Sets SPBR field in SPBRR
389 * @master: Pointer to struct spi_master.
390 * @speed_hz: Baud rate.
391 */
392 static void pch_spi_set_baud_rate(struct spi_master *master, u32 speed_hz)
393 {
394 u32 n_spbr = PCH_CLOCK_HZ / (speed_hz * 2);
395
396 /* if baud rate is less than we can support limit it */
397 if (n_spbr > PCH_MAX_SPBR)
398 n_spbr = PCH_MAX_SPBR;
399
400 pch_spi_setclr_reg(master, PCH_SPBRR, n_spbr, MASK_SPBRR_SPBR_BITS);
401 }
402
403 /**
404 * pch_spi_set_bits_per_word() - Sets SIZE field in SPBRR
405 * @master: Pointer to struct spi_master.
406 * @bits_per_word: Bits per word for SPI transfer.
407 */
408 static void pch_spi_set_bits_per_word(struct spi_master *master,
409 u8 bits_per_word)
410 {
411 if (bits_per_word == 8)
412 pch_spi_setclr_reg(master, PCH_SPBRR, 0, SPBRR_SIZE_BIT);
413 else
414 pch_spi_setclr_reg(master, PCH_SPBRR, SPBRR_SIZE_BIT, 0);
415 }
416
417 /**
418 * pch_spi_setup_transfer() - Configures the PCH SPI hardware for transfer
419 * @spi: Pointer to struct spi_device.
420 */
421 static void pch_spi_setup_transfer(struct spi_device *spi)
422 {
423 u32 flags = 0;
424
425 dev_dbg(&spi->dev, "%s SPBRR content =%x setting baud rate=%d\n",
426 __func__, pch_spi_readreg(spi->master, PCH_SPBRR),
427 spi->max_speed_hz);
428 pch_spi_set_baud_rate(spi->master, spi->max_speed_hz);
429
430 /* set bits per word */
431 pch_spi_set_bits_per_word(spi->master, spi->bits_per_word);
432
433 if (!(spi->mode & SPI_LSB_FIRST))
434 flags |= SPCR_LSBF_BIT;
435 if (spi->mode & SPI_CPOL)
436 flags |= SPCR_CPOL_BIT;
437 if (spi->mode & SPI_CPHA)
438 flags |= SPCR_CPHA_BIT;
439 pch_spi_setclr_reg(spi->master, PCH_SPCR, flags,
440 (SPCR_LSBF_BIT | SPCR_CPOL_BIT | SPCR_CPHA_BIT));
441
442 /* Clear the FIFO by toggling FICLR to 1 and back to 0 */
443 pch_spi_clear_fifo(spi->master);
444 }
445
446 /**
447 * pch_spi_reset() - Clears SPI registers
448 * @master: Pointer to struct spi_master.
449 */
450 static void pch_spi_reset(struct spi_master *master)
451 {
452 /* write 1 to reset SPI */
453 pch_spi_writereg(master, PCH_SRST, 0x1);
454
455 /* clear reset */
456 pch_spi_writereg(master, PCH_SRST, 0x0);
457 }
458
459 static int pch_spi_transfer(struct spi_device *pspi, struct spi_message *pmsg)
460 {
461
462 struct spi_transfer *transfer;
463 struct pch_spi_data *data = spi_master_get_devdata(pspi->master);
464 int retval;
465 unsigned long flags;
466
467 spin_lock_irqsave(&data->lock, flags);
468 /* validate Tx/Rx buffers and Transfer length */
469 list_for_each_entry(transfer, &pmsg->transfers, transfer_list) {
470 if (!transfer->tx_buf && !transfer->rx_buf) {
471 dev_err(&pspi->dev,
472 "%s Tx and Rx buffer NULL\n", __func__);
473 retval = -EINVAL;
474 goto err_return_spinlock;
475 }
476
477 if (!transfer->len) {
478 dev_err(&pspi->dev, "%s Transfer length invalid\n",
479 __func__);
480 retval = -EINVAL;
481 goto err_return_spinlock;
482 }
483
484 dev_dbg(&pspi->dev,
485 "%s Tx/Rx buffer valid. Transfer length valid\n",
486 __func__);
487 }
488 spin_unlock_irqrestore(&data->lock, flags);
489
490 /* We won't process any messages if we have been asked to terminate */
491 if (data->status == STATUS_EXITING) {
492 dev_err(&pspi->dev, "%s status = STATUS_EXITING.\n", __func__);
493 retval = -ESHUTDOWN;
494 goto err_out;
495 }
496
497 /* If suspended ,return -EINVAL */
498 if (data->board_dat->suspend_sts) {
499 dev_err(&pspi->dev, "%s suspend; returning EINVAL\n", __func__);
500 retval = -EINVAL;
501 goto err_out;
502 }
503
504 /* set status of message */
505 pmsg->actual_length = 0;
506 dev_dbg(&pspi->dev, "%s - pmsg->status =%d\n", __func__, pmsg->status);
507
508 pmsg->status = -EINPROGRESS;
509 spin_lock_irqsave(&data->lock, flags);
510 /* add message to queue */
511 list_add_tail(&pmsg->queue, &data->queue);
512 spin_unlock_irqrestore(&data->lock, flags);
513
514 dev_dbg(&pspi->dev, "%s - Invoked list_add_tail\n", __func__);
515
516 schedule_work(&data->work);
517 dev_dbg(&pspi->dev, "%s - Invoked queue work\n", __func__);
518
519 retval = 0;
520
521 err_out:
522 dev_dbg(&pspi->dev, "%s RETURN=%d\n", __func__, retval);
523 return retval;
524 err_return_spinlock:
525 dev_dbg(&pspi->dev, "%s RETURN=%d\n", __func__, retval);
526 spin_unlock_irqrestore(&data->lock, flags);
527 return retval;
528 }
529
530 static inline void pch_spi_select_chip(struct pch_spi_data *data,
531 struct spi_device *pspi)
532 {
533 if (data->current_chip != NULL) {
534 if (pspi->chip_select != data->n_curnt_chip) {
535 dev_dbg(&pspi->dev, "%s : different slave\n", __func__);
536 data->current_chip = NULL;
537 }
538 }
539
540 data->current_chip = pspi;
541
542 data->n_curnt_chip = data->current_chip->chip_select;
543
544 dev_dbg(&pspi->dev, "%s :Invoking pch_spi_setup_transfer\n", __func__);
545 pch_spi_setup_transfer(pspi);
546 }
547
548 static void pch_spi_set_tx(struct pch_spi_data *data, int *bpw)
549 {
550 int size;
551 u32 n_writes;
552 int j;
553 struct spi_message *pmsg, *tmp;
554 const u8 *tx_buf;
555 const u16 *tx_sbuf;
556
557 /* set baud rate if needed */
558 if (data->cur_trans->speed_hz) {
559 dev_dbg(&data->master->dev, "%s:setting baud rate\n", __func__);
560 pch_spi_set_baud_rate(data->master, data->cur_trans->speed_hz);
561 }
562
563 /* set bits per word if needed */
564 if (data->cur_trans->bits_per_word &&
565 (data->current_msg->spi->bits_per_word != data->cur_trans->bits_per_word)) {
566 dev_dbg(&data->master->dev, "%s:set bits per word\n", __func__);
567 pch_spi_set_bits_per_word(data->master,
568 data->cur_trans->bits_per_word);
569 *bpw = data->cur_trans->bits_per_word;
570 } else {
571 *bpw = data->current_msg->spi->bits_per_word;
572 }
573
574 /* reset Tx/Rx index */
575 data->tx_index = 0;
576 data->rx_index = 0;
577
578 data->bpw_len = data->cur_trans->len / (*bpw / 8);
579
580 /* find alloc size */
581 size = data->cur_trans->len * sizeof(*data->pkt_tx_buff);
582
583 /* allocate memory for pkt_tx_buff & pkt_rx_buffer */
584 data->pkt_tx_buff = kzalloc(size, GFP_KERNEL);
585 if (data->pkt_tx_buff != NULL) {
586 data->pkt_rx_buff = kzalloc(size, GFP_KERNEL);
587 if (!data->pkt_rx_buff)
588 kfree(data->pkt_tx_buff);
589 }
590
591 if (!data->pkt_rx_buff) {
592 /* flush queue and set status of all transfers to -ENOMEM */
593 list_for_each_entry_safe(pmsg, tmp, data->queue.next, queue) {
594 pmsg->status = -ENOMEM;
595
596 if (pmsg->complete)
597 pmsg->complete(pmsg->context);
598
599 /* delete from queue */
600 list_del_init(&pmsg->queue);
601 }
602 return;
603 }
604
605 /* copy Tx Data */
606 if (data->cur_trans->tx_buf != NULL) {
607 if (*bpw == 8) {
608 tx_buf = data->cur_trans->tx_buf;
609 for (j = 0; j < data->bpw_len; j++)
610 data->pkt_tx_buff[j] = *tx_buf++;
611 } else {
612 tx_sbuf = data->cur_trans->tx_buf;
613 for (j = 0; j < data->bpw_len; j++)
614 data->pkt_tx_buff[j] = *tx_sbuf++;
615 }
616 }
617
618 /* if len greater than PCH_MAX_FIFO_DEPTH, write 16,else len bytes */
619 n_writes = data->bpw_len;
620 if (n_writes > PCH_MAX_FIFO_DEPTH)
621 n_writes = PCH_MAX_FIFO_DEPTH;
622
623 dev_dbg(&data->master->dev,
624 "\n%s:Pulling down SSN low - writing 0x2 to SSNXCR\n",
625 __func__);
626 pch_spi_writereg(data->master, PCH_SSNXCR, SSN_LOW);
627
628 for (j = 0; j < n_writes; j++)
629 pch_spi_writereg(data->master, PCH_SPDWR, data->pkt_tx_buff[j]);
630
631 /* update tx_index */
632 data->tx_index = j;
633
634 /* reset transfer complete flag */
635 data->transfer_complete = false;
636 data->transfer_active = true;
637 }
638
639 static void pch_spi_nomore_transfer(struct pch_spi_data *data)
640 {
641 struct spi_message *pmsg, *tmp;
642 dev_dbg(&data->master->dev, "%s called\n", __func__);
643 /* Invoke complete callback
644 * [To the spi core..indicating end of transfer] */
645 data->current_msg->status = 0;
646
647 if (data->current_msg->complete) {
648 dev_dbg(&data->master->dev,
649 "%s:Invoking callback of SPI core\n", __func__);
650 data->current_msg->complete(data->current_msg->context);
651 }
652
653 /* update status in global variable */
654 data->bcurrent_msg_processing = false;
655
656 dev_dbg(&data->master->dev,
657 "%s:data->bcurrent_msg_processing = false\n", __func__);
658
659 data->current_msg = NULL;
660 data->cur_trans = NULL;
661
662 /* check if we have items in list and not suspending
663 * return 1 if list empty */
664 if ((list_empty(&data->queue) == 0) &&
665 (!data->board_dat->suspend_sts) &&
666 (data->status != STATUS_EXITING)) {
667 /* We have some more work to do (either there is more tranint
668 * bpw;sfer requests in the current message or there are
669 *more messages)
670 */
671 dev_dbg(&data->master->dev, "%s:Invoke queue_work\n", __func__);
672 schedule_work(&data->work);
673 } else if (data->board_dat->suspend_sts ||
674 data->status == STATUS_EXITING) {
675 dev_dbg(&data->master->dev,
676 "%s suspend/remove initiated, flushing queue\n",
677 __func__);
678 list_for_each_entry_safe(pmsg, tmp, data->queue.next, queue) {
679 pmsg->status = -EIO;
680
681 if (pmsg->complete)
682 pmsg->complete(pmsg->context);
683
684 /* delete from queue */
685 list_del_init(&pmsg->queue);
686 }
687 }
688 }
689
690 static void pch_spi_set_ir(struct pch_spi_data *data)
691 {
692 /* enable interrupts, set threshold, enable SPI */
693 if ((data->bpw_len) > PCH_MAX_FIFO_DEPTH)
694 /* set receive threshold to PCH_RX_THOLD */
695 pch_spi_setclr_reg(data->master, PCH_SPCR,
696 PCH_RX_THOLD << SPCR_RFIC_FIELD |
697 SPCR_FIE_BIT | SPCR_RFIE_BIT |
698 SPCR_ORIE_BIT | SPCR_SPE_BIT,
699 MASK_RFIC_SPCR_BITS | PCH_ALL);
700 else
701 /* set receive threshold to maximum */
702 pch_spi_setclr_reg(data->master, PCH_SPCR,
703 PCH_RX_THOLD_MAX << SPCR_RFIC_FIELD |
704 SPCR_FIE_BIT | SPCR_ORIE_BIT |
705 SPCR_SPE_BIT,
706 MASK_RFIC_SPCR_BITS | PCH_ALL);
707
708 /* Wait until the transfer completes; go to sleep after
709 initiating the transfer. */
710 dev_dbg(&data->master->dev,
711 "%s:waiting for transfer to get over\n", __func__);
712
713 wait_event_interruptible(data->wait, data->transfer_complete);
714
715 /* clear all interrupts */
716 pch_spi_writereg(data->master, PCH_SPSR,
717 pch_spi_readreg(data->master, PCH_SPSR));
718 /* Disable interrupts and SPI transfer */
719 pch_spi_setclr_reg(data->master, PCH_SPCR, 0, PCH_ALL | SPCR_SPE_BIT);
720 /* clear FIFO */
721 pch_spi_clear_fifo(data->master);
722 }
723
724 static void pch_spi_copy_rx_data(struct pch_spi_data *data, int bpw)
725 {
726 int j;
727 u8 *rx_buf;
728 u16 *rx_sbuf;
729
730 /* copy Rx Data */
731 if (!data->cur_trans->rx_buf)
732 return;
733
734 if (bpw == 8) {
735 rx_buf = data->cur_trans->rx_buf;
736 for (j = 0; j < data->bpw_len; j++)
737 *rx_buf++ = data->pkt_rx_buff[j] & 0xFF;
738 } else {
739 rx_sbuf = data->cur_trans->rx_buf;
740 for (j = 0; j < data->bpw_len; j++)
741 *rx_sbuf++ = data->pkt_rx_buff[j];
742 }
743 }
744
745 static void pch_spi_copy_rx_data_for_dma(struct pch_spi_data *data, int bpw)
746 {
747 int j;
748 u8 *rx_buf;
749 u16 *rx_sbuf;
750 const u8 *rx_dma_buf;
751 const u16 *rx_dma_sbuf;
752
753 /* copy Rx Data */
754 if (!data->cur_trans->rx_buf)
755 return;
756
757 if (bpw == 8) {
758 rx_buf = data->cur_trans->rx_buf;
759 rx_dma_buf = data->dma.rx_buf_virt;
760 for (j = 0; j < data->bpw_len; j++)
761 *rx_buf++ = *rx_dma_buf++ & 0xFF;
762 data->cur_trans->rx_buf = rx_buf;
763 } else {
764 rx_sbuf = data->cur_trans->rx_buf;
765 rx_dma_sbuf = data->dma.rx_buf_virt;
766 for (j = 0; j < data->bpw_len; j++)
767 *rx_sbuf++ = *rx_dma_sbuf++;
768 data->cur_trans->rx_buf = rx_sbuf;
769 }
770 }
771
772 static int pch_spi_start_transfer(struct pch_spi_data *data)
773 {
774 struct pch_spi_dma_ctrl *dma;
775 unsigned long flags;
776 int rtn;
777
778 dma = &data->dma;
779
780 spin_lock_irqsave(&data->lock, flags);
781
782 /* disable interrupts, SPI set enable */
783 pch_spi_setclr_reg(data->master, PCH_SPCR, SPCR_SPE_BIT, PCH_ALL);
784
785 spin_unlock_irqrestore(&data->lock, flags);
786
787 /* Wait until the transfer completes; go to sleep after
788 initiating the transfer. */
789 dev_dbg(&data->master->dev,
790 "%s:waiting for transfer to get over\n", __func__);
791 rtn = wait_event_interruptible_timeout(data->wait,
792 data->transfer_complete,
793 msecs_to_jiffies(2 * HZ));
794 if (!rtn)
795 dev_err(&data->master->dev,
796 "%s wait-event timeout\n", __func__);
797
798 dma_sync_sg_for_cpu(&data->master->dev, dma->sg_rx_p, dma->nent,
799 DMA_FROM_DEVICE);
800
801 dma_sync_sg_for_cpu(&data->master->dev, dma->sg_tx_p, dma->nent,
802 DMA_FROM_DEVICE);
803 memset(data->dma.tx_buf_virt, 0, PAGE_SIZE);
804
805 async_tx_ack(dma->desc_rx);
806 async_tx_ack(dma->desc_tx);
807 kfree(dma->sg_tx_p);
808 kfree(dma->sg_rx_p);
809
810 spin_lock_irqsave(&data->lock, flags);
811
812 /* clear fifo threshold, disable interrupts, disable SPI transfer */
813 pch_spi_setclr_reg(data->master, PCH_SPCR, 0,
814 MASK_RFIC_SPCR_BITS | MASK_TFIC_SPCR_BITS | PCH_ALL |
815 SPCR_SPE_BIT);
816 /* clear all interrupts */
817 pch_spi_writereg(data->master, PCH_SPSR,
818 pch_spi_readreg(data->master, PCH_SPSR));
819 /* clear FIFO */
820 pch_spi_clear_fifo(data->master);
821
822 spin_unlock_irqrestore(&data->lock, flags);
823
824 return rtn;
825 }
826
827 static void pch_dma_rx_complete(void *arg)
828 {
829 struct pch_spi_data *data = arg;
830
831 /* transfer is completed;inform pch_spi_process_messages_dma */
832 data->transfer_complete = true;
833 wake_up_interruptible(&data->wait);
834 }
835
836 static bool pch_spi_filter(struct dma_chan *chan, void *slave)
837 {
838 struct pch_dma_slave *param = slave;
839
840 if ((chan->chan_id == param->chan_id) &&
841 (param->dma_dev == chan->device->dev)) {
842 chan->private = param;
843 return true;
844 } else {
845 return false;
846 }
847 }
848
849 static void pch_spi_request_dma(struct pch_spi_data *data, int bpw)
850 {
851 dma_cap_mask_t mask;
852 struct dma_chan *chan;
853 struct pci_dev *dma_dev;
854 struct pch_dma_slave *param;
855 struct pch_spi_dma_ctrl *dma;
856 unsigned int width;
857
858 if (bpw == 8)
859 width = PCH_DMA_WIDTH_1_BYTE;
860 else
861 width = PCH_DMA_WIDTH_2_BYTES;
862
863 dma = &data->dma;
864 dma_cap_zero(mask);
865 dma_cap_set(DMA_SLAVE, mask);
866
867 /* Get DMA's dev information */
868 dma_dev = pci_get_slot(data->board_dat->pdev->bus,
869 PCI_DEVFN(PCI_SLOT(data->board_dat->pdev->devfn), 0));
870
871 /* Set Tx DMA */
872 param = &dma->param_tx;
873 param->dma_dev = &dma_dev->dev;
874 param->chan_id = data->ch * 2; /* Tx = 0, 2 */;
875 param->tx_reg = data->io_base_addr + PCH_SPDWR;
876 param->width = width;
877 chan = dma_request_channel(mask, pch_spi_filter, param);
878 if (!chan) {
879 dev_err(&data->master->dev,
880 "ERROR: dma_request_channel FAILS(Tx)\n");
881 data->use_dma = 0;
882 return;
883 }
884 dma->chan_tx = chan;
885
886 /* Set Rx DMA */
887 param = &dma->param_rx;
888 param->dma_dev = &dma_dev->dev;
889 param->chan_id = data->ch * 2 + 1; /* Rx = Tx + 1 */;
890 param->rx_reg = data->io_base_addr + PCH_SPDRR;
891 param->width = width;
892 chan = dma_request_channel(mask, pch_spi_filter, param);
893 if (!chan) {
894 dev_err(&data->master->dev,
895 "ERROR: dma_request_channel FAILS(Rx)\n");
896 dma_release_channel(dma->chan_tx);
897 dma->chan_tx = NULL;
898 data->use_dma = 0;
899 return;
900 }
901 dma->chan_rx = chan;
902 }
903
904 static void pch_spi_release_dma(struct pch_spi_data *data)
905 {
906 struct pch_spi_dma_ctrl *dma;
907
908 dma = &data->dma;
909 if (dma->chan_tx) {
910 dma_release_channel(dma->chan_tx);
911 dma->chan_tx = NULL;
912 }
913 if (dma->chan_rx) {
914 dma_release_channel(dma->chan_rx);
915 dma->chan_rx = NULL;
916 }
917 }
918
919 static void pch_spi_handle_dma(struct pch_spi_data *data, int *bpw)
920 {
921 const u8 *tx_buf;
922 const u16 *tx_sbuf;
923 u8 *tx_dma_buf;
924 u16 *tx_dma_sbuf;
925 struct scatterlist *sg;
926 struct dma_async_tx_descriptor *desc_tx;
927 struct dma_async_tx_descriptor *desc_rx;
928 int num;
929 int i;
930 int size;
931 int rem;
932 int head;
933 unsigned long flags;
934 struct pch_spi_dma_ctrl *dma;
935
936 dma = &data->dma;
937
938 /* set baud rate if needed */
939 if (data->cur_trans->speed_hz) {
940 dev_dbg(&data->master->dev, "%s:setting baud rate\n", __func__);
941 spin_lock_irqsave(&data->lock, flags);
942 pch_spi_set_baud_rate(data->master, data->cur_trans->speed_hz);
943 spin_unlock_irqrestore(&data->lock, flags);
944 }
945
946 /* set bits per word if needed */
947 if (data->cur_trans->bits_per_word &&
948 (data->current_msg->spi->bits_per_word !=
949 data->cur_trans->bits_per_word)) {
950 dev_dbg(&data->master->dev, "%s:set bits per word\n", __func__);
951 spin_lock_irqsave(&data->lock, flags);
952 pch_spi_set_bits_per_word(data->master,
953 data->cur_trans->bits_per_word);
954 spin_unlock_irqrestore(&data->lock, flags);
955 *bpw = data->cur_trans->bits_per_word;
956 } else {
957 *bpw = data->current_msg->spi->bits_per_word;
958 }
959 data->bpw_len = data->cur_trans->len / (*bpw / 8);
960
961 if (data->bpw_len > PCH_BUF_SIZE) {
962 data->bpw_len = PCH_BUF_SIZE;
963 data->cur_trans->len -= PCH_BUF_SIZE;
964 }
965
966 /* copy Tx Data */
967 if (data->cur_trans->tx_buf != NULL) {
968 if (*bpw == 8) {
969 tx_buf = data->cur_trans->tx_buf;
970 tx_dma_buf = dma->tx_buf_virt;
971 for (i = 0; i < data->bpw_len; i++)
972 *tx_dma_buf++ = *tx_buf++;
973 } else {
974 tx_sbuf = data->cur_trans->tx_buf;
975 tx_dma_sbuf = dma->tx_buf_virt;
976 for (i = 0; i < data->bpw_len; i++)
977 *tx_dma_sbuf++ = *tx_sbuf++;
978 }
979 }
980
981 /* Calculate Rx parameter for DMA transmitting */
982 if (data->bpw_len > PCH_DMA_TRANS_SIZE) {
983 if (data->bpw_len % PCH_DMA_TRANS_SIZE) {
984 num = data->bpw_len / PCH_DMA_TRANS_SIZE + 1;
985 rem = data->bpw_len % PCH_DMA_TRANS_SIZE;
986 } else {
987 num = data->bpw_len / PCH_DMA_TRANS_SIZE;
988 rem = PCH_DMA_TRANS_SIZE;
989 }
990 size = PCH_DMA_TRANS_SIZE;
991 } else {
992 num = 1;
993 size = data->bpw_len;
994 rem = data->bpw_len;
995 }
996 dev_dbg(&data->master->dev, "%s num=%d size=%d rem=%d\n",
997 __func__, num, size, rem);
998 spin_lock_irqsave(&data->lock, flags);
999
1000 /* set receive fifo threshold and transmit fifo threshold */
1001 pch_spi_setclr_reg(data->master, PCH_SPCR,
1002 ((size - 1) << SPCR_RFIC_FIELD) |
1003 (PCH_TX_THOLD << SPCR_TFIC_FIELD),
1004 MASK_RFIC_SPCR_BITS | MASK_TFIC_SPCR_BITS);
1005
1006 spin_unlock_irqrestore(&data->lock, flags);
1007
1008 /* RX */
1009 dma->sg_rx_p = kcalloc(num, sizeof(*dma->sg_rx_p), GFP_ATOMIC);
1010 if (!dma->sg_rx_p)
1011 return;
1012
1013 sg_init_table(dma->sg_rx_p, num); /* Initialize SG table */
1014 /* offset, length setting */
1015 sg = dma->sg_rx_p;
1016 for (i = 0; i < num; i++, sg++) {
1017 if (i == (num - 2)) {
1018 sg->offset = size * i;
1019 sg->offset = sg->offset * (*bpw / 8);
1020 sg_set_page(sg, virt_to_page(dma->rx_buf_virt), rem,
1021 sg->offset);
1022 sg_dma_len(sg) = rem;
1023 } else if (i == (num - 1)) {
1024 sg->offset = size * (i - 1) + rem;
1025 sg->offset = sg->offset * (*bpw / 8);
1026 sg_set_page(sg, virt_to_page(dma->rx_buf_virt), size,
1027 sg->offset);
1028 sg_dma_len(sg) = size;
1029 } else {
1030 sg->offset = size * i;
1031 sg->offset = sg->offset * (*bpw / 8);
1032 sg_set_page(sg, virt_to_page(dma->rx_buf_virt), size,
1033 sg->offset);
1034 sg_dma_len(sg) = size;
1035 }
1036 sg_dma_address(sg) = dma->rx_buf_dma + sg->offset;
1037 }
1038 sg = dma->sg_rx_p;
1039 desc_rx = dmaengine_prep_slave_sg(dma->chan_rx, sg,
1040 num, DMA_DEV_TO_MEM,
1041 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1042 if (!desc_rx) {
1043 dev_err(&data->master->dev,
1044 "%s:dmaengine_prep_slave_sg Failed\n", __func__);
1045 return;
1046 }
1047 dma_sync_sg_for_device(&data->master->dev, sg, num, DMA_FROM_DEVICE);
1048 desc_rx->callback = pch_dma_rx_complete;
1049 desc_rx->callback_param = data;
1050 dma->nent = num;
1051 dma->desc_rx = desc_rx;
1052
1053 /* Calculate Tx parameter for DMA transmitting */
1054 if (data->bpw_len > PCH_MAX_FIFO_DEPTH) {
1055 head = PCH_MAX_FIFO_DEPTH - PCH_DMA_TRANS_SIZE;
1056 if (data->bpw_len % PCH_DMA_TRANS_SIZE > 4) {
1057 num = data->bpw_len / PCH_DMA_TRANS_SIZE + 1;
1058 rem = data->bpw_len % PCH_DMA_TRANS_SIZE - head;
1059 } else {
1060 num = data->bpw_len / PCH_DMA_TRANS_SIZE;
1061 rem = data->bpw_len % PCH_DMA_TRANS_SIZE +
1062 PCH_DMA_TRANS_SIZE - head;
1063 }
1064 size = PCH_DMA_TRANS_SIZE;
1065 } else {
1066 num = 1;
1067 size = data->bpw_len;
1068 rem = data->bpw_len;
1069 head = 0;
1070 }
1071
1072 dma->sg_tx_p = kcalloc(num, sizeof(*dma->sg_tx_p), GFP_ATOMIC);
1073 if (!dma->sg_tx_p)
1074 return;
1075
1076 sg_init_table(dma->sg_tx_p, num); /* Initialize SG table */
1077 /* offset, length setting */
1078 sg = dma->sg_tx_p;
1079 for (i = 0; i < num; i++, sg++) {
1080 if (i == 0) {
1081 sg->offset = 0;
1082 sg_set_page(sg, virt_to_page(dma->tx_buf_virt), size + head,
1083 sg->offset);
1084 sg_dma_len(sg) = size + head;
1085 } else if (i == (num - 1)) {
1086 sg->offset = head + size * i;
1087 sg->offset = sg->offset * (*bpw / 8);
1088 sg_set_page(sg, virt_to_page(dma->tx_buf_virt), rem,
1089 sg->offset);
1090 sg_dma_len(sg) = rem;
1091 } else {
1092 sg->offset = head + size * i;
1093 sg->offset = sg->offset * (*bpw / 8);
1094 sg_set_page(sg, virt_to_page(dma->tx_buf_virt), size,
1095 sg->offset);
1096 sg_dma_len(sg) = size;
1097 }
1098 sg_dma_address(sg) = dma->tx_buf_dma + sg->offset;
1099 }
1100 sg = dma->sg_tx_p;
1101 desc_tx = dmaengine_prep_slave_sg(dma->chan_tx,
1102 sg, num, DMA_MEM_TO_DEV,
1103 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1104 if (!desc_tx) {
1105 dev_err(&data->master->dev,
1106 "%s:dmaengine_prep_slave_sg Failed\n", __func__);
1107 return;
1108 }
1109 dma_sync_sg_for_device(&data->master->dev, sg, num, DMA_TO_DEVICE);
1110 desc_tx->callback = NULL;
1111 desc_tx->callback_param = data;
1112 dma->nent = num;
1113 dma->desc_tx = desc_tx;
1114
1115 dev_dbg(&data->master->dev, "%s:Pulling down SSN low - writing 0x2 to SSNXCR\n", __func__);
1116
1117 spin_lock_irqsave(&data->lock, flags);
1118 pch_spi_writereg(data->master, PCH_SSNXCR, SSN_LOW);
1119 desc_rx->tx_submit(desc_rx);
1120 desc_tx->tx_submit(desc_tx);
1121 spin_unlock_irqrestore(&data->lock, flags);
1122
1123 /* reset transfer complete flag */
1124 data->transfer_complete = false;
1125 }
1126
1127 static void pch_spi_process_messages(struct work_struct *pwork)
1128 {
1129 struct spi_message *pmsg, *tmp;
1130 struct pch_spi_data *data;
1131 int bpw;
1132
1133 data = container_of(pwork, struct pch_spi_data, work);
1134 dev_dbg(&data->master->dev, "%s data initialized\n", __func__);
1135
1136 spin_lock(&data->lock);
1137 /* check if suspend has been initiated;if yes flush queue */
1138 if (data->board_dat->suspend_sts || (data->status == STATUS_EXITING)) {
1139 dev_dbg(&data->master->dev,
1140 "%s suspend/remove initiated, flushing queue\n", __func__);
1141 list_for_each_entry_safe(pmsg, tmp, data->queue.next, queue) {
1142 pmsg->status = -EIO;
1143
1144 if (pmsg->complete) {
1145 spin_unlock(&data->lock);
1146 pmsg->complete(pmsg->context);
1147 spin_lock(&data->lock);
1148 }
1149
1150 /* delete from queue */
1151 list_del_init(&pmsg->queue);
1152 }
1153
1154 spin_unlock(&data->lock);
1155 return;
1156 }
1157
1158 data->bcurrent_msg_processing = true;
1159 dev_dbg(&data->master->dev,
1160 "%s Set data->bcurrent_msg_processing= true\n", __func__);
1161
1162 /* Get the message from the queue and delete it from there. */
1163 data->current_msg = list_entry(data->queue.next, struct spi_message,
1164 queue);
1165
1166 list_del_init(&data->current_msg->queue);
1167
1168 data->current_msg->status = 0;
1169
1170 pch_spi_select_chip(data, data->current_msg->spi);
1171
1172 spin_unlock(&data->lock);
1173
1174 if (data->use_dma)
1175 pch_spi_request_dma(data,
1176 data->current_msg->spi->bits_per_word);
1177 pch_spi_writereg(data->master, PCH_SSNXCR, SSN_NO_CONTROL);
1178 do {
1179 int cnt;
1180 /* If we are already processing a message get the next
1181 transfer structure from the message otherwise retrieve
1182 the 1st transfer request from the message. */
1183 spin_lock(&data->lock);
1184 if (data->cur_trans == NULL) {
1185 data->cur_trans =
1186 list_entry(data->current_msg->transfers.next,
1187 struct spi_transfer, transfer_list);
1188 dev_dbg(&data->master->dev,
1189 "%s :Getting 1st transfer message\n",
1190 __func__);
1191 } else {
1192 data->cur_trans =
1193 list_entry(data->cur_trans->transfer_list.next,
1194 struct spi_transfer, transfer_list);
1195 dev_dbg(&data->master->dev,
1196 "%s :Getting next transfer message\n",
1197 __func__);
1198 }
1199 spin_unlock(&data->lock);
1200
1201 if (!data->cur_trans->len)
1202 goto out;
1203 cnt = (data->cur_trans->len - 1) / PCH_BUF_SIZE + 1;
1204 data->save_total_len = data->cur_trans->len;
1205 if (data->use_dma) {
1206 int i;
1207 char *save_rx_buf = data->cur_trans->rx_buf;
1208 for (i = 0; i < cnt; i ++) {
1209 pch_spi_handle_dma(data, &bpw);
1210 if (!pch_spi_start_transfer(data)) {
1211 data->transfer_complete = true;
1212 data->current_msg->status = -EIO;
1213 data->current_msg->complete
1214 (data->current_msg->context);
1215 data->bcurrent_msg_processing = false;
1216 data->current_msg = NULL;
1217 data->cur_trans = NULL;
1218 goto out;
1219 }
1220 pch_spi_copy_rx_data_for_dma(data, bpw);
1221 }
1222 data->cur_trans->rx_buf = save_rx_buf;
1223 } else {
1224 pch_spi_set_tx(data, &bpw);
1225 pch_spi_set_ir(data);
1226 pch_spi_copy_rx_data(data, bpw);
1227 kfree(data->pkt_rx_buff);
1228 data->pkt_rx_buff = NULL;
1229 kfree(data->pkt_tx_buff);
1230 data->pkt_tx_buff = NULL;
1231 }
1232 /* increment message count */
1233 data->cur_trans->len = data->save_total_len;
1234 data->current_msg->actual_length += data->cur_trans->len;
1235
1236 dev_dbg(&data->master->dev,
1237 "%s:data->current_msg->actual_length=%d\n",
1238 __func__, data->current_msg->actual_length);
1239
1240 /* check for delay */
1241 if (data->cur_trans->delay_usecs) {
1242 dev_dbg(&data->master->dev, "%s:delay in usec=%d\n",
1243 __func__, data->cur_trans->delay_usecs);
1244 udelay(data->cur_trans->delay_usecs);
1245 }
1246
1247 spin_lock(&data->lock);
1248
1249 /* No more transfer in this message. */
1250 if ((data->cur_trans->transfer_list.next) ==
1251 &(data->current_msg->transfers)) {
1252 pch_spi_nomore_transfer(data);
1253 }
1254
1255 spin_unlock(&data->lock);
1256
1257 } while (data->cur_trans != NULL);
1258
1259 out:
1260 pch_spi_writereg(data->master, PCH_SSNXCR, SSN_HIGH);
1261 if (data->use_dma)
1262 pch_spi_release_dma(data);
1263 }
1264
1265 static void pch_spi_free_resources(struct pch_spi_board_data *board_dat,
1266 struct pch_spi_data *data)
1267 {
1268 dev_dbg(&board_dat->pdev->dev, "%s ENTRY\n", __func__);
1269
1270 flush_work(&data->work);
1271 }
1272
1273 static int pch_spi_get_resources(struct pch_spi_board_data *board_dat,
1274 struct pch_spi_data *data)
1275 {
1276 dev_dbg(&board_dat->pdev->dev, "%s ENTRY\n", __func__);
1277
1278 /* reset PCH SPI h/w */
1279 pch_spi_reset(data->master);
1280 dev_dbg(&board_dat->pdev->dev,
1281 "%s pch_spi_reset invoked successfully\n", __func__);
1282
1283 dev_dbg(&board_dat->pdev->dev, "%s data->irq_reg_sts=true\n", __func__);
1284
1285 return 0;
1286 }
1287
1288 static void pch_free_dma_buf(struct pch_spi_board_data *board_dat,
1289 struct pch_spi_data *data)
1290 {
1291 struct pch_spi_dma_ctrl *dma;
1292
1293 dma = &data->dma;
1294 if (dma->tx_buf_dma)
1295 dma_free_coherent(&board_dat->pdev->dev, PCH_BUF_SIZE,
1296 dma->tx_buf_virt, dma->tx_buf_dma);
1297 if (dma->rx_buf_dma)
1298 dma_free_coherent(&board_dat->pdev->dev, PCH_BUF_SIZE,
1299 dma->rx_buf_virt, dma->rx_buf_dma);
1300 }
1301
1302 static int pch_alloc_dma_buf(struct pch_spi_board_data *board_dat,
1303 struct pch_spi_data *data)
1304 {
1305 struct pch_spi_dma_ctrl *dma;
1306 int ret;
1307
1308 dma = &data->dma;
1309 ret = 0;
1310 /* Get Consistent memory for Tx DMA */
1311 dma->tx_buf_virt = dma_alloc_coherent(&board_dat->pdev->dev,
1312 PCH_BUF_SIZE, &dma->tx_buf_dma, GFP_KERNEL);
1313 if (!dma->tx_buf_virt)
1314 ret = -ENOMEM;
1315
1316 /* Get Consistent memory for Rx DMA */
1317 dma->rx_buf_virt = dma_alloc_coherent(&board_dat->pdev->dev,
1318 PCH_BUF_SIZE, &dma->rx_buf_dma, GFP_KERNEL);
1319 if (!dma->rx_buf_virt)
1320 ret = -ENOMEM;
1321
1322 return ret;
1323 }
1324
1325 static int pch_spi_pd_probe(struct platform_device *plat_dev)
1326 {
1327 int ret;
1328 struct spi_master *master;
1329 struct pch_spi_board_data *board_dat = dev_get_platdata(&plat_dev->dev);
1330 struct pch_spi_data *data;
1331
1332 dev_dbg(&plat_dev->dev, "%s:debug\n", __func__);
1333
1334 master = spi_alloc_master(&board_dat->pdev->dev,
1335 sizeof(struct pch_spi_data));
1336 if (!master) {
1337 dev_err(&plat_dev->dev, "spi_alloc_master[%d] failed.\n",
1338 plat_dev->id);
1339 return -ENOMEM;
1340 }
1341
1342 data = spi_master_get_devdata(master);
1343 data->master = master;
1344
1345 platform_set_drvdata(plat_dev, data);
1346
1347 /* baseaddress + address offset) */
1348 data->io_base_addr = pci_resource_start(board_dat->pdev, 1) +
1349 PCH_ADDRESS_SIZE * plat_dev->id;
1350 data->io_remap_addr = pci_iomap(board_dat->pdev, 1, 0);
1351 if (!data->io_remap_addr) {
1352 dev_err(&plat_dev->dev, "%s pci_iomap failed\n", __func__);
1353 ret = -ENOMEM;
1354 goto err_pci_iomap;
1355 }
1356 data->io_remap_addr += PCH_ADDRESS_SIZE * plat_dev->id;
1357
1358 dev_dbg(&plat_dev->dev, "[ch%d] remap_addr=%p\n",
1359 plat_dev->id, data->io_remap_addr);
1360
1361 /* initialize members of SPI master */
1362 master->num_chipselect = PCH_MAX_CS;
1363 master->transfer = pch_spi_transfer;
1364 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST;
1365 master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16);
1366 master->max_speed_hz = PCH_MAX_BAUDRATE;
1367
1368 data->board_dat = board_dat;
1369 data->plat_dev = plat_dev;
1370 data->n_curnt_chip = 255;
1371 data->status = STATUS_RUNNING;
1372 data->ch = plat_dev->id;
1373 data->use_dma = use_dma;
1374
1375 INIT_LIST_HEAD(&data->queue);
1376 spin_lock_init(&data->lock);
1377 INIT_WORK(&data->work, pch_spi_process_messages);
1378 init_waitqueue_head(&data->wait);
1379
1380 ret = pch_spi_get_resources(board_dat, data);
1381 if (ret) {
1382 dev_err(&plat_dev->dev, "%s fail(retval=%d)\n", __func__, ret);
1383 goto err_spi_get_resources;
1384 }
1385
1386 ret = request_irq(board_dat->pdev->irq, pch_spi_handler,
1387 IRQF_SHARED, KBUILD_MODNAME, data);
1388 if (ret) {
1389 dev_err(&plat_dev->dev,
1390 "%s request_irq failed\n", __func__);
1391 goto err_request_irq;
1392 }
1393 data->irq_reg_sts = true;
1394
1395 pch_spi_set_master_mode(master);
1396
1397 if (use_dma) {
1398 dev_info(&plat_dev->dev, "Use DMA for data transfers\n");
1399 ret = pch_alloc_dma_buf(board_dat, data);
1400 if (ret)
1401 goto err_spi_register_master;
1402 }
1403
1404 ret = spi_register_master(master);
1405 if (ret != 0) {
1406 dev_err(&plat_dev->dev,
1407 "%s spi_register_master FAILED\n", __func__);
1408 goto err_spi_register_master;
1409 }
1410
1411 return 0;
1412
1413 err_spi_register_master:
1414 pch_free_dma_buf(board_dat, data);
1415 free_irq(board_dat->pdev->irq, data);
1416 err_request_irq:
1417 pch_spi_free_resources(board_dat, data);
1418 err_spi_get_resources:
1419 pci_iounmap(board_dat->pdev, data->io_remap_addr);
1420 err_pci_iomap:
1421 spi_master_put(master);
1422
1423 return ret;
1424 }
1425
1426 static int pch_spi_pd_remove(struct platform_device *plat_dev)
1427 {
1428 struct pch_spi_board_data *board_dat = dev_get_platdata(&plat_dev->dev);
1429 struct pch_spi_data *data = platform_get_drvdata(plat_dev);
1430 int count;
1431 unsigned long flags;
1432
1433 dev_dbg(&plat_dev->dev, "%s:[ch%d] irq=%d\n",
1434 __func__, plat_dev->id, board_dat->pdev->irq);
1435
1436 if (use_dma)
1437 pch_free_dma_buf(board_dat, data);
1438
1439 /* check for any pending messages; no action is taken if the queue
1440 * is still full; but at least we tried. Unload anyway */
1441 count = 500;
1442 spin_lock_irqsave(&data->lock, flags);
1443 data->status = STATUS_EXITING;
1444 while ((list_empty(&data->queue) == 0) && --count) {
1445 dev_dbg(&board_dat->pdev->dev, "%s :queue not empty\n",
1446 __func__);
1447 spin_unlock_irqrestore(&data->lock, flags);
1448 msleep(PCH_SLEEP_TIME);
1449 spin_lock_irqsave(&data->lock, flags);
1450 }
1451 spin_unlock_irqrestore(&data->lock, flags);
1452
1453 pch_spi_free_resources(board_dat, data);
1454 /* disable interrupts & free IRQ */
1455 if (data->irq_reg_sts) {
1456 /* disable interrupts */
1457 pch_spi_setclr_reg(data->master, PCH_SPCR, 0, PCH_ALL);
1458 data->irq_reg_sts = false;
1459 free_irq(board_dat->pdev->irq, data);
1460 }
1461
1462 pci_iounmap(board_dat->pdev, data->io_remap_addr);
1463 spi_unregister_master(data->master);
1464
1465 return 0;
1466 }
1467 #ifdef CONFIG_PM
1468 static int pch_spi_pd_suspend(struct platform_device *pd_dev,
1469 pm_message_t state)
1470 {
1471 u8 count;
1472 struct pch_spi_board_data *board_dat = dev_get_platdata(&pd_dev->dev);
1473 struct pch_spi_data *data = platform_get_drvdata(pd_dev);
1474
1475 dev_dbg(&pd_dev->dev, "%s ENTRY\n", __func__);
1476
1477 if (!board_dat) {
1478 dev_err(&pd_dev->dev,
1479 "%s pci_get_drvdata returned NULL\n", __func__);
1480 return -EFAULT;
1481 }
1482
1483 /* check if the current message is processed:
1484 Only after thats done the transfer will be suspended */
1485 count = 255;
1486 while ((--count) > 0) {
1487 if (!(data->bcurrent_msg_processing))
1488 break;
1489 msleep(PCH_SLEEP_TIME);
1490 }
1491
1492 /* Free IRQ */
1493 if (data->irq_reg_sts) {
1494 /* disable all interrupts */
1495 pch_spi_setclr_reg(data->master, PCH_SPCR, 0, PCH_ALL);
1496 pch_spi_reset(data->master);
1497 free_irq(board_dat->pdev->irq, data);
1498
1499 data->irq_reg_sts = false;
1500 dev_dbg(&pd_dev->dev,
1501 "%s free_irq invoked successfully.\n", __func__);
1502 }
1503
1504 return 0;
1505 }
1506
1507 static int pch_spi_pd_resume(struct platform_device *pd_dev)
1508 {
1509 struct pch_spi_board_data *board_dat = dev_get_platdata(&pd_dev->dev);
1510 struct pch_spi_data *data = platform_get_drvdata(pd_dev);
1511 int retval;
1512
1513 if (!board_dat) {
1514 dev_err(&pd_dev->dev,
1515 "%s pci_get_drvdata returned NULL\n", __func__);
1516 return -EFAULT;
1517 }
1518
1519 if (!data->irq_reg_sts) {
1520 /* register IRQ */
1521 retval = request_irq(board_dat->pdev->irq, pch_spi_handler,
1522 IRQF_SHARED, KBUILD_MODNAME, data);
1523 if (retval < 0) {
1524 dev_err(&pd_dev->dev,
1525 "%s request_irq failed\n", __func__);
1526 return retval;
1527 }
1528
1529 /* reset PCH SPI h/w */
1530 pch_spi_reset(data->master);
1531 pch_spi_set_master_mode(data->master);
1532 data->irq_reg_sts = true;
1533 }
1534 return 0;
1535 }
1536 #else
1537 #define pch_spi_pd_suspend NULL
1538 #define pch_spi_pd_resume NULL
1539 #endif
1540
1541 static struct platform_driver pch_spi_pd_driver = {
1542 .driver = {
1543 .name = "pch-spi",
1544 },
1545 .probe = pch_spi_pd_probe,
1546 .remove = pch_spi_pd_remove,
1547 .suspend = pch_spi_pd_suspend,
1548 .resume = pch_spi_pd_resume
1549 };
1550
1551 static int pch_spi_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1552 {
1553 struct pch_spi_board_data *board_dat;
1554 struct platform_device *pd_dev = NULL;
1555 int retval;
1556 int i;
1557 struct pch_pd_dev_save *pd_dev_save;
1558
1559 pd_dev_save = kzalloc(sizeof(*pd_dev_save), GFP_KERNEL);
1560 if (!pd_dev_save)
1561 return -ENOMEM;
1562
1563 board_dat = kzalloc(sizeof(*board_dat), GFP_KERNEL);
1564 if (!board_dat) {
1565 retval = -ENOMEM;
1566 goto err_no_mem;
1567 }
1568
1569 retval = pci_request_regions(pdev, KBUILD_MODNAME);
1570 if (retval) {
1571 dev_err(&pdev->dev, "%s request_region failed\n", __func__);
1572 goto pci_request_regions;
1573 }
1574
1575 board_dat->pdev = pdev;
1576 board_dat->num = id->driver_data;
1577 pd_dev_save->num = id->driver_data;
1578 pd_dev_save->board_dat = board_dat;
1579
1580 retval = pci_enable_device(pdev);
1581 if (retval) {
1582 dev_err(&pdev->dev, "%s pci_enable_device failed\n", __func__);
1583 goto pci_enable_device;
1584 }
1585
1586 for (i = 0; i < board_dat->num; i++) {
1587 pd_dev = platform_device_alloc("pch-spi", i);
1588 if (!pd_dev) {
1589 dev_err(&pdev->dev, "platform_device_alloc failed\n");
1590 retval = -ENOMEM;
1591 goto err_platform_device;
1592 }
1593 pd_dev_save->pd_save[i] = pd_dev;
1594 pd_dev->dev.parent = &pdev->dev;
1595
1596 retval = platform_device_add_data(pd_dev, board_dat,
1597 sizeof(*board_dat));
1598 if (retval) {
1599 dev_err(&pdev->dev,
1600 "platform_device_add_data failed\n");
1601 platform_device_put(pd_dev);
1602 goto err_platform_device;
1603 }
1604
1605 retval = platform_device_add(pd_dev);
1606 if (retval) {
1607 dev_err(&pdev->dev, "platform_device_add failed\n");
1608 platform_device_put(pd_dev);
1609 goto err_platform_device;
1610 }
1611 }
1612
1613 pci_set_drvdata(pdev, pd_dev_save);
1614
1615 return 0;
1616
1617 err_platform_device:
1618 while (--i >= 0)
1619 platform_device_unregister(pd_dev_save->pd_save[i]);
1620 pci_disable_device(pdev);
1621 pci_enable_device:
1622 pci_release_regions(pdev);
1623 pci_request_regions:
1624 kfree(board_dat);
1625 err_no_mem:
1626 kfree(pd_dev_save);
1627
1628 return retval;
1629 }
1630
1631 static void pch_spi_remove(struct pci_dev *pdev)
1632 {
1633 int i;
1634 struct pch_pd_dev_save *pd_dev_save = pci_get_drvdata(pdev);
1635
1636 dev_dbg(&pdev->dev, "%s ENTRY:pdev=%p\n", __func__, pdev);
1637
1638 for (i = 0; i < pd_dev_save->num; i++)
1639 platform_device_unregister(pd_dev_save->pd_save[i]);
1640
1641 pci_disable_device(pdev);
1642 pci_release_regions(pdev);
1643 kfree(pd_dev_save->board_dat);
1644 kfree(pd_dev_save);
1645 }
1646
1647 #ifdef CONFIG_PM
1648 static int pch_spi_suspend(struct pci_dev *pdev, pm_message_t state)
1649 {
1650 int retval;
1651 struct pch_pd_dev_save *pd_dev_save = pci_get_drvdata(pdev);
1652
1653 dev_dbg(&pdev->dev, "%s ENTRY\n", __func__);
1654
1655 pd_dev_save->board_dat->suspend_sts = true;
1656
1657 /* save config space */
1658 retval = pci_save_state(pdev);
1659 if (retval == 0) {
1660 pci_enable_wake(pdev, PCI_D3hot, 0);
1661 pci_disable_device(pdev);
1662 pci_set_power_state(pdev, PCI_D3hot);
1663 } else {
1664 dev_err(&pdev->dev, "%s pci_save_state failed\n", __func__);
1665 }
1666
1667 return retval;
1668 }
1669
1670 static int pch_spi_resume(struct pci_dev *pdev)
1671 {
1672 int retval;
1673 struct pch_pd_dev_save *pd_dev_save = pci_get_drvdata(pdev);
1674 dev_dbg(&pdev->dev, "%s ENTRY\n", __func__);
1675
1676 pci_set_power_state(pdev, PCI_D0);
1677 pci_restore_state(pdev);
1678
1679 retval = pci_enable_device(pdev);
1680 if (retval < 0) {
1681 dev_err(&pdev->dev,
1682 "%s pci_enable_device failed\n", __func__);
1683 } else {
1684 pci_enable_wake(pdev, PCI_D3hot, 0);
1685
1686 /* set suspend status to false */
1687 pd_dev_save->board_dat->suspend_sts = false;
1688 }
1689
1690 return retval;
1691 }
1692 #else
1693 #define pch_spi_suspend NULL
1694 #define pch_spi_resume NULL
1695
1696 #endif
1697
1698 static struct pci_driver pch_spi_pcidev_driver = {
1699 .name = "pch_spi",
1700 .id_table = pch_spi_pcidev_id,
1701 .probe = pch_spi_probe,
1702 .remove = pch_spi_remove,
1703 .suspend = pch_spi_suspend,
1704 .resume = pch_spi_resume,
1705 };
1706
1707 static int __init pch_spi_init(void)
1708 {
1709 int ret;
1710 ret = platform_driver_register(&pch_spi_pd_driver);
1711 if (ret)
1712 return ret;
1713
1714 ret = pci_register_driver(&pch_spi_pcidev_driver);
1715 if (ret) {
1716 platform_driver_unregister(&pch_spi_pd_driver);
1717 return ret;
1718 }
1719
1720 return 0;
1721 }
1722 module_init(pch_spi_init);
1723
1724 static void __exit pch_spi_exit(void)
1725 {
1726 pci_unregister_driver(&pch_spi_pcidev_driver);
1727 platform_driver_unregister(&pch_spi_pd_driver);
1728 }
1729 module_exit(pch_spi_exit);
1730
1731 module_param(use_dma, int, 0644);
1732 MODULE_PARM_DESC(use_dma,
1733 "to use DMA for data transfers pass 1 else 0; default 1");
1734
1735 MODULE_LICENSE("GPL");
1736 MODULE_DESCRIPTION("Intel EG20T PCH/LAPIS Semiconductor ML7xxx IOH SPI Driver");
1737 MODULE_DEVICE_TABLE(pci, pch_spi_pcidev_id);
1738
Linux with added FPC-III support