| blob | b2e681c78466bec87ae437d18ee7b7a7765595e9 |
1 [
2 {
3 "EventCode": "0x2",
4 "Counter": "0,1",
5 "UMask": "0x83",
6 "EventName": "STORE_FORWARDS.ANY",
7 "SampleAfterValue": "200000",
8 "BriefDescription": "All store forwards"
9 },
10 {
11 "EventCode": "0x2",
12 "Counter": "0,1",
13 "UMask": "0x81",
14 "EventName": "STORE_FORWARDS.GOOD",
15 "SampleAfterValue": "200000",
16 "BriefDescription": "Good store forwards"
17 },
18 {
19 "EventCode": "0x3",
20 "Counter": "0,1",
21 "UMask": "0x7f",
22 "EventName": "REISSUE.ANY",
23 "SampleAfterValue": "200000",
24 "BriefDescription": "Micro-op reissues for any cause"
25 },
26 {
27 "EventCode": "0x3",
28 "Counter": "0,1",
29 "UMask": "0xff",
30 "EventName": "REISSUE.ANY.AR",
31 "SampleAfterValue": "200000",
32 "BriefDescription": "Micro-op reissues for any cause (At Retirement)"
33 },
34 {
35 "EventCode": "0x12",
36 "Counter": "0,1",
37 "UMask": "0x1",
38 "EventName": "MUL.S",
39 "SampleAfterValue": "2000000",
40 "BriefDescription": "Multiply operations executed."
41 },
42 {
43 "EventCode": "0x12",
44 "Counter": "0,1",
45 "UMask": "0x81",
46 "EventName": "MUL.AR",
47 "SampleAfterValue": "2000000",
48 "BriefDescription": "Multiply operations retired"
49 },
50 {
51 "EventCode": "0x13",
52 "Counter": "0,1",
53 "UMask": "0x1",
54 "EventName": "DIV.S",
55 "SampleAfterValue": "2000000",
56 "BriefDescription": "Divide operations executed."
57 },
58 {
59 "EventCode": "0x13",
60 "Counter": "0,1",
61 "UMask": "0x81",
62 "EventName": "DIV.AR",
63 "SampleAfterValue": "2000000",
64 "BriefDescription": "Divide operations retired"
65 },
66 {
67 "EventCode": "0x14",
68 "Counter": "0,1",
69 "UMask": "0x1",
70 "EventName": "CYCLES_DIV_BUSY",
71 "SampleAfterValue": "2000000",
72 "BriefDescription": "Cycles the divider is busy."
73 },
74 {
75 "EventCode": "0x3C",
76 "Counter": "0,1",
77 "UMask": "0x0",
78 "EventName": "CPU_CLK_UNHALTED.CORE_P",
79 "SampleAfterValue": "2000000",
80 "BriefDescription": "Core cycles when core is not halted"
81 },
82 {
83 "EventCode": "0x3C",
84 "Counter": "0,1",
85 "UMask": "0x1",
86 "EventName": "CPU_CLK_UNHALTED.BUS",
87 "SampleAfterValue": "200000",
88 "BriefDescription": "Bus cycles when core is not halted"
89 },
90 {
91 "EventCode": "0xA",
92 "Counter": "Fixed counter 2",
93 "UMask": "0x0",
94 "EventName": "CPU_CLK_UNHALTED.CORE",
95 "SampleAfterValue": "2000000",
96 "BriefDescription": "Core cycles when core is not halted"
97 },
98 {
99 "EventCode": "0xA",
100 "Counter": "Fixed counter 3",
101 "UMask": "0x0",
102 "EventName": "CPU_CLK_UNHALTED.REF",
103 "SampleAfterValue": "2000000",
104 "BriefDescription": "Reference cycles when core is not halted."
105 },
106 {
107 "EventCode": "0x88",
108 "Counter": "0,1",
109 "UMask": "0x1",
110 "EventName": "BR_INST_TYPE_RETIRED.COND",
111 "SampleAfterValue": "2000000",
112 "BriefDescription": "All macro conditional branch instructions."
113 },
114 {
115 "EventCode": "0x88",
116 "Counter": "0,1",
117 "UMask": "0x2",
118 "EventName": "BR_INST_TYPE_RETIRED.UNCOND",
119 "SampleAfterValue": "2000000",
120 "BriefDescription": "All macro unconditional branch instructions, excluding calls and indirects"
121 },
122 {
123 "EventCode": "0x88",
124 "Counter": "0,1",
125 "UMask": "0x4",
126 "EventName": "BR_INST_TYPE_RETIRED.IND",
127 "SampleAfterValue": "2000000",
128 "BriefDescription": "All indirect branches that are not calls."
129 },
130 {
131 "EventCode": "0x88",
132 "Counter": "0,1",
133 "UMask": "0x8",
134 "EventName": "BR_INST_TYPE_RETIRED.RET",
135 "SampleAfterValue": "2000000",
136 "BriefDescription": "All indirect branches that have a return mnemonic"
137 },
138 {
139 "EventCode": "0x88",
140 "Counter": "0,1",
141 "UMask": "0x10",
142 "EventName": "BR_INST_TYPE_RETIRED.DIR_CALL",
143 "SampleAfterValue": "2000000",
144 "BriefDescription": "All non-indirect calls"
145 },
146 {
147 "EventCode": "0x88",
148 "Counter": "0,1",
149 "UMask": "0x20",
150 "EventName": "BR_INST_TYPE_RETIRED.IND_CALL",
151 "SampleAfterValue": "2000000",
152 "BriefDescription": "All indirect calls, including both register and memory indirect."
153 },
154 {
155 "EventCode": "0x88",
156 "Counter": "0,1",
157 "UMask": "0x41",
158 "EventName": "BR_INST_TYPE_RETIRED.COND_TAKEN",
159 "SampleAfterValue": "2000000",
160 "BriefDescription": "Only taken macro conditional branch instructions"
161 },
162 {
163 "EventCode": "0x89",
164 "Counter": "0,1",
165 "UMask": "0x1",
166 "EventName": "BR_MISSP_TYPE_RETIRED.COND",
167 "SampleAfterValue": "200000",
168 "BriefDescription": "Mispredicted cond branch instructions retired"
169 },
170 {
171 "EventCode": "0x89",
172 "Counter": "0,1",
173 "UMask": "0x2",
174 "EventName": "BR_MISSP_TYPE_RETIRED.IND",
175 "SampleAfterValue": "200000",
176 "BriefDescription": "Mispredicted ind branches that are not calls"
177 },
178 {
179 "EventCode": "0x89",
180 "Counter": "0,1",
181 "UMask": "0x4",
182 "EventName": "BR_MISSP_TYPE_RETIRED.RETURN",
183 "SampleAfterValue": "200000",
184 "BriefDescription": "Mispredicted return branches"
185 },
186 {
187 "EventCode": "0x89",
188 "Counter": "0,1",
189 "UMask": "0x8",
190 "EventName": "BR_MISSP_TYPE_RETIRED.IND_CALL",
191 "SampleAfterValue": "200000",
192 "BriefDescription": "Mispredicted indirect calls, including both register and memory indirect. "
193 },
194 {
195 "EventCode": "0x89",
196 "Counter": "0,1",
197 "UMask": "0x11",
198 "EventName": "BR_MISSP_TYPE_RETIRED.COND_TAKEN",
199 "SampleAfterValue": "200000",
200 "BriefDescription": "Mispredicted and taken cond branch instructions retired"
201 },
202 {
203 "PEBS": "2",
204 "EventCode": "0xC0",
205 "Counter": "0,1",
206 "UMask": "0x0",
207 "EventName": "INST_RETIRED.ANY_P",
208 "SampleAfterValue": "2000000",
209 "BriefDescription": "Instructions retired (precise event)."
210 },
211 {
212 "EventCode": "0xA",
213 "Counter": "Fixed counter 1",
214 "UMask": "0x0",
215 "EventName": "INST_RETIRED.ANY",
216 "SampleAfterValue": "2000000",
217 "BriefDescription": "Instructions retired."
218 },
219 {
220 "EventCode": "0xC2",
221 "Counter": "0,1",
222 "UMask": "0x10",
223 "EventName": "UOPS_RETIRED.ANY",
224 "SampleAfterValue": "2000000",
225 "BriefDescription": "Micro-ops retired."
226 },
227 {
228 "EventCode": "0xC2",
229 "Counter": "0,1",
230 "UMask": "0x10",
231 "EventName": "UOPS_RETIRED.STALLED_CYCLES",
232 "SampleAfterValue": "2000000",
233 "BriefDescription": "Cycles no micro-ops retired."
234 },
235 {
236 "EventCode": "0xC2",
237 "Counter": "0,1",
238 "UMask": "0x10",
239 "EventName": "UOPS_RETIRED.STALLS",
240 "SampleAfterValue": "2000000",
241 "BriefDescription": "Periods no micro-ops retired."
242 },
243 {
244 "EventCode": "0xC3",
245 "Counter": "0,1",
246 "UMask": "0x1",
247 "EventName": "MACHINE_CLEARS.SMC",
248 "SampleAfterValue": "200000",
249 "BriefDescription": "Self-Modifying Code detected."
250 },
251 {
252 "EventCode": "0xC4",
253 "Counter": "0,1",
254 "UMask": "0x0",
255 "EventName": "BR_INST_RETIRED.ANY",
256 "SampleAfterValue": "2000000",
257 "BriefDescription": "Retired branch instructions."
258 },
259 {
260 "EventCode": "0xC4",
261 "Counter": "0,1",
262 "UMask": "0x1",
263 "EventName": "BR_INST_RETIRED.PRED_NOT_TAKEN",
264 "SampleAfterValue": "2000000",
265 "BriefDescription": "Retired branch instructions that were predicted not-taken."
266 },
267 {
268 "EventCode": "0xC4",
269 "Counter": "0,1",
270 "UMask": "0x2",
271 "EventName": "BR_INST_RETIRED.MISPRED_NOT_TAKEN",
272 "SampleAfterValue": "200000",
273 "BriefDescription": "Retired branch instructions that were mispredicted not-taken."
274 },
275 {
276 "EventCode": "0xC4",
277 "Counter": "0,1",
278 "UMask": "0x4",
279 "EventName": "BR_INST_RETIRED.PRED_TAKEN",
280 "SampleAfterValue": "2000000",
281 "BriefDescription": "Retired branch instructions that were predicted taken."
282 },
283 {
284 "EventCode": "0xC4",
285 "Counter": "0,1",
286 "UMask": "0x8",
287 "EventName": "BR_INST_RETIRED.MISPRED_TAKEN",
288 "SampleAfterValue": "200000",
289 "BriefDescription": "Retired branch instructions that were mispredicted taken."
290 },
291 {
292 "EventCode": "0xC4",
293 "Counter": "0,1",
294 "UMask": "0xc",
295 "EventName": "BR_INST_RETIRED.TAKEN",
296 "SampleAfterValue": "2000000",
297 "BriefDescription": "Retired taken branch instructions."
298 },
299 {
300 "EventCode": "0xC4",
301 "Counter": "0,1",
302 "UMask": "0xf",
303 "EventName": "BR_INST_RETIRED.ANY1",
304 "SampleAfterValue": "2000000",
305 "BriefDescription": "Retired branch instructions."
306 },
307 {
308 "PEBS": "1",
309 "EventCode": "0xC5",
310 "Counter": "0,1",
311 "UMask": "0x0",
312 "EventName": "BR_INST_RETIRED.MISPRED",
313 "SampleAfterValue": "200000",
314 "BriefDescription": "Retired mispredicted branch instructions (precise event)."
315 },
316 {
317 "EventCode": "0xDC",
318 "Counter": "0,1",
319 "UMask": "0x2",
320 "EventName": "RESOURCE_STALLS.DIV_BUSY",
321 "SampleAfterValue": "2000000",
322 "BriefDescription": "Cycles issue is stalled due to div busy."
323 },
324 {
325 "EventCode": "0xE0",
326 "Counter": "0,1",
327 "UMask": "0x1",
328 "EventName": "BR_INST_DECODED",
329 "SampleAfterValue": "2000000",
330 "BriefDescription": "Branch instructions decoded"
331 },
332 {
333 "EventCode": "0xE4",
334 "Counter": "0,1",
335 "UMask": "0x1",
336 "EventName": "BOGUS_BR",
337 "SampleAfterValue": "2000000",
338 "BriefDescription": "Bogus branches"
339 },
340 {
341 "EventCode": "0xE6",
342 "Counter": "0,1",
343 "UMask": "0x1",
344 "EventName": "BACLEARS.ANY",
345 "SampleAfterValue": "2000000",
346 "BriefDescription": "BACLEARS asserted."
347 },
348 {
349 "EventCode": "0x3",
350 "Counter": "0,1",
351 "UMask": "0x1",
352 "EventName": "REISSUE.OVERLAP_STORE",
353 "SampleAfterValue": "200000",
354 "BriefDescription": "Micro-op reissues on a store-load collision"
355 },
356 {
357 "EventCode": "0x3",
358 "Counter": "0,1",
359 "UMask": "0x81",
360 "EventName": "REISSUE.OVERLAP_STORE.AR",
361 "SampleAfterValue": "200000",
362 "BriefDescription": "Micro-op reissues on a store-load collision (At Retirement)"
363 }
364 ]