| blob | 91b38de138f2d6759eef6cddb7839e837ec9c0c4 |
1 [
2 {
3 "EventCode": "0xC7",
4 "UMask": "0x1",
5 "BriefDescription": "Number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
6 "Counter": "0,1,2,3",
7 "EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE",
8 "SampleAfterValue": "2000003",
9 "CounterHTOff": "0,1,2,3,4,5,6,7"
10 },
11 {
12 "EventCode": "0xC7",
13 "UMask": "0x2",
14 "BriefDescription": "Number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
15 "Counter": "0,1,2,3",
16 "EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE",
17 "SampleAfterValue": "2000003",
18 "CounterHTOff": "0,1,2,3,4,5,6,7"
19 },
20 {
21 "EventCode": "0xC7",
22 "UMask": "0x4",
23 "BriefDescription": "Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT14 RCP14 DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
24 "Counter": "0,1,2,3",
25 "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE",
26 "SampleAfterValue": "2000003",
27 "CounterHTOff": "0,1,2,3,4,5,6,7"
28 },
29 {
30 "EventCode": "0xC7",
31 "UMask": "0x8",
32 "BriefDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 4 calculations per element.",
33 "Counter": "0,1,2,3",
34 "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE",
35 "SampleAfterValue": "2000003",
36 "CounterHTOff": "0,1,2,3,4,5,6,7"
37 },
38 {
39 "EventCode": "0xC7",
40 "UMask": "0x10",
41 "BriefDescription": "Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 4 calculations per element.",
42 "Counter": "0,1,2,3",
43 "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE",
44 "SampleAfterValue": "2000003",
45 "CounterHTOff": "0,1,2,3,4,5,6,7"
46 },
47 {
48 "EventCode": "0xC7",
49 "UMask": "0x20",
50 "BriefDescription": "Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 8 calculations per element.",
51 "Counter": "0,1,2,3",
52 "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE",
53 "SampleAfterValue": "2000003",
54 "CounterHTOff": "0,1,2,3,4,5,6,7"
55 },
56 {
57 "EventCode": "0xC7",
58 "UMask": "0x40",
59 "BriefDescription": "Number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 8 calculations per element.",
60 "Counter": "0,1,2,3",
61 "EventName": "FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE",
62 "SampleAfterValue": "2000003",
63 "CounterHTOff": "0,1,2,3,4,5,6,7"
64 },
65 {
66 "EventCode": "0xC7",
67 "UMask": "0x80",
68 "BriefDescription": "Number of SSE/AVX computational 512-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 16 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 16 calculations per element.",
69 "Counter": "0,1,2,3",
70 "EventName": "FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE",
71 "SampleAfterValue": "2000003",
72 "CounterHTOff": "0,1,2,3,4,5,6,7"
73 },
74 {
75 "EventCode": "0xCA",
76 "UMask": "0x1e",
77 "BriefDescription": "Cycles with any input/output SSE or FP assist",
78 "Counter": "0,1,2,3",
79 "EventName": "FP_ASSIST.ANY",
80 "CounterMask": "1",
81 "PublicDescription": "Counts cycles with any input and output SSE or x87 FP assist. If an input and output assist are detected on the same cycle the event increments by 1.",
82 "SampleAfterValue": "100003",
83 "CounterHTOff": "0,1,2,3,4,5,6,7"
84 }
85 ]