| blob | da4d6ddd4f924d5e8527c45668151ce17cfcb346 |
1 [
2 {
3 "PublicDescription": "Demand data read requests that missed L2, no rejects.",
4 "EventCode": "0x24",
5 "Counter": "0,1,2,3",
6 "UMask": "0x21",
7 "Errata": "HSD78",
8 "EventName": "L2_RQSTS.DEMAND_DATA_RD_MISS",
9 "SampleAfterValue": "200003",
10 "BriefDescription": "Demand Data Read miss L2, no rejects",
11 "CounterHTOff": "0,1,2,3,4,5,6,7"
12 },
13 {
14 "PublicDescription": "Counts the number of store RFO requests that miss the L2 cache.",
15 "EventCode": "0x24",
16 "Counter": "0,1,2,3",
17 "UMask": "0x22",
18 "EventName": "L2_RQSTS.RFO_MISS",
19 "SampleAfterValue": "200003",
20 "BriefDescription": "RFO requests that miss L2 cache",
21 "CounterHTOff": "0,1,2,3,4,5,6,7"
22 },
23 {
24 "PublicDescription": "Number of instruction fetches that missed the L2 cache.",
25 "EventCode": "0x24",
26 "Counter": "0,1,2,3",
27 "UMask": "0x24",
28 "EventName": "L2_RQSTS.CODE_RD_MISS",
29 "SampleAfterValue": "200003",
30 "BriefDescription": "L2 cache misses when fetching instructions",
31 "CounterHTOff": "0,1,2,3,4,5,6,7"
32 },
33 {
34 "PublicDescription": "Demand requests that miss L2 cache.",
35 "EventCode": "0x24",
36 "Counter": "0,1,2,3",
37 "UMask": "0x27",
38 "Errata": "HSD78",
39 "EventName": "L2_RQSTS.ALL_DEMAND_MISS",
40 "SampleAfterValue": "200003",
41 "BriefDescription": "Demand requests that miss L2 cache",
42 "CounterHTOff": "0,1,2,3,4,5,6,7"
43 },
44 {
45 "PublicDescription": "Counts all L2 HW prefetcher requests that missed L2.",
46 "EventCode": "0x24",
47 "Counter": "0,1,2,3",
48 "UMask": "0x30",
49 "EventName": "L2_RQSTS.L2_PF_MISS",
50 "SampleAfterValue": "200003",
51 "BriefDescription": "L2 prefetch requests that miss L2 cache",
52 "CounterHTOff": "0,1,2,3,4,5,6,7"
53 },
54 {
55 "PublicDescription": "All requests that missed L2.",
56 "EventCode": "0x24",
57 "Counter": "0,1,2,3",
58 "UMask": "0x3f",
59 "Errata": "HSD78",
60 "EventName": "L2_RQSTS.MISS",
61 "SampleAfterValue": "200003",
62 "BriefDescription": "All requests that miss L2 cache",
63 "CounterHTOff": "0,1,2,3,4,5,6,7"
64 },
65 {
66 "PublicDescription": "Demand data read requests that hit L2 cache.",
67 "EventCode": "0x24",
68 "Counter": "0,1,2,3",
69 "UMask": "0x41",
70 "Errata": "HSD78",
71 "EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT",
72 "SampleAfterValue": "200003",
73 "BriefDescription": "Demand Data Read requests that hit L2 cache",
74 "CounterHTOff": "0,1,2,3,4,5,6,7"
75 },
76 {
77 "PublicDescription": "Counts the number of store RFO requests that hit the L2 cache.",
78 "EventCode": "0x24",
79 "Counter": "0,1,2,3",
80 "UMask": "0x42",
81 "EventName": "L2_RQSTS.RFO_HIT",
82 "SampleAfterValue": "200003",
83 "BriefDescription": "RFO requests that hit L2 cache",
84 "CounterHTOff": "0,1,2,3,4,5,6,7"
85 },
86 {
87 "PublicDescription": "Number of instruction fetches that hit the L2 cache.",
88 "EventCode": "0x24",
89 "Counter": "0,1,2,3",
90 "UMask": "0x44",
91 "EventName": "L2_RQSTS.CODE_RD_HIT",
92 "SampleAfterValue": "200003",
93 "BriefDescription": "L2 cache hits when fetching instructions, code reads.",
94 "CounterHTOff": "0,1,2,3,4,5,6,7"
95 },
96 {
97 "PublicDescription": "Counts all L2 HW prefetcher requests that hit L2.",
98 "EventCode": "0x24",
99 "Counter": "0,1,2,3",
100 "UMask": "0x50",
101 "EventName": "L2_RQSTS.L2_PF_HIT",
102 "SampleAfterValue": "200003",
103 "BriefDescription": "L2 prefetch requests that hit L2 cache",
104 "CounterHTOff": "0,1,2,3,4,5,6,7"
105 },
106 {
107 "PublicDescription": "Counts any demand and L1 HW prefetch data load requests to L2.",
108 "EventCode": "0x24",
109 "Counter": "0,1,2,3",
110 "UMask": "0xe1",
111 "Errata": "HSD78",
112 "EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD",
113 "SampleAfterValue": "200003",
114 "BriefDescription": "Demand Data Read requests",
115 "CounterHTOff": "0,1,2,3,4,5,6,7"
116 },
117 {
118 "PublicDescription": "Counts all L2 store RFO requests.",
119 "EventCode": "0x24",
120 "Counter": "0,1,2,3",
121 "UMask": "0xe2",
122 "EventName": "L2_RQSTS.ALL_RFO",
123 "SampleAfterValue": "200003",
124 "BriefDescription": "RFO requests to L2 cache",
125 "CounterHTOff": "0,1,2,3,4,5,6,7"
126 },
127 {
128 "PublicDescription": "Counts all L2 code requests.",
129 "EventCode": "0x24",
130 "Counter": "0,1,2,3",
131 "UMask": "0xe4",
132 "EventName": "L2_RQSTS.ALL_CODE_RD",
133 "SampleAfterValue": "200003",
134 "BriefDescription": "L2 code requests",
135 "CounterHTOff": "0,1,2,3,4,5,6,7"
136 },
137 {
138 "PublicDescription": "Demand requests to L2 cache.",
139 "EventCode": "0x24",
140 "Counter": "0,1,2,3",
141 "UMask": "0xe7",
142 "Errata": "HSD78",
143 "EventName": "L2_RQSTS.ALL_DEMAND_REFERENCES",
144 "SampleAfterValue": "200003",
145 "BriefDescription": "Demand requests to L2 cache",
146 "CounterHTOff": "0,1,2,3,4,5,6,7"
147 },
148 {
149 "PublicDescription": "Counts all L2 HW prefetcher requests.",
150 "EventCode": "0x24",
151 "Counter": "0,1,2,3",
152 "UMask": "0xf8",
153 "EventName": "L2_RQSTS.ALL_PF",
154 "SampleAfterValue": "200003",
155 "BriefDescription": "Requests from L2 hardware prefetchers",
156 "CounterHTOff": "0,1,2,3,4,5,6,7"
157 },
158 {
159 "PublicDescription": "All requests to L2 cache.",
160 "EventCode": "0x24",
161 "Counter": "0,1,2,3",
162 "UMask": "0xff",
163 "Errata": "HSD78",
164 "EventName": "L2_RQSTS.REFERENCES",
165 "SampleAfterValue": "200003",
166 "BriefDescription": "All L2 requests",
167 "CounterHTOff": "0,1,2,3,4,5,6,7"
168 },
169 {
170 "PublicDescription": "Not rejected writebacks that hit L2 cache.",
171 "EventCode": "0x27",
172 "Counter": "0,1,2,3",
173 "UMask": "0x50",
174 "EventName": "L2_DEMAND_RQSTS.WB_HIT",
175 "SampleAfterValue": "200003",
176 "BriefDescription": "Not rejected writebacks that hit L2 cache",
177 "CounterHTOff": "0,1,2,3,4,5,6,7"
178 },
179 {
180 "PublicDescription": "This event counts each cache miss condition for references to the last level cache.",
181 "EventCode": "0x2E",
182 "Counter": "0,1,2,3",
183 "UMask": "0x41",
184 "EventName": "LONGEST_LAT_CACHE.MISS",
185 "SampleAfterValue": "100003",
186 "BriefDescription": "Core-originated cacheable demand requests missed L3",
187 "CounterHTOff": "0,1,2,3,4,5,6,7"
188 },
189 {
190 "PublicDescription": "This event counts requests originating from the core that reference a cache line in the last level cache.",
191 "EventCode": "0x2E",
192 "Counter": "0,1,2,3",
193 "UMask": "0x4f",
194 "EventName": "LONGEST_LAT_CACHE.REFERENCE",
195 "SampleAfterValue": "100003",
196 "BriefDescription": "Core-originated cacheable demand requests that refer to L3",
197 "CounterHTOff": "0,1,2,3,4,5,6,7"
198 },
199 {
200 "PublicDescription": "Increments the number of outstanding L1D misses every cycle. Set Cmask = 1 and Edge =1 to count occurrences.",
201 "EventCode": "0x48",
202 "Counter": "2",
203 "UMask": "0x1",
204 "EventName": "L1D_PEND_MISS.PENDING",
205 "SampleAfterValue": "2000003",
206 "BriefDescription": "L1D miss oustandings duration in cycles",
207 "CounterHTOff": "2"
208 },
209 {
210 "EventCode": "0x48",
211 "Counter": "2",
212 "UMask": "0x1",
213 "EventName": "L1D_PEND_MISS.PENDING_CYCLES",
214 "SampleAfterValue": "2000003",
215 "BriefDescription": "Cycles with L1D load Misses outstanding.",
216 "CounterMask": "1",
217 "CounterHTOff": "2"
218 },
219 {
220 "EventCode": "0x48",
221 "Counter": "2",
222 "UMask": "0x1",
223 "AnyThread": "1",
224 "EventName": "L1D_PEND_MISS.PENDING_CYCLES_ANY",
225 "SampleAfterValue": "2000003",
226 "BriefDescription": "Cycles with L1D load Misses outstanding from any thread on physical core.",
227 "CounterMask": "1",
228 "CounterHTOff": "2"
229 },
230 {
231 "EventCode": "0x48",
232 "Counter": "0,1,2,3",
233 "UMask": "0x2",
234 "EventName": "L1D_PEND_MISS.REQUEST_FB_FULL",
235 "SampleAfterValue": "2000003",
236 "BriefDescription": "Number of times a request needed a FB entry but there was no entry available for it. That is the FB unavailability was dominant reason for blocking the request. A request includes cacheable/uncacheable demands that is load, store or SW prefetch. HWP are e.",
237 "CounterHTOff": "0,1,2,3,4,5,6,7"
238 },
239 {
240 "EventCode": "0x48",
241 "Counter": "0,1,2,3",
242 "UMask": "0x2",
243 "EventName": "L1D_PEND_MISS.FB_FULL",
244 "SampleAfterValue": "2000003",
245 "BriefDescription": "Cycles a demand request was blocked due to Fill Buffers inavailability.",
246 "CounterMask": "1",
247 "CounterHTOff": "0,1,2,3,4,5,6,7"
248 },
249 {
250 "PublicDescription": "This event counts when new data lines are brought into the L1 Data cache, which cause other lines to be evicted from the cache.",
251 "EventCode": "0x51",
252 "Counter": "0,1,2,3",
253 "UMask": "0x1",
254 "EventName": "L1D.REPLACEMENT",
255 "SampleAfterValue": "2000003",
256 "BriefDescription": "L1D data line replacements",
257 "CounterHTOff": "0,1,2,3,4,5,6,7"
258 },
259 {
260 "PublicDescription": "Offcore outstanding demand data read transactions in SQ to uncore. Set Cmask=1 to count cycles.",
261 "EventCode": "0x60",
262 "Counter": "0,1,2,3",
263 "UMask": "0x1",
264 "Errata": "HSD78, HSD62, HSD61",
265 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD",
266 "SampleAfterValue": "2000003",
267 "BriefDescription": "Offcore outstanding Demand Data Read transactions in uncore queue.",
268 "CounterHTOff": "0,1,2,3,4,5,6,7"
269 },
270 {
271 "EventCode": "0x60",
272 "Counter": "0,1,2,3",
273 "UMask": "0x1",
274 "Errata": "HSD78, HSD62, HSD61",
275 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD",
276 "SampleAfterValue": "2000003",
277 "BriefDescription": "Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore.",
278 "CounterMask": "1",
279 "CounterHTOff": "0,1,2,3,4,5,6,7"
280 },
281 {
282 "EventCode": "0x60",
283 "Counter": "0,1,2,3",
284 "UMask": "0x1",
285 "Errata": "HSD78, HSD62, HSD61",
286 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD_GE_6",
287 "SampleAfterValue": "2000003",
288 "BriefDescription": "Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue.",
289 "CounterMask": "6",
290 "CounterHTOff": "0,1,2,3,4,5,6,7"
291 },
292 {
293 "PublicDescription": "Offcore outstanding Demand code Read transactions in SQ to uncore. Set Cmask=1 to count cycles.",
294 "EventCode": "0x60",
295 "Counter": "0,1,2,3",
296 "UMask": "0x2",
297 "Errata": "HSD62, HSD61",
298 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD",
299 "SampleAfterValue": "2000003",
300 "BriefDescription": "Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle",
301 "CounterHTOff": "0,1,2,3,4,5,6,7"
302 },
303 {
304 "PublicDescription": "Offcore outstanding RFO store transactions in SQ to uncore. Set Cmask=1 to count cycles.",
305 "EventCode": "0x60",
306 "Counter": "0,1,2,3",
307 "UMask": "0x4",
308 "Errata": "HSD62, HSD61",
309 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO",
310 "SampleAfterValue": "2000003",
311 "BriefDescription": "Offcore outstanding RFO store transactions in SuperQueue (SQ), queue to uncore",
312 "CounterHTOff": "0,1,2,3,4,5,6,7"
313 },
314 {
315 "EventCode": "0x60",
316 "Counter": "0,1,2,3",
317 "UMask": "0x4",
318 "Errata": "HSD62, HSD61",
319 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO",
320 "SampleAfterValue": "2000003",
321 "BriefDescription": "Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle.",
322 "CounterMask": "1",
323 "CounterHTOff": "0,1,2,3,4,5,6,7"
324 },
325 {
326 "PublicDescription": "Offcore outstanding cacheable data read transactions in SQ to uncore. Set Cmask=1 to count cycles.",
327 "EventCode": "0x60",
328 "Counter": "0,1,2,3",
329 "UMask": "0x8",
330 "Errata": "HSD62, HSD61",
331 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD",
332 "SampleAfterValue": "2000003",
333 "BriefDescription": "Offcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ), queue to uncore",
334 "CounterHTOff": "0,1,2,3,4,5,6,7"
335 },
336 {
337 "EventCode": "0x60",
338 "Counter": "0,1,2,3",
339 "UMask": "0x8",
340 "Errata": "HSD62, HSD61",
341 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD",
342 "SampleAfterValue": "2000003",
343 "BriefDescription": "Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore.",
344 "CounterMask": "1",
345 "CounterHTOff": "0,1,2,3,4,5,6,7"
346 },
347 {
348 "PublicDescription": "Cycles in which the L1D is locked.",
349 "EventCode": "0x63",
350 "Counter": "0,1,2,3",
351 "UMask": "0x2",
352 "EventName": "LOCK_CYCLES.CACHE_LOCK_DURATION",
353 "SampleAfterValue": "2000003",
354 "BriefDescription": "Cycles when L1D is locked",
355 "CounterHTOff": "0,1,2,3,4,5,6,7"
356 },
357 {
358 "PublicDescription": "Demand data read requests sent to uncore.",
359 "EventCode": "0xB0",
360 "Counter": "0,1,2,3",
361 "UMask": "0x1",
362 "Errata": "HSD78",
363 "EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD",
364 "SampleAfterValue": "100003",
365 "BriefDescription": "Demand Data Read requests sent to uncore",
366 "CounterHTOff": "0,1,2,3,4,5,6,7"
367 },
368 {
369 "PublicDescription": "Demand code read requests sent to uncore.",
370 "EventCode": "0xB0",
371 "Counter": "0,1,2,3",
372 "UMask": "0x2",
373 "EventName": "OFFCORE_REQUESTS.DEMAND_CODE_RD",
374 "SampleAfterValue": "100003",
375 "BriefDescription": "Cacheable and noncachaeble code read requests",
376 "CounterHTOff": "0,1,2,3,4,5,6,7"
377 },
378 {
379 "PublicDescription": "Demand RFO read requests sent to uncore, including regular RFOs, locks, ItoM.",
380 "EventCode": "0xB0",
381 "Counter": "0,1,2,3",
382 "UMask": "0x4",
383 "EventName": "OFFCORE_REQUESTS.DEMAND_RFO",
384 "SampleAfterValue": "100003",
385 "BriefDescription": "Demand RFO requests including regular RFOs, locks, ItoM",
386 "CounterHTOff": "0,1,2,3,4,5,6,7"
387 },
388 {
389 "PublicDescription": "Data read requests sent to uncore (demand and prefetch).",
390 "EventCode": "0xB0",
391 "Counter": "0,1,2,3",
392 "UMask": "0x8",
393 "EventName": "OFFCORE_REQUESTS.ALL_DATA_RD",
394 "SampleAfterValue": "100003",
395 "BriefDescription": "Demand and prefetch data reads",
396 "CounterHTOff": "0,1,2,3,4,5,6,7"
397 },
398 {
399 "EventCode": "0xb2",
400 "Counter": "0,1,2,3",
401 "UMask": "0x1",
402 "EventName": "OFFCORE_REQUESTS_BUFFER.SQ_FULL",
403 "SampleAfterValue": "2000003",
404 "BriefDescription": "Offcore requests buffer cannot take more entries for this thread core.",
405 "CounterHTOff": "0,1,2,3,4,5,6,7"
406 },
407 {
408 "EventCode": "0xB7, 0xBB",
409 "Counter": "0,1,2,3",
410 "UMask": "0x1",
411 "EventName": "OFFCORE_RESPONSE",
412 "SampleAfterValue": "100003",
413 "BriefDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
414 "CounterHTOff": "0,1,2,3"
415 },
416 {
417 "PEBS": "1",
418 "EventCode": "0xD0",
419 "Counter": "0,1,2,3",
420 "UMask": "0x11",
421 "Errata": "HSD29, HSM30",
422 "EventName": "MEM_UOPS_RETIRED.STLB_MISS_LOADS",
423 "SampleAfterValue": "100003",
424 "BriefDescription": "Retired load uops that miss the STLB. (precise Event)",
425 "CounterHTOff": "0,1,2,3",
426 "Data_LA": "1"
427 },
428 {
429 "PEBS": "1",
430 "EventCode": "0xD0",
431 "Counter": "0,1,2,3",
432 "UMask": "0x12",
433 "Errata": "HSD29, HSM30",
434 "EventName": "MEM_UOPS_RETIRED.STLB_MISS_STORES",
435 "SampleAfterValue": "100003",
436 "BriefDescription": "Retired store uops that miss the STLB. (precise Event)",
437 "CounterHTOff": "0,1,2,3",
438 "Data_LA": "1",
439 "L1_Hit_Indication": "1"
440 },
441 {
442 "PEBS": "1",
443 "EventCode": "0xD0",
444 "Counter": "0,1,2,3",
445 "UMask": "0x21",
446 "Errata": "HSD76, HSD29, HSM30",
447 "EventName": "MEM_UOPS_RETIRED.LOCK_LOADS",
448 "SampleAfterValue": "100003",
449 "BriefDescription": "Retired load uops with locked access. (precise Event)",
450 "CounterHTOff": "0,1,2,3",
451 "Data_LA": "1"
452 },
453 {
454 "PEBS": "1",
455 "PublicDescription": "This event counts load uops retired which had memory addresses spilt across 2 cache lines. A line split is across 64B cache-lines which may include a page split (4K). This is a precise event.",
456 "EventCode": "0xD0",
457 "Counter": "0,1,2,3",
458 "UMask": "0x41",
459 "Errata": "HSD29, HSM30",
460 "EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS",
461 "SampleAfterValue": "100003",
462 "BriefDescription": "Retired load uops that split across a cacheline boundary. (precise Event)",
463 "CounterHTOff": "0,1,2,3",
464 "Data_LA": "1"
465 },
466 {
467 "PEBS": "1",
468 "PublicDescription": "This event counts store uops retired which had memory addresses spilt across 2 cache lines. A line split is across 64B cache-lines which may include a page split (4K). This is a precise event.",
469 "EventCode": "0xD0",
470 "Counter": "0,1,2,3",
471 "UMask": "0x42",
472 "Errata": "HSD29, HSM30",
473 "EventName": "MEM_UOPS_RETIRED.SPLIT_STORES",
474 "SampleAfterValue": "100003",
475 "BriefDescription": "Retired store uops that split across a cacheline boundary. (precise Event)",
476 "CounterHTOff": "0,1,2,3",
477 "Data_LA": "1",
478 "L1_Hit_Indication": "1"
479 },
480 {
481 "PEBS": "1",
482 "EventCode": "0xD0",
483 "Counter": "0,1,2,3",
484 "UMask": "0x81",
485 "Errata": "HSD29, HSM30",
486 "EventName": "MEM_UOPS_RETIRED.ALL_LOADS",
487 "SampleAfterValue": "2000003",
488 "BriefDescription": "All retired load uops. (precise Event)",
489 "CounterHTOff": "0,1,2,3",
490 "Data_LA": "1"
491 },
492 {
493 "PEBS": "1",
494 "PublicDescription": "This event counts all store uops retired. This is a precise event.",
495 "EventCode": "0xD0",
496 "Counter": "0,1,2,3",
497 "UMask": "0x82",
498 "Errata": "HSD29, HSM30",
499 "EventName": "MEM_UOPS_RETIRED.ALL_STORES",
500 "SampleAfterValue": "2000003",
501 "BriefDescription": "All retired store uops. (precise Event)",
502 "CounterHTOff": "0,1,2,3",
503 "Data_LA": "1",
504 "L1_Hit_Indication": "1"
505 },
506 {
507 "PEBS": "1",
508 "EventCode": "0xD1",
509 "Counter": "0,1,2,3",
510 "UMask": "0x1",
511 "Errata": "HSD29, HSM30",
512 "EventName": "MEM_LOAD_UOPS_RETIRED.L1_HIT",
513 "SampleAfterValue": "2000003",
514 "BriefDescription": "Retired load uops with L1 cache hits as data sources.",
515 "CounterHTOff": "0,1,2,3",
516 "Data_LA": "1"
517 },
518 {
519 "PEBS": "1",
520 "EventCode": "0xD1",
521 "Counter": "0,1,2,3",
522 "UMask": "0x2",
523 "Errata": "HSD76, HSD29, HSM30",
524 "EventName": "MEM_LOAD_UOPS_RETIRED.L2_HIT",
525 "SampleAfterValue": "100003",
526 "BriefDescription": "Retired load uops with L2 cache hits as data sources.",
527 "CounterHTOff": "0,1,2,3",
528 "Data_LA": "1"
529 },
530 {
531 "PEBS": "1",
532 "PublicDescription": "This event counts retired load uops in which data sources were data hits in the L3 cache without snoops required. This does not include hardware prefetches. This is a precise event.",
533 "EventCode": "0xD1",
534 "Counter": "0,1,2,3",
535 "UMask": "0x4",
536 "Errata": "HSD74, HSD29, HSD25, HSM26, HSM30",
537 "EventName": "MEM_LOAD_UOPS_RETIRED.L3_HIT",
538 "SampleAfterValue": "50021",
539 "BriefDescription": "Miss in last-level (L3) cache. Excludes Unknown data-source.",
540 "CounterHTOff": "0,1,2,3",
541 "Data_LA": "1"
542 },
543 {
544 "PEBS": "1",
545 "PublicDescription": "This event counts retired load uops in which data sources missed in the L1 cache. This does not include hardware prefetches. This is a precise event.",
546 "EventCode": "0xD1",
547 "Counter": "0,1,2,3",
548 "UMask": "0x8",
549 "Errata": "HSM30",
550 "EventName": "MEM_LOAD_UOPS_RETIRED.L1_MISS",
551 "SampleAfterValue": "100003",
552 "BriefDescription": "Retired load uops misses in L1 cache as data sources.",
553 "CounterHTOff": "0,1,2,3",
554 "Data_LA": "1"
555 },
556 {
557 "PEBS": "1",
558 "EventCode": "0xD1",
559 "Counter": "0,1,2,3",
560 "UMask": "0x10",
561 "Errata": "HSD29, HSM30",
562 "EventName": "MEM_LOAD_UOPS_RETIRED.L2_MISS",
563 "SampleAfterValue": "50021",
564 "BriefDescription": "Retired load uops with L2 cache misses as data sources.",
565 "CounterHTOff": "0,1,2,3",
566 "Data_LA": "1"
567 },
568 {
569 "PEBS": "1",
570 "EventCode": "0xD1",
571 "Counter": "0,1,2,3",
572 "UMask": "0x20",
573 "Errata": "HSD74, HSD29, HSD25, HSM26, HSM30",
574 "EventName": "MEM_LOAD_UOPS_RETIRED.L3_MISS",
575 "SampleAfterValue": "100003",
576 "BriefDescription": "Miss in last-level (L3) cache. Excludes Unknown data-source.",
577 "CounterHTOff": "0,1,2,3",
578 "Data_LA": "1"
579 },
580 {
581 "PEBS": "1",
582 "EventCode": "0xD1",
583 "Counter": "0,1,2,3",
584 "UMask": "0x40",
585 "Errata": "HSM30",
586 "EventName": "MEM_LOAD_UOPS_RETIRED.HIT_LFB",
587 "SampleAfterValue": "100003",
588 "BriefDescription": "Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready.",
589 "CounterHTOff": "0,1,2,3",
590 "Data_LA": "1"
591 },
592 {
593 "PEBS": "1",
594 "EventCode": "0xD2",
595 "Counter": "0,1,2,3",
596 "UMask": "0x1",
597 "Errata": "HSD29, HSD25, HSM26, HSM30",
598 "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS",
599 "SampleAfterValue": "20011",
600 "BriefDescription": "Retired load uops which data sources were L3 hit and cross-core snoop missed in on-pkg core cache.",
601 "CounterHTOff": "0,1,2,3",
602 "Data_LA": "1"
603 },
604 {
605 "PEBS": "1",
606 "PublicDescription": "This event counts retired load uops that hit in the L3 cache, but required a cross-core snoop which resulted in a HIT in an on-pkg core cache. This does not include hardware prefetches. This is a precise event.",
607 "EventCode": "0xD2",
608 "Counter": "0,1,2,3",
609 "UMask": "0x2",
610 "Errata": "HSD29, HSD25, HSM26, HSM30",
611 "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT",
612 "SampleAfterValue": "20011",
613 "BriefDescription": "Retired load uops which data sources were L3 and cross-core snoop hits in on-pkg core cache. ",
614 "CounterHTOff": "0,1,2,3",
615 "Data_LA": "1"
616 },
617 {
618 "PEBS": "1",
619 "PublicDescription": "This event counts retired load uops that hit in the L3 cache, but required a cross-core snoop which resulted in a HITM (hit modified) in an on-pkg core cache. This does not include hardware prefetches. This is a precise event.",
620 "EventCode": "0xD2",
621 "Counter": "0,1,2,3",
622 "UMask": "0x4",
623 "Errata": "HSD29, HSD25, HSM26, HSM30",
624 "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM",
625 "SampleAfterValue": "20011",
626 "BriefDescription": "Retired load uops which data sources were HitM responses from shared L3. ",
627 "CounterHTOff": "0,1,2,3",
628 "Data_LA": "1"
629 },
630 {
631 "PEBS": "1",
632 "EventCode": "0xD2",
633 "Counter": "0,1,2,3",
634 "UMask": "0x8",
635 "Errata": "HSD74, HSD29, HSD25, HSM26, HSM30",
636 "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_NONE",
637 "SampleAfterValue": "100003",
638 "BriefDescription": "Retired load uops which data sources were hits in L3 without snoops required.",
639 "CounterHTOff": "0,1,2,3",
640 "Data_LA": "1"
641 },
642 {
643 "PEBS": "1",
644 "PublicDescription": "This event counts retired load uops where the data came from local DRAM. This does not include hardware prefetches. This is a precise event.",
645 "EventCode": "0xD3",
646 "Counter": "0,1,2,3",
647 "UMask": "0x1",
648 "Errata": "HSD74, HSD29, HSD25, HSM30",
649 "EventName": "MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM",
650 "SampleAfterValue": "100003",
651 "CounterHTOff": "0,1,2,3",
652 "Data_LA": "1"
653 },
654 {
655 "PublicDescription": "Demand data read requests that access L2 cache.",
656 "EventCode": "0xf0",
657 "Counter": "0,1,2,3",
658 "UMask": "0x1",
659 "EventName": "L2_TRANS.DEMAND_DATA_RD",
660 "SampleAfterValue": "200003",
661 "BriefDescription": "Demand Data Read requests that access L2 cache",
662 "CounterHTOff": "0,1,2,3,4,5,6,7"
663 },
664 {
665 "PublicDescription": "RFO requests that access L2 cache.",
666 "EventCode": "0xf0",
667 "Counter": "0,1,2,3",
668 "UMask": "0x2",
669 "EventName": "L2_TRANS.RFO",
670 "SampleAfterValue": "200003",
671 "BriefDescription": "RFO requests that access L2 cache",
672 "CounterHTOff": "0,1,2,3,4,5,6,7"
673 },
674 {
675 "PublicDescription": "L2 cache accesses when fetching instructions.",
676 "EventCode": "0xf0",
677 "Counter": "0,1,2,3",
678 "UMask": "0x4",
679 "EventName": "L2_TRANS.CODE_RD",
680 "SampleAfterValue": "200003",
681 "BriefDescription": "L2 cache accesses when fetching instructions",
682 "CounterHTOff": "0,1,2,3,4,5,6,7"
683 },
684 {
685 "PublicDescription": "Any MLC or L3 HW prefetch accessing L2, including rejects.",
686 "EventCode": "0xf0",
687 "Counter": "0,1,2,3",
688 "UMask": "0x8",
689 "EventName": "L2_TRANS.ALL_PF",
690 "SampleAfterValue": "200003",
691 "BriefDescription": "L2 or L3 HW prefetches that access L2 cache",
692 "CounterHTOff": "0,1,2,3,4,5,6,7"
693 },
694 {
695 "PublicDescription": "L1D writebacks that access L2 cache.",
696 "EventCode": "0xf0",
697 "Counter": "0,1,2,3",
698 "UMask": "0x10",
699 "EventName": "L2_TRANS.L1D_WB",
700 "SampleAfterValue": "200003",
701 "BriefDescription": "L1D writebacks that access L2 cache",
702 "CounterHTOff": "0,1,2,3,4,5,6,7"
703 },
704 {
705 "PublicDescription": "L2 fill requests that access L2 cache.",
706 "EventCode": "0xf0",
707 "Counter": "0,1,2,3",
708 "UMask": "0x20",
709 "EventName": "L2_TRANS.L2_FILL",
710 "SampleAfterValue": "200003",
711 "BriefDescription": "L2 fill requests that access L2 cache",
712 "CounterHTOff": "0,1,2,3,4,5,6,7"
713 },
714 {
715 "PublicDescription": "L2 writebacks that access L2 cache.",
716 "EventCode": "0xf0",
717 "Counter": "0,1,2,3",
718 "UMask": "0x40",
719 "EventName": "L2_TRANS.L2_WB",
720 "SampleAfterValue": "200003",
721 "BriefDescription": "L2 writebacks that access L2 cache",
722 "CounterHTOff": "0,1,2,3,4,5,6,7"
723 },
724 {
725 "PublicDescription": "Transactions accessing L2 pipe.",
726 "EventCode": "0xf0",
727 "Counter": "0,1,2,3",
728 "UMask": "0x80",
729 "EventName": "L2_TRANS.ALL_REQUESTS",
730 "SampleAfterValue": "200003",
731 "BriefDescription": "Transactions accessing L2 pipe",
732 "CounterHTOff": "0,1,2,3,4,5,6,7"
733 },
734 {
735 "PublicDescription": "L2 cache lines in I state filling L2.",
736 "EventCode": "0xF1",
737 "Counter": "0,1,2,3",
738 "UMask": "0x1",
739 "EventName": "L2_LINES_IN.I",
740 "SampleAfterValue": "100003",
741 "BriefDescription": "L2 cache lines in I state filling L2",
742 "CounterHTOff": "0,1,2,3,4,5,6,7"
743 },
744 {
745 "PublicDescription": "L2 cache lines in S state filling L2.",
746 "EventCode": "0xF1",
747 "Counter": "0,1,2,3",
748 "UMask": "0x2",
749 "EventName": "L2_LINES_IN.S",
750 "SampleAfterValue": "100003",
751 "BriefDescription": "L2 cache lines in S state filling L2",
752 "CounterHTOff": "0,1,2,3,4,5,6,7"
753 },
754 {
755 "PublicDescription": "L2 cache lines in E state filling L2.",
756 "EventCode": "0xF1",
757 "Counter": "0,1,2,3",
758 "UMask": "0x4",
759 "EventName": "L2_LINES_IN.E",
760 "SampleAfterValue": "100003",
761 "BriefDescription": "L2 cache lines in E state filling L2",
762 "CounterHTOff": "0,1,2,3,4,5,6,7"
763 },
764 {
765 "PublicDescription": "This event counts the number of L2 cache lines brought into the L2 cache. Lines are filled into the L2 cache when there was an L2 miss.",
766 "EventCode": "0xF1",
767 "Counter": "0,1,2,3",
768 "UMask": "0x7",
769 "EventName": "L2_LINES_IN.ALL",
770 "SampleAfterValue": "100003",
771 "BriefDescription": "L2 cache lines filling L2",
772 "CounterHTOff": "0,1,2,3,4,5,6,7"
773 },
774 {
775 "PublicDescription": "Clean L2 cache lines evicted by demand.",
776 "EventCode": "0xF2",
777 "Counter": "0,1,2,3",
778 "UMask": "0x5",
779 "EventName": "L2_LINES_OUT.DEMAND_CLEAN",
780 "SampleAfterValue": "100003",
781 "BriefDescription": "Clean L2 cache lines evicted by demand",
782 "CounterHTOff": "0,1,2,3,4,5,6,7"
783 },
784 {
785 "PublicDescription": "Dirty L2 cache lines evicted by demand.",
786 "EventCode": "0xF2",
787 "Counter": "0,1,2,3",
788 "UMask": "0x6",
789 "EventName": "L2_LINES_OUT.DEMAND_DIRTY",
790 "SampleAfterValue": "100003",
791 "BriefDescription": "Dirty L2 cache lines evicted by demand",
792 "CounterHTOff": "0,1,2,3,4,5,6,7"
793 },
794 {
795 "PublicDescription": "",
796 "EventCode": "0xf4",
797 "Counter": "0,1,2,3",
798 "UMask": "0x10",
799 "EventName": "SQ_MISC.SPLIT_LOCK",
800 "SampleAfterValue": "100003",
801 "BriefDescription": "Split locks in SQ",
802 "CounterHTOff": "0,1,2,3,4,5,6,7"
803 },
804 {
805 "PublicDescription": "Counts all requests that hit in the L3 Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
806 "EventCode": "0xB7, 0xBB",
807 "MSRValue": "0x3f803c8fff",
808 "Counter": "0,1,2,3",
809 "UMask": "0x1",
810 "EventName": "OFFCORE_RESPONSE.ALL_REQUESTS.L3_HIT.ANY_RESPONSE",
811 "MSRIndex": "0x1a6,0x1a7",
812 "SampleAfterValue": "100003",
813 "BriefDescription": "Counts all requests that hit in the L3",
814 "Offcore": "1",
815 "CounterHTOff": "0,1,2,3"
816 },
817 {
818 "PublicDescription": "Counts all data/code/rfo reads (demand & prefetch) that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
819 "EventCode": "0xB7, 0xBB",
820 "MSRValue": "0x10003c07f7",
821 "Counter": "0,1,2,3",
822 "UMask": "0x1",
823 "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT.HITM_OTHER_CORE",
824 "MSRIndex": "0x1a6,0x1a7",
825 "SampleAfterValue": "100003",
826 "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
827 "Offcore": "1",
828 "CounterHTOff": "0,1,2,3"
829 },
830 {
831 "PublicDescription": "Counts all data/code/rfo reads (demand & prefetch) that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
832 "EventCode": "0xB7, 0xBB",
833 "MSRValue": "0x04003c07f7",
834 "Counter": "0,1,2,3",
835 "UMask": "0x1",
836 "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT.HIT_OTHER_CORE_NO_FWD",
837 "MSRIndex": "0x1a6,0x1a7",
838 "SampleAfterValue": "100003",
839 "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
840 "Offcore": "1",
841 "CounterHTOff": "0,1,2,3"
842 },
843 {
844 "PublicDescription": "Counts all demand & prefetch code reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
845 "EventCode": "0xB7, 0xBB",
846 "MSRValue": "0x04003c0244",
847 "Counter": "0,1,2,3",
848 "UMask": "0x1",
849 "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD",
850 "MSRIndex": "0x1a6,0x1a7",
851 "SampleAfterValue": "100003",
852 "BriefDescription": "Counts all demand & prefetch code reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
853 "Offcore": "1",
854 "CounterHTOff": "0,1,2,3"
855 },
856 {
857 "PublicDescription": "Counts all demand & prefetch RFOs that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
858 "EventCode": "0xB7, 0xBB",
859 "MSRValue": "0x10003c0122",
860 "Counter": "0,1,2,3",
861 "UMask": "0x1",
862 "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.HITM_OTHER_CORE",
863 "MSRIndex": "0x1a6,0x1a7",
864 "SampleAfterValue": "100003",
865 "BriefDescription": "Counts all demand & prefetch RFOs that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
866 "Offcore": "1",
867 "CounterHTOff": "0,1,2,3"
868 },
869 {
870 "PublicDescription": "Counts all demand & prefetch RFOs that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
871 "EventCode": "0xB7, 0xBB",
872 "MSRValue": "0x04003c0122",
873 "Counter": "0,1,2,3",
874 "UMask": "0x1",
875 "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD",
876 "MSRIndex": "0x1a6,0x1a7",
877 "SampleAfterValue": "100003",
878 "BriefDescription": "Counts all demand & prefetch RFOs that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
879 "Offcore": "1",
880 "CounterHTOff": "0,1,2,3"
881 },
882 {
883 "PublicDescription": "Counts all demand & prefetch data reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
884 "EventCode": "0xB7, 0xBB",
885 "MSRValue": "0x10003c0091",
886 "Counter": "0,1,2,3",
887 "UMask": "0x1",
888 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.HITM_OTHER_CORE",
889 "MSRIndex": "0x1a6,0x1a7",
890 "SampleAfterValue": "100003",
891 "BriefDescription": "Counts all demand & prefetch data reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
892 "Offcore": "1",
893 "CounterHTOff": "0,1,2,3"
894 },
895 {
896 "PublicDescription": "Counts all demand & prefetch data reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
897 "EventCode": "0xB7, 0xBB",
898 "MSRValue": "0x04003c0091",
899 "Counter": "0,1,2,3",
900 "UMask": "0x1",
901 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD",
902 "MSRIndex": "0x1a6,0x1a7",
903 "SampleAfterValue": "100003",
904 "BriefDescription": "Counts all demand & prefetch data reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
905 "Offcore": "1",
906 "CounterHTOff": "0,1,2,3"
907 },
908 {
909 "PublicDescription": "Counts prefetch (that bring data to LLC only) code reads that hit in the L3 Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
910 "EventCode": "0xB7, 0xBB",
911 "MSRValue": "0x3f803c0200",
912 "Counter": "0,1,2,3",
913 "UMask": "0x1",
914 "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_HIT.ANY_RESPONSE",
915 "MSRIndex": "0x1a6,0x1a7",
916 "SampleAfterValue": "100003",
917 "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads that hit in the L3",
918 "Offcore": "1",
919 "CounterHTOff": "0,1,2,3"
920 },
921 {
922 "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs that hit in the L3 Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
923 "EventCode": "0xB7, 0xBB",
924 "MSRValue": "0x3f803c0100",
925 "Counter": "0,1,2,3",
926 "UMask": "0x1",
927 "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.ANY_RESPONSE",
928 "MSRIndex": "0x1a6,0x1a7",
929 "SampleAfterValue": "100003",
930 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that hit in the L3",
931 "Offcore": "1",
932 "CounterHTOff": "0,1,2,3"
933 },
934 {
935 "PublicDescription": "Counts all prefetch (that bring data to LLC only) data reads that hit in the L3 Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
936 "EventCode": "0xB7, 0xBB",
937 "MSRValue": "0x3f803c0080",
938 "Counter": "0,1,2,3",
939 "UMask": "0x1",
940 "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.ANY_RESPONSE",
941 "MSRIndex": "0x1a6,0x1a7",
942 "SampleAfterValue": "100003",
943 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that hit in the L3",
944 "Offcore": "1",
945 "CounterHTOff": "0,1,2,3"
946 },
947 {
948 "PublicDescription": "Counts all prefetch (that bring data to LLC only) code reads that hit in the L3 Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
949 "EventCode": "0xB7, 0xBB",
950 "MSRValue": "0x3f803c0040",
951 "Counter": "0,1,2,3",
952 "UMask": "0x1",
953 "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_HIT.ANY_RESPONSE",
954 "MSRIndex": "0x1a6,0x1a7",
955 "SampleAfterValue": "100003",
956 "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads that hit in the L3",
957 "Offcore": "1",
958 "CounterHTOff": "0,1,2,3"
959 },
960 {
961 "PublicDescription": "Counts all prefetch (that bring data to L2) RFOs that hit in the L3 Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
962 "EventCode": "0xB7, 0xBB",
963 "MSRValue": "0x3f803c0020",
964 "Counter": "0,1,2,3",
965 "UMask": "0x1",
966 "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.ANY_RESPONSE",
967 "MSRIndex": "0x1a6,0x1a7",
968 "SampleAfterValue": "100003",
969 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that hit in the L3",
970 "Offcore": "1",
971 "CounterHTOff": "0,1,2,3"
972 },
973 {
974 "PublicDescription": "Counts prefetch (that bring data to L2) data reads that hit in the L3 Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
975 "EventCode": "0xB7, 0xBB",
976 "MSRValue": "0x3f803c0010",
977 "Counter": "0,1,2,3",
978 "UMask": "0x1",
979 "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT.ANY_RESPONSE",
980 "MSRIndex": "0x1a6,0x1a7",
981 "SampleAfterValue": "100003",
982 "BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the L3",
983 "Offcore": "1",
984 "CounterHTOff": "0,1,2,3"
985 },
986 {
987 "PublicDescription": "Counts all demand code reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
988 "EventCode": "0xB7, 0xBB",
989 "MSRValue": "0x10003c0004",
990 "Counter": "0,1,2,3",
991 "UMask": "0x1",
992 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.HITM_OTHER_CORE",
993 "MSRIndex": "0x1a6,0x1a7",
994 "SampleAfterValue": "100003",
995 "BriefDescription": "Counts all demand code reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
996 "Offcore": "1",
997 "CounterHTOff": "0,1,2,3"
998 },
999 {
1000 "PublicDescription": "Counts all demand code reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
1001 "EventCode": "0xB7, 0xBB",
1002 "MSRValue": "0x04003c0004",
1003 "Counter": "0,1,2,3",
1004 "UMask": "0x1",
1005 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD",
1006 "MSRIndex": "0x1a6,0x1a7",
1007 "SampleAfterValue": "100003",
1008 "BriefDescription": "Counts all demand code reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
1009 "Offcore": "1",
1010 "CounterHTOff": "0,1,2,3"
1011 },
1012 {
1013 "PublicDescription": "Counts all demand data writes (RFOs) that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
1014 "EventCode": "0xB7, 0xBB",
1015 "MSRValue": "0x10003c0002",
1016 "Counter": "0,1,2,3",
1017 "UMask": "0x1",
1018 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.HITM_OTHER_CORE",
1019 "MSRIndex": "0x1a6,0x1a7",
1020 "SampleAfterValue": "100003",
1021 "BriefDescription": "Counts all demand data writes (RFOs) that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
1022 "Offcore": "1",
1023 "CounterHTOff": "0,1,2,3"
1024 },
1025 {
1026 "PublicDescription": "Counts all demand data writes (RFOs) that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
1027 "EventCode": "0xB7, 0xBB",
1028 "MSRValue": "0x04003c0002",
1029 "Counter": "0,1,2,3",
1030 "UMask": "0x1",
1031 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD",
1032 "MSRIndex": "0x1a6,0x1a7",
1033 "SampleAfterValue": "100003",
1034 "BriefDescription": "Counts all demand data writes (RFOs) that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
1035 "Offcore": "1",
1036 "CounterHTOff": "0,1,2,3"
1037 },
1038 {
1039 "PublicDescription": "Counts demand data reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
1040 "EventCode": "0xB7, 0xBB",
1041 "MSRValue": "0x10003c0001",
1042 "Counter": "0,1,2,3",
1043 "UMask": "0x1",
1044 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE",
1045 "MSRIndex": "0x1a6,0x1a7",
1046 "SampleAfterValue": "100003",
1047 "BriefDescription": "Counts demand data reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
1048 "Offcore": "1",
1049 "CounterHTOff": "0,1,2,3"
1050 },
1051 {
1052 "PublicDescription": "Counts demand data reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
1053 "EventCode": "0xB7, 0xBB",
1054 "MSRValue": "0x04003c0001",
1055 "Counter": "0,1,2,3",
1056 "UMask": "0x1",
1057 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD",
1058 "MSRIndex": "0x1a6,0x1a7",
1059 "SampleAfterValue": "100003",
1060 "BriefDescription": "Counts demand data reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
1061 "Offcore": "1",
1062 "CounterHTOff": "0,1,2,3"
1063 }
1064 ]