| blob | 168df552b1a82d339b559b746f5b9c63735a09d3 |
1 [
2 {
3 "EventCode": "0x08",
4 "UMask": "0x1",
5 "BriefDescription": "Load misses in all DTLB levels that cause page walks",
6 "Counter": "0,1,2,3",
7 "EventName": "DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK",
8 "PublicDescription": "Misses in all TLB levels that cause a page walk of any page size.",
9 "SampleAfterValue": "100003",
10 "CounterHTOff": "0,1,2,3,4,5,6,7"
11 },
12 {
13 "EventCode": "0x08",
14 "UMask": "0x2",
15 "BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (4K).",
16 "Counter": "0,1,2,3",
17 "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K",
18 "PublicDescription": "Completed page walks due to demand load misses that caused 4K page walks in any TLB levels.",
19 "SampleAfterValue": "2000003",
20 "CounterHTOff": "0,1,2,3,4,5,6,7"
21 },
22 {
23 "EventCode": "0x08",
24 "UMask": "0x4",
25 "BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (2M/4M).",
26 "Counter": "0,1,2,3",
27 "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M",
28 "PublicDescription": "Completed page walks due to demand load misses that caused 2M/4M page walks in any TLB levels.",
29 "SampleAfterValue": "2000003",
30 "CounterHTOff": "0,1,2,3,4,5,6,7"
31 },
32 {
33 "EventCode": "0x08",
34 "UMask": "0x8",
35 "BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (1G)",
36 "Counter": "0,1,2,3",
37 "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_1G",
38 "SampleAfterValue": "2000003",
39 "CounterHTOff": "0,1,2,3,4,5,6,7"
40 },
41 {
42 "EventCode": "0x08",
43 "UMask": "0xe",
44 "BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes of any page size.",
45 "Counter": "0,1,2,3",
46 "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED",
47 "PublicDescription": "Completed page walks in any TLB of any page size due to demand load misses.",
48 "SampleAfterValue": "100003",
49 "CounterHTOff": "0,1,2,3,4,5,6,7"
50 },
51 {
52 "EventCode": "0x08",
53 "UMask": "0x10",
54 "BriefDescription": "Cycles when PMH is busy with page walks",
55 "Counter": "0,1,2,3",
56 "EventName": "DTLB_LOAD_MISSES.WALK_DURATION",
57 "PublicDescription": "This event counts cycles when the page miss handler (PMH) is servicing page walks caused by DTLB load misses.",
58 "SampleAfterValue": "2000003",
59 "CounterHTOff": "0,1,2,3,4,5,6,7"
60 },
61 {
62 "EventCode": "0x08",
63 "UMask": "0x20",
64 "BriefDescription": "Load misses that miss the DTLB and hit the STLB (4K)",
65 "Counter": "0,1,2,3",
66 "EventName": "DTLB_LOAD_MISSES.STLB_HIT_4K",
67 "PublicDescription": "This event counts load operations from a 4K page that miss the first DTLB level but hit the second and do not cause page walks.",
68 "SampleAfterValue": "2000003",
69 "CounterHTOff": "0,1,2,3,4,5,6,7"
70 },
71 {
72 "EventCode": "0x08",
73 "UMask": "0x40",
74 "BriefDescription": "Load misses that miss the DTLB and hit the STLB (2M)",
75 "Counter": "0,1,2,3",
76 "EventName": "DTLB_LOAD_MISSES.STLB_HIT_2M",
77 "PublicDescription": "This event counts load operations from a 2M page that miss the first DTLB level but hit the second and do not cause page walks.",
78 "SampleAfterValue": "2000003",
79 "CounterHTOff": "0,1,2,3,4,5,6,7"
80 },
81 {
82 "EventCode": "0x08",
83 "UMask": "0x60",
84 "BriefDescription": "Load operations that miss the first DTLB level but hit the second and do not cause page walks",
85 "Counter": "0,1,2,3",
86 "EventName": "DTLB_LOAD_MISSES.STLB_HIT",
87 "PublicDescription": "Number of cache load STLB hits. No page walk.",
88 "SampleAfterValue": "2000003",
89 "CounterHTOff": "0,1,2,3,4,5,6,7"
90 },
91 {
92 "EventCode": "0x08",
93 "UMask": "0x80",
94 "BriefDescription": "DTLB demand load misses with low part of linear-to-physical address translation missed",
95 "Counter": "0,1,2,3",
96 "EventName": "DTLB_LOAD_MISSES.PDE_CACHE_MISS",
97 "PublicDescription": "DTLB demand load misses with low part of linear-to-physical address translation missed.",
98 "SampleAfterValue": "100003",
99 "CounterHTOff": "0,1,2,3,4,5,6,7"
100 },
101 {
102 "EventCode": "0x49",
103 "UMask": "0x1",
104 "BriefDescription": "Store misses in all DTLB levels that cause page walks",
105 "Counter": "0,1,2,3",
106 "EventName": "DTLB_STORE_MISSES.MISS_CAUSES_A_WALK",
107 "PublicDescription": "Miss in all TLB levels causes a page walk of any page size (4K/2M/4M/1G).",
108 "SampleAfterValue": "100003",
109 "CounterHTOff": "0,1,2,3,4,5,6,7"
110 },
111 {
112 "EventCode": "0x49",
113 "UMask": "0x2",
114 "BriefDescription": "Store miss in all TLB levels causes a page walk that completes. (4K)",
115 "Counter": "0,1,2,3",
116 "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K",
117 "PublicDescription": "Completed page walks due to store misses in one or more TLB levels of 4K page structure.",
118 "SampleAfterValue": "100003",
119 "CounterHTOff": "0,1,2,3,4,5,6,7"
120 },
121 {
122 "EventCode": "0x49",
123 "UMask": "0x4",
124 "BriefDescription": "Store misses in all DTLB levels that cause completed page walks (2M/4M)",
125 "Counter": "0,1,2,3",
126 "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M",
127 "PublicDescription": "Completed page walks due to store misses in one or more TLB levels of 2M/4M page structure.",
128 "SampleAfterValue": "100003",
129 "CounterHTOff": "0,1,2,3,4,5,6,7"
130 },
131 {
132 "EventCode": "0x49",
133 "UMask": "0x8",
134 "BriefDescription": "Store misses in all DTLB levels that cause completed page walks. (1G)",
135 "Counter": "0,1,2,3",
136 "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_1G",
137 "SampleAfterValue": "100003",
138 "CounterHTOff": "0,1,2,3,4,5,6,7"
139 },
140 {
141 "EventCode": "0x49",
142 "UMask": "0xe",
143 "BriefDescription": "Store misses in all DTLB levels that cause completed page walks",
144 "Counter": "0,1,2,3",
145 "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED",
146 "PublicDescription": "Completed page walks due to store miss in any TLB levels of any page size (4K/2M/4M/1G).",
147 "SampleAfterValue": "100003",
148 "CounterHTOff": "0,1,2,3,4,5,6,7"
149 },
150 {
151 "EventCode": "0x49",
152 "UMask": "0x10",
153 "BriefDescription": "Cycles when PMH is busy with page walks",
154 "Counter": "0,1,2,3",
155 "EventName": "DTLB_STORE_MISSES.WALK_DURATION",
156 "PublicDescription": "This event counts cycles when the page miss handler (PMH) is servicing page walks caused by DTLB store misses.",
157 "SampleAfterValue": "100003",
158 "CounterHTOff": "0,1,2,3,4,5,6,7"
159 },
160 {
161 "EventCode": "0x49",
162 "UMask": "0x20",
163 "BriefDescription": "Store misses that miss the DTLB and hit the STLB (4K)",
164 "Counter": "0,1,2,3",
165 "EventName": "DTLB_STORE_MISSES.STLB_HIT_4K",
166 "PublicDescription": "This event counts store operations from a 4K page that miss the first DTLB level but hit the second and do not cause page walks.",
167 "SampleAfterValue": "100003",
168 "CounterHTOff": "0,1,2,3,4,5,6,7"
169 },
170 {
171 "EventCode": "0x49",
172 "UMask": "0x40",
173 "BriefDescription": "Store misses that miss the DTLB and hit the STLB (2M)",
174 "Counter": "0,1,2,3",
175 "EventName": "DTLB_STORE_MISSES.STLB_HIT_2M",
176 "PublicDescription": "This event counts store operations from a 2M page that miss the first DTLB level but hit the second and do not cause page walks.",
177 "SampleAfterValue": "100003",
178 "CounterHTOff": "0,1,2,3,4,5,6,7"
179 },
180 {
181 "EventCode": "0x49",
182 "UMask": "0x60",
183 "BriefDescription": "Store operations that miss the first TLB level but hit the second and do not cause page walks",
184 "Counter": "0,1,2,3",
185 "EventName": "DTLB_STORE_MISSES.STLB_HIT",
186 "PublicDescription": "Store operations that miss the first TLB level but hit the second and do not cause page walks.",
187 "SampleAfterValue": "100003",
188 "CounterHTOff": "0,1,2,3,4,5,6,7"
189 },
190 {
191 "EventCode": "0x49",
192 "UMask": "0x80",
193 "BriefDescription": "DTLB store misses with low part of linear-to-physical address translation missed",
194 "Counter": "0,1,2,3",
195 "EventName": "DTLB_STORE_MISSES.PDE_CACHE_MISS",
196 "PublicDescription": "DTLB store misses with low part of linear-to-physical address translation missed.",
197 "SampleAfterValue": "100003",
198 "CounterHTOff": "0,1,2,3,4,5,6,7"
199 },
200 {
201 "EventCode": "0x4f",
202 "UMask": "0x10",
203 "BriefDescription": "Cycle count for an Extended Page table walk.",
204 "Counter": "0,1,2,3",
205 "EventName": "EPT.WALK_CYCLES",
206 "SampleAfterValue": "2000003",
207 "CounterHTOff": "0,1,2,3,4,5,6,7"
208 },
209 {
210 "EventCode": "0x85",
211 "UMask": "0x1",
212 "BriefDescription": "Misses at all ITLB levels that cause page walks",
213 "Counter": "0,1,2,3",
214 "EventName": "ITLB_MISSES.MISS_CAUSES_A_WALK",
215 "PublicDescription": "Misses in ITLB that causes a page walk of any page size.",
216 "SampleAfterValue": "100003",
217 "CounterHTOff": "0,1,2,3,4,5,6,7"
218 },
219 {
220 "EventCode": "0x85",
221 "UMask": "0x2",
222 "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (4K)",
223 "Counter": "0,1,2,3",
224 "EventName": "ITLB_MISSES.WALK_COMPLETED_4K",
225 "PublicDescription": "Completed page walks due to misses in ITLB 4K page entries.",
226 "SampleAfterValue": "100003",
227 "CounterHTOff": "0,1,2,3,4,5,6,7"
228 },
229 {
230 "EventCode": "0x85",
231 "UMask": "0x4",
232 "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (2M/4M)",
233 "Counter": "0,1,2,3",
234 "EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M",
235 "PublicDescription": "Completed page walks due to misses in ITLB 2M/4M page entries.",
236 "SampleAfterValue": "100003",
237 "CounterHTOff": "0,1,2,3,4,5,6,7"
238 },
239 {
240 "EventCode": "0x85",
241 "UMask": "0x8",
242 "BriefDescription": "Store miss in all TLB levels causes a page walk that completes. (1G)",
243 "Counter": "0,1,2,3",
244 "EventName": "ITLB_MISSES.WALK_COMPLETED_1G",
245 "SampleAfterValue": "100003",
246 "CounterHTOff": "0,1,2,3,4,5,6,7"
247 },
248 {
249 "EventCode": "0x85",
250 "UMask": "0xe",
251 "BriefDescription": "Misses in all ITLB levels that cause completed page walks",
252 "Counter": "0,1,2,3",
253 "EventName": "ITLB_MISSES.WALK_COMPLETED",
254 "PublicDescription": "Completed page walks in ITLB of any page size.",
255 "SampleAfterValue": "100003",
256 "CounterHTOff": "0,1,2,3,4,5,6,7"
257 },
258 {
259 "EventCode": "0x85",
260 "UMask": "0x10",
261 "BriefDescription": "Cycles when PMH is busy with page walks",
262 "Counter": "0,1,2,3",
263 "EventName": "ITLB_MISSES.WALK_DURATION",
264 "PublicDescription": "This event counts cycles when the page miss handler (PMH) is servicing page walks caused by ITLB misses.",
265 "SampleAfterValue": "100003",
266 "CounterHTOff": "0,1,2,3,4,5,6,7"
267 },
268 {
269 "EventCode": "0x85",
270 "UMask": "0x20",
271 "BriefDescription": "Core misses that miss the DTLB and hit the STLB (4K)",
272 "Counter": "0,1,2,3",
273 "EventName": "ITLB_MISSES.STLB_HIT_4K",
274 "PublicDescription": "ITLB misses that hit STLB (4K).",
275 "SampleAfterValue": "100003",
276 "CounterHTOff": "0,1,2,3,4,5,6,7"
277 },
278 {
279 "EventCode": "0x85",
280 "UMask": "0x40",
281 "BriefDescription": "Code misses that miss the DTLB and hit the STLB (2M)",
282 "Counter": "0,1,2,3",
283 "EventName": "ITLB_MISSES.STLB_HIT_2M",
284 "PublicDescription": "ITLB misses that hit STLB (2M).",
285 "SampleAfterValue": "100003",
286 "CounterHTOff": "0,1,2,3,4,5,6,7"
287 },
288 {
289 "EventCode": "0x85",
290 "UMask": "0x60",
291 "BriefDescription": "Operations that miss the first ITLB level but hit the second and do not cause any page walks",
292 "Counter": "0,1,2,3",
293 "EventName": "ITLB_MISSES.STLB_HIT",
294 "PublicDescription": "ITLB misses that hit STLB. No page walk.",
295 "SampleAfterValue": "100003",
296 "CounterHTOff": "0,1,2,3,4,5,6,7"
297 },
298 {
299 "EventCode": "0xae",
300 "UMask": "0x1",
301 "BriefDescription": "Flushing of the Instruction TLB (ITLB) pages, includes 4k/2M/4M pages.",
302 "Counter": "0,1,2,3",
303 "EventName": "ITLB.ITLB_FLUSH",
304 "PublicDescription": "Counts the number of ITLB flushes, includes 4k/2M/4M pages.",
305 "SampleAfterValue": "100003",
306 "CounterHTOff": "0,1,2,3,4,5,6,7"
307 },
308 {
309 "EventCode": "0xBC",
310 "UMask": "0x11",
311 "BriefDescription": "Number of DTLB page walker hits in the L1+FB",
312 "Counter": "0,1,2,3",
313 "EventName": "PAGE_WALKER_LOADS.DTLB_L1",
314 "PublicDescription": "Number of DTLB page walker loads that hit in the L1+FB.",
315 "SampleAfterValue": "2000003",
316 "CounterHTOff": "0,1,2,3"
317 },
318 {
319 "EventCode": "0xBC",
320 "UMask": "0x12",
321 "BriefDescription": "Number of DTLB page walker hits in the L2",
322 "Counter": "0,1,2,3",
323 "EventName": "PAGE_WALKER_LOADS.DTLB_L2",
324 "PublicDescription": "Number of DTLB page walker loads that hit in the L2.",
325 "SampleAfterValue": "2000003",
326 "CounterHTOff": "0,1,2,3"
327 },
328 {
329 "EventCode": "0xBC",
330 "UMask": "0x14",
331 "BriefDescription": "Number of DTLB page walker hits in the L3 + XSNP",
332 "Counter": "0,1,2,3",
333 "EventName": "PAGE_WALKER_LOADS.DTLB_L3",
334 "Errata": "HSD25",
335 "PublicDescription": "Number of DTLB page walker loads that hit in the L3.",
336 "SampleAfterValue": "2000003",
337 "CounterHTOff": "0,1,2,3"
338 },
339 {
340 "EventCode": "0xBC",
341 "UMask": "0x18",
342 "BriefDescription": "Number of DTLB page walker hits in Memory",
343 "Counter": "0,1,2,3",
344 "EventName": "PAGE_WALKER_LOADS.DTLB_MEMORY",
345 "Errata": "HSD25",
346 "PublicDescription": "Number of DTLB page walker loads from memory.",
347 "SampleAfterValue": "2000003",
348 "CounterHTOff": "0,1,2,3"
349 },
350 {
351 "EventCode": "0xBC",
352 "UMask": "0x21",
353 "BriefDescription": "Number of ITLB page walker hits in the L1+FB",
354 "Counter": "0,1,2,3",
355 "EventName": "PAGE_WALKER_LOADS.ITLB_L1",
356 "PublicDescription": "Number of ITLB page walker loads that hit in the L1+FB.",
357 "SampleAfterValue": "2000003",
358 "CounterHTOff": "0,1,2,3"
359 },
360 {
361 "EventCode": "0xBC",
362 "UMask": "0x22",
363 "BriefDescription": "Number of ITLB page walker hits in the L2",
364 "Counter": "0,1,2,3",
365 "EventName": "PAGE_WALKER_LOADS.ITLB_L2",
366 "PublicDescription": "Number of ITLB page walker loads that hit in the L2.",
367 "SampleAfterValue": "2000003",
368 "CounterHTOff": "0,1,2,3"
369 },
370 {
371 "EventCode": "0xBC",
372 "UMask": "0x24",
373 "BriefDescription": "Number of ITLB page walker hits in the L3 + XSNP",
374 "Counter": "0,1,2,3",
375 "EventName": "PAGE_WALKER_LOADS.ITLB_L3",
376 "Errata": "HSD25",
377 "PublicDescription": "Number of ITLB page walker loads that hit in the L3.",
378 "SampleAfterValue": "2000003",
379 "CounterHTOff": "0,1,2,3"
380 },
381 {
382 "EventCode": "0xBC",
383 "UMask": "0x28",
384 "BriefDescription": "Number of ITLB page walker hits in Memory",
385 "Counter": "0,1,2,3",
386 "EventName": "PAGE_WALKER_LOADS.ITLB_MEMORY",
387 "Errata": "HSD25",
388 "PublicDescription": "Number of ITLB page walker loads from memory.",
389 "SampleAfterValue": "2000003",
390 "CounterHTOff": "0,1,2,3"
391 },
392 {
393 "EventCode": "0xBC",
394 "UMask": "0x41",
395 "BriefDescription": "Counts the number of Extended Page Table walks from the DTLB that hit in the L1 and FB.",
396 "Counter": "0,1,2,3",
397 "EventName": "PAGE_WALKER_LOADS.EPT_DTLB_L1",
398 "SampleAfterValue": "2000003",
399 "CounterHTOff": "0,1,2,3"
400 },
401 {
402 "EventCode": "0xBC",
403 "UMask": "0x42",
404 "BriefDescription": "Counts the number of Extended Page Table walks from the DTLB that hit in the L2.",
405 "Counter": "0,1,2,3",
406 "EventName": "PAGE_WALKER_LOADS.EPT_DTLB_L2",
407 "SampleAfterValue": "2000003",
408 "CounterHTOff": "0,1,2,3"
409 },
410 {
411 "EventCode": "0xBC",
412 "UMask": "0x44",
413 "BriefDescription": "Counts the number of Extended Page Table walks from the DTLB that hit in the L3.",
414 "Counter": "0,1,2,3",
415 "EventName": "PAGE_WALKER_LOADS.EPT_DTLB_L3",
416 "SampleAfterValue": "2000003",
417 "CounterHTOff": "0,1,2,3"
418 },
419 {
420 "EventCode": "0xBC",
421 "UMask": "0x48",
422 "BriefDescription": "Counts the number of Extended Page Table walks from the DTLB that hit in memory.",
423 "Counter": "0,1,2,3",
424 "EventName": "PAGE_WALKER_LOADS.EPT_DTLB_MEMORY",
425 "SampleAfterValue": "2000003",
426 "CounterHTOff": "0,1,2,3"
427 },
428 {
429 "EventCode": "0xBC",
430 "UMask": "0x81",
431 "BriefDescription": "Counts the number of Extended Page Table walks from the ITLB that hit in the L1 and FB.",
432 "Counter": "0,1,2,3",
433 "EventName": "PAGE_WALKER_LOADS.EPT_ITLB_L1",
434 "SampleAfterValue": "2000003",
435 "CounterHTOff": "0,1,2,3"
436 },
437 {
438 "EventCode": "0xBC",
439 "UMask": "0x82",
440 "BriefDescription": "Counts the number of Extended Page Table walks from the ITLB that hit in the L2.",
441 "Counter": "0,1,2,3",
442 "EventName": "PAGE_WALKER_LOADS.EPT_ITLB_L2",
443 "SampleAfterValue": "2000003",
444 "CounterHTOff": "0,1,2,3"
445 },
446 {
447 "EventCode": "0xBC",
448 "UMask": "0x84",
449 "BriefDescription": "Counts the number of Extended Page Table walks from the ITLB that hit in the L2.",
450 "Counter": "0,1,2,3",
451 "EventName": "PAGE_WALKER_LOADS.EPT_ITLB_L3",
452 "SampleAfterValue": "2000003",
453 "CounterHTOff": "0,1,2,3"
454 },
455 {
456 "EventCode": "0xBC",
457 "UMask": "0x88",
458 "BriefDescription": "Counts the number of Extended Page Table walks from the ITLB that hit in memory.",
459 "Counter": "0,1,2,3",
460 "EventName": "PAGE_WALKER_LOADS.EPT_ITLB_MEMORY",
461 "SampleAfterValue": "2000003",
462 "CounterHTOff": "0,1,2,3"
463 },
464 {
465 "EventCode": "0xBD",
466 "UMask": "0x1",
467 "BriefDescription": "DTLB flush attempts of the thread-specific entries",
468 "Counter": "0,1,2,3",
469 "EventName": "TLB_FLUSH.DTLB_THREAD",
470 "PublicDescription": "DTLB flush attempts of the thread-specific entries.",
471 "SampleAfterValue": "100003",
472 "CounterHTOff": "0,1,2,3,4,5,6,7"
473 },
474 {
475 "EventCode": "0xBD",
476 "UMask": "0x20",
477 "BriefDescription": "STLB flush attempts",
478 "Counter": "0,1,2,3",
479 "EventName": "TLB_FLUSH.STLB_ANY",
480 "PublicDescription": "Count number of STLB flush attempts.",
481 "SampleAfterValue": "100003",
482 "CounterHTOff": "0,1,2,3,4,5,6,7"
483 }
484 ]