tools/perf/pmu-events/arch/x86/ivybridge/other.json

   1 [
   2     {
   3         "PublicDescription": "Unhalted core cycles when the thread is in ring 0.",
   4         "EventCode": "0x5C",
   5         "Counter": "0,1,2,3",
   6         "UMask": "0x1",
   7         "EventName": "CPL_CYCLES.RING0",
   8         "SampleAfterValue": "2000003",
   9         "BriefDescription": "Unhalted core cycles when the thread is in ring 0",
  10         "CounterHTOff": "0,1,2,3,4,5,6,7"
  11     },
  12     {
  13         "PublicDescription": "Number of intervals between processor halts while thread is in ring 0.",
  14         "EventCode": "0x5C",
  15         "Counter": "0,1,2,3",
  16         "UMask": "0x1",
  17         "EdgeDetect": "1",
  18         "EventName": "CPL_CYCLES.RING0_TRANS",
  19         "SampleAfterValue": "100007",
  20         "BriefDescription": "Number of intervals between processor halts while thread is in ring 0",
  21         "CounterMask": "1",
  22         "CounterHTOff": "0,1,2,3,4,5,6,7"
  23     },
  24     {
  25         "PublicDescription": "Unhalted core cycles when the thread is not in ring 0.",
  26         "EventCode": "0x5C",
  27         "Counter": "0,1,2,3",
  28         "UMask": "0x2",
  29         "EventName": "CPL_CYCLES.RING123",
  30         "SampleAfterValue": "2000003",
  31         "BriefDescription": "Unhalted core cycles when thread is in rings 1, 2, or 3",
  32         "CounterHTOff": "0,1,2,3,4,5,6,7"
  33     },
  34     {
  35         "PublicDescription": "Cycles in which the L1D and L2 are locked, due to a UC lock or split lock.",
  36         "EventCode": "0x63",
  37         "Counter": "0,1,2,3",
  38         "UMask": "0x1",
  39         "EventName": "LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION",
  40         "SampleAfterValue": "2000003",
  41         "BriefDescription": "Cycles when L1 and L2 are locked due to UC or split lock",
  42         "CounterHTOff": "0,1,2,3,4,5,6,7"
  43     }
  44 ]