| blob | efaa949ead31ee2037efd88490b6df9c2f95eb12 |
1 [
2 {
3 "PublicDescription": "Counts cycles the IDQ is empty.",
4 "EventCode": "0x79",
5 "Counter": "0,1,2,3",
6 "UMask": "0x2",
7 "EventName": "IDQ.EMPTY",
8 "SampleAfterValue": "2000003",
9 "BriefDescription": "Instruction Decode Queue (IDQ) empty cycles",
10 "CounterHTOff": "0,1,2,3"
11 },
12 {
13 "PublicDescription": "Increment each cycle # of uops delivered to IDQ from MITE path. Set Cmask = 1 to count cycles.",
14 "EventCode": "0x79",
15 "Counter": "0,1,2,3",
16 "UMask": "0x4",
17 "EventName": "IDQ.MITE_UOPS",
18 "SampleAfterValue": "2000003",
19 "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path",
20 "CounterHTOff": "0,1,2,3,4,5,6,7"
21 },
22 {
23 "PublicDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path.",
24 "EventCode": "0x79",
25 "Counter": "0,1,2,3",
26 "UMask": "0x4",
27 "EventName": "IDQ.MITE_CYCLES",
28 "SampleAfterValue": "2000003",
29 "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path",
30 "CounterMask": "1",
31 "CounterHTOff": "0,1,2,3,4,5,6,7"
32 },
33 {
34 "PublicDescription": "Increment each cycle. # of uops delivered to IDQ from DSB path. Set Cmask = 1 to count cycles.",
35 "EventCode": "0x79",
36 "Counter": "0,1,2,3",
37 "UMask": "0x8",
38 "EventName": "IDQ.DSB_UOPS",
39 "SampleAfterValue": "2000003",
40 "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path",
41 "CounterHTOff": "0,1,2,3,4,5,6,7"
42 },
43 {
44 "PublicDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path.",
45 "EventCode": "0x79",
46 "Counter": "0,1,2,3",
47 "UMask": "0x8",
48 "EventName": "IDQ.DSB_CYCLES",
49 "SampleAfterValue": "2000003",
50 "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path",
51 "CounterMask": "1",
52 "CounterHTOff": "0,1,2,3,4,5,6,7"
53 },
54 {
55 "PublicDescription": "Increment each cycle # of uops delivered to IDQ when MS_busy by DSB. Set Cmask = 1 to count cycles. Add Edge=1 to count # of delivery.",
56 "EventCode": "0x79",
57 "Counter": "0,1,2,3",
58 "UMask": "0x10",
59 "EventName": "IDQ.MS_DSB_UOPS",
60 "SampleAfterValue": "2000003",
61 "BriefDescription": "Uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
62 "CounterHTOff": "0,1,2,3,4,5,6,7"
63 },
64 {
65 "PublicDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy.",
66 "EventCode": "0x79",
67 "Counter": "0,1,2,3",
68 "UMask": "0x10",
69 "EventName": "IDQ.MS_DSB_CYCLES",
70 "SampleAfterValue": "2000003",
71 "BriefDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
72 "CounterMask": "1",
73 "CounterHTOff": "0,1,2,3,4,5,6,7"
74 },
75 {
76 "PublicDescription": "Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequenser (MS) is busy.",
77 "EventCode": "0x79",
78 "Counter": "0,1,2,3",
79 "UMask": "0x10",
80 "EdgeDetect": "1",
81 "EventName": "IDQ.MS_DSB_OCCUR",
82 "SampleAfterValue": "2000003",
83 "BriefDescription": "Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequenser (MS) is busy",
84 "CounterMask": "1",
85 "CounterHTOff": "0,1,2,3,4,5,6,7"
86 },
87 {
88 "PublicDescription": "Counts cycles DSB is delivered four uops. Set Cmask = 4.",
89 "EventCode": "0x79",
90 "Counter": "0,1,2,3",
91 "UMask": "0x18",
92 "EventName": "IDQ.ALL_DSB_CYCLES_4_UOPS",
93 "SampleAfterValue": "2000003",
94 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops",
95 "CounterMask": "4",
96 "CounterHTOff": "0,1,2,3,4,5,6,7"
97 },
98 {
99 "PublicDescription": "Counts cycles DSB is delivered at least one uops. Set Cmask = 1.",
100 "EventCode": "0x79",
101 "Counter": "0,1,2,3",
102 "UMask": "0x18",
103 "EventName": "IDQ.ALL_DSB_CYCLES_ANY_UOPS",
104 "SampleAfterValue": "2000003",
105 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop",
106 "CounterMask": "1",
107 "CounterHTOff": "0,1,2,3,4,5,6,7"
108 },
109 {
110 "PublicDescription": "Increment each cycle # of uops delivered to IDQ when MS_busy by MITE. Set Cmask = 1 to count cycles.",
111 "EventCode": "0x79",
112 "Counter": "0,1,2,3",
113 "UMask": "0x20",
114 "EventName": "IDQ.MS_MITE_UOPS",
115 "SampleAfterValue": "2000003",
116 "BriefDescription": "Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
117 "CounterHTOff": "0,1,2,3,4,5,6,7"
118 },
119 {
120 "PublicDescription": "Counts cycles MITE is delivered four uops. Set Cmask = 4.",
121 "EventCode": "0x79",
122 "Counter": "0,1,2,3",
123 "UMask": "0x24",
124 "EventName": "IDQ.ALL_MITE_CYCLES_4_UOPS",
125 "SampleAfterValue": "2000003",
126 "BriefDescription": "Cycles MITE is delivering 4 Uops",
127 "CounterMask": "4",
128 "CounterHTOff": "0,1,2,3,4,5,6,7"
129 },
130 {
131 "PublicDescription": "Counts cycles MITE is delivered at least one uops. Set Cmask = 1.",
132 "EventCode": "0x79",
133 "Counter": "0,1,2,3",
134 "UMask": "0x24",
135 "EventName": "IDQ.ALL_MITE_CYCLES_ANY_UOPS",
136 "SampleAfterValue": "2000003",
137 "BriefDescription": "Cycles MITE is delivering any Uop",
138 "CounterMask": "1",
139 "CounterHTOff": "0,1,2,3,4,5,6,7"
140 },
141 {
142 "PublicDescription": "Increment each cycle # of uops delivered to IDQ from MS by either DSB or MITE. Set Cmask = 1 to count cycles.",
143 "EventCode": "0x79",
144 "Counter": "0,1,2,3",
145 "UMask": "0x30",
146 "EventName": "IDQ.MS_UOPS",
147 "SampleAfterValue": "2000003",
148 "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
149 "CounterHTOff": "0,1,2,3,4,5,6,7"
150 },
151 {
152 "PublicDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy.",
153 "EventCode": "0x79",
154 "Counter": "0,1,2,3",
155 "UMask": "0x30",
156 "EventName": "IDQ.MS_CYCLES",
157 "SampleAfterValue": "2000003",
158 "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
159 "CounterMask": "1",
160 "CounterHTOff": "0,1,2,3,4,5,6,7"
161 },
162 {
163 "PublicDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer.",
164 "EventCode": "0x79",
165 "Counter": "0,1,2,3",
166 "UMask": "0x30",
167 "EdgeDetect": "1",
168 "EventName": "IDQ.MS_SWITCHES",
169 "SampleAfterValue": "2000003",
170 "BriefDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer",
171 "CounterMask": "1",
172 "CounterHTOff": "0,1,2,3,4,5,6,7"
173 },
174 {
175 "PublicDescription": "Number of uops delivered to IDQ from any path.",
176 "EventCode": "0x79",
177 "Counter": "0,1,2,3",
178 "UMask": "0x3c",
179 "EventName": "IDQ.MITE_ALL_UOPS",
180 "SampleAfterValue": "2000003",
181 "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path",
182 "CounterHTOff": "0,1,2,3,4,5,6,7"
183 },
184 {
185 "PublicDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Reads. both cacheable and noncacheable, including UC fetches.",
186 "EventCode": "0x80",
187 "Counter": "0,1,2,3",
188 "UMask": "0x1",
189 "EventName": "ICACHE.HIT",
190 "SampleAfterValue": "2000003",
191 "BriefDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Reads. both cacheable and noncacheable, including UC fetches",
192 "CounterHTOff": "0,1,2,3,4,5,6,7"
193 },
194 {
195 "PublicDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Misses. Includes UC accesses.",
196 "EventCode": "0x80",
197 "Counter": "0,1,2,3",
198 "UMask": "0x2",
199 "EventName": "ICACHE.MISSES",
200 "SampleAfterValue": "200003",
201 "BriefDescription": "Instruction cache, streaming buffer and victim cache misses",
202 "CounterHTOff": "0,1,2,3,4,5,6,7"
203 },
204 {
205 "PublicDescription": "Cycles where a code-fetch stalled due to L1 instruction-cache miss or an iTLB miss.",
206 "EventCode": "0x80",
207 "Counter": "0,1,2,3",
208 "UMask": "0x4",
209 "EventName": "ICACHE.IFETCH_STALL",
210 "SampleAfterValue": "2000003",
211 "BriefDescription": "Cycles where a code-fetch stalled due to L1 instruction-cache miss or an iTLB miss",
212 "CounterHTOff": "0,1,2,3,4,5,6,7"
213 },
214 {
215 "PublicDescription": "Count issue pipeline slots where no uop was delivered from the front end to the back end when there is no back-end stall.",
216 "EventCode": "0x9C",
217 "Counter": "0,1,2,3",
218 "UMask": "0x1",
219 "EventName": "IDQ_UOPS_NOT_DELIVERED.CORE",
220 "SampleAfterValue": "2000003",
221 "BriefDescription": "Uops not delivered to Resource Allocation Table (RAT) per thread when backend of the machine is not stalled",
222 "CounterHTOff": "0,1,2,3"
223 },
224 {
225 "EventCode": "0x9C",
226 "Counter": "0,1,2,3",
227 "UMask": "0x1",
228 "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE",
229 "SampleAfterValue": "2000003",
230 "BriefDescription": "Cycles per thread when 4 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled.",
231 "CounterMask": "4",
232 "CounterHTOff": "0,1,2,3"
233 },
234 {
235 "EventCode": "0x9C",
236 "Counter": "0,1,2,3",
237 "UMask": "0x1",
238 "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_1_UOP_DELIV.CORE",
239 "SampleAfterValue": "2000003",
240 "BriefDescription": "Cycles per thread when 3 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled.",
241 "CounterMask": "3",
242 "CounterHTOff": "0,1,2,3"
243 },
244 {
245 "EventCode": "0x9C",
246 "Counter": "0,1,2,3",
247 "UMask": "0x1",
248 "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_2_UOP_DELIV.CORE",
249 "SampleAfterValue": "2000003",
250 "BriefDescription": "Cycles with less than 2 uops delivered by the front end.",
251 "CounterMask": "2",
252 "CounterHTOff": "0,1,2,3"
253 },
254 {
255 "EventCode": "0x9C",
256 "Counter": "0,1,2,3",
257 "UMask": "0x1",
258 "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_3_UOP_DELIV.CORE",
259 "SampleAfterValue": "2000003",
260 "BriefDescription": "Cycles with less than 3 uops delivered by the front end.",
261 "CounterMask": "1",
262 "CounterHTOff": "0,1,2,3"
263 },
264 {
265 "EventCode": "0x9C",
266 "Invert": "1",
267 "Counter": "0,1,2,3",
268 "UMask": "0x1",
269 "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK",
270 "SampleAfterValue": "2000003",
271 "BriefDescription": "Counts cycles FE delivered 4 uops or Resource Allocation Table (RAT) was stalling FE.",
272 "CounterMask": "1",
273 "CounterHTOff": "0,1,2,3"
274 },
275 {
276 "PublicDescription": "Number of DSB to MITE switches.",
277 "EventCode": "0xAB",
278 "Counter": "0,1,2,3",
279 "UMask": "0x1",
280 "EventName": "DSB2MITE_SWITCHES.COUNT",
281 "SampleAfterValue": "2000003",
282 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches",
283 "CounterHTOff": "0,1,2,3,4,5,6,7"
284 },
285 {
286 "PublicDescription": "Cycles DSB to MITE switches caused delay.",
287 "EventCode": "0xAB",
288 "Counter": "0,1,2,3",
289 "UMask": "0x2",
290 "EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES",
291 "SampleAfterValue": "2000003",
292 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles",
293 "CounterHTOff": "0,1,2,3,4,5,6,7"
294 },
295 {
296 "PublicDescription": "DSB Fill encountered > 3 DSB lines.",
297 "EventCode": "0xAC",
298 "Counter": "0,1,2,3",
299 "UMask": "0x8",
300 "EventName": "DSB_FILL.EXCEED_DSB_LINES",
301 "SampleAfterValue": "2000003",
302 "BriefDescription": "Cycles when Decode Stream Buffer (DSB) fill encounter more than 3 Decode Stream Buffer (DSB) lines",
303 "CounterHTOff": "0,1,2,3,4,5,6,7"
304 }
305 ]