tools/perf/pmu-events/arch/x86/westmereep-sp/cache.json

   1 [
   2     {
   3         "EventCode": "0x63",
   4         "Counter": "0,1",
   5         "UMask": "0x2",
   6         "EventName": "CACHE_LOCK_CYCLES.L1D",
   7         "SampleAfterValue": "2000000",
   8         "BriefDescription": "Cycles L1D locked"
   9     },
  10     {
  11         "EventCode": "0x63",
  12         "Counter": "0,1",
  13         "UMask": "0x1",
  14         "EventName": "CACHE_LOCK_CYCLES.L1D_L2",
  15         "SampleAfterValue": "2000000",
  16         "BriefDescription": "Cycles L1D and L2 locked"
  17     },
  18     {
  19         "EventCode": "0x51",
  20         "Counter": "0,1",
  21         "UMask": "0x4",
  22         "EventName": "L1D.M_EVICT",
  23         "SampleAfterValue": "2000000",
  24         "BriefDescription": "L1D cache lines replaced in M state"
  25     },
  26     {
  27         "EventCode": "0x51",
  28         "Counter": "0,1",
  29         "UMask": "0x2",
  30         "EventName": "L1D.M_REPL",
  31         "SampleAfterValue": "2000000",
  32         "BriefDescription": "L1D cache lines allocated in the M state"
  33     },
  34     {
  35         "EventCode": "0x51",
  36         "Counter": "0,1",
  37         "UMask": "0x8",
  38         "EventName": "L1D.M_SNOOP_EVICT",
  39         "SampleAfterValue": "2000000",
  40         "BriefDescription": "L1D snoop eviction of cache lines in M state"
  41     },
  42     {
  43         "EventCode": "0x51",
  44         "Counter": "0,1",
  45         "UMask": "0x1",
  46         "EventName": "L1D.REPL",
  47         "SampleAfterValue": "2000000",
  48         "BriefDescription": "L1 data cache lines allocated"
  49     },
  50     {
  51         "EventCode": "0x52",
  52         "Counter": "0,1",
  53         "UMask": "0x1",
  54         "EventName": "L1D_CACHE_PREFETCH_LOCK_FB_HIT",
  55         "SampleAfterValue": "2000000",
  56         "BriefDescription": "L1D prefetch load lock accepted in fill buffer"
  57     },
  58     {
  59         "EventCode": "0x4E",
  60         "Counter": "0,1",
  61         "UMask": "0x2",
  62         "EventName": "L1D_PREFETCH.MISS",
  63         "SampleAfterValue": "200000",
  64         "BriefDescription": "L1D hardware prefetch misses"
  65     },
  66     {
  67         "EventCode": "0x4E",
  68         "Counter": "0,1",
  69         "UMask": "0x1",
  70         "EventName": "L1D_PREFETCH.REQUESTS",
  71         "SampleAfterValue": "200000",
  72         "BriefDescription": "L1D hardware prefetch requests"
  73     },
  74     {
  75         "EventCode": "0x4E",
  76         "Counter": "0,1",
  77         "UMask": "0x4",
  78         "EventName": "L1D_PREFETCH.TRIGGERS",
  79         "SampleAfterValue": "200000",
  80         "BriefDescription": "L1D hardware prefetch requests triggered"
  81     },
  82     {
  83         "EventCode": "0x28",
  84         "Counter": "0,1,2,3",
  85         "UMask": "0x4",
  86         "EventName": "L1D_WB_L2.E_STATE",
  87         "SampleAfterValue": "100000",
  88         "BriefDescription": "L1 writebacks to L2 in E state"
  89     },
  90     {
  91         "EventCode": "0x28",
  92         "Counter": "0,1,2,3",
  93         "UMask": "0x1",
  94         "EventName": "L1D_WB_L2.I_STATE",
  95         "SampleAfterValue": "100000",
  96         "BriefDescription": "L1 writebacks to L2 in I state (misses)"
  97     },
  98     {
  99         "EventCode": "0x28",
 100         "Counter": "0,1,2,3",
 101         "UMask": "0x8",
 102         "EventName": "L1D_WB_L2.M_STATE",
 103         "SampleAfterValue": "100000",
 104         "BriefDescription": "L1 writebacks to L2 in M state"
 105     },
 106     {
 107         "EventCode": "0x28",
 108         "Counter": "0,1,2,3",
 109         "UMask": "0xf",
 110         "EventName": "L1D_WB_L2.MESI",
 111         "SampleAfterValue": "100000",
 112         "BriefDescription": "All L1 writebacks to L2"
 113     },
 114     {
 115         "EventCode": "0x28",
 116         "Counter": "0,1,2,3",
 117         "UMask": "0x2",
 118         "EventName": "L1D_WB_L2.S_STATE",
 119         "SampleAfterValue": "100000",
 120         "BriefDescription": "L1 writebacks to L2 in S state"
 121     },
 122     {
 123         "EventCode": "0x26",
 124         "Counter": "0,1,2,3",
 125         "UMask": "0xff",
 126         "EventName": "L2_DATA_RQSTS.ANY",
 127         "SampleAfterValue": "200000",
 128         "BriefDescription": "All L2 data requests"
 129     },
 130     {
 131         "EventCode": "0x26",
 132         "Counter": "0,1,2,3",
 133         "UMask": "0x4",
 134         "EventName": "L2_DATA_RQSTS.DEMAND.E_STATE",
 135         "SampleAfterValue": "200000",
 136         "BriefDescription": "L2 data demand loads in E state"
 137     },
 138     {
 139         "EventCode": "0x26",
 140         "Counter": "0,1,2,3",
 141         "UMask": "0x1",
 142         "EventName": "L2_DATA_RQSTS.DEMAND.I_STATE",
 143         "SampleAfterValue": "200000",
 144         "BriefDescription": "L2 data demand loads in I state (misses)"
 145     },
 146     {
 147         "EventCode": "0x26",
 148         "Counter": "0,1,2,3",
 149         "UMask": "0x8",
 150         "EventName": "L2_DATA_RQSTS.DEMAND.M_STATE",
 151         "SampleAfterValue": "200000",
 152         "BriefDescription": "L2 data demand loads in M state"
 153     },
 154     {
 155         "EventCode": "0x26",
 156         "Counter": "0,1,2,3",
 157         "UMask": "0xf",
 158         "EventName": "L2_DATA_RQSTS.DEMAND.MESI",
 159         "SampleAfterValue": "200000",
 160         "BriefDescription": "L2 data demand requests"
 161     },
 162     {
 163         "EventCode": "0x26",
 164         "Counter": "0,1,2,3",
 165         "UMask": "0x2",
 166         "EventName": "L2_DATA_RQSTS.DEMAND.S_STATE",
 167         "SampleAfterValue": "200000",
 168         "BriefDescription": "L2 data demand loads in S state"
 169     },
 170     {
 171         "EventCode": "0x26",
 172         "Counter": "0,1,2,3",
 173         "UMask": "0x40",
 174         "EventName": "L2_DATA_RQSTS.PREFETCH.E_STATE",
 175         "SampleAfterValue": "200000",
 176         "BriefDescription": "L2 data prefetches in E state"
 177     },
 178     {
 179         "EventCode": "0x26",
 180         "Counter": "0,1,2,3",
 181         "UMask": "0x10",
 182         "EventName": "L2_DATA_RQSTS.PREFETCH.I_STATE",
 183         "SampleAfterValue": "200000",
 184         "BriefDescription": "L2 data prefetches in the I state (misses)"
 185     },
 186     {
 187         "EventCode": "0x26",
 188         "Counter": "0,1,2,3",
 189         "UMask": "0x80",
 190         "EventName": "L2_DATA_RQSTS.PREFETCH.M_STATE",
 191         "SampleAfterValue": "200000",
 192         "BriefDescription": "L2 data prefetches in M state"
 193     },
 194     {
 195         "EventCode": "0x26",
 196         "Counter": "0,1,2,3",
 197         "UMask": "0xf0",
 198         "EventName": "L2_DATA_RQSTS.PREFETCH.MESI",
 199         "SampleAfterValue": "200000",
 200         "BriefDescription": "All L2 data prefetches"
 201     },
 202     {
 203         "EventCode": "0x26",
 204         "Counter": "0,1,2,3",
 205         "UMask": "0x20",
 206         "EventName": "L2_DATA_RQSTS.PREFETCH.S_STATE",
 207         "SampleAfterValue": "200000",
 208         "BriefDescription": "L2 data prefetches in the S state"
 209     },
 210     {
 211         "EventCode": "0xF1",
 212         "Counter": "0,1,2,3",
 213         "UMask": "0x7",
 214         "EventName": "L2_LINES_IN.ANY",
 215         "SampleAfterValue": "100000",
 216         "BriefDescription": "L2 lines alloacated"
 217     },
 218     {
 219         "EventCode": "0xF1",
 220         "Counter": "0,1,2,3",
 221         "UMask": "0x4",
 222         "EventName": "L2_LINES_IN.E_STATE",
 223         "SampleAfterValue": "100000",
 224         "BriefDescription": "L2 lines allocated in the E state"
 225     },
 226     {
 227         "EventCode": "0xF1",
 228         "Counter": "0,1,2,3",
 229         "UMask": "0x2",
 230         "EventName": "L2_LINES_IN.S_STATE",
 231         "SampleAfterValue": "100000",
 232         "BriefDescription": "L2 lines allocated in the S state"
 233     },
 234     {
 235         "EventCode": "0xF2",
 236         "Counter": "0,1,2,3",
 237         "UMask": "0xf",
 238         "EventName": "L2_LINES_OUT.ANY",
 239         "SampleAfterValue": "100000",
 240         "BriefDescription": "L2 lines evicted"
 241     },
 242     {
 243         "EventCode": "0xF2",
 244         "Counter": "0,1,2,3",
 245         "UMask": "0x1",
 246         "EventName": "L2_LINES_OUT.DEMAND_CLEAN",
 247         "SampleAfterValue": "100000",
 248         "BriefDescription": "L2 lines evicted by a demand request"
 249     },
 250     {
 251         "EventCode": "0xF2",
 252         "Counter": "0,1,2,3",
 253         "UMask": "0x2",
 254         "EventName": "L2_LINES_OUT.DEMAND_DIRTY",
 255         "SampleAfterValue": "100000",
 256         "BriefDescription": "L2 modified lines evicted by a demand request"
 257     },
 258     {
 259         "EventCode": "0xF2",
 260         "Counter": "0,1,2,3",
 261         "UMask": "0x4",
 262         "EventName": "L2_LINES_OUT.PREFETCH_CLEAN",
 263         "SampleAfterValue": "100000",
 264         "BriefDescription": "L2 lines evicted by a prefetch request"
 265     },
 266     {
 267         "EventCode": "0xF2",
 268         "Counter": "0,1,2,3",
 269         "UMask": "0x8",
 270         "EventName": "L2_LINES_OUT.PREFETCH_DIRTY",
 271         "SampleAfterValue": "100000",
 272         "BriefDescription": "L2 modified lines evicted by a prefetch request"
 273     },
 274     {
 275         "EventCode": "0x24",
 276         "Counter": "0,1,2,3",
 277         "UMask": "0x10",
 278         "EventName": "L2_RQSTS.IFETCH_HIT",
 279         "SampleAfterValue": "200000",
 280         "BriefDescription": "L2 instruction fetch hits"
 281     },
 282     {
 283         "EventCode": "0x24",
 284         "Counter": "0,1,2,3",
 285         "UMask": "0x20",
 286         "EventName": "L2_RQSTS.IFETCH_MISS",
 287         "SampleAfterValue": "200000",
 288         "BriefDescription": "L2 instruction fetch misses"
 289     },
 290     {
 291         "EventCode": "0x24",
 292         "Counter": "0,1,2,3",
 293         "UMask": "0x30",
 294         "EventName": "L2_RQSTS.IFETCHES",
 295         "SampleAfterValue": "200000",
 296         "BriefDescription": "L2 instruction fetches"
 297     },
 298     {
 299         "EventCode": "0x24",
 300         "Counter": "0,1,2,3",
 301         "UMask": "0x1",
 302         "EventName": "L2_RQSTS.LD_HIT",
 303         "SampleAfterValue": "200000",
 304         "BriefDescription": "L2 load hits"
 305     },
 306     {
 307         "EventCode": "0x24",
 308         "Counter": "0,1,2,3",
 309         "UMask": "0x2",
 310         "EventName": "L2_RQSTS.LD_MISS",
 311         "SampleAfterValue": "200000",
 312         "BriefDescription": "L2 load misses"
 313     },
 314     {
 315         "EventCode": "0x24",
 316         "Counter": "0,1,2,3",
 317         "UMask": "0x3",
 318         "EventName": "L2_RQSTS.LOADS",
 319         "SampleAfterValue": "200000",
 320         "BriefDescription": "L2 requests"
 321     },
 322     {
 323         "EventCode": "0x24",
 324         "Counter": "0,1,2,3",
 325         "UMask": "0xaa",
 326         "EventName": "L2_RQSTS.MISS",
 327         "SampleAfterValue": "200000",
 328         "BriefDescription": "All L2 misses"
 329     },
 330     {
 331         "EventCode": "0x24",
 332         "Counter": "0,1,2,3",
 333         "UMask": "0x40",
 334         "EventName": "L2_RQSTS.PREFETCH_HIT",
 335         "SampleAfterValue": "200000",
 336         "BriefDescription": "L2 prefetch hits"
 337     },
 338     {
 339         "EventCode": "0x24",
 340         "Counter": "0,1,2,3",
 341         "UMask": "0x80",
 342         "EventName": "L2_RQSTS.PREFETCH_MISS",
 343         "SampleAfterValue": "200000",
 344         "BriefDescription": "L2 prefetch misses"
 345     },
 346     {
 347         "EventCode": "0x24",
 348         "Counter": "0,1,2,3",
 349         "UMask": "0xc0",
 350         "EventName": "L2_RQSTS.PREFETCHES",
 351         "SampleAfterValue": "200000",
 352         "BriefDescription": "All L2 prefetches"
 353     },
 354     {
 355         "EventCode": "0x24",
 356         "Counter": "0,1,2,3",
 357         "UMask": "0xff",
 358         "EventName": "L2_RQSTS.REFERENCES",
 359         "SampleAfterValue": "200000",
 360         "BriefDescription": "All L2 requests"
 361     },
 362     {
 363         "EventCode": "0x24",
 364         "Counter": "0,1,2,3",
 365         "UMask": "0x4",
 366         "EventName": "L2_RQSTS.RFO_HIT",
 367         "SampleAfterValue": "200000",
 368         "BriefDescription": "L2 RFO hits"
 369     },
 370     {
 371         "EventCode": "0x24",
 372         "Counter": "0,1,2,3",
 373         "UMask": "0x8",
 374         "EventName": "L2_RQSTS.RFO_MISS",
 375         "SampleAfterValue": "200000",
 376         "BriefDescription": "L2 RFO misses"
 377     },
 378     {
 379         "EventCode": "0x24",
 380         "Counter": "0,1,2,3",
 381         "UMask": "0xc",
 382         "EventName": "L2_RQSTS.RFOS",
 383         "SampleAfterValue": "200000",
 384         "BriefDescription": "L2 RFO requests"
 385     },
 386     {
 387         "EventCode": "0xF0",
 388         "Counter": "0,1,2,3",
 389         "UMask": "0x80",
 390         "EventName": "L2_TRANSACTIONS.ANY",
 391         "SampleAfterValue": "200000",
 392         "BriefDescription": "All L2 transactions"
 393     },
 394     {
 395         "EventCode": "0xF0",
 396         "Counter": "0,1,2,3",
 397         "UMask": "0x20",
 398         "EventName": "L2_TRANSACTIONS.FILL",
 399         "SampleAfterValue": "200000",
 400         "BriefDescription": "L2 fill transactions"
 401     },
 402     {
 403         "EventCode": "0xF0",
 404         "Counter": "0,1,2,3",
 405         "UMask": "0x4",
 406         "EventName": "L2_TRANSACTIONS.IFETCH",
 407         "SampleAfterValue": "200000",
 408         "BriefDescription": "L2 instruction fetch transactions"
 409     },
 410     {
 411         "EventCode": "0xF0",
 412         "Counter": "0,1,2,3",
 413         "UMask": "0x10",
 414         "EventName": "L2_TRANSACTIONS.L1D_WB",
 415         "SampleAfterValue": "200000",
 416         "BriefDescription": "L1D writeback to L2 transactions"
 417     },
 418     {
 419         "EventCode": "0xF0",
 420         "Counter": "0,1,2,3",
 421         "UMask": "0x1",
 422         "EventName": "L2_TRANSACTIONS.LOAD",
 423         "SampleAfterValue": "200000",
 424         "BriefDescription": "L2 Load transactions"
 425     },
 426     {
 427         "EventCode": "0xF0",
 428         "Counter": "0,1,2,3",
 429         "UMask": "0x8",
 430         "EventName": "L2_TRANSACTIONS.PREFETCH",
 431         "SampleAfterValue": "200000",
 432         "BriefDescription": "L2 prefetch transactions"
 433     },
 434     {
 435         "EventCode": "0xF0",
 436         "Counter": "0,1,2,3",
 437         "UMask": "0x2",
 438         "EventName": "L2_TRANSACTIONS.RFO",
 439         "SampleAfterValue": "200000",
 440         "BriefDescription": "L2 RFO transactions"
 441     },
 442     {
 443         "EventCode": "0xF0",
 444         "Counter": "0,1,2,3",
 445         "UMask": "0x40",
 446         "EventName": "L2_TRANSACTIONS.WB",
 447         "SampleAfterValue": "200000",
 448         "BriefDescription": "L2 writeback to LLC transactions"
 449     },
 450     {
 451         "EventCode": "0x27",
 452         "Counter": "0,1,2,3",
 453         "UMask": "0x40",
 454         "EventName": "L2_WRITE.LOCK.E_STATE",
 455         "SampleAfterValue": "100000",
 456         "BriefDescription": "L2 demand lock RFOs in E state"
 457     },
 458     {
 459         "EventCode": "0x27",
 460         "Counter": "0,1,2,3",
 461         "UMask": "0xe0",
 462         "EventName": "L2_WRITE.LOCK.HIT",
 463         "SampleAfterValue": "100000",
 464         "BriefDescription": "All demand L2 lock RFOs that hit the cache"
 465     },
 466     {
 467         "EventCode": "0x27",
 468         "Counter": "0,1,2,3",
 469         "UMask": "0x10",
 470         "EventName": "L2_WRITE.LOCK.I_STATE",
 471         "SampleAfterValue": "100000",
 472         "BriefDescription": "L2 demand lock RFOs in I state (misses)"
 473     },
 474     {
 475         "EventCode": "0x27",
 476         "Counter": "0,1,2,3",
 477         "UMask": "0x80",
 478         "EventName": "L2_WRITE.LOCK.M_STATE",
 479         "SampleAfterValue": "100000",
 480         "BriefDescription": "L2 demand lock RFOs in M state"
 481     },
 482     {
 483         "EventCode": "0x27",
 484         "Counter": "0,1,2,3",
 485         "UMask": "0xf0",
 486         "EventName": "L2_WRITE.LOCK.MESI",
 487         "SampleAfterValue": "100000",
 488         "BriefDescription": "All demand L2 lock RFOs"
 489     },
 490     {
 491         "EventCode": "0x27",
 492         "Counter": "0,1,2,3",
 493         "UMask": "0x20",
 494         "EventName": "L2_WRITE.LOCK.S_STATE",
 495         "SampleAfterValue": "100000",
 496         "BriefDescription": "L2 demand lock RFOs in S state"
 497     },
 498     {
 499         "EventCode": "0x27",
 500         "Counter": "0,1,2,3",
 501         "UMask": "0xe",
 502         "EventName": "L2_WRITE.RFO.HIT",
 503         "SampleAfterValue": "100000",
 504         "BriefDescription": "All L2 demand store RFOs that hit the cache"
 505     },
 506     {
 507         "EventCode": "0x27",
 508         "Counter": "0,1,2,3",
 509         "UMask": "0x1",
 510         "EventName": "L2_WRITE.RFO.I_STATE",
 511         "SampleAfterValue": "100000",
 512         "BriefDescription": "L2 demand store RFOs in I state (misses)"
 513     },
 514     {
 515         "EventCode": "0x27",
 516         "Counter": "0,1,2,3",
 517         "UMask": "0x8",
 518         "EventName": "L2_WRITE.RFO.M_STATE",
 519         "SampleAfterValue": "100000",
 520         "BriefDescription": "L2 demand store RFOs in M state"
 521     },
 522     {
 523         "EventCode": "0x27",
 524         "Counter": "0,1,2,3",
 525         "UMask": "0xf",
 526         "EventName": "L2_WRITE.RFO.MESI",
 527         "SampleAfterValue": "100000",
 528         "BriefDescription": "All L2 demand store RFOs"
 529     },
 530     {
 531         "EventCode": "0x27",
 532         "Counter": "0,1,2,3",
 533         "UMask": "0x2",
 534         "EventName": "L2_WRITE.RFO.S_STATE",
 535         "SampleAfterValue": "100000",
 536         "BriefDescription": "L2 demand store RFOs in S state"
 537     },
 538     {
 539         "EventCode": "0x2E",
 540         "Counter": "0,1,2,3",
 541         "UMask": "0x41",
 542         "EventName": "LONGEST_LAT_CACHE.MISS",
 543         "SampleAfterValue": "100000",
 544         "BriefDescription": "Longest latency cache miss"
 545     },
 546     {
 547         "EventCode": "0x2E",
 548         "Counter": "0,1,2,3",
 549         "UMask": "0x4f",
 550         "EventName": "LONGEST_LAT_CACHE.REFERENCE",
 551         "SampleAfterValue": "200000",
 552         "BriefDescription": "Longest latency cache reference"
 553     },
 554     {
 555         "PEBS": "1",
 556         "EventCode": "0xB",
 557         "Counter": "0,1,2,3",
 558         "UMask": "0x1",
 559         "EventName": "MEM_INST_RETIRED.LOADS",
 560         "SampleAfterValue": "2000000",
 561         "BriefDescription": "Instructions retired which contains a load (Precise Event)"
 562     },
 563     {
 564         "PEBS": "1",
 565         "EventCode": "0xB",
 566         "Counter": "0,1,2,3",
 567         "UMask": "0x2",
 568         "EventName": "MEM_INST_RETIRED.STORES",
 569         "SampleAfterValue": "2000000",
 570         "BriefDescription": "Instructions retired which contains a store (Precise Event)"
 571     },
 572     {
 573         "PEBS": "1",
 574         "EventCode": "0xCB",
 575         "Counter": "0,1,2,3",
 576         "UMask": "0x40",
 577         "EventName": "MEM_LOAD_RETIRED.HIT_LFB",
 578         "SampleAfterValue": "200000",
 579         "BriefDescription": "Retired loads that miss L1D and hit an previously allocated LFB (Precise Event)"
 580     },
 581     {
 582         "PEBS": "1",
 583         "EventCode": "0xCB",
 584         "Counter": "0,1,2,3",
 585         "UMask": "0x1",
 586         "EventName": "MEM_LOAD_RETIRED.L1D_HIT",
 587         "SampleAfterValue": "2000000",
 588         "BriefDescription": "Retired loads that hit the L1 data cache (Precise Event)"
 589     },
 590     {
 591         "PEBS": "1",
 592         "EventCode": "0xCB",
 593         "Counter": "0,1,2,3",
 594         "UMask": "0x2",
 595         "EventName": "MEM_LOAD_RETIRED.L2_HIT",
 596         "SampleAfterValue": "200000",
 597         "BriefDescription": "Retired loads that hit the L2 cache (Precise Event)"
 598     },
 599     {
 600         "PEBS": "1",
 601         "EventCode": "0xCB",
 602         "Counter": "0,1,2,3",
 603         "UMask": "0x10",
 604         "EventName": "MEM_LOAD_RETIRED.LLC_MISS",
 605         "SampleAfterValue": "10000",
 606         "BriefDescription": "Retired loads that miss the LLC cache (Precise Event)"
 607     },
 608     {
 609         "PEBS": "1",
 610         "EventCode": "0xCB",
 611         "Counter": "0,1,2,3",
 612         "UMask": "0x4",
 613         "EventName": "MEM_LOAD_RETIRED.LLC_UNSHARED_HIT",
 614         "SampleAfterValue": "40000",
 615         "BriefDescription": "Retired loads that hit valid versions in the LLC cache (Precise Event)"
 616     },
 617     {
 618         "PEBS": "1",
 619         "EventCode": "0xCB",
 620         "Counter": "0,1,2,3",
 621         "UMask": "0x8",
 622         "EventName": "MEM_LOAD_RETIRED.OTHER_CORE_L2_HIT_HITM",
 623         "SampleAfterValue": "40000",
 624         "BriefDescription": "Retired loads that hit sibling core's L2 in modified or unmodified states (Precise Event)"
 625     },
 626     {
 627         "PEBS": "1",
 628         "EventCode": "0xF",
 629         "Counter": "0,1,2,3",
 630         "UMask": "0x10",
 631         "EventName": "MEM_UNCORE_RETIRED.LOCAL_DRAM",
 632         "SampleAfterValue": "10000",
 633         "BriefDescription": "Load instructions retired with a data source of local DRAM or locally homed remote hitm (Precise Event)"
 634     },
 635     {
 636         "PEBS": "1",
 637         "EventCode": "0xF",
 638         "Counter": "0,1,2,3",
 639         "UMask": "0x2",
 640         "EventName": "MEM_UNCORE_RETIRED.OTHER_CORE_L2_HITM",
 641         "SampleAfterValue": "40000",
 642         "BriefDescription": "Load instructions retired that HIT modified data in sibling core (Precise Event)"
 643     },
 644     {
 645         "PEBS": "1",
 646         "EventCode": "0xF",
 647         "Counter": "0,1,2,3",
 648         "UMask": "0x8",
 649         "EventName": "MEM_UNCORE_RETIRED.REMOTE_CACHE_LOCAL_HOME_HIT",
 650         "SampleAfterValue": "20000",
 651         "BriefDescription": "Load instructions retired remote cache HIT data source (Precise Event)"
 652     },
 653     {
 654         "PEBS": "1",
 655         "EventCode": "0xF",
 656         "Counter": "0,1,2,3",
 657         "UMask": "0x20",
 658         "EventName": "MEM_UNCORE_RETIRED.REMOTE_DRAM",
 659         "SampleAfterValue": "10000",
 660         "BriefDescription": "Load instructions retired remote DRAM and remote home-remote cache HITM (Precise Event)"
 661     },
 662     {
 663         "PEBS": "1",
 664         "EventCode": "0xF",
 665         "Counter": "0,1,2,3",
 666         "UMask": "0x80",
 667         "EventName": "MEM_UNCORE_RETIRED.UNCACHEABLE",
 668         "SampleAfterValue": "4000",
 669         "BriefDescription": "Load instructions retired IO (Precise Event)"
 670     },
 671     {
 672         "EventCode": "0xB0",
 673         "Counter": "0,1,2,3",
 674         "UMask": "0x80",
 675         "EventName": "OFFCORE_REQUESTS.ANY",
 676         "SampleAfterValue": "100000",
 677         "BriefDescription": "All offcore requests"
 678     },
 679     {
 680         "EventCode": "0xB0",
 681         "Counter": "0,1,2,3",
 682         "UMask": "0x8",
 683         "EventName": "OFFCORE_REQUESTS.ANY.READ",
 684         "SampleAfterValue": "100000",
 685         "BriefDescription": "Offcore read requests"
 686     },
 687     {
 688         "EventCode": "0xB0",
 689         "Counter": "0,1,2,3",
 690         "UMask": "0x10",
 691         "EventName": "OFFCORE_REQUESTS.ANY.RFO",
 692         "SampleAfterValue": "100000",
 693         "BriefDescription": "Offcore RFO requests"
 694     },
 695     {
 696         "EventCode": "0xB0",
 697         "Counter": "0,1,2,3",
 698         "UMask": "0x2",
 699         "EventName": "OFFCORE_REQUESTS.DEMAND.READ_CODE",
 700         "SampleAfterValue": "100000",
 701         "BriefDescription": "Offcore demand code read requests"
 702     },
 703     {
 704         "EventCode": "0xB0",
 705         "Counter": "0,1,2,3",
 706         "UMask": "0x1",
 707         "EventName": "OFFCORE_REQUESTS.DEMAND.READ_DATA",
 708         "SampleAfterValue": "100000",
 709         "BriefDescription": "Offcore demand data read requests"
 710     },
 711     {
 712         "EventCode": "0xB0",
 713         "Counter": "0,1,2,3",
 714         "UMask": "0x4",
 715         "EventName": "OFFCORE_REQUESTS.DEMAND.RFO",
 716         "SampleAfterValue": "100000",
 717         "BriefDescription": "Offcore demand RFO requests"
 718     },
 719     {
 720         "EventCode": "0xB0",
 721         "Counter": "0,1,2,3",
 722         "UMask": "0x40",
 723         "EventName": "OFFCORE_REQUESTS.L1D_WRITEBACK",
 724         "SampleAfterValue": "100000",
 725         "BriefDescription": "Offcore L1 data cache writebacks"
 726     },
 727     {
 728         "EventCode": "0xB0",
 729         "Counter": "0,1,2,3",
 730         "UMask": "0x20",
 731         "EventName": "OFFCORE_REQUESTS.UNCACHED_MEM",
 732         "SampleAfterValue": "100000",
 733         "BriefDescription": "Offcore uncached memory accesses"
 734     },
 735     {
 736         "EventCode": "0x60",
 737         "UMask": "0x8",
 738         "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ANY.READ",
 739         "SampleAfterValue": "2000000",
 740         "BriefDescription": "Outstanding offcore reads"
 741     },
 742     {
 743         "EventCode": "0x60",
 744         "UMask": "0x8",
 745         "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ANY.READ_NOT_EMPTY",
 746         "SampleAfterValue": "2000000",
 747         "BriefDescription": "Cycles offcore reads busy",
 748         "CounterMask": "1"
 749     },
 750     {
 751         "EventCode": "0x60",
 752         "UMask": "0x2",
 753         "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_CODE",
 754         "SampleAfterValue": "2000000",
 755         "BriefDescription": "Outstanding offcore demand code reads"
 756     },
 757     {
 758         "EventCode": "0x60",
 759         "UMask": "0x2",
 760         "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_CODE_NOT_EMPTY",
 761         "SampleAfterValue": "2000000",
 762         "BriefDescription": "Cycles offcore demand code read busy",
 763         "CounterMask": "1"
 764     },
 765     {
 766         "EventCode": "0x60",
 767         "UMask": "0x1",
 768         "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_DATA",
 769         "SampleAfterValue": "2000000",
 770         "BriefDescription": "Outstanding offcore demand data reads"
 771     },
 772     {
 773         "EventCode": "0x60",
 774         "UMask": "0x1",
 775         "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_DATA_NOT_EMPTY",
 776         "SampleAfterValue": "2000000",
 777         "BriefDescription": "Cycles offcore demand data read busy",
 778         "CounterMask": "1"
 779     },
 780     {
 781         "EventCode": "0x60",
 782         "UMask": "0x4",
 783         "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.RFO",
 784         "SampleAfterValue": "2000000",
 785         "BriefDescription": "Outstanding offcore demand RFOs"
 786     },
 787     {
 788         "EventCode": "0x60",
 789         "UMask": "0x4",
 790         "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.RFO_NOT_EMPTY",
 791         "SampleAfterValue": "2000000",
 792         "BriefDescription": "Cycles offcore demand RFOs busy",
 793         "CounterMask": "1"
 794     },
 795     {
 796         "EventCode": "0xB2",
 797         "Counter": "0,1,2,3",
 798         "UMask": "0x1",
 799         "EventName": "OFFCORE_REQUESTS_SQ_FULL",
 800         "SampleAfterValue": "100000",
 801         "BriefDescription": "Offcore requests blocked due to Super Queue full"
 802     },
 803     {
 804         "EventCode": "0xF4",
 805         "Counter": "0,1,2,3",
 806         "UMask": "0x4",
 807         "EventName": "SQ_MISC.LRU_HINTS",
 808         "SampleAfterValue": "2000000",
 809         "BriefDescription": "Super Queue LRU hints sent to LLC"
 810     },
 811     {
 812         "EventCode": "0xF4",
 813         "Counter": "0,1,2,3",
 814         "UMask": "0x10",
 815         "EventName": "SQ_MISC.SPLIT_LOCK",
 816         "SampleAfterValue": "2000000",
 817         "BriefDescription": "Super Queue lock splits across a cache line"
 818     },
 819     {
 820         "EventCode": "0x6",
 821         "Counter": "0,1,2,3",
 822         "UMask": "0x4",
 823         "EventName": "STORE_BLOCKS.AT_RET",
 824         "SampleAfterValue": "200000",
 825         "BriefDescription": "Loads delayed with at-Retirement block code"
 826     },
 827     {
 828         "EventCode": "0x6",
 829         "Counter": "0,1,2,3",
 830         "UMask": "0x8",
 831         "EventName": "STORE_BLOCKS.L1D_BLOCK",
 832         "SampleAfterValue": "200000",
 833         "BriefDescription": "Cacheable loads delayed with L1D block code"
 834     },
 835     {
 836         "PEBS": "2",
 837         "EventCode": "0xB",
 838         "MSRValue": "0x0",
 839         "Counter": "3",
 840         "UMask": "0x10",
 841         "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_0",
 842         "MSRIndex": "0x3F6",
 843         "SampleAfterValue": "2000000",
 844         "BriefDescription": "Memory instructions retired above 0 clocks (Precise Event)"
 845     },
 846     {
 847         "PEBS": "2",
 848         "EventCode": "0xB",
 849         "MSRValue": "0x400",
 850         "Counter": "3",
 851         "UMask": "0x10",
 852         "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_1024",
 853         "MSRIndex": "0x3F6",
 854         "SampleAfterValue": "100",
 855         "BriefDescription": "Memory instructions retired above 1024 clocks (Precise Event)"
 856     },
 857     {
 858         "PEBS": "2",
 859         "EventCode": "0xB",
 860         "MSRValue": "0x80",
 861         "Counter": "3",
 862         "UMask": "0x10",
 863         "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_128",
 864         "MSRIndex": "0x3F6",
 865         "SampleAfterValue": "1000",
 866         "BriefDescription": "Memory instructions retired above 128 clocks (Precise Event)"
 867     },
 868     {
 869         "PEBS": "2",
 870         "EventCode": "0xB",
 871         "MSRValue": "0x10",
 872         "Counter": "3",
 873         "UMask": "0x10",
 874         "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_16",
 875         "MSRIndex": "0x3F6",
 876         "SampleAfterValue": "10000",
 877         "BriefDescription": "Memory instructions retired above 16 clocks (Precise Event)"
 878     },
 879     {
 880         "PEBS": "2",
 881         "EventCode": "0xB",
 882         "MSRValue": "0x4000",
 883         "Counter": "3",
 884         "UMask": "0x10",
 885         "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_16384",
 886         "MSRIndex": "0x3F6",
 887         "SampleAfterValue": "5",
 888         "BriefDescription": "Memory instructions retired above 16384 clocks (Precise Event)"
 889     },
 890     {
 891         "PEBS": "2",
 892         "EventCode": "0xB",
 893         "MSRValue": "0x800",
 894         "Counter": "3",
 895         "UMask": "0x10",
 896         "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_2048",
 897         "MSRIndex": "0x3F6",
 898         "SampleAfterValue": "50",
 899         "BriefDescription": "Memory instructions retired above 2048 clocks (Precise Event)"
 900     },
 901     {
 902         "PEBS": "2",
 903         "EventCode": "0xB",
 904         "MSRValue": "0x100",
 905         "Counter": "3",
 906         "UMask": "0x10",
 907         "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_256",
 908         "MSRIndex": "0x3F6",
 909         "SampleAfterValue": "500",
 910         "BriefDescription": "Memory instructions retired above 256 clocks (Precise Event)"
 911     },
 912     {
 913         "PEBS": "2",
 914         "EventCode": "0xB",
 915         "MSRValue": "0x20",
 916         "Counter": "3",
 917         "UMask": "0x10",
 918         "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_32",
 919         "MSRIndex": "0x3F6",
 920         "SampleAfterValue": "5000",
 921         "BriefDescription": "Memory instructions retired above 32 clocks (Precise Event)"
 922     },
 923     {
 924         "PEBS": "2",
 925         "EventCode": "0xB",
 926         "MSRValue": "0x8000",
 927         "Counter": "3",
 928         "UMask": "0x10",
 929         "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_32768",
 930         "MSRIndex": "0x3F6",
 931         "SampleAfterValue": "3",
 932         "BriefDescription": "Memory instructions retired above 32768 clocks (Precise Event)"
 933     },
 934     {
 935         "PEBS": "2",
 936         "EventCode": "0xB",
 937         "MSRValue": "0x4",
 938         "Counter": "3",
 939         "UMask": "0x10",
 940         "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_4",
 941         "MSRIndex": "0x3F6",
 942         "SampleAfterValue": "50000",
 943         "BriefDescription": "Memory instructions retired above 4 clocks (Precise Event)"
 944     },
 945     {
 946         "PEBS": "2",
 947         "EventCode": "0xB",
 948         "MSRValue": "0x1000",
 949         "Counter": "3",
 950         "UMask": "0x10",
 951         "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_4096",
 952         "MSRIndex": "0x3F6",
 953         "SampleAfterValue": "20",
 954         "BriefDescription": "Memory instructions retired above 4096 clocks (Precise Event)"
 955     },
 956     {
 957         "PEBS": "2",
 958         "EventCode": "0xB",
 959         "MSRValue": "0x200",
 960         "Counter": "3",
 961         "UMask": "0x10",
 962         "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_512",
 963         "MSRIndex": "0x3F6",
 964         "SampleAfterValue": "200",
 965         "BriefDescription": "Memory instructions retired above 512 clocks (Precise Event)"
 966     },
 967     {
 968         "PEBS": "2",
 969         "EventCode": "0xB",
 970         "MSRValue": "0x40",
 971         "Counter": "3",
 972         "UMask": "0x10",
 973         "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_64",
 974         "MSRIndex": "0x3F6",
 975         "SampleAfterValue": "2000",
 976         "BriefDescription": "Memory instructions retired above 64 clocks (Precise Event)"
 977     },
 978     {
 979         "PEBS": "2",
 980         "EventCode": "0xB",
 981         "MSRValue": "0x8",
 982         "Counter": "3",
 983         "UMask": "0x10",
 984         "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_8",
 985         "MSRIndex": "0x3F6",
 986         "SampleAfterValue": "20000",
 987         "BriefDescription": "Memory instructions retired above 8 clocks (Precise Event)"
 988     },
 989     {
 990         "PEBS": "2",
 991         "EventCode": "0xB",
 992         "MSRValue": "0x2000",
 993         "Counter": "3",
 994         "UMask": "0x10",
 995         "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_8192",
 996         "MSRIndex": "0x3F6",
 997         "SampleAfterValue": "10",
 998         "BriefDescription": "Memory instructions retired above 8192 clocks (Precise Event)"
 999     },
1000     {
1001         "EventCode": "0xB7, 0xBB",
1002         "MSRValue": "0x7F11",
1003         "Counter": "0,1,2,3",
1004         "UMask": "0x1",
1005         "EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_CACHE_DRAM",
1006         "MSRIndex": "0x1a6,0x1a7",
1007         "SampleAfterValue": "100000",
1008         "BriefDescription": "Offcore data reads satisfied by any cache or DRAM",
1009         "Offcore": "1"
1010     },
1011     {
1012         "EventCode": "0xB7, 0xBB",
1013         "MSRValue": "0xFF11",
1014         "Counter": "0,1,2,3",
1015         "UMask": "0x1",
1016         "EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_LOCATION",
1017         "MSRIndex": "0x1a6,0x1a7",
1018         "SampleAfterValue": "100000",
1019         "BriefDescription": "All offcore data reads",
1020         "Offcore": "1"
1021     },
1022     {
1023         "EventCode": "0xB7, 0xBB",
1024         "MSRValue": "0x8011",
1025         "Counter": "0,1,2,3",
1026         "UMask": "0x1",
1027         "EventName": "OFFCORE_RESPONSE.ANY_DATA.IO_CSR_MMIO",
1028         "MSRIndex": "0x1a6,0x1a7",
1029         "SampleAfterValue": "100000",
1030         "BriefDescription": "Offcore data reads satisfied by the IO, CSR, MMIO unit",
1031         "Offcore": "1"
1032     },
1033     {
1034         "EventCode": "0xB7, 0xBB",
1035         "MSRValue": "0x111",
1036         "Counter": "0,1,2,3",
1037         "UMask": "0x1",
1038         "EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_NO_OTHER_CORE",
1039         "MSRIndex": "0x1a6,0x1a7",
1040         "SampleAfterValue": "100000",
1041         "BriefDescription": "Offcore data reads satisfied by the LLC and not found in a sibling core",
1042         "Offcore": "1"
1043     },
1044     {
1045         "EventCode": "0xB7, 0xBB",
1046         "MSRValue": "0x211",
1047         "Counter": "0,1,2,3",
1048         "UMask": "0x1",
1049         "EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_OTHER_CORE_HIT",
1050         "MSRIndex": "0x1a6,0x1a7",
1051         "SampleAfterValue": "100000",
1052         "BriefDescription": "Offcore data reads satisfied by the LLC and HIT in a sibling core",
1053         "Offcore": "1"
1054     },
1055     {
1056         "EventCode": "0xB7, 0xBB",
1057         "MSRValue": "0x411",
1058         "Counter": "0,1,2,3",
1059         "UMask": "0x1",
1060         "EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_OTHER_CORE_HITM",
1061         "MSRIndex": "0x1a6,0x1a7",
1062         "SampleAfterValue": "100000",
1063         "BriefDescription": "Offcore data reads satisfied by the LLC  and HITM in a sibling core",
1064         "Offcore": "1"
1065     },
1066     {
1067         "EventCode": "0xB7, 0xBB",
1068         "MSRValue": "0x711",
1069         "Counter": "0,1,2,3",
1070         "UMask": "0x1",
1071         "EventName": "OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE",
1072         "MSRIndex": "0x1a6,0x1a7",
1073         "SampleAfterValue": "100000",
1074         "BriefDescription": "Offcore data reads satisfied by the LLC",
1075         "Offcore": "1"
1076     },
1077     {
1078         "EventCode": "0xB7, 0xBB",
1079         "MSRValue": "0x2711",
1080         "Counter": "0,1,2,3",
1081         "UMask": "0x1",
1082         "EventName": "OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE_DRAM",
1083         "MSRIndex": "0x1a6,0x1a7",
1084         "SampleAfterValue": "100000",
1085         "BriefDescription": "Offcore data reads satisfied by the LLC or local DRAM",
1086         "Offcore": "1"
1087     },
1088     {
1089         "EventCode": "0xB7, 0xBB",
1090         "MSRValue": "0x1811",
1091         "Counter": "0,1,2,3",
1092         "UMask": "0x1",
1093         "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE",
1094         "MSRIndex": "0x1a6,0x1a7",
1095         "SampleAfterValue": "100000",
1096         "BriefDescription": "Offcore data reads satisfied by a remote cache",
1097         "Offcore": "1"
1098     },
1099     {
1100         "EventCode": "0xB7, 0xBB",
1101         "MSRValue": "0x5811",
1102         "Counter": "0,1,2,3",
1103         "UMask": "0x1",
1104         "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_DRAM",
1105         "MSRIndex": "0x1a6,0x1a7",
1106         "SampleAfterValue": "100000",
1107         "BriefDescription": "Offcore data reads satisfied by a remote cache or remote DRAM",
1108         "Offcore": "1"
1109     },
1110     {
1111         "EventCode": "0xB7, 0xBB",
1112         "MSRValue": "0x1011",
1113         "Counter": "0,1,2,3",
1114         "UMask": "0x1",
1115         "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_HIT",
1116         "MSRIndex": "0x1a6,0x1a7",
1117         "SampleAfterValue": "100000",
1118         "BriefDescription": "Offcore data reads that HIT in a remote cache",
1119         "Offcore": "1"
1120     },
1121     {
1122         "EventCode": "0xB7, 0xBB",
1123         "MSRValue": "0x811",
1124         "Counter": "0,1,2,3",
1125         "UMask": "0x1",
1126         "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_HITM",
1127         "MSRIndex": "0x1a6,0x1a7",
1128         "SampleAfterValue": "100000",
1129         "BriefDescription": "Offcore data reads that HITM in a remote cache",
1130         "Offcore": "1"
1131     },
1132     {
1133         "EventCode": "0xB7, 0xBB",
1134         "MSRValue": "0x7F44",
1135         "Counter": "0,1,2,3",
1136         "UMask": "0x1",
1137         "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_CACHE_DRAM",
1138         "MSRIndex": "0x1a6,0x1a7",
1139         "SampleAfterValue": "100000",
1140         "BriefDescription": "Offcore code reads satisfied by any cache or DRAM",
1141         "Offcore": "1"
1142     },
1143     {
1144         "EventCode": "0xB7, 0xBB",
1145         "MSRValue": "0xFF44",
1146         "Counter": "0,1,2,3",
1147         "UMask": "0x1",
1148         "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_LOCATION",
1149         "MSRIndex": "0x1a6,0x1a7",
1150         "SampleAfterValue": "100000",
1151         "BriefDescription": "All offcore code reads",
1152         "Offcore": "1"
1153     },
1154     {
1155         "EventCode": "0xB7, 0xBB",
1156         "MSRValue": "0x8044",
1157         "Counter": "0,1,2,3",
1158         "UMask": "0x1",
1159         "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.IO_CSR_MMIO",
1160         "MSRIndex": "0x1a6,0x1a7",
1161         "SampleAfterValue": "100000",
1162         "BriefDescription": "Offcore code reads satisfied by the IO, CSR, MMIO unit",
1163         "Offcore": "1"
1164     },
1165     {
1166         "EventCode": "0xB7, 0xBB",
1167         "MSRValue": "0x144",
1168         "Counter": "0,1,2,3",
1169         "UMask": "0x1",
1170         "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_NO_OTHER_CORE",
1171         "MSRIndex": "0x1a6,0x1a7",
1172         "SampleAfterValue": "100000",
1173         "BriefDescription": "Offcore code reads satisfied by the LLC and not found in a sibling core",
1174         "Offcore": "1"
1175     },
1176     {
1177         "EventCode": "0xB7, 0xBB",
1178         "MSRValue": "0x244",
1179         "Counter": "0,1,2,3",
1180         "UMask": "0x1",
1181         "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_OTHER_CORE_HIT",
1182         "MSRIndex": "0x1a6,0x1a7",
1183         "SampleAfterValue": "100000",
1184         "BriefDescription": "Offcore code reads satisfied by the LLC and HIT in a sibling core",
1185         "Offcore": "1"
1186     },
1187     {
1188         "EventCode": "0xB7, 0xBB",
1189         "MSRValue": "0x444",
1190         "Counter": "0,1,2,3",
1191         "UMask": "0x1",
1192         "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_OTHER_CORE_HITM",
1193         "MSRIndex": "0x1a6,0x1a7",
1194         "SampleAfterValue": "100000",
1195         "BriefDescription": "Offcore code reads satisfied by the LLC  and HITM in a sibling core",
1196         "Offcore": "1"
1197     },
1198     {
1199         "EventCode": "0xB7, 0xBB",
1200         "MSRValue": "0x744",
1201         "Counter": "0,1,2,3",
1202         "UMask": "0x1",
1203         "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LOCAL_CACHE",
1204         "MSRIndex": "0x1a6,0x1a7",
1205         "SampleAfterValue": "100000",
1206         "BriefDescription": "Offcore code reads satisfied by the LLC",
1207         "Offcore": "1"
1208     },
1209     {
1210         "EventCode": "0xB7, 0xBB",
1211         "MSRValue": "0x2744",
1212         "Counter": "0,1,2,3",
1213         "UMask": "0x1",
1214         "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LOCAL_CACHE_DRAM",
1215         "MSRIndex": "0x1a6,0x1a7",
1216         "SampleAfterValue": "100000",
1217         "BriefDescription": "Offcore code reads satisfied by the LLC or local DRAM",
1218         "Offcore": "1"
1219     },
1220     {
1221         "EventCode": "0xB7, 0xBB",
1222         "MSRValue": "0x1844",
1223         "Counter": "0,1,2,3",
1224         "UMask": "0x1",
1225         "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE",
1226         "MSRIndex": "0x1a6,0x1a7",
1227         "SampleAfterValue": "100000",
1228         "BriefDescription": "Offcore code reads satisfied by a remote cache",
1229         "Offcore": "1"
1230     },
1231     {
1232         "EventCode": "0xB7, 0xBB",
1233         "MSRValue": "0x5844",
1234         "Counter": "0,1,2,3",
1235         "UMask": "0x1",
1236         "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_DRAM",
1237         "MSRIndex": "0x1a6,0x1a7",
1238         "SampleAfterValue": "100000",
1239         "BriefDescription": "Offcore code reads satisfied by a remote cache or remote DRAM",
1240         "Offcore": "1"
1241     },
1242     {
1243         "EventCode": "0xB7, 0xBB",
1244         "MSRValue": "0x1044",
1245         "Counter": "0,1,2,3",
1246         "UMask": "0x1",
1247         "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_HIT",
1248         "MSRIndex": "0x1a6,0x1a7",
1249         "SampleAfterValue": "100000",
1250         "BriefDescription": "Offcore code reads that HIT in a remote cache",
1251         "Offcore": "1"
1252     },
1253     {
1254         "EventCode": "0xB7, 0xBB",
1255         "MSRValue": "0x844",
1256         "Counter": "0,1,2,3",
1257         "UMask": "0x1",
1258         "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_HITM",
1259         "MSRIndex": "0x1a6,0x1a7",
1260         "SampleAfterValue": "100000",
1261         "BriefDescription": "Offcore code reads that HITM in a remote cache",
1262         "Offcore": "1"
1263     },
1264     {
1265         "EventCode": "0xB7, 0xBB",
1266         "MSRValue": "0x7FFF",
1267         "Counter": "0,1,2,3",
1268         "UMask": "0x1",
1269         "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_CACHE_DRAM",
1270         "MSRIndex": "0x1a6,0x1a7",
1271         "SampleAfterValue": "100000",
1272         "BriefDescription": "Offcore requests satisfied by any cache or DRAM",
1273         "Offcore": "1"
1274     },
1275     {
1276         "EventCode": "0xB7, 0xBB",
1277         "MSRValue": "0xFFFF",
1278         "Counter": "0,1,2,3",
1279         "UMask": "0x1",
1280         "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_LOCATION",
1281         "MSRIndex": "0x1a6,0x1a7",
1282         "SampleAfterValue": "100000",
1283         "BriefDescription": "All offcore requests",
1284         "Offcore": "1"
1285     },
1286     {
1287         "EventCode": "0xB7, 0xBB",
1288         "MSRValue": "0x80FF",
1289         "Counter": "0,1,2,3",
1290         "UMask": "0x1",
1291         "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.IO_CSR_MMIO",
1292         "MSRIndex": "0x1a6,0x1a7",
1293         "SampleAfterValue": "100000",
1294         "BriefDescription": "Offcore requests satisfied by the IO, CSR, MMIO unit",
1295         "Offcore": "1"
1296     },
1297     {
1298         "EventCode": "0xB7, 0xBB",
1299         "MSRValue": "0x1FF",
1300         "Counter": "0,1,2,3",
1301         "UMask": "0x1",
1302         "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_NO_OTHER_CORE",
1303         "MSRIndex": "0x1a6,0x1a7",
1304         "SampleAfterValue": "100000",
1305         "BriefDescription": "Offcore requests satisfied by the LLC and not found in a sibling core",
1306         "Offcore": "1"
1307     },
1308     {
1309         "EventCode": "0xB7, 0xBB",
1310         "MSRValue": "0x2FF",
1311         "Counter": "0,1,2,3",
1312         "UMask": "0x1",
1313         "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_OTHER_CORE_HIT",
1314         "MSRIndex": "0x1a6,0x1a7",
1315         "SampleAfterValue": "100000",
1316         "BriefDescription": "Offcore requests satisfied by the LLC and HIT in a sibling core",
1317         "Offcore": "1"
1318     },
1319     {
1320         "EventCode": "0xB7, 0xBB",
1321         "MSRValue": "0x4FF",
1322         "Counter": "0,1,2,3",
1323         "UMask": "0x1",
1324         "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_OTHER_CORE_HITM",
1325         "MSRIndex": "0x1a6,0x1a7",
1326         "SampleAfterValue": "100000",
1327         "BriefDescription": "Offcore requests satisfied by the LLC  and HITM in a sibling core",
1328         "Offcore": "1"
1329     },
1330     {
1331         "EventCode": "0xB7, 0xBB",
1332         "MSRValue": "0x7FF",
1333         "Counter": "0,1,2,3",
1334         "UMask": "0x1",
1335         "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LOCAL_CACHE",
1336         "MSRIndex": "0x1a6,0x1a7",
1337         "SampleAfterValue": "100000",
1338         "BriefDescription": "Offcore requests satisfied by the LLC",
1339         "Offcore": "1"
1340     },
1341     {
1342         "EventCode": "0xB7, 0xBB",
1343         "MSRValue": "0x27FF",
1344         "Counter": "0,1,2,3",
1345         "UMask": "0x1",
1346         "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LOCAL_CACHE_DRAM",
1347         "MSRIndex": "0x1a6,0x1a7",
1348         "SampleAfterValue": "100000",
1349         "BriefDescription": "Offcore requests satisfied by the LLC or local DRAM",
1350         "Offcore": "1"
1351     },
1352     {
1353         "EventCode": "0xB7, 0xBB",
1354         "MSRValue": "0x18FF",
1355         "Counter": "0,1,2,3",
1356         "UMask": "0x1",
1357         "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE",
1358         "MSRIndex": "0x1a6,0x1a7",
1359         "SampleAfterValue": "100000",
1360         "BriefDescription": "Offcore requests satisfied by a remote cache",
1361         "Offcore": "1"
1362     },
1363     {
1364         "EventCode": "0xB7, 0xBB",
1365         "MSRValue": "0x58FF",
1366         "Counter": "0,1,2,3",
1367         "UMask": "0x1",
1368         "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_DRAM",
1369         "MSRIndex": "0x1a6,0x1a7",
1370         "SampleAfterValue": "100000",
1371         "BriefDescription": "Offcore requests satisfied by a remote cache or remote DRAM",
1372         "Offcore": "1"
1373     },
1374     {
1375         "EventCode": "0xB7, 0xBB",
1376         "MSRValue": "0x10FF",
1377         "Counter": "0,1,2,3",
1378         "UMask": "0x1",
1379         "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_HIT",
1380         "MSRIndex": "0x1a6,0x1a7",
1381         "SampleAfterValue": "100000",
1382         "BriefDescription": "Offcore requests that HIT in a remote cache",
1383         "Offcore": "1"
1384     },
1385     {
1386         "EventCode": "0xB7, 0xBB",
1387         "MSRValue": "0x8FF",
1388         "Counter": "0,1,2,3",
1389         "UMask": "0x1",
1390         "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_HITM",
1391         "MSRIndex": "0x1a6,0x1a7",
1392         "SampleAfterValue": "100000",
1393         "BriefDescription": "Offcore requests that HITM in a remote cache",
1394         "Offcore": "1"
1395     },
1396     {
1397         "EventCode": "0xB7, 0xBB",
1398         "MSRValue": "0x7F22",
1399         "Counter": "0,1,2,3",
1400         "UMask": "0x1",
1401         "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_CACHE_DRAM",
1402         "MSRIndex": "0x1a6,0x1a7",
1403         "SampleAfterValue": "100000",
1404         "BriefDescription": "Offcore RFO requests satisfied by any cache or DRAM",
1405         "Offcore": "1"
1406     },
1407     {
1408         "EventCode": "0xB7, 0xBB",
1409         "MSRValue": "0xFF22",
1410         "Counter": "0,1,2,3",
1411         "UMask": "0x1",
1412         "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_LOCATION",
1413         "MSRIndex": "0x1a6,0x1a7",
1414         "SampleAfterValue": "100000",
1415         "BriefDescription": "All offcore RFO requests",
1416         "Offcore": "1"
1417     },
1418     {
1419         "EventCode": "0xB7, 0xBB",
1420         "MSRValue": "0x8022",
1421         "Counter": "0,1,2,3",
1422         "UMask": "0x1",
1423         "EventName": "OFFCORE_RESPONSE.ANY_RFO.IO_CSR_MMIO",
1424         "MSRIndex": "0x1a6,0x1a7",
1425         "SampleAfterValue": "100000",
1426         "BriefDescription": "Offcore RFO requests satisfied by the IO, CSR, MMIO unit",
1427         "Offcore": "1"
1428     },
1429     {
1430         "EventCode": "0xB7, 0xBB",
1431         "MSRValue": "0x122",
1432         "Counter": "0,1,2,3",
1433         "UMask": "0x1",
1434         "EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_NO_OTHER_CORE",
1435         "MSRIndex": "0x1a6,0x1a7",
1436         "SampleAfterValue": "100000",
1437         "BriefDescription": "Offcore RFO requests satisfied by the LLC and not found in a sibling core",
1438         "Offcore": "1"
1439     },
1440     {
1441         "EventCode": "0xB7, 0xBB",
1442         "MSRValue": "0x222",
1443         "Counter": "0,1,2,3",
1444         "UMask": "0x1",
1445         "EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_OTHER_CORE_HIT",
1446         "MSRIndex": "0x1a6,0x1a7",
1447         "SampleAfterValue": "100000",
1448         "BriefDescription": "Offcore RFO requests satisfied by the LLC and HIT in a sibling core",
1449         "Offcore": "1"
1450     },
1451     {
1452         "EventCode": "0xB7, 0xBB",
1453         "MSRValue": "0x422",
1454         "Counter": "0,1,2,3",
1455         "UMask": "0x1",
1456         "EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_OTHER_CORE_HITM",
1457         "MSRIndex": "0x1a6,0x1a7",
1458         "SampleAfterValue": "100000",
1459         "BriefDescription": "Offcore RFO requests satisfied by the LLC  and HITM in a sibling core",
1460         "Offcore": "1"
1461     },
1462     {
1463         "EventCode": "0xB7, 0xBB",
1464         "MSRValue": "0x722",
1465         "Counter": "0,1,2,3",
1466         "UMask": "0x1",
1467         "EventName": "OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE",
1468         "MSRIndex": "0x1a6,0x1a7",
1469         "SampleAfterValue": "100000",
1470         "BriefDescription": "Offcore RFO requests satisfied by the LLC",
1471         "Offcore": "1"
1472     },
1473     {
1474         "EventCode": "0xB7, 0xBB",
1475         "MSRValue": "0x2722",
1476         "Counter": "0,1,2,3",
1477         "UMask": "0x1",
1478         "EventName": "OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE_DRAM",
1479         "MSRIndex": "0x1a6,0x1a7",
1480         "SampleAfterValue": "100000",
1481         "BriefDescription": "Offcore RFO requests satisfied by the LLC or local DRAM",
1482         "Offcore": "1"
1483     },
1484     {
1485         "EventCode": "0xB7, 0xBB",
1486         "MSRValue": "0x1822",
1487         "Counter": "0,1,2,3",
1488         "UMask": "0x1",
1489         "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE",
1490         "MSRIndex": "0x1a6,0x1a7",
1491         "SampleAfterValue": "100000",
1492         "BriefDescription": "Offcore RFO requests satisfied by a remote cache",
1493         "Offcore": "1"
1494     },
1495     {
1496         "EventCode": "0xB7, 0xBB",
1497         "MSRValue": "0x5822",
1498         "Counter": "0,1,2,3",
1499         "UMask": "0x1",
1500         "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_DRAM",
1501         "MSRIndex": "0x1a6,0x1a7",
1502         "SampleAfterValue": "100000",
1503         "BriefDescription": "Offcore RFO requests satisfied by a remote cache or remote DRAM",
1504         "Offcore": "1"
1505     },
1506     {
1507         "EventCode": "0xB7, 0xBB",
1508         "MSRValue": "0x1022",
1509         "Counter": "0,1,2,3",
1510         "UMask": "0x1",
1511         "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_HIT",
1512         "MSRIndex": "0x1a6,0x1a7",
1513         "SampleAfterValue": "100000",
1514         "BriefDescription": "Offcore RFO requests that HIT in a remote cache",
1515         "Offcore": "1"
1516     },
1517     {
1518         "EventCode": "0xB7, 0xBB",
1519         "MSRValue": "0x822",
1520         "Counter": "0,1,2,3",
1521         "UMask": "0x1",
1522         "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_HITM",
1523         "MSRIndex": "0x1a6,0x1a7",
1524         "SampleAfterValue": "100000",
1525         "BriefDescription": "Offcore RFO requests that HITM in a remote cache",
1526         "Offcore": "1"
1527     },
1528     {
1529         "EventCode": "0xB7, 0xBB",
1530         "MSRValue": "0x7F08",
1531         "Counter": "0,1,2,3",
1532         "UMask": "0x1",
1533         "EventName": "OFFCORE_RESPONSE.COREWB.ANY_CACHE_DRAM",
1534         "MSRIndex": "0x1a6,0x1a7",
1535         "SampleAfterValue": "100000",
1536         "BriefDescription": "Offcore writebacks to any cache or DRAM.",
1537         "Offcore": "1"
1538     },
1539     {
1540         "EventCode": "0xB7, 0xBB",
1541         "MSRValue": "0xFF08",
1542         "Counter": "0,1,2,3",
1543         "UMask": "0x1",
1544         "EventName": "OFFCORE_RESPONSE.COREWB.ANY_LOCATION",
1545         "MSRIndex": "0x1a6,0x1a7",
1546         "SampleAfterValue": "100000",
1547         "BriefDescription": "All offcore writebacks",
1548         "Offcore": "1"
1549     },
1550     {
1551         "EventCode": "0xB7, 0xBB",
1552         "MSRValue": "0x8008",
1553         "Counter": "0,1,2,3",
1554         "UMask": "0x1",
1555         "EventName": "OFFCORE_RESPONSE.COREWB.IO_CSR_MMIO",
1556         "MSRIndex": "0x1a6,0x1a7",
1557         "SampleAfterValue": "100000",
1558         "BriefDescription": "Offcore writebacks to the IO, CSR, MMIO unit.",
1559         "Offcore": "1"
1560     },
1561     {
1562         "EventCode": "0xB7, 0xBB",
1563         "MSRValue": "0x108",
1564         "Counter": "0,1,2,3",
1565         "UMask": "0x1",
1566         "EventName": "OFFCORE_RESPONSE.COREWB.LLC_HIT_NO_OTHER_CORE",
1567         "MSRIndex": "0x1a6,0x1a7",
1568         "SampleAfterValue": "100000",
1569         "BriefDescription": "Offcore writebacks to the LLC and not found in a sibling core",
1570         "Offcore": "1"
1571     },
1572     {
1573         "EventCode": "0xB7, 0xBB",
1574         "MSRValue": "0x408",
1575         "Counter": "0,1,2,3",
1576         "UMask": "0x1",
1577         "EventName": "OFFCORE_RESPONSE.COREWB.LLC_HIT_OTHER_CORE_HITM",
1578         "MSRIndex": "0x1a6,0x1a7",
1579         "SampleAfterValue": "100000",
1580         "BriefDescription": "Offcore writebacks to the LLC  and HITM in a sibling core",
1581         "Offcore": "1"
1582     },
1583     {
1584         "EventCode": "0xB7, 0xBB",
1585         "MSRValue": "0x708",
1586         "Counter": "0,1,2,3",
1587         "UMask": "0x1",
1588         "EventName": "OFFCORE_RESPONSE.COREWB.LOCAL_CACHE",
1589         "MSRIndex": "0x1a6,0x1a7",
1590         "SampleAfterValue": "100000",
1591         "BriefDescription": "Offcore writebacks to the LLC",
1592         "Offcore": "1"
1593     },
1594     {
1595         "EventCode": "0xB7, 0xBB",
1596         "MSRValue": "0x2708",
1597         "Counter": "0,1,2,3",
1598         "UMask": "0x1",
1599         "EventName": "OFFCORE_RESPONSE.COREWB.LOCAL_CACHE_DRAM",
1600         "MSRIndex": "0x1a6,0x1a7",
1601         "SampleAfterValue": "100000",
1602         "BriefDescription": "Offcore writebacks to the LLC or local DRAM",
1603         "Offcore": "1"
1604     },
1605     {
1606         "EventCode": "0xB7, 0xBB",
1607         "MSRValue": "0x1808",
1608         "Counter": "0,1,2,3",
1609         "UMask": "0x1",
1610         "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE",
1611         "MSRIndex": "0x1a6,0x1a7",
1612         "SampleAfterValue": "100000",
1613         "BriefDescription": "Offcore writebacks to a remote cache",
1614         "Offcore": "1"
1615     },
1616     {
1617         "EventCode": "0xB7, 0xBB",
1618         "MSRValue": "0x5808",
1619         "Counter": "0,1,2,3",
1620         "UMask": "0x1",
1621         "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_DRAM",
1622         "MSRIndex": "0x1a6,0x1a7",
1623         "SampleAfterValue": "100000",
1624         "BriefDescription": "Offcore writebacks to a remote cache or remote DRAM",
1625         "Offcore": "1"
1626     },
1627     {
1628         "EventCode": "0xB7, 0xBB",
1629         "MSRValue": "0x1008",
1630         "Counter": "0,1,2,3",
1631         "UMask": "0x1",
1632         "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_HIT",
1633         "MSRIndex": "0x1a6,0x1a7",
1634         "SampleAfterValue": "100000",
1635         "BriefDescription": "Offcore writebacks that HIT in a remote cache",
1636         "Offcore": "1"
1637     },
1638     {
1639         "EventCode": "0xB7, 0xBB",
1640         "MSRValue": "0x808",
1641         "Counter": "0,1,2,3",
1642         "UMask": "0x1",
1643         "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_HITM",
1644         "MSRIndex": "0x1a6,0x1a7",
1645         "SampleAfterValue": "100000",
1646         "BriefDescription": "Offcore writebacks that HITM in a remote cache",
1647         "Offcore": "1"
1648     },
1649     {
1650         "EventCode": "0xB7, 0xBB",
1651         "MSRValue": "0x7F77",
1652         "Counter": "0,1,2,3",
1653         "UMask": "0x1",
1654         "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_CACHE_DRAM",
1655         "MSRIndex": "0x1a6,0x1a7",
1656         "SampleAfterValue": "100000",
1657         "BriefDescription": "Offcore code or data read requests satisfied by any cache or DRAM.",
1658         "Offcore": "1"
1659     },
1660     {
1661         "EventCode": "0xB7, 0xBB",
1662         "MSRValue": "0xFF77",
1663         "Counter": "0,1,2,3",
1664         "UMask": "0x1",
1665         "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_LOCATION",
1666         "MSRIndex": "0x1a6,0x1a7",
1667         "SampleAfterValue": "100000",
1668         "BriefDescription": "All offcore code or data read requests",
1669         "Offcore": "1"
1670     },
1671     {
1672         "EventCode": "0xB7, 0xBB",
1673         "MSRValue": "0x8077",
1674         "Counter": "0,1,2,3",
1675         "UMask": "0x1",
1676         "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.IO_CSR_MMIO",
1677         "MSRIndex": "0x1a6,0x1a7",
1678         "SampleAfterValue": "100000",
1679         "BriefDescription": "Offcore code or data read requests satisfied by the IO, CSR, MMIO unit.",
1680         "Offcore": "1"
1681     },
1682     {
1683         "EventCode": "0xB7, 0xBB",
1684         "MSRValue": "0x177",
1685         "Counter": "0,1,2,3",
1686         "UMask": "0x1",
1687         "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_NO_OTHER_CORE",
1688         "MSRIndex": "0x1a6,0x1a7",
1689         "SampleAfterValue": "100000",
1690         "BriefDescription": "Offcore code or data read requests satisfied by the LLC and not found in a sibling core",
1691         "Offcore": "1"
1692     },
1693     {
1694         "EventCode": "0xB7, 0xBB",
1695         "MSRValue": "0x277",
1696         "Counter": "0,1,2,3",
1697         "UMask": "0x1",
1698         "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_OTHER_CORE_HIT",
1699         "MSRIndex": "0x1a6,0x1a7",
1700         "SampleAfterValue": "100000",
1701         "BriefDescription": "Offcore code or data read requests satisfied by the LLC and HIT in a sibling core",
1702         "Offcore": "1"
1703     },
1704     {
1705         "EventCode": "0xB7, 0xBB",
1706         "MSRValue": "0x477",
1707         "Counter": "0,1,2,3",
1708         "UMask": "0x1",
1709         "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_OTHER_CORE_HITM",
1710         "MSRIndex": "0x1a6,0x1a7",
1711         "SampleAfterValue": "100000",
1712         "BriefDescription": "Offcore code or data read requests satisfied by the LLC  and HITM in a sibling core",
1713         "Offcore": "1"
1714     },
1715     {
1716         "EventCode": "0xB7, 0xBB",
1717         "MSRValue": "0x777",
1718         "Counter": "0,1,2,3",
1719         "UMask": "0x1",
1720         "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LOCAL_CACHE",
1721         "MSRIndex": "0x1a6,0x1a7",
1722         "SampleAfterValue": "100000",
1723         "BriefDescription": "Offcore code or data read requests satisfied by the LLC",
1724         "Offcore": "1"
1725     },
1726     {
1727         "EventCode": "0xB7, 0xBB",
1728         "MSRValue": "0x2777",
1729         "Counter": "0,1,2,3",
1730         "UMask": "0x1",
1731         "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LOCAL_CACHE_DRAM",
1732         "MSRIndex": "0x1a6,0x1a7",
1733         "SampleAfterValue": "100000",
1734         "BriefDescription": "Offcore code or data read requests satisfied by the LLC or local DRAM",
1735         "Offcore": "1"
1736     },
1737     {
1738         "EventCode": "0xB7, 0xBB",
1739         "MSRValue": "0x1877",
1740         "Counter": "0,1,2,3",
1741         "UMask": "0x1",
1742         "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE",
1743         "MSRIndex": "0x1a6,0x1a7",
1744         "SampleAfterValue": "100000",
1745         "BriefDescription": "Offcore code or data read requests satisfied by a remote cache",
1746         "Offcore": "1"
1747     },
1748     {
1749         "EventCode": "0xB7, 0xBB",
1750         "MSRValue": "0x5877",
1751         "Counter": "0,1,2,3",
1752         "UMask": "0x1",
1753         "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_DRAM",
1754         "MSRIndex": "0x1a6,0x1a7",
1755         "SampleAfterValue": "100000",
1756         "BriefDescription": "Offcore code or data read requests satisfied by a remote cache or remote DRAM",
1757         "Offcore": "1"
1758     },
1759     {
1760         "EventCode": "0xB7, 0xBB",
1761         "MSRValue": "0x1077",
1762         "Counter": "0,1,2,3",
1763         "UMask": "0x1",
1764         "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_HIT",
1765         "MSRIndex": "0x1a6,0x1a7",
1766         "SampleAfterValue": "100000",
1767         "BriefDescription": "Offcore code or data read requests that HIT in a remote cache",
1768         "Offcore": "1"
1769     },
1770     {
1771         "EventCode": "0xB7, 0xBB",
1772         "MSRValue": "0x877",
1773         "Counter": "0,1,2,3",
1774         "UMask": "0x1",
1775         "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_HITM",
1776         "MSRIndex": "0x1a6,0x1a7",
1777         "SampleAfterValue": "100000",
1778         "BriefDescription": "Offcore code or data read requests that HITM in a remote cache",
1779         "Offcore": "1"
1780     },
1781     {
1782         "EventCode": "0xB7, 0xBB",
1783         "MSRValue": "0x7F33",
1784         "Counter": "0,1,2,3",
1785         "UMask": "0x1",
1786         "EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_CACHE_DRAM",
1787         "MSRIndex": "0x1a6,0x1a7",
1788         "SampleAfterValue": "100000",
1789         "BriefDescription": "Offcore request = all data, response = any cache_dram",
1790         "Offcore": "1"
1791     },
1792     {
1793         "EventCode": "0xB7, 0xBB",
1794         "MSRValue": "0xFF33",
1795         "Counter": "0,1,2,3",
1796         "UMask": "0x1",
1797         "EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_LOCATION",
1798         "MSRIndex": "0x1a6,0x1a7",
1799         "SampleAfterValue": "100000",
1800         "BriefDescription": "Offcore request = all data, response = any location",
1801         "Offcore": "1"
1802     },
1803     {
1804         "EventCode": "0xB7, 0xBB",
1805         "MSRValue": "0x8033",
1806         "Counter": "0,1,2,3",
1807         "UMask": "0x1",
1808         "EventName": "OFFCORE_RESPONSE.DATA_IN.IO_CSR_MMIO",
1809         "MSRIndex": "0x1a6,0x1a7",
1810         "SampleAfterValue": "100000",
1811         "BriefDescription": "Offcore data reads, RFO's and prefetches satisfied by the IO, CSR, MMIO unit",
1812         "Offcore": "1"
1813     },
1814     {
1815         "EventCode": "0xB7, 0xBB",
1816         "MSRValue": "0x133",
1817         "Counter": "0,1,2,3",
1818         "UMask": "0x1",
1819         "EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_NO_OTHER_CORE",
1820         "MSRIndex": "0x1a6,0x1a7",
1821         "SampleAfterValue": "100000",
1822         "BriefDescription": "Offcore data reads, RFO's and prefetches statisfied by the LLC and not found in a sibling core",
1823         "Offcore": "1"
1824     },
1825     {
1826         "EventCode": "0xB7, 0xBB",
1827         "MSRValue": "0x233",
1828         "Counter": "0,1,2,3",
1829         "UMask": "0x1",
1830         "EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_OTHER_CORE_HIT",
1831         "MSRIndex": "0x1a6,0x1a7",
1832         "SampleAfterValue": "100000",
1833         "BriefDescription": "Offcore data reads, RFO's and prefetches satisfied by the LLC and HIT in a sibling core",
1834         "Offcore": "1"
1835     },
1836     {
1837         "EventCode": "0xB7, 0xBB",
1838         "MSRValue": "0x433",
1839         "Counter": "0,1,2,3",
1840         "UMask": "0x1",
1841         "EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_OTHER_CORE_HITM",
1842         "MSRIndex": "0x1a6,0x1a7",
1843         "SampleAfterValue": "100000",
1844         "BriefDescription": "Offcore data reads, RFO's and prefetches satisfied by the LLC  and HITM in a sibling core",
1845         "Offcore": "1"
1846     },
1847     {
1848         "EventCode": "0xB7, 0xBB",
1849         "MSRValue": "0x733",
1850         "Counter": "0,1,2,3",
1851         "UMask": "0x1",
1852         "EventName": "OFFCORE_RESPONSE.DATA_IN.LOCAL_CACHE",
1853         "MSRIndex": "0x1a6,0x1a7",
1854         "SampleAfterValue": "100000",
1855         "BriefDescription": "Offcore request = all data, response = local cache",
1856         "Offcore": "1"
1857     },
1858     {
1859         "EventCode": "0xB7, 0xBB",
1860         "MSRValue": "0x2733",
1861         "Counter": "0,1,2,3",
1862         "UMask": "0x1",
1863         "EventName": "OFFCORE_RESPONSE.DATA_IN.LOCAL_CACHE_DRAM",
1864         "MSRIndex": "0x1a6,0x1a7",
1865         "SampleAfterValue": "100000",
1866         "BriefDescription": "Offcore request = all data, response = local cache or dram",
1867         "Offcore": "1"
1868     },
1869     {
1870         "EventCode": "0xB7, 0xBB",
1871         "MSRValue": "0x1833",
1872         "Counter": "0,1,2,3",
1873         "UMask": "0x1",
1874         "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE",
1875         "MSRIndex": "0x1a6,0x1a7",
1876         "SampleAfterValue": "100000",
1877         "BriefDescription": "Offcore request = all data, response = remote cache",
1878         "Offcore": "1"
1879     },
1880     {
1881         "EventCode": "0xB7, 0xBB",
1882         "MSRValue": "0x5833",
1883         "Counter": "0,1,2,3",
1884         "UMask": "0x1",
1885         "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_DRAM",
1886         "MSRIndex": "0x1a6,0x1a7",
1887         "SampleAfterValue": "100000",
1888         "BriefDescription": "Offcore request = all data, response = remote cache or dram",
1889         "Offcore": "1"
1890     },
1891     {
1892         "EventCode": "0xB7, 0xBB",
1893         "MSRValue": "0x1033",
1894         "Counter": "0,1,2,3",
1895         "UMask": "0x1",
1896         "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_HIT",
1897         "MSRIndex": "0x1a6,0x1a7",
1898         "SampleAfterValue": "100000",
1899         "BriefDescription": "Offcore data reads, RFO's and prefetches that HIT in a remote cache ",
1900         "Offcore": "1"
1901     },
1902     {
1903         "EventCode": "0xB7, 0xBB",
1904         "MSRValue": "0x833",
1905         "Counter": "0,1,2,3",
1906         "UMask": "0x1",
1907         "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_HITM",
1908         "MSRIndex": "0x1a6,0x1a7",
1909         "SampleAfterValue": "100000",
1910         "BriefDescription": "Offcore data reads, RFO's and prefetches that HITM in a remote cache",
1911         "Offcore": "1"
1912     },
1913     {
1914         "EventCode": "0xB7, 0xBB",
1915         "MSRValue": "0x7F03",
1916         "Counter": "0,1,2,3",
1917         "UMask": "0x1",
1918         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_CACHE_DRAM",
1919         "MSRIndex": "0x1a6,0x1a7",
1920         "SampleAfterValue": "100000",
1921         "BriefDescription": "Offcore demand data requests satisfied by any cache or DRAM",
1922         "Offcore": "1"
1923     },
1924     {
1925         "EventCode": "0xB7, 0xBB",
1926         "MSRValue": "0xFF03",
1927         "Counter": "0,1,2,3",
1928         "UMask": "0x1",
1929         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_LOCATION",
1930         "MSRIndex": "0x1a6,0x1a7",
1931         "SampleAfterValue": "100000",
1932         "BriefDescription": "All offcore demand data requests",
1933         "Offcore": "1"
1934     },
1935     {
1936         "EventCode": "0xB7, 0xBB",
1937         "MSRValue": "0x8003",
1938         "Counter": "0,1,2,3",
1939         "UMask": "0x1",
1940         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.IO_CSR_MMIO",
1941         "MSRIndex": "0x1a6,0x1a7",
1942         "SampleAfterValue": "100000",
1943         "BriefDescription": "Offcore demand data requests satisfied by the IO, CSR, MMIO unit.",
1944         "Offcore": "1"
1945     },
1946     {
1947         "EventCode": "0xB7, 0xBB",
1948         "MSRValue": "0x103",
1949         "Counter": "0,1,2,3",
1950         "UMask": "0x1",
1951         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_NO_OTHER_CORE",
1952         "MSRIndex": "0x1a6,0x1a7",
1953         "SampleAfterValue": "100000",
1954         "BriefDescription": "Offcore demand data requests satisfied by the LLC and not found in a sibling core",
1955         "Offcore": "1"
1956     },
1957     {
1958         "EventCode": "0xB7, 0xBB",
1959         "MSRValue": "0x203",
1960         "Counter": "0,1,2,3",
1961         "UMask": "0x1",
1962         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_OTHER_CORE_HIT",
1963         "MSRIndex": "0x1a6,0x1a7",
1964         "SampleAfterValue": "100000",
1965         "BriefDescription": "Offcore demand data requests satisfied by the LLC and HIT in a sibling core",
1966         "Offcore": "1"
1967     },
1968     {
1969         "EventCode": "0xB7, 0xBB",
1970         "MSRValue": "0x403",
1971         "Counter": "0,1,2,3",
1972         "UMask": "0x1",
1973         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_OTHER_CORE_HITM",
1974         "MSRIndex": "0x1a6,0x1a7",
1975         "SampleAfterValue": "100000",
1976         "BriefDescription": "Offcore demand data requests satisfied by the LLC  and HITM in a sibling core",
1977         "Offcore": "1"
1978     },
1979     {
1980         "EventCode": "0xB7, 0xBB",
1981         "MSRValue": "0x703",
1982         "Counter": "0,1,2,3",
1983         "UMask": "0x1",
1984         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LOCAL_CACHE",
1985         "MSRIndex": "0x1a6,0x1a7",
1986         "SampleAfterValue": "100000",
1987         "BriefDescription": "Offcore demand data requests satisfied by the LLC",
1988         "Offcore": "1"
1989     },
1990     {
1991         "EventCode": "0xB7, 0xBB",
1992         "MSRValue": "0x2703",
1993         "Counter": "0,1,2,3",
1994         "UMask": "0x1",
1995         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LOCAL_CACHE_DRAM",
1996         "MSRIndex": "0x1a6,0x1a7",
1997         "SampleAfterValue": "100000",
1998         "BriefDescription": "Offcore demand data requests satisfied by the LLC or local DRAM",
1999         "Offcore": "1"
2000     },
2001     {
2002         "EventCode": "0xB7, 0xBB",
2003         "MSRValue": "0x1803",
2004         "Counter": "0,1,2,3",
2005         "UMask": "0x1",
2006         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE",
2007         "MSRIndex": "0x1a6,0x1a7",
2008         "SampleAfterValue": "100000",
2009         "BriefDescription": "Offcore demand data requests satisfied by a remote cache",
2010         "Offcore": "1"
2011     },
2012     {
2013         "EventCode": "0xB7, 0xBB",
2014         "MSRValue": "0x5803",
2015         "Counter": "0,1,2,3",
2016         "UMask": "0x1",
2017         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_DRAM",
2018         "MSRIndex": "0x1a6,0x1a7",
2019         "SampleAfterValue": "100000",
2020         "BriefDescription": "Offcore demand data requests satisfied by a remote cache or remote DRAM",
2021         "Offcore": "1"
2022     },
2023     {
2024         "EventCode": "0xB7, 0xBB",
2025         "MSRValue": "0x1003",
2026         "Counter": "0,1,2,3",
2027         "UMask": "0x1",
2028         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_HIT",
2029         "MSRIndex": "0x1a6,0x1a7",
2030         "SampleAfterValue": "100000",
2031         "BriefDescription": "Offcore demand data requests that HIT in a remote cache",
2032         "Offcore": "1"
2033     },
2034     {
2035         "EventCode": "0xB7, 0xBB",
2036         "MSRValue": "0x803",
2037         "Counter": "0,1,2,3",
2038         "UMask": "0x1",
2039         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_HITM",
2040         "MSRIndex": "0x1a6,0x1a7",
2041         "SampleAfterValue": "100000",
2042         "BriefDescription": "Offcore demand data requests that HITM in a remote cache",
2043         "Offcore": "1"
2044     },
2045     {
2046         "EventCode": "0xB7, 0xBB",
2047         "MSRValue": "0x7F01",
2048         "Counter": "0,1,2,3",
2049         "UMask": "0x1",
2050         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_CACHE_DRAM",
2051         "MSRIndex": "0x1a6,0x1a7",
2052         "SampleAfterValue": "100000",
2053         "BriefDescription": "Offcore demand data reads satisfied by any cache or DRAM.",
2054         "Offcore": "1"
2055     },
2056     {
2057         "EventCode": "0xB7, 0xBB",
2058         "MSRValue": "0xFF01",
2059         "Counter": "0,1,2,3",
2060         "UMask": "0x1",
2061         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_LOCATION",
2062         "MSRIndex": "0x1a6,0x1a7",
2063         "SampleAfterValue": "100000",
2064         "BriefDescription": "All offcore demand data reads",
2065         "Offcore": "1"
2066     },
2067     {
2068         "EventCode": "0xB7, 0xBB",
2069         "MSRValue": "0x8001",
2070         "Counter": "0,1,2,3",
2071         "UMask": "0x1",
2072         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.IO_CSR_MMIO",
2073         "MSRIndex": "0x1a6,0x1a7",
2074         "SampleAfterValue": "100000",
2075         "BriefDescription": "Offcore demand data reads satisfied by the IO, CSR, MMIO unit",
2076         "Offcore": "1"
2077     },
2078     {
2079         "EventCode": "0xB7, 0xBB",
2080         "MSRValue": "0x101",
2081         "Counter": "0,1,2,3",
2082         "UMask": "0x1",
2083         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_NO_OTHER_CORE",
2084         "MSRIndex": "0x1a6,0x1a7",
2085         "SampleAfterValue": "100000",
2086         "BriefDescription": "Offcore demand data reads satisfied by the LLC and not found in a sibling core",
2087         "Offcore": "1"
2088     },
2089     {
2090         "EventCode": "0xB7, 0xBB",
2091         "MSRValue": "0x201",
2092         "Counter": "0,1,2,3",
2093         "UMask": "0x1",
2094         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_OTHER_CORE_HIT",
2095         "MSRIndex": "0x1a6,0x1a7",
2096         "SampleAfterValue": "100000",
2097         "BriefDescription": "Offcore demand data reads satisfied by the LLC and HIT in a sibling core",
2098         "Offcore": "1"
2099     },
2100     {
2101         "EventCode": "0xB7, 0xBB",
2102         "MSRValue": "0x401",
2103         "Counter": "0,1,2,3",
2104         "UMask": "0x1",
2105         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_OTHER_CORE_HITM",
2106         "MSRIndex": "0x1a6,0x1a7",
2107         "SampleAfterValue": "100000",
2108         "BriefDescription": "Offcore demand data reads satisfied by the LLC  and HITM in a sibling core",
2109         "Offcore": "1"
2110     },
2111     {
2112         "EventCode": "0xB7, 0xBB",
2113         "MSRValue": "0x701",
2114         "Counter": "0,1,2,3",
2115         "UMask": "0x1",
2116         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LOCAL_CACHE",
2117         "MSRIndex": "0x1a6,0x1a7",
2118         "SampleAfterValue": "100000",
2119         "BriefDescription": "Offcore demand data reads satisfied by the LLC",
2120         "Offcore": "1"
2121     },
2122     {
2123         "EventCode": "0xB7, 0xBB",
2124         "MSRValue": "0x2701",
2125         "Counter": "0,1,2,3",
2126         "UMask": "0x1",
2127         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LOCAL_CACHE_DRAM",
2128         "MSRIndex": "0x1a6,0x1a7",
2129         "SampleAfterValue": "100000",
2130         "BriefDescription": "Offcore demand data reads satisfied by the LLC or local DRAM",
2131         "Offcore": "1"
2132     },
2133     {
2134         "EventCode": "0xB7, 0xBB",
2135         "MSRValue": "0x1801",
2136         "Counter": "0,1,2,3",
2137         "UMask": "0x1",
2138         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE",
2139         "MSRIndex": "0x1a6,0x1a7",
2140         "SampleAfterValue": "100000",
2141         "BriefDescription": "Offcore demand data reads satisfied by a remote cache",
2142         "Offcore": "1"
2143     },
2144     {
2145         "EventCode": "0xB7, 0xBB",
2146         "MSRValue": "0x5801",
2147         "Counter": "0,1,2,3",
2148         "UMask": "0x1",
2149         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_DRAM",
2150         "MSRIndex": "0x1a6,0x1a7",
2151         "SampleAfterValue": "100000",
2152         "BriefDescription": "Offcore demand data reads satisfied by a remote cache or remote DRAM",
2153         "Offcore": "1"
2154     },
2155     {
2156         "EventCode": "0xB7, 0xBB",
2157         "MSRValue": "0x1001",
2158         "Counter": "0,1,2,3",
2159         "UMask": "0x1",
2160         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_HIT",
2161         "MSRIndex": "0x1a6,0x1a7",
2162         "SampleAfterValue": "100000",
2163         "BriefDescription": "Offcore demand data reads that HIT in a remote cache",
2164         "Offcore": "1"
2165     },
2166     {
2167         "EventCode": "0xB7, 0xBB",
2168         "MSRValue": "0x801",
2169         "Counter": "0,1,2,3",
2170         "UMask": "0x1",
2171         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_HITM",
2172         "MSRIndex": "0x1a6,0x1a7",
2173         "SampleAfterValue": "100000",
2174         "BriefDescription": "Offcore demand data reads that HITM in a remote cache",
2175         "Offcore": "1"
2176     },
2177     {
2178         "EventCode": "0xB7, 0xBB",
2179         "MSRValue": "0x7F04",
2180         "Counter": "0,1,2,3",
2181         "UMask": "0x1",
2182         "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_CACHE_DRAM",
2183         "MSRIndex": "0x1a6,0x1a7",
2184         "SampleAfterValue": "100000",
2185         "BriefDescription": "Offcore demand code reads satisfied by any cache or DRAM.",
2186         "Offcore": "1"
2187     },
2188     {
2189         "EventCode": "0xB7, 0xBB",
2190         "MSRValue": "0xFF04",
2191         "Counter": "0,1,2,3",
2192         "UMask": "0x1",
2193         "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_LOCATION",
2194         "MSRIndex": "0x1a6,0x1a7",
2195         "SampleAfterValue": "100000",
2196         "BriefDescription": "All offcore demand code reads",
2197         "Offcore": "1"
2198     },
2199     {
2200         "EventCode": "0xB7, 0xBB",
2201         "MSRValue": "0x8004",
2202         "Counter": "0,1,2,3",
2203         "UMask": "0x1",
2204         "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.IO_CSR_MMIO",
2205         "MSRIndex": "0x1a6,0x1a7",
2206         "SampleAfterValue": "100000",
2207         "BriefDescription": "Offcore demand code reads satisfied by the IO, CSR, MMIO unit",
2208         "Offcore": "1"
2209     },
2210     {
2211         "EventCode": "0xB7, 0xBB",
2212         "MSRValue": "0x104",
2213         "Counter": "0,1,2,3",
2214         "UMask": "0x1",
2215         "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_NO_OTHER_CORE",
2216         "MSRIndex": "0x1a6,0x1a7",
2217         "SampleAfterValue": "100000",
2218         "BriefDescription": "Offcore demand code reads satisfied by the LLC and not found in a sibling core",
2219         "Offcore": "1"
2220     },
2221     {
2222         "EventCode": "0xB7, 0xBB",
2223         "MSRValue": "0x204",
2224         "Counter": "0,1,2,3",
2225         "UMask": "0x1",
2226         "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_OTHER_CORE_HIT",
2227         "MSRIndex": "0x1a6,0x1a7",
2228         "SampleAfterValue": "100000",
2229         "BriefDescription": "Offcore demand code reads satisfied by the LLC and HIT in a sibling core",
2230         "Offcore": "1"
2231     },
2232     {
2233         "EventCode": "0xB7, 0xBB",
2234         "MSRValue": "0x404",
2235         "Counter": "0,1,2,3",
2236         "UMask": "0x1",
2237         "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_OTHER_CORE_HITM",
2238         "MSRIndex": "0x1a6,0x1a7",
2239         "SampleAfterValue": "100000",
2240         "BriefDescription": "Offcore demand code reads satisfied by the LLC  and HITM in a sibling core",
2241         "Offcore": "1"
2242     },
2243     {
2244         "EventCode": "0xB7, 0xBB",
2245         "MSRValue": "0x704",
2246         "Counter": "0,1,2,3",
2247         "UMask": "0x1",
2248         "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LOCAL_CACHE",
2249         "MSRIndex": "0x1a6,0x1a7",
2250         "SampleAfterValue": "100000",
2251         "BriefDescription": "Offcore demand code reads satisfied by the LLC",
2252         "Offcore": "1"
2253     },
2254     {
2255         "EventCode": "0xB7, 0xBB",
2256         "MSRValue": "0x2704",
2257         "Counter": "0,1,2,3",
2258         "UMask": "0x1",
2259         "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LOCAL_CACHE_DRAM",
2260         "MSRIndex": "0x1a6,0x1a7",
2261         "SampleAfterValue": "100000",
2262         "BriefDescription": "Offcore demand code reads satisfied by the LLC or local DRAM",
2263         "Offcore": "1"
2264     },
2265     {
2266         "EventCode": "0xB7, 0xBB",
2267         "MSRValue": "0x1804",
2268         "Counter": "0,1,2,3",
2269         "UMask": "0x1",
2270         "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE",
2271         "MSRIndex": "0x1a6,0x1a7",
2272         "SampleAfterValue": "100000",
2273         "BriefDescription": "Offcore demand code reads satisfied by a remote cache",
2274         "Offcore": "1"
2275     },
2276     {
2277         "EventCode": "0xB7, 0xBB",
2278         "MSRValue": "0x5804",
2279         "Counter": "0,1,2,3",
2280         "UMask": "0x1",
2281         "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_DRAM",
2282         "MSRIndex": "0x1a6,0x1a7",
2283         "SampleAfterValue": "100000",
2284         "BriefDescription": "Offcore demand code reads satisfied by a remote cache or remote DRAM",
2285         "Offcore": "1"
2286     },
2287     {
2288         "EventCode": "0xB7, 0xBB",
2289         "MSRValue": "0x1004",
2290         "Counter": "0,1,2,3",
2291         "UMask": "0x1",
2292         "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_HIT",
2293         "MSRIndex": "0x1a6,0x1a7",
2294         "SampleAfterValue": "100000",
2295         "BriefDescription": "Offcore demand code reads that HIT in a remote cache",
2296         "Offcore": "1"
2297     },
2298     {
2299         "EventCode": "0xB7, 0xBB",
2300         "MSRValue": "0x804",
2301         "Counter": "0,1,2,3",
2302         "UMask": "0x1",
2303         "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_HITM",
2304         "MSRIndex": "0x1a6,0x1a7",
2305         "SampleAfterValue": "100000",
2306         "BriefDescription": "Offcore demand code reads that HITM in a remote cache",
2307         "Offcore": "1"
2308     },
2309     {
2310         "EventCode": "0xB7, 0xBB",
2311         "MSRValue": "0x7F02",
2312         "Counter": "0,1,2,3",
2313         "UMask": "0x1",
2314         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_CACHE_DRAM",
2315         "MSRIndex": "0x1a6,0x1a7",
2316         "SampleAfterValue": "100000",
2317         "BriefDescription": "Offcore demand RFO requests satisfied by any cache or DRAM.",
2318         "Offcore": "1"
2319     },
2320     {
2321         "EventCode": "0xB7, 0xBB",
2322         "MSRValue": "0xFF02",
2323         "Counter": "0,1,2,3",
2324         "UMask": "0x1",
2325         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_LOCATION",
2326         "MSRIndex": "0x1a6,0x1a7",
2327         "SampleAfterValue": "100000",
2328         "BriefDescription": "All offcore demand RFO requests",
2329         "Offcore": "1"
2330     },
2331     {
2332         "EventCode": "0xB7, 0xBB",
2333         "MSRValue": "0x8002",
2334         "Counter": "0,1,2,3",
2335         "UMask": "0x1",
2336         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.IO_CSR_MMIO",
2337         "MSRIndex": "0x1a6,0x1a7",
2338         "SampleAfterValue": "100000",
2339         "BriefDescription": "Offcore demand RFO requests satisfied by the IO, CSR, MMIO unit",
2340         "Offcore": "1"
2341     },
2342     {
2343         "EventCode": "0xB7, 0xBB",
2344         "MSRValue": "0x102",
2345         "Counter": "0,1,2,3",
2346         "UMask": "0x1",
2347         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_NO_OTHER_CORE",
2348         "MSRIndex": "0x1a6,0x1a7",
2349         "SampleAfterValue": "100000",
2350         "BriefDescription": "Offcore demand RFO requests satisfied by the LLC and not found in a sibling core",
2351         "Offcore": "1"
2352     },
2353     {
2354         "EventCode": "0xB7, 0xBB",
2355         "MSRValue": "0x202",
2356         "Counter": "0,1,2,3",
2357         "UMask": "0x1",
2358         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_OTHER_CORE_HIT",
2359         "MSRIndex": "0x1a6,0x1a7",
2360         "SampleAfterValue": "100000",
2361         "BriefDescription": "Offcore demand RFO requests satisfied by the LLC and HIT in a sibling core",
2362         "Offcore": "1"
2363     },
2364     {
2365         "EventCode": "0xB7, 0xBB",
2366         "MSRValue": "0x402",
2367         "Counter": "0,1,2,3",
2368         "UMask": "0x1",
2369         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_OTHER_CORE_HITM",
2370         "MSRIndex": "0x1a6,0x1a7",
2371         "SampleAfterValue": "100000",
2372         "BriefDescription": "Offcore demand RFO requests satisfied by the LLC  and HITM in a sibling core",
2373         "Offcore": "1"
2374     },
2375     {
2376         "EventCode": "0xB7, 0xBB",
2377         "MSRValue": "0x702",
2378         "Counter": "0,1,2,3",
2379         "UMask": "0x1",
2380         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LOCAL_CACHE",
2381         "MSRIndex": "0x1a6,0x1a7",
2382         "SampleAfterValue": "100000",
2383         "BriefDescription": "Offcore demand RFO requests satisfied by the LLC",
2384         "Offcore": "1"
2385     },
2386     {
2387         "EventCode": "0xB7, 0xBB",
2388         "MSRValue": "0x2702",
2389         "Counter": "0,1,2,3",
2390         "UMask": "0x1",
2391         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LOCAL_CACHE_DRAM",
2392         "MSRIndex": "0x1a6,0x1a7",
2393         "SampleAfterValue": "100000",
2394         "BriefDescription": "Offcore demand RFO requests satisfied by the LLC or local DRAM",
2395         "Offcore": "1"
2396     },
2397     {
2398         "EventCode": "0xB7, 0xBB",
2399         "MSRValue": "0x1802",
2400         "Counter": "0,1,2,3",
2401         "UMask": "0x1",
2402         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE",
2403         "MSRIndex": "0x1a6,0x1a7",
2404         "SampleAfterValue": "100000",
2405         "BriefDescription": "Offcore demand RFO requests satisfied by a remote cache",
2406         "Offcore": "1"
2407     },
2408     {
2409         "EventCode": "0xB7, 0xBB",
2410         "MSRValue": "0x5802",
2411         "Counter": "0,1,2,3",
2412         "UMask": "0x1",
2413         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_DRAM",
2414         "MSRIndex": "0x1a6,0x1a7",
2415         "SampleAfterValue": "100000",
2416         "BriefDescription": "Offcore demand RFO requests satisfied by a remote cache or remote DRAM",
2417         "Offcore": "1"
2418     },
2419     {
2420         "EventCode": "0xB7, 0xBB",
2421         "MSRValue": "0x1002",
2422         "Counter": "0,1,2,3",
2423         "UMask": "0x1",
2424         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_HIT",
2425         "MSRIndex": "0x1a6,0x1a7",
2426         "SampleAfterValue": "100000",
2427         "BriefDescription": "Offcore demand RFO requests that HIT in a remote cache",
2428         "Offcore": "1"
2429     },
2430     {
2431         "EventCode": "0xB7, 0xBB",
2432         "MSRValue": "0x802",
2433         "Counter": "0,1,2,3",
2434         "UMask": "0x1",
2435         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_HITM",
2436         "MSRIndex": "0x1a6,0x1a7",
2437         "SampleAfterValue": "100000",
2438         "BriefDescription": "Offcore demand RFO requests that HITM in a remote cache",
2439         "Offcore": "1"
2440     },
2441     {
2442         "EventCode": "0xB7, 0xBB",
2443         "MSRValue": "0x7F80",
2444         "Counter": "0,1,2,3",
2445         "UMask": "0x1",
2446         "EventName": "OFFCORE_RESPONSE.OTHER.ANY_CACHE_DRAM",
2447         "MSRIndex": "0x1a6,0x1a7",
2448         "SampleAfterValue": "100000",
2449         "BriefDescription": "Offcore other requests satisfied by any cache or DRAM.",
2450         "Offcore": "1"
2451     },
2452     {
2453         "EventCode": "0xB7, 0xBB",
2454         "MSRValue": "0xFF80",
2455         "Counter": "0,1,2,3",
2456         "UMask": "0x1",
2457         "EventName": "OFFCORE_RESPONSE.OTHER.ANY_LOCATION",
2458         "MSRIndex": "0x1a6,0x1a7",
2459         "SampleAfterValue": "100000",
2460         "BriefDescription": "All offcore other requests",
2461         "Offcore": "1"
2462     },
2463     {
2464         "EventCode": "0xB7, 0xBB",
2465         "MSRValue": "0x8080",
2466         "Counter": "0,1,2,3",
2467         "UMask": "0x1",
2468         "EventName": "OFFCORE_RESPONSE.OTHER.IO_CSR_MMIO",
2469         "MSRIndex": "0x1a6,0x1a7",
2470         "SampleAfterValue": "100000",
2471         "BriefDescription": "Offcore other requests satisfied by the IO, CSR, MMIO unit",
2472         "Offcore": "1"
2473     },
2474     {
2475         "EventCode": "0xB7, 0xBB",
2476         "MSRValue": "0x180",
2477         "Counter": "0,1,2,3",
2478         "UMask": "0x1",
2479         "EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_NO_OTHER_CORE",
2480         "MSRIndex": "0x1a6,0x1a7",
2481         "SampleAfterValue": "100000",
2482         "BriefDescription": "Offcore other requests satisfied by the LLC and not found in a sibling core",
2483         "Offcore": "1"
2484     },
2485     {
2486         "EventCode": "0xB7, 0xBB",
2487         "MSRValue": "0x280",
2488         "Counter": "0,1,2,3",
2489         "UMask": "0x1",
2490         "EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_OTHER_CORE_HIT",
2491         "MSRIndex": "0x1a6,0x1a7",
2492         "SampleAfterValue": "100000",
2493         "BriefDescription": "Offcore other requests satisfied by the LLC and HIT in a sibling core",
2494         "Offcore": "1"
2495     },
2496     {
2497         "EventCode": "0xB7, 0xBB",
2498         "MSRValue": "0x480",
2499         "Counter": "0,1,2,3",
2500         "UMask": "0x1",
2501         "EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_OTHER_CORE_HITM",
2502         "MSRIndex": "0x1a6,0x1a7",
2503         "SampleAfterValue": "100000",
2504         "BriefDescription": "Offcore other requests satisfied by the LLC  and HITM in a sibling core",
2505         "Offcore": "1"
2506     },
2507     {
2508         "EventCode": "0xB7, 0xBB",
2509         "MSRValue": "0x780",
2510         "Counter": "0,1,2,3",
2511         "UMask": "0x1",
2512         "EventName": "OFFCORE_RESPONSE.OTHER.LOCAL_CACHE",
2513         "MSRIndex": "0x1a6,0x1a7",
2514         "SampleAfterValue": "100000",
2515         "BriefDescription": "Offcore other requests satisfied by the LLC",
2516         "Offcore": "1"
2517     },
2518     {
2519         "EventCode": "0xB7, 0xBB",
2520         "MSRValue": "0x2780",
2521         "Counter": "0,1,2,3",
2522         "UMask": "0x1",
2523         "EventName": "OFFCORE_RESPONSE.OTHER.LOCAL_CACHE_DRAM",
2524         "MSRIndex": "0x1a6,0x1a7",
2525         "SampleAfterValue": "100000",
2526         "BriefDescription": "Offcore other requests satisfied by the LLC or local DRAM",
2527         "Offcore": "1"
2528     },
2529     {
2530         "EventCode": "0xB7, 0xBB",
2531         "MSRValue": "0x1880",
2532         "Counter": "0,1,2,3",
2533         "UMask": "0x1",
2534         "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE",
2535         "MSRIndex": "0x1a6,0x1a7",
2536         "SampleAfterValue": "100000",
2537         "BriefDescription": "Offcore other requests satisfied by a remote cache",
2538         "Offcore": "1"
2539     },
2540     {
2541         "EventCode": "0xB7, 0xBB",
2542         "MSRValue": "0x5880",
2543         "Counter": "0,1,2,3",
2544         "UMask": "0x1",
2545         "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE_DRAM",
2546         "MSRIndex": "0x1a6,0x1a7",
2547         "SampleAfterValue": "100000",
2548         "BriefDescription": "Offcore other requests satisfied by a remote cache or remote DRAM",
2549         "Offcore": "1"
2550     },
2551     {
2552         "EventCode": "0xB7, 0xBB",
2553         "MSRValue": "0x1080",
2554         "Counter": "0,1,2,3",
2555         "UMask": "0x1",
2556         "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE_HIT",
2557         "MSRIndex": "0x1a6,0x1a7",
2558         "SampleAfterValue": "100000",
2559         "BriefDescription": "Offcore other requests that HIT in a remote cache",
2560         "Offcore": "1"
2561     },
2562     {
2563         "EventCode": "0xB7, 0xBB",
2564         "MSRValue": "0x880",
2565         "Counter": "0,1,2,3",
2566         "UMask": "0x1",
2567         "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE_HITM",
2568         "MSRIndex": "0x1a6,0x1a7",
2569         "SampleAfterValue": "100000",
2570         "BriefDescription": "Offcore other requests that HITM in a remote cache",
2571         "Offcore": "1"
2572     },
2573     {
2574         "EventCode": "0xB7, 0xBB",
2575         "MSRValue": "0x7F50",
2576         "Counter": "0,1,2,3",
2577         "UMask": "0x1",
2578         "EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_CACHE_DRAM",
2579         "MSRIndex": "0x1a6,0x1a7",
2580         "SampleAfterValue": "100000",
2581         "BriefDescription": "Offcore prefetch data requests satisfied by any cache or DRAM",
2582         "Offcore": "1"
2583     },
2584     {
2585         "EventCode": "0xB7, 0xBB",
2586         "MSRValue": "0xFF50",
2587         "Counter": "0,1,2,3",
2588         "UMask": "0x1",
2589         "EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_LOCATION",
2590         "MSRIndex": "0x1a6,0x1a7",
2591         "SampleAfterValue": "100000",
2592         "BriefDescription": "All offcore prefetch data requests",
2593         "Offcore": "1"
2594     },
2595     {
2596         "EventCode": "0xB7, 0xBB",
2597         "MSRValue": "0x8050",
2598         "Counter": "0,1,2,3",
2599         "UMask": "0x1",
2600         "EventName": "OFFCORE_RESPONSE.PF_DATA.IO_CSR_MMIO",
2601         "MSRIndex": "0x1a6,0x1a7",
2602         "SampleAfterValue": "100000",
2603         "BriefDescription": "Offcore prefetch data requests satisfied by the IO, CSR, MMIO unit.",
2604         "Offcore": "1"
2605     },
2606     {
2607         "EventCode": "0xB7, 0xBB",
2608         "MSRValue": "0x150",
2609         "Counter": "0,1,2,3",
2610         "UMask": "0x1",
2611         "EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_NO_OTHER_CORE",
2612         "MSRIndex": "0x1a6,0x1a7",
2613         "SampleAfterValue": "100000",
2614         "BriefDescription": "Offcore prefetch data requests satisfied by the LLC and not found in a sibling core",
2615         "Offcore": "1"
2616     },
2617     {
2618         "EventCode": "0xB7, 0xBB",
2619         "MSRValue": "0x250",
2620         "Counter": "0,1,2,3",
2621         "UMask": "0x1",
2622         "EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_OTHER_CORE_HIT",
2623         "MSRIndex": "0x1a6,0x1a7",
2624         "SampleAfterValue": "100000",
2625         "BriefDescription": "Offcore prefetch data requests satisfied by the LLC and HIT in a sibling core",
2626         "Offcore": "1"
2627     },
2628     {
2629         "EventCode": "0xB7, 0xBB",
2630         "MSRValue": "0x450",
2631         "Counter": "0,1,2,3",
2632         "UMask": "0x1",
2633         "EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_OTHER_CORE_HITM",
2634         "MSRIndex": "0x1a6,0x1a7",
2635         "SampleAfterValue": "100000",
2636         "BriefDescription": "Offcore prefetch data requests satisfied by the LLC  and HITM in a sibling core",
2637         "Offcore": "1"
2638     },
2639     {
2640         "EventCode": "0xB7, 0xBB",
2641         "MSRValue": "0x750",
2642         "Counter": "0,1,2,3",
2643         "UMask": "0x1",
2644         "EventName": "OFFCORE_RESPONSE.PF_DATA.LOCAL_CACHE",
2645         "MSRIndex": "0x1a6,0x1a7",
2646         "SampleAfterValue": "100000",
2647         "BriefDescription": "Offcore prefetch data requests satisfied by the LLC",
2648         "Offcore": "1"
2649     },
2650     {
2651         "EventCode": "0xB7, 0xBB",
2652         "MSRValue": "0x2750",
2653         "Counter": "0,1,2,3",
2654         "UMask": "0x1",
2655         "EventName": "OFFCORE_RESPONSE.PF_DATA.LOCAL_CACHE_DRAM",
2656         "MSRIndex": "0x1a6,0x1a7",
2657         "SampleAfterValue": "100000",
2658         "BriefDescription": "Offcore prefetch data requests satisfied by the LLC or local DRAM",
2659         "Offcore": "1"
2660     },
2661     {
2662         "EventCode": "0xB7, 0xBB",
2663         "MSRValue": "0x1850",
2664         "Counter": "0,1,2,3",
2665         "UMask": "0x1",
2666         "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE",
2667         "MSRIndex": "0x1a6,0x1a7",
2668         "SampleAfterValue": "100000",
2669         "BriefDescription": "Offcore prefetch data requests satisfied by a remote cache",
2670         "Offcore": "1"
2671     },
2672     {
2673         "EventCode": "0xB7, 0xBB",
2674         "MSRValue": "0x5850",
2675         "Counter": "0,1,2,3",
2676         "UMask": "0x1",
2677         "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE_DRAM",
2678         "MSRIndex": "0x1a6,0x1a7",
2679         "SampleAfterValue": "100000",
2680         "BriefDescription": "Offcore prefetch data requests satisfied by a remote cache or remote DRAM",
2681         "Offcore": "1"
2682     },
2683     {
2684         "EventCode": "0xB7, 0xBB",
2685         "MSRValue": "0x1050",
2686         "Counter": "0,1,2,3",
2687         "UMask": "0x1",
2688         "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE_HIT",
2689         "MSRIndex": "0x1a6,0x1a7",
2690         "SampleAfterValue": "100000",
2691         "BriefDescription": "Offcore prefetch data requests that HIT in a remote cache",
2692         "Offcore": "1"
2693     },
2694     {
2695         "EventCode": "0xB7, 0xBB",
2696         "MSRValue": "0x850",
2697         "Counter": "0,1,2,3",
2698         "UMask": "0x1",
2699         "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE_HITM",
2700         "MSRIndex": "0x1a6,0x1a7",
2701         "SampleAfterValue": "100000",
2702         "BriefDescription": "Offcore prefetch data requests that HITM in a remote cache",
2703         "Offcore": "1"
2704     },
2705     {
2706         "EventCode": "0xB7, 0xBB",
2707         "MSRValue": "0x7F10",
2708         "Counter": "0,1,2,3",
2709         "UMask": "0x1",
2710         "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_CACHE_DRAM",
2711         "MSRIndex": "0x1a6,0x1a7",
2712         "SampleAfterValue": "100000",
2713         "BriefDescription": "Offcore prefetch data reads satisfied by any cache or DRAM.",
2714         "Offcore": "1"
2715     },
2716     {
2717         "EventCode": "0xB7, 0xBB",
2718         "MSRValue": "0xFF10",
2719         "Counter": "0,1,2,3",
2720         "UMask": "0x1",
2721         "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_LOCATION",
2722         "MSRIndex": "0x1a6,0x1a7",
2723         "SampleAfterValue": "100000",
2724         "BriefDescription": "All offcore prefetch data reads",
2725         "Offcore": "1"
2726     },
2727     {
2728         "EventCode": "0xB7, 0xBB",
2729         "MSRValue": "0x8010",
2730         "Counter": "0,1,2,3",
2731         "UMask": "0x1",
2732         "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.IO_CSR_MMIO",
2733         "MSRIndex": "0x1a6,0x1a7",
2734         "SampleAfterValue": "100000",
2735         "BriefDescription": "Offcore prefetch data reads satisfied by the IO, CSR, MMIO unit",
2736         "Offcore": "1"
2737     },
2738     {
2739         "EventCode": "0xB7, 0xBB",
2740         "MSRValue": "0x110",
2741         "Counter": "0,1,2,3",
2742         "UMask": "0x1",
2743         "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_NO_OTHER_CORE",
2744         "MSRIndex": "0x1a6,0x1a7",
2745         "SampleAfterValue": "100000",
2746         "BriefDescription": "Offcore prefetch data reads satisfied by the LLC and not found in a sibling core",
2747         "Offcore": "1"
2748     },
2749     {
2750         "EventCode": "0xB7, 0xBB",
2751         "MSRValue": "0x210",
2752         "Counter": "0,1,2,3",
2753         "UMask": "0x1",
2754         "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_OTHER_CORE_HIT",
2755         "MSRIndex": "0x1a6,0x1a7",
2756         "SampleAfterValue": "100000",
2757         "BriefDescription": "Offcore prefetch data reads satisfied by the LLC and HIT in a sibling core",
2758         "Offcore": "1"
2759     },
2760     {
2761         "EventCode": "0xB7, 0xBB",
2762         "MSRValue": "0x410",
2763         "Counter": "0,1,2,3",
2764         "UMask": "0x1",
2765         "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_OTHER_CORE_HITM",
2766         "MSRIndex": "0x1a6,0x1a7",
2767         "SampleAfterValue": "100000",
2768         "BriefDescription": "Offcore prefetch data reads satisfied by the LLC  and HITM in a sibling core",
2769         "Offcore": "1"
2770     },
2771     {
2772         "EventCode": "0xB7, 0xBB",
2773         "MSRValue": "0x710",
2774         "Counter": "0,1,2,3",
2775         "UMask": "0x1",
2776         "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LOCAL_CACHE",
2777         "MSRIndex": "0x1a6,0x1a7",
2778         "SampleAfterValue": "100000",
2779         "BriefDescription": "Offcore prefetch data reads satisfied by the LLC",
2780         "Offcore": "1"
2781     },
2782     {
2783         "EventCode": "0xB7, 0xBB",
2784         "MSRValue": "0x2710",
2785         "Counter": "0,1,2,3",
2786         "UMask": "0x1",
2787         "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LOCAL_CACHE_DRAM",
2788         "MSRIndex": "0x1a6,0x1a7",
2789         "SampleAfterValue": "100000",
2790         "BriefDescription": "Offcore prefetch data reads satisfied by the LLC or local DRAM",
2791         "Offcore": "1"
2792     },
2793     {
2794         "EventCode": "0xB7, 0xBB",
2795         "MSRValue": "0x1810",
2796         "Counter": "0,1,2,3",
2797         "UMask": "0x1",
2798         "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE",
2799         "MSRIndex": "0x1a6,0x1a7",
2800         "SampleAfterValue": "100000",
2801         "BriefDescription": "Offcore prefetch data reads satisfied by a remote cache",
2802         "Offcore": "1"
2803     },
2804     {
2805         "EventCode": "0xB7, 0xBB",
2806         "MSRValue": "0x5810",
2807         "Counter": "0,1,2,3",
2808         "UMask": "0x1",
2809         "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE_DRAM",
2810         "MSRIndex": "0x1a6,0x1a7",
2811         "SampleAfterValue": "100000",
2812         "BriefDescription": "Offcore prefetch data reads satisfied by a remote cache or remote DRAM",
2813         "Offcore": "1"
2814     },
2815     {
2816         "EventCode": "0xB7, 0xBB",
2817         "MSRValue": "0x1010",
2818         "Counter": "0,1,2,3",
2819         "UMask": "0x1",
2820         "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE_HIT",
2821         "MSRIndex": "0x1a6,0x1a7",
2822         "SampleAfterValue": "100000",
2823         "BriefDescription": "Offcore prefetch data reads that HIT in a remote cache",
2824         "Offcore": "1"
2825     },
2826     {
2827         "EventCode": "0xB7, 0xBB",
2828         "MSRValue": "0x810",
2829         "Counter": "0,1,2,3",
2830         "UMask": "0x1",
2831         "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE_HITM",
2832         "MSRIndex": "0x1a6,0x1a7",
2833         "SampleAfterValue": "100000",
2834         "BriefDescription": "Offcore prefetch data reads that HITM in a remote cache",
2835         "Offcore": "1"
2836     },
2837     {
2838         "EventCode": "0xB7, 0xBB",
2839         "MSRValue": "0x7F40",
2840         "Counter": "0,1,2,3",
2841         "UMask": "0x1",
2842         "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_CACHE_DRAM",
2843         "MSRIndex": "0x1a6,0x1a7",
2844         "SampleAfterValue": "100000",
2845         "BriefDescription": "Offcore prefetch code reads satisfied by any cache or DRAM.",
2846         "Offcore": "1"
2847     },
2848     {
2849         "EventCode": "0xB7, 0xBB",
2850         "MSRValue": "0xFF40",
2851         "Counter": "0,1,2,3",
2852         "UMask": "0x1",
2853         "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_LOCATION",
2854         "MSRIndex": "0x1a6,0x1a7",
2855         "SampleAfterValue": "100000",
2856         "BriefDescription": "All offcore prefetch code reads",
2857         "Offcore": "1"
2858     },
2859     {
2860         "EventCode": "0xB7, 0xBB",
2861         "MSRValue": "0x8040",
2862         "Counter": "0,1,2,3",
2863         "UMask": "0x1",
2864         "EventName": "OFFCORE_RESPONSE.PF_IFETCH.IO_CSR_MMIO",
2865         "MSRIndex": "0x1a6,0x1a7",
2866         "SampleAfterValue": "100000",
2867         "BriefDescription": "Offcore prefetch code reads satisfied by the IO, CSR, MMIO unit",
2868         "Offcore": "1"
2869     },
2870     {
2871         "EventCode": "0xB7, 0xBB",
2872         "MSRValue": "0x140",
2873         "Counter": "0,1,2,3",
2874         "UMask": "0x1",
2875         "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_NO_OTHER_CORE",
2876         "MSRIndex": "0x1a6,0x1a7",
2877         "SampleAfterValue": "100000",
2878         "BriefDescription": "Offcore prefetch code reads satisfied by the LLC and not found in a sibling core",
2879         "Offcore": "1"
2880     },
2881     {
2882         "EventCode": "0xB7, 0xBB",
2883         "MSRValue": "0x240",
2884         "Counter": "0,1,2,3",
2885         "UMask": "0x1",
2886         "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_OTHER_CORE_HIT",
2887         "MSRIndex": "0x1a6,0x1a7",
2888         "SampleAfterValue": "100000",
2889         "BriefDescription": "Offcore prefetch code reads satisfied by the LLC and HIT in a sibling core",
2890         "Offcore": "1"
2891     },
2892     {
2893         "EventCode": "0xB7, 0xBB",
2894         "MSRValue": "0x440",
2895         "Counter": "0,1,2,3",
2896         "UMask": "0x1",
2897         "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_OTHER_CORE_HITM",
2898         "MSRIndex": "0x1a6,0x1a7",
2899         "SampleAfterValue": "100000",
2900         "BriefDescription": "Offcore prefetch code reads satisfied by the LLC  and HITM in a sibling core",
2901         "Offcore": "1"
2902     },
2903     {
2904         "EventCode": "0xB7, 0xBB",
2905         "MSRValue": "0x740",
2906         "Counter": "0,1,2,3",
2907         "UMask": "0x1",
2908         "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LOCAL_CACHE",
2909         "MSRIndex": "0x1a6,0x1a7",
2910         "SampleAfterValue": "100000",
2911         "BriefDescription": "Offcore prefetch code reads satisfied by the LLC",
2912         "Offcore": "1"
2913     },
2914     {
2915         "EventCode": "0xB7, 0xBB",
2916         "MSRValue": "0x2740",
2917         "Counter": "0,1,2,3",
2918         "UMask": "0x1",
2919         "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LOCAL_CACHE_DRAM",
2920         "MSRIndex": "0x1a6,0x1a7",
2921         "SampleAfterValue": "100000",
2922         "BriefDescription": "Offcore prefetch code reads satisfied by the LLC or local DRAM",
2923         "Offcore": "1"
2924     },
2925     {
2926         "EventCode": "0xB7, 0xBB",
2927         "MSRValue": "0x1840",
2928         "Counter": "0,1,2,3",
2929         "UMask": "0x1",
2930         "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE",
2931         "MSRIndex": "0x1a6,0x1a7",
2932         "SampleAfterValue": "100000",
2933         "BriefDescription": "Offcore prefetch code reads satisfied by a remote cache",
2934         "Offcore": "1"
2935     },
2936     {
2937         "EventCode": "0xB7, 0xBB",
2938         "MSRValue": "0x5840",
2939         "Counter": "0,1,2,3",
2940         "UMask": "0x1",
2941         "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE_DRAM",
2942         "MSRIndex": "0x1a6,0x1a7",
2943         "SampleAfterValue": "100000",
2944         "BriefDescription": "Offcore prefetch code reads satisfied by a remote cache or remote DRAM",
2945         "Offcore": "1"
2946     },
2947     {
2948         "EventCode": "0xB7, 0xBB",
2949         "MSRValue": "0x1040",
2950         "Counter": "0,1,2,3",
2951         "UMask": "0x1",
2952         "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE_HIT",
2953         "MSRIndex": "0x1a6,0x1a7",
2954         "SampleAfterValue": "100000",
2955         "BriefDescription": "Offcore prefetch code reads that HIT in a remote cache",
2956         "Offcore": "1"
2957     },
2958     {
2959         "EventCode": "0xB7, 0xBB",
2960         "MSRValue": "0x840",
2961         "Counter": "0,1,2,3",
2962         "UMask": "0x1",
2963         "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE_HITM",
2964         "MSRIndex": "0x1a6,0x1a7",
2965         "SampleAfterValue": "100000",
2966         "BriefDescription": "Offcore prefetch code reads that HITM in a remote cache",
2967         "Offcore": "1"
2968     },
2969     {
2970         "EventCode": "0xB7, 0xBB",
2971         "MSRValue": "0x7F20",
2972         "Counter": "0,1,2,3",
2973         "UMask": "0x1",
2974         "EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_CACHE_DRAM",
2975         "MSRIndex": "0x1a6,0x1a7",
2976         "SampleAfterValue": "100000",
2977         "BriefDescription": "Offcore prefetch RFO requests satisfied by any cache or DRAM.",
2978         "Offcore": "1"
2979     },
2980     {
2981         "EventCode": "0xB7, 0xBB",
2982         "MSRValue": "0xFF20",
2983         "Counter": "0,1,2,3",
2984         "UMask": "0x1",
2985         "EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_LOCATION",
2986         "MSRIndex": "0x1a6,0x1a7",
2987         "SampleAfterValue": "100000",
2988         "BriefDescription": "All offcore prefetch RFO requests",
2989         "Offcore": "1"
2990     },
2991     {
2992         "EventCode": "0xB7, 0xBB",
2993         "MSRValue": "0x8020",
2994         "Counter": "0,1,2,3",
2995         "UMask": "0x1",
2996         "EventName": "OFFCORE_RESPONSE.PF_RFO.IO_CSR_MMIO",
2997         "MSRIndex": "0x1a6,0x1a7",
2998         "SampleAfterValue": "100000",
2999         "BriefDescription": "Offcore prefetch RFO requests satisfied by the IO, CSR, MMIO unit",
3000         "Offcore": "1"
3001     },
3002     {
3003         "EventCode": "0xB7, 0xBB",
3004         "MSRValue": "0x120",
3005         "Counter": "0,1,2,3",
3006         "UMask": "0x1",
3007         "EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_NO_OTHER_CORE",
3008         "MSRIndex": "0x1a6,0x1a7",
3009         "SampleAfterValue": "100000",
3010         "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC and not found in a sibling core",
3011         "Offcore": "1"
3012     },
3013     {
3014         "EventCode": "0xB7, 0xBB",
3015         "MSRValue": "0x220",
3016         "Counter": "0,1,2,3",
3017         "UMask": "0x1",
3018         "EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_OTHER_CORE_HIT",
3019         "MSRIndex": "0x1a6,0x1a7",
3020         "SampleAfterValue": "100000",
3021         "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC and HIT in a sibling core",
3022         "Offcore": "1"
3023     },
3024     {
3025         "EventCode": "0xB7, 0xBB",
3026         "MSRValue": "0x420",
3027         "Counter": "0,1,2,3",
3028         "UMask": "0x1",
3029         "EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_OTHER_CORE_HITM",
3030         "MSRIndex": "0x1a6,0x1a7",
3031         "SampleAfterValue": "100000",
3032         "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC  and HITM in a sibling core",
3033         "Offcore": "1"
3034     },
3035     {
3036         "EventCode": "0xB7, 0xBB",
3037         "MSRValue": "0x720",
3038         "Counter": "0,1,2,3",
3039         "UMask": "0x1",
3040         "EventName": "OFFCORE_RESPONSE.PF_RFO.LOCAL_CACHE",
3041         "MSRIndex": "0x1a6,0x1a7",
3042         "SampleAfterValue": "100000",
3043         "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC",
3044         "Offcore": "1"
3045     },
3046     {
3047         "EventCode": "0xB7, 0xBB",
3048         "MSRValue": "0x2720",
3049         "Counter": "0,1,2,3",
3050         "UMask": "0x1",
3051         "EventName": "OFFCORE_RESPONSE.PF_RFO.LOCAL_CACHE_DRAM",
3052         "MSRIndex": "0x1a6,0x1a7",
3053         "SampleAfterValue": "100000",
3054         "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC or local DRAM",
3055         "Offcore": "1"
3056     },
3057     {
3058         "EventCode": "0xB7, 0xBB",
3059         "MSRValue": "0x1820",
3060         "Counter": "0,1,2,3",
3061         "UMask": "0x1",
3062         "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE",
3063         "MSRIndex": "0x1a6,0x1a7",
3064         "SampleAfterValue": "100000",
3065         "BriefDescription": "Offcore prefetch RFO requests satisfied by a remote cache",
3066         "Offcore": "1"
3067     },
3068     {
3069         "EventCode": "0xB7, 0xBB",
3070         "MSRValue": "0x5820",
3071         "Counter": "0,1,2,3",
3072         "UMask": "0x1",
3073         "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE_DRAM",
3074         "MSRIndex": "0x1a6,0x1a7",
3075         "SampleAfterValue": "100000",
3076         "BriefDescription": "Offcore prefetch RFO requests satisfied by a remote cache or remote DRAM",
3077         "Offcore": "1"
3078     },
3079     {
3080         "EventCode": "0xB7, 0xBB",
3081         "MSRValue": "0x1020",
3082         "Counter": "0,1,2,3",
3083         "UMask": "0x1",
3084         "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE_HIT",
3085         "MSRIndex": "0x1a6,0x1a7",
3086         "SampleAfterValue": "100000",
3087         "BriefDescription": "Offcore prefetch RFO requests that HIT in a remote cache",
3088         "Offcore": "1"
3089     },
3090     {
3091         "EventCode": "0xB7, 0xBB",
3092         "MSRValue": "0x820",
3093         "Counter": "0,1,2,3",
3094         "UMask": "0x1",
3095         "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE_HITM",
3096         "MSRIndex": "0x1a6,0x1a7",
3097         "SampleAfterValue": "100000",
3098         "BriefDescription": "Offcore prefetch RFO requests that HITM in a remote cache",
3099         "Offcore": "1"
3100     },
3101     {
3102         "EventCode": "0xB7, 0xBB",
3103         "MSRValue": "0x7F70",
3104         "Counter": "0,1,2,3",
3105         "UMask": "0x1",
3106         "EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_CACHE_DRAM",
3107         "MSRIndex": "0x1a6,0x1a7",
3108         "SampleAfterValue": "100000",
3109         "BriefDescription": "Offcore prefetch requests satisfied by any cache or DRAM.",
3110         "Offcore": "1"
3111     },
3112     {
3113         "EventCode": "0xB7, 0xBB",
3114         "MSRValue": "0xFF70",
3115         "Counter": "0,1,2,3",
3116         "UMask": "0x1",
3117         "EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_LOCATION",
3118         "MSRIndex": "0x1a6,0x1a7",
3119         "SampleAfterValue": "100000",
3120         "BriefDescription": "All offcore prefetch requests",
3121         "Offcore": "1"
3122     },
3123     {
3124         "EventCode": "0xB7, 0xBB",
3125         "MSRValue": "0x8070",
3126         "Counter": "0,1,2,3",
3127         "UMask": "0x1",
3128         "EventName": "OFFCORE_RESPONSE.PREFETCH.IO_CSR_MMIO",
3129         "MSRIndex": "0x1a6,0x1a7",
3130         "SampleAfterValue": "100000",
3131         "BriefDescription": "Offcore prefetch requests satisfied by the IO, CSR, MMIO unit",
3132         "Offcore": "1"
3133     },
3134     {
3135         "EventCode": "0xB7, 0xBB",
3136         "MSRValue": "0x170",
3137         "Counter": "0,1,2,3",
3138         "UMask": "0x1",
3139         "EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_NO_OTHER_CORE",
3140         "MSRIndex": "0x1a6,0x1a7",
3141         "SampleAfterValue": "100000",
3142         "BriefDescription": "Offcore prefetch requests satisfied by the LLC and not found in a sibling core",
3143         "Offcore": "1"
3144     },
3145     {
3146         "EventCode": "0xB7, 0xBB",
3147         "MSRValue": "0x270",
3148         "Counter": "0,1,2,3",
3149         "UMask": "0x1",
3150         "EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_OTHER_CORE_HIT",
3151         "MSRIndex": "0x1a6,0x1a7",
3152         "SampleAfterValue": "100000",
3153         "BriefDescription": "Offcore prefetch requests satisfied by the LLC and HIT in a sibling core",
3154         "Offcore": "1"
3155     },
3156     {
3157         "EventCode": "0xB7, 0xBB",
3158         "MSRValue": "0x470",
3159         "Counter": "0,1,2,3",
3160         "UMask": "0x1",
3161         "EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_OTHER_CORE_HITM",
3162         "MSRIndex": "0x1a6,0x1a7",
3163         "SampleAfterValue": "100000",
3164         "BriefDescription": "Offcore prefetch requests satisfied by the LLC  and HITM in a sibling core",
3165         "Offcore": "1"
3166     },
3167     {
3168         "EventCode": "0xB7, 0xBB",
3169         "MSRValue": "0x770",
3170         "Counter": "0,1,2,3",
3171         "UMask": "0x1",
3172         "EventName": "OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE",
3173         "MSRIndex": "0x1a6,0x1a7",
3174         "SampleAfterValue": "100000",
3175         "BriefDescription": "Offcore prefetch requests satisfied by the LLC",
3176         "Offcore": "1"
3177     },
3178     {
3179         "EventCode": "0xB7, 0xBB",
3180         "MSRValue": "0x2770",
3181         "Counter": "0,1,2,3",
3182         "UMask": "0x1",
3183         "EventName": "OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE_DRAM",
3184         "MSRIndex": "0x1a6,0x1a7",
3185         "SampleAfterValue": "100000",
3186         "BriefDescription": "Offcore prefetch requests satisfied by the LLC or local DRAM",
3187         "Offcore": "1"
3188     },
3189     {
3190         "EventCode": "0xB7, 0xBB",
3191         "MSRValue": "0x1870",
3192         "Counter": "0,1,2,3",
3193         "UMask": "0x1",
3194         "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE",
3195         "MSRIndex": "0x1a6,0x1a7",
3196         "SampleAfterValue": "100000",
3197         "BriefDescription": "Offcore prefetch requests satisfied by a remote cache",
3198         "Offcore": "1"
3199     },
3200     {
3201         "EventCode": "0xB7, 0xBB",
3202         "MSRValue": "0x5870",
3203         "Counter": "0,1,2,3",
3204         "UMask": "0x1",
3205         "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_DRAM",
3206         "MSRIndex": "0x1a6,0x1a7",
3207         "SampleAfterValue": "100000",
3208         "BriefDescription": "Offcore prefetch requests satisfied by a remote cache or remote DRAM",
3209         "Offcore": "1"
3210     },
3211     {
3212         "EventCode": "0xB7, 0xBB",
3213         "MSRValue": "0x1070",
3214         "Counter": "0,1,2,3",
3215         "UMask": "0x1",
3216         "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_HIT",
3217         "MSRIndex": "0x1a6,0x1a7",
3218         "SampleAfterValue": "100000",
3219         "BriefDescription": "Offcore prefetch requests that HIT in a remote cache",
3220         "Offcore": "1"
3221     },
3222     {
3223         "EventCode": "0xB7, 0xBB",
3224         "MSRValue": "0x870",
3225         "Counter": "0,1,2,3",
3226         "UMask": "0x1",
3227         "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_HITM",
3228         "MSRIndex": "0x1a6,0x1a7",
3229         "SampleAfterValue": "100000",
3230         "BriefDescription": "Offcore prefetch requests that HITM in a remote cache",
3231         "Offcore": "1"
3232     }
3233 ]