tools/perf/pmu-events/arch/x86/westmereep-sp/virtual-memory.json

   1 [
   2     {
   3         "EventCode": "0x8",
   4         "Counter": "0,1,2,3",
   5         "UMask": "0x1",
   6         "EventName": "DTLB_LOAD_MISSES.ANY",
   7         "SampleAfterValue": "200000",
   8         "BriefDescription": "DTLB load misses"
   9     },
  10     {
  11         "EventCode": "0x8",
  12         "Counter": "0,1,2,3",
  13         "UMask": "0x20",
  14         "EventName": "DTLB_LOAD_MISSES.PDE_MISS",
  15         "SampleAfterValue": "200000",
  16         "BriefDescription": "DTLB load miss caused by low part of address"
  17     },
  18     {
  19         "EventCode": "0x8",
  20         "Counter": "0,1,2,3",
  21         "UMask": "0x10",
  22         "EventName": "DTLB_LOAD_MISSES.STLB_HIT",
  23         "SampleAfterValue": "2000000",
  24         "BriefDescription": "DTLB second level hit"
  25     },
  26     {
  27         "EventCode": "0x8",
  28         "Counter": "0,1,2,3",
  29         "UMask": "0x2",
  30         "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED",
  31         "SampleAfterValue": "200000",
  32         "BriefDescription": "DTLB load miss page walks complete"
  33     },
  34     {
  35         "EventCode": "0x8",
  36         "Counter": "0,1,2,3",
  37         "UMask": "0x4",
  38         "EventName": "DTLB_LOAD_MISSES.WALK_CYCLES",
  39         "SampleAfterValue": "200000",
  40         "BriefDescription": "DTLB load miss page walk cycles"
  41     },
  42     {
  43         "EventCode": "0x49",
  44         "Counter": "0,1,2,3",
  45         "UMask": "0x1",
  46         "EventName": "DTLB_MISSES.ANY",
  47         "SampleAfterValue": "200000",
  48         "BriefDescription": "DTLB misses"
  49     },
  50     {
  51         "EventCode": "0x49",
  52         "Counter": "0,1,2,3",
  53         "UMask": "0x80",
  54         "EventName": "DTLB_MISSES.LARGE_WALK_COMPLETED",
  55         "SampleAfterValue": "200000",
  56         "BriefDescription": "DTLB miss large page walks"
  57     },
  58     {
  59         "EventCode": "0x49",
  60         "Counter": "0,1,2,3",
  61         "UMask": "0x10",
  62         "EventName": "DTLB_MISSES.STLB_HIT",
  63         "SampleAfterValue": "200000",
  64         "BriefDescription": "DTLB first level misses but second level hit"
  65     },
  66     {
  67         "EventCode": "0x49",
  68         "Counter": "0,1,2,3",
  69         "UMask": "0x2",
  70         "EventName": "DTLB_MISSES.WALK_COMPLETED",
  71         "SampleAfterValue": "200000",
  72         "BriefDescription": "DTLB miss page walks"
  73     },
  74     {
  75         "EventCode": "0x49",
  76         "Counter": "0,1,2,3",
  77         "UMask": "0x4",
  78         "EventName": "DTLB_MISSES.WALK_CYCLES",
  79         "SampleAfterValue": "2000000",
  80         "BriefDescription": "DTLB miss page walk cycles"
  81     },
  82     {
  83         "EventCode": "0x4F",
  84         "Counter": "0,1,2,3",
  85         "UMask": "0x10",
  86         "EventName": "EPT.WALK_CYCLES",
  87         "SampleAfterValue": "2000000",
  88         "BriefDescription": "Extended Page Table walk cycles"
  89     },
  90     {
  91         "EventCode": "0xAE",
  92         "Counter": "0,1,2,3",
  93         "UMask": "0x1",
  94         "EventName": "ITLB_FLUSH",
  95         "SampleAfterValue": "2000000",
  96         "BriefDescription": "ITLB flushes"
  97     },
  98     {
  99         "PEBS": "1",
 100         "EventCode": "0xC8",
 101         "Counter": "0,1,2,3",
 102         "UMask": "0x20",
 103         "EventName": "ITLB_MISS_RETIRED",
 104         "SampleAfterValue": "200000",
 105         "BriefDescription": "Retired instructions that missed the ITLB (Precise Event)"
 106     },
 107     {
 108         "EventCode": "0x85",
 109         "Counter": "0,1,2,3",
 110         "UMask": "0x1",
 111         "EventName": "ITLB_MISSES.ANY",
 112         "SampleAfterValue": "200000",
 113         "BriefDescription": "ITLB miss"
 114     },
 115     {
 116         "EventCode": "0x85",
 117         "Counter": "0,1,2,3",
 118         "UMask": "0x2",
 119         "EventName": "ITLB_MISSES.WALK_COMPLETED",
 120         "SampleAfterValue": "200000",
 121         "BriefDescription": "ITLB miss page walks"
 122     },
 123     {
 124         "EventCode": "0x85",
 125         "Counter": "0,1,2,3",
 126         "UMask": "0x4",
 127         "EventName": "ITLB_MISSES.WALK_CYCLES",
 128         "SampleAfterValue": "2000000",
 129         "BriefDescription": "ITLB miss page walk cycles"
 130     },
 131     {
 132         "PEBS": "1",
 133         "EventCode": "0xCB",
 134         "Counter": "0,1,2,3",
 135         "UMask": "0x80",
 136         "EventName": "MEM_LOAD_RETIRED.DTLB_MISS",
 137         "SampleAfterValue": "200000",
 138         "BriefDescription": "Retired loads that miss the DTLB (Precise Event)"
 139     },
 140     {
 141         "PEBS": "1",
 142         "EventCode": "0xC",
 143         "Counter": "0,1,2,3",
 144         "UMask": "0x1",
 145         "EventName": "MEM_STORE_RETIRED.DTLB_MISS",
 146         "SampleAfterValue": "200000",
 147         "BriefDescription": "Retired stores that miss the DTLB (Precise Event)"
 148     }
 149 ]