tools/perf/pmu-events/arch/x86/westmereex/virtual-memory.json

   1 [
   2     {
   3         "EventCode": "0x8",
   4         "Counter": "0,1,2,3",
   5         "UMask": "0x1",
   6         "EventName": "DTLB_LOAD_MISSES.ANY",
   7         "SampleAfterValue": "200000",
   8         "BriefDescription": "DTLB load misses"
   9     },
  10     {
  11         "EventCode": "0x8",
  12         "Counter": "0,1,2,3",
  13         "UMask": "0x80",
  14         "EventName": "DTLB_LOAD_MISSES.LARGE_WALK_COMPLETED",
  15         "SampleAfterValue": "200000",
  16         "BriefDescription": "DTLB load miss large page walks"
  17     },
  18     {
  19         "EventCode": "0x8",
  20         "Counter": "0,1,2,3",
  21         "UMask": "0x20",
  22         "EventName": "DTLB_LOAD_MISSES.PDE_MISS",
  23         "SampleAfterValue": "200000",
  24         "BriefDescription": "DTLB load miss caused by low part of address"
  25     },
  26     {
  27         "EventCode": "0x8",
  28         "Counter": "0,1,2,3",
  29         "UMask": "0x10",
  30         "EventName": "DTLB_LOAD_MISSES.STLB_HIT",
  31         "SampleAfterValue": "2000000",
  32         "BriefDescription": "DTLB second level hit"
  33     },
  34     {
  35         "EventCode": "0x8",
  36         "Counter": "0,1,2,3",
  37         "UMask": "0x2",
  38         "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED",
  39         "SampleAfterValue": "200000",
  40         "BriefDescription": "DTLB load miss page walks complete"
  41     },
  42     {
  43         "EventCode": "0x8",
  44         "Counter": "0,1,2,3",
  45         "UMask": "0x4",
  46         "EventName": "DTLB_LOAD_MISSES.WALK_CYCLES",
  47         "SampleAfterValue": "200000",
  48         "BriefDescription": "DTLB load miss page walk cycles"
  49     },
  50     {
  51         "EventCode": "0x49",
  52         "Counter": "0,1,2,3",
  53         "UMask": "0x1",
  54         "EventName": "DTLB_MISSES.ANY",
  55         "SampleAfterValue": "200000",
  56         "BriefDescription": "DTLB misses"
  57     },
  58     {
  59         "EventCode": "0x49",
  60         "Counter": "0,1,2,3",
  61         "UMask": "0x80",
  62         "EventName": "DTLB_MISSES.LARGE_WALK_COMPLETED",
  63         "SampleAfterValue": "200000",
  64         "BriefDescription": "DTLB miss large page walks"
  65     },
  66     {
  67         "EventCode": "0x49",
  68         "Counter": "0,1,2,3",
  69         "UMask": "0x20",
  70         "EventName": "DTLB_MISSES.PDE_MISS",
  71         "SampleAfterValue": "200000",
  72         "BriefDescription": "DTLB misses caused by low part of address. Count also includes 2M page references because 2M pages do not use the PDE."
  73     },
  74     {
  75         "EventCode": "0x49",
  76         "Counter": "0,1,2,3",
  77         "UMask": "0x10",
  78         "EventName": "DTLB_MISSES.STLB_HIT",
  79         "SampleAfterValue": "200000",
  80         "BriefDescription": "DTLB first level misses but second level hit"
  81     },
  82     {
  83         "EventCode": "0x49",
  84         "Counter": "0,1,2,3",
  85         "UMask": "0x2",
  86         "EventName": "DTLB_MISSES.WALK_COMPLETED",
  87         "SampleAfterValue": "200000",
  88         "BriefDescription": "DTLB miss page walks"
  89     },
  90     {
  91         "EventCode": "0x49",
  92         "Counter": "0,1,2,3",
  93         "UMask": "0x4",
  94         "EventName": "DTLB_MISSES.WALK_CYCLES",
  95         "SampleAfterValue": "2000000",
  96         "BriefDescription": "DTLB miss page walk cycles"
  97     },
  98     {
  99         "EventCode": "0x4F",
 100         "Counter": "0,1,2,3",
 101         "UMask": "0x10",
 102         "EventName": "EPT.WALK_CYCLES",
 103         "SampleAfterValue": "2000000",
 104         "BriefDescription": "Extended Page Table walk cycles"
 105     },
 106     {
 107         "EventCode": "0xAE",
 108         "Counter": "0,1,2,3",
 109         "UMask": "0x1",
 110         "EventName": "ITLB_FLUSH",
 111         "SampleAfterValue": "2000000",
 112         "BriefDescription": "ITLB flushes"
 113     },
 114     {
 115         "PEBS": "1",
 116         "EventCode": "0xC8",
 117         "Counter": "0,1,2,3",
 118         "UMask": "0x20",
 119         "EventName": "ITLB_MISS_RETIRED",
 120         "SampleAfterValue": "200000",
 121         "BriefDescription": "Retired instructions that missed the ITLB (Precise Event)"
 122     },
 123     {
 124         "EventCode": "0x85",
 125         "Counter": "0,1,2,3",
 126         "UMask": "0x1",
 127         "EventName": "ITLB_MISSES.ANY",
 128         "SampleAfterValue": "200000",
 129         "BriefDescription": "ITLB miss"
 130     },
 131     {
 132         "EventCode": "0x85",
 133         "Counter": "0,1,2,3",
 134         "UMask": "0x80",
 135         "EventName": "ITLB_MISSES.LARGE_WALK_COMPLETED",
 136         "SampleAfterValue": "200000",
 137         "BriefDescription": "ITLB miss large page walks"
 138     },
 139     {
 140         "EventCode": "0x85",
 141         "Counter": "0,1,2,3",
 142         "UMask": "0x2",
 143         "EventName": "ITLB_MISSES.WALK_COMPLETED",
 144         "SampleAfterValue": "200000",
 145         "BriefDescription": "ITLB miss page walks"
 146     },
 147     {
 148         "EventCode": "0x85",
 149         "Counter": "0,1,2,3",
 150         "UMask": "0x4",
 151         "EventName": "ITLB_MISSES.WALK_CYCLES",
 152         "SampleAfterValue": "2000000",
 153         "BriefDescription": "ITLB miss page walk cycles"
 154     },
 155     {
 156         "PEBS": "1",
 157         "EventCode": "0xCB",
 158         "Counter": "0,1,2,3",
 159         "UMask": "0x80",
 160         "EventName": "MEM_LOAD_RETIRED.DTLB_MISS",
 161         "SampleAfterValue": "200000",
 162         "BriefDescription": "Retired loads that miss the DTLB (Precise Event)"
 163     },
 164     {
 165         "PEBS": "1",
 166         "EventCode": "0xC",
 167         "Counter": "0,1,2,3",
 168         "UMask": "0x1",
 169         "EventName": "MEM_STORE_RETIRED.DTLB_MISS",
 170         "SampleAfterValue": "200000",
 171         "BriefDescription": "Retired stores that miss the DTLB (Precise Event)"
 172     }
 173 ]